Display panel and display device

Abstract

The present application discloses a display panel and a display device. The display panel comprises a display area and a fan-out area; the display panel comprises a substrate, a light-emitting layer and a driver chip; the substrate comprises a base, a first conductive layer and a second conductive layer; the substrate comprises fan-out lines located in the fan-out area, and each fan-out line comprises a first wire located on the first conductive layer and a second wire located on the second conductive layer; the light-emitting layer comprises first light-emitting unit groups and second light-emitting unit groups alternately arranged in a second direction, the first light-emitting unit groups and the second light-emitting unit groups each comprise a plurality of light-emitting units arranged in a first direction, and the colors of the light-emitting units in the first light-emitting unit groups are different from those of the light-emitting units in the second light-emitting unit groups; the first wires are used for electrically connecting the light-emitting units in the first light-emitting unit groups to the driver chip, and the second wires are used for electrically connecting the light-emitting units in the second light-emitting unit groups to the driver chip. The display panel provided by the present application can effectively reduce the display difference between light-emitting units of the same color.

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310792177.9, filed on June 29, 2023, entitled “Electronic paper driving circuit, preparation method and electronic paper display panel,” and the entire contents of that application are incorporated herein by reference. Technical Field

[0003] The present application belongs to the field of display technology, and in particular relates to a display panel and a display device. Background Art

[0004] With the development of display technology, the requirements for display quality of display devices are getting higher and higher. In the related art, the display panel has the phenomenon of vertical stripes appearing on the screen, which seriously affects the display quality of the display panel.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a display panel and a display device, which can improve the display quality of the display panel.

[0007] An embodiment of a first aspect of the present application provides a display panel, including a display area and a fan-out area, wherein the display panel includes:

[0008] A substrate, the substrate comprising a substrate and a first conductive layer and a second conductive layer stacked on the substrate, a fan-out line formed in the substrate, the fan-out line being located in the fan-out area, the fan-out line comprising a first trace and a second trace, the first trace being located in the first conductive layer, and the second trace being located in the second conductive layer;

[0009] a light-emitting layer comprising a plurality of light-emitting units formed on one side of the substrate, the light-emitting layer comprising a first light-emitting unit group and a second light-emitting unit group, the first light-emitting unit group comprising a plurality of the light-emitting units arranged along a first direction, the second light-emitting unit group comprising a plurality of the light-emitting units arranged along the first direction, the light-emitting units in the first light-emitting unit group and the second light-emitting unit group having different colors, the first light-emitting unit group and the second light-emitting unit group being alternately arranged along a second direction, and the first direction intersecting the second direction;

[0010] A driver chip is located in the fan-out area;

[0011] The first wiring is used to electrically connect the light-emitting units in the first light-emitting unit group with the driver chip, and the second wiring is used to electrically connect the light-emitting units in the second light-emitting unit group with the driver chip.

[0012] An embodiment of the second aspect of the present application further provides a display device, comprising any one of the display panels provided in the first aspect of the present application.

[0013] The display panel includes a display area and a fan-out area. The display area includes light-emitting units. The fan-out area includes fan-out lines and a driving circuit. The light-emitting units are electrically connected to the driving circuit via the fan-out lines. The fan-out lines include a first trace and a second trace. The first trace is located in a first conductive layer, and the second trace is located in a second conductive layer. The fan-out lines are arranged in two conductive layers, thereby reducing the bezel size of the display panel and simplifying wiring. The light-emitting units are divided into a first light-emitting unit group and a second light-emitting unit group. The color of the light-emitting units in the first light-emitting unit group is different from the color of the light-emitting units in the second light-emitting unit group. The light-emitting units in the first light-emitting unit group are connected to the first trace, and the light-emitting units in the second light-emitting unit group are connected to the second trace. This allows light-emitting units of the same color to be connected to the same fan-out line. Since the first traces are all located in the first conductive layer, the differences between different first traces due to process fluctuations are relatively small; since the second traces are all located in the second conductive layer, the differences between different second traces due to process fluctuations are relatively small; after the light-emitting units in the first light-emitting unit group are electrically connected to the driver chip via the first traces, and after the light-emitting units in the second light-emitting unit group are electrically connected to the driver chip via the second traces, the fan-out lines connected to the same light-emitting units can be located in the same layer, thereby reducing the display differences between light-emitting units of the same color due to differences in the fan-out lines themselves. That is, in the display panel provided by the present application, the light-emitting units of each color are connected to the same fan-out line (first trace or second trace), which can effectively reduce the display differences between the light-emitting units of the same color, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a schematic structural diagram of a display panel in the prior art;

[0015] FIG2 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0016] FIG3 is a cross-sectional view along PP' in FIG2;

[0017] FIG4 is a cross-sectional view taken along line J-J' in FIG2 ;

[0018] FIG5 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0019] FIG6 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0020] FIG7 is a cross-sectional view taken along line Q-Q' in FIG6;

[0021] FIG8 is a cross-sectional view of another display panel provided in an embodiment of the present application;

[0022] FIG9 is a cross-sectional view of another display panel provided in an embodiment of the present application;

[0023] FIG10 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0024] FIG11 is a schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating the examples of the present application.

[0026] As shown in Figure 1, the data lines connected to the sub-pixels in the display panel 1' are electrically connected to the fan-out lines 11' after being connected to the fan-out lines. This facilitates the electrical connection between the sub-pixels and the driver chip 12' via the fan-out lines, which in turn drives the sub-pixels to emit light. However, since a certain spacing must be maintained between the fan-out lines 11', some fan-out lines 11' corresponding to the arc angle area are longer and have a larger inclination. This requires the bottom frame to maintain a larger width D' to maintain the required spacing between adjacent fan-out lines 11'. The inventors have discovered that the vertical stripes in the display panel 1' are caused by: in order to achieve a narrow bezel for the display panel 1' and avoid the arc angle area of ​​the bottom bezel, the fan-out lines 11' in the display panel 1' are arranged in different layers. This reduces the number of fan-out lines 11' provided on each layer, thereby reducing the width D' of the bottom bezel to a certain extent while maintaining the preset spacing. However, this approach may result in fan-out lines 11' connected to sub-pixels of the same color being located on different layers. The process fluctuations between the fan-out lines 11' located on the same layer are small, resulting in a small difference in the line width of the fan-out lines 11' located on the same layer. The process fluctuations between the fan-out lines 11' located on different layers are large, resulting in a large difference in the line width between the fan-out lines 11' located on different layers. Due to the above-mentioned differences between the fan-out lines 11' on different layers, there are differences in the display between the sub-pixels of the same color connected to the fan-out lines 11' on different layers, resulting in vertical stripes on the monochrome screen of the display panel 1'. Based on the research on the above-mentioned problems, the inventors provide a display panel 1' and a display device to improve the display quality of the display panel 1'.

[0027] In order to better understand the present application, the display panel and the display device according to the embodiments of the present application are described in detail below with reference to Figures 2 to 11.

[0028] Referring to Figures 2 to 4 , an embodiment of the present application provides a display panel 1 including a display area AA and a fan-out area NA. The display panel 1 includes a substrate 11, a light-emitting layer 10, and a driver chip 12. The substrate 11 includes a base 111 and a first conductive layer 112 and a second conductive layer 113 stacked on the base 111. A fan-out line 114 is formed within the substrate 11 and is located within the fan-out area NA. The fan-out line 114 includes a first trace 1141 and a second trace 1142. The first trace 1141 is located in the first conductive layer 112, and the second trace 1142 is located in the second conductive layer 113. The light-emitting layer 10 includes a plurality of light-emitting units 101 formed on one side of the substrate 11. The light-emitting layer 10 includes a first light-emitting unit group 102 and a second light-emitting unit group 103. The first light-emitting unit group 102 includes a plurality of light-emitting units 101 arranged along a first direction x, and the second light-emitting unit group 103 includes a plurality of light-emitting units 101 arranged along the first direction x. The light-emitting units 101 in the first light-emitting unit group 102 and the second light-emitting unit group 103 have different colors. The first light-emitting unit group 102 and the second light-emitting unit group 103 are alternately arranged along a second direction y, and the first direction x intersects the second direction y. The driver chip 12 is located in the fan-out area NA. The first trace 1141 is used to electrically connect the light-emitting units 101 in the first light-emitting unit group 102 to the driver chip 12, and the second trace 1142 is used to electrically connect the light-emitting units 101 in the second light-emitting unit group 103 to the driver chip 12.

[0029] The display panel 1 includes a display area AA and a fan-out area NA. The display area AA includes a light-emitting unit 101, and the fan-out area NA includes fan-out lines 114 and a driving circuit. The light-emitting unit 101 is electrically connected to the driving circuit via the fan-out lines 114. The fan-out lines 114 include a first trace 1141 and a second trace 1142. The first trace 1141 is located in the first conductive layer 112, and the second trace 1142 is located in the second conductive layer 113. Placing the fan-out lines 114 within two conductive layers can reduce the bezel size of the display panel 1 and simplify wiring. The light-emitting units 101 are divided into a first light-emitting unit group 102 and a second light-emitting unit group 103. The color of the light-emitting units 101 in the first light-emitting unit group 102 is different from the color of the light-emitting units 101 in the second light-emitting unit group 103. The light-emitting units 101 in the first light-emitting unit group 102 are connected to the first routing 1141, and the light-emitting units 101 in the second light-emitting unit group 103 are connected to the second routing 1142, so that the light-emitting units 101 of the same color can be connected to the same fan-out line 114. Since the first routing lines 1141 are all located in the first conductive layer 112, the differences between different first routing lines 1141 caused by process fluctuations are relatively small; since the second routing lines 1142 are all located in the second conductive layer 113, the differences between different second routing lines 1142 caused by process fluctuations are relatively small; after the light-emitting units 101 in the first light-emitting unit group 102 are electrically connected to the driver chip 12 through the first routing lines 1141, and after the light-emitting units 101 in the second light-emitting unit group 103 are electrically connected to the driver chip 12 through the second routing lines 1142, the fan-out lines 114 connected to the same light-emitting units 101 can be located in the same layer, so that the display differences of the light-emitting units 101 of the same color caused by the differences in the fan-out lines 114 themselves are relatively small. That is, in the display panel 1 provided in the present application, the light-emitting units 101 of each color are connected to the same fan-out line 114 (first line 1141 or second line 1142), which can effectively reduce the display difference of the light-emitting units 101 of the same color, so that the display effect of the display panel 1 is better.

[0030] In a feasible embodiment, as shown in FIG2 and FIG5 , one of the first light emitting unit group 102 and the second light emitting unit group 103 includes at least two colors of light emitting units 101 , and the other includes at least one color of light emitting units 101 .

[0031] 2 , the first light emitting unit group 102 may include first color light emitting units 101 and second color light emitting units 101 alternately arranged along the first direction x, and the second light emitting unit group 103 may include third color light emitting units 101 arranged along the first direction x.

[0032] Specifically, as shown in FIG2 , the first color light emitting unit 101 may be a red light emitting unit 101 , the second color light emitting unit 101 may be a blue light emitting unit 101 , and the third color light emitting unit 101 may be a green light emitting unit 101 .

[0033] Alternatively, as shown in Figure 5, the second light-emitting unit group 103 also includes a fourth color light-emitting unit 101, and the fourth color light-emitting unit 101 and the third color light-emitting unit 101 are arranged alternately along the first direction x. At this time, the first color light-emitting unit 101, the second color light-emitting unit 101, the third color light-emitting unit 101 and the fourth color light-emitting unit 101 can correspond to the red light-emitting unit 101, the green light-emitting unit 101, the blue light-emitting unit 101 and the white light-emitting unit 101. The specific correspondence method is not particularly limited in this application.

[0034] In a feasible embodiment, as shown in Figures 2 and 5, the substrate 11 also includes a plurality of data lines 115, the plurality of data lines 115 include a first data line 1151 and a second data line 1152, the first data line 1151 is electrically connected to the light-emitting unit 101 in the first light-emitting unit group 102, the second data line 1152 is electrically connected to the light-emitting unit 101 in the second light-emitting unit group 103, the first routing line 1141 corresponds one-to-one to the first data line 1151 and is electrically connected, and the second routing line 1142 corresponds one-to-one to the second data line 1152 and is electrically connected.

[0035] In the display panel 1, the first trace 1141 is used to connect the first data line 1151 to the driver chip 12 to provide data signals to the light-emitting units 101 in the first light-emitting unit group 102. The second trace 1142 is used to connect the second data line 1152 to the driver chip 12 to provide data signals to the light-emitting units 101 in the second light-emitting unit group 103.

[0036] The substrate 11 includes a driving circuit for driving the light-emitting unit 101 to emit light. The driving circuit is connected to the light-emitting unit 101 and the data line 115 respectively.

[0037] In a feasible embodiment, as shown in Figures 3 and 4, the substrate 11 includes a substrate 111 and a first metal layer 119, a second metal layer 120, a third metal layer 121, a fourth metal layer 122, a fifth metal layer 123, and a sixth metal layer 124 stacked in a direction away from the substrate 111. The substrate 11 includes a transistor 125 and a capacitor 126. The driving circuit for driving the light-emitting unit 101 to emit light includes the above-mentioned transistor 125 and capacitor 126.

[0038] The first metal layer 119 is located between the substrate 111 and the transistor 125 and serves as a shielding metal layer to protect the performance of the transistor 125 .

[0039] The second metal layer 120 is used to form a gate 1251 of the transistor 125 and a first plate 1261 of the capacitor 126 .

[0040] The third metal layer 121 is used to form the second plate 1262 of the capacitor 126 .

[0041] The fourth metal layer 122 is used to form the source and drain 1252 of the transistor 125 .

[0042] The fifth metal layer 123 and the sixth metal layer 124 are used to form the data line 115 .

[0043] The first conductive layer 112 is disposed on the same layer as one of the first metal layer 119 , the second metal layer 120 and the third metal layer 121 , and the second conductive layer 113 is disposed on the same layer as the other one of the first metal layer 119 , the second metal layer 120 and the third metal layer 121 .

[0044] In the above embodiment, the first trace 1141 may be located in one of the first metal layer 119, the second metal layer 120, and the third metal layer 121, and the second trace 1142 may be located in the other of the first metal layer 119, the second metal layer 120, and the third metal layer 121. The first trace 1141 and the second trace 1142 may be electrically connected to the data line 115 through a via.

[0045] As shown in FIG4 , the first conductive layer 112 and the second metal layer 120 are provided on the same layer; as shown in FIG3 , the second conductive layer 113 and the third metal layer 121 are provided on the same layer. Other situations are not shown in the figures.

[0046] In a feasible embodiment, the substrate 11 includes a third conductive layer 116 and a fourth conductive layer 117 stacked on a side of the second conductive layer 113 facing away from the substrate 111 , and the data line 115 is located in the third conductive layer 116 or the fourth conductive layer 117 .

[0047] In a feasible embodiment, as shown in FIG. 4 , the third conductive layer 116 and the fifth metal layer 123 are disposed in the same layer, and the fourth conductive layer 117 and the sixth metal layer 124 are disposed in the same layer.

[0048] In the above embodiment, the data line 115 is disposed in the fifth metal layer 123 or the sixth metal layer 124 , thereby avoiding devices such as the transistor 125 and the capacitor 126 located in the second metal layer 120 , the third metal layer 121 , and the fourth metal layer 122 .

[0049] In a feasible embodiment, as shown in Figure 6, the display area AA includes a middle area AA1 and edge areas AA2 located on both sides of the middle area AA1 along the second direction y. Along the first direction x, the positive projection of the fan-out line 114 in the display area AA is located in the middle area AA1, and the first data line 1151 and the fan-out line 114 in the edge area AA2 are connected to the fan-out line 114, and the second data line 1152 and the fan-out line 114 are respectively connected through the first connecting portion 118, and the first connecting portion 118 is at least partially located in the display area AA.

[0050] In the above-described embodiment, the display panel 1 may include an arc-angle region, which is arranged relative to the edge region AA2 along the first direction x. The space in the arc-angle region is relatively small. Therefore, in one embodiment, the fan-out line 114 may be partially located in the arc-angle region and arranged at an angle. However, the fan-out line 114 arranged at an angle requires more space than the fan-out line 114 arranged parallel to the first direction x, which is not conducive to achieving a narrow bezel design. Therefore, in another embodiment, as shown in Figure 6, the fan-out line 114 is concentrated in an area arranged relative to the middle region AA1 along the first direction x, and the fan-out line 114 is electrically connected to the data line 115 via a first connecting portion 118. The first connecting portion 118 is at least partially located within the display area AA. This can effectively solve the interference of the smaller space in the arc-angle region on the wiring of the fan-out line 114 and help achieve a narrow bezel.

[0051] In one feasible embodiment, as shown in FIG6 , the first connecting portion 118 includes a first sub-portion 1181 and a second sub-portion 1182 . The first sub-portion 1181 is parallel to the first direction x, and the second sub-portion 1182 is parallel to the second direction y. The orthographic projections of the first sub-portion 1181 and the data line 115 on the substrate 111 do not overlap. On the one hand, configuring the first connecting portion 118 as two portions extending along the first direction x and the second direction y facilitates wiring. On the other hand, the presence of the first connecting portion 118 increases light reflection. By designing the first connecting portion 118 as the first sub-portion 1181 and the second sub-portion 1182 , the distribution range of the first connecting portion 118 can be increased, thereby improving display uniformity in the display area AA.

[0052] In the above embodiment, the first connection portion 118 is located in the third conductive layer 116 or the fourth conductive layer 117 , and the first connection portion 118 and the data line 115 are disposed in different layers.

[0053] In the above embodiment, as shown in Figures 6 and 7, since the third conductive layer 116 is disposed on the same layer as the fifth metal layer 123, and the fourth conductive layer 117 is disposed on the same layer as the sixth metal layer 124, the first connector 118 is formed in the fifth metal layer 123 or the sixth metal layer 124, and is disposed on a different layer from the data line 115. Specifically, Figure 7 illustrates a case where the data line 115 is located in the fifth metal layer 123 and the first connector 118 is located in the sixth metal layer 124. Alternatively, the data line 115 may be located in the sixth metal layer 124, and the first connector 118 may be located in the fifth metal layer 123, although this is not illustrated in the figures. Since the first connector 118 is used to connect the data line 115 and the fan-out line 114, and the first connector 118 is at least partially located in the display area AA, and the first connector 118 connects the data line 115 located in the edge area AA2 and the fan-out line 114 located opposite the middle area AA1, the first connector 118 extends from the edge area AA2 to the middle area AA1 within the display area AA. Therefore, the first connection portion 118 and the data line 115 need to be provided in different layers, otherwise the first connection portion 118 will interfere with the data line 115 and cannot be insulated from the data line 115 .

[0054] Specifically, the first connecting portion 118 can be located on a different layer from the data lines 115, while each data line 115 is located on the same layer. The first connecting portion 118 and the data lines 115 are connected via vias. The first subsection 1181 extends in the same direction as the data lines 115. However, due to the limited space between adjacent data lines 115, placing the first subsection 1181 on the same layer as the data lines 115 would result in a smaller spacing between the first subsection 1181 and the adjacent data lines 115. This would increase wiring complexity and cause mutual interference between the two. Therefore, in the above embodiment, the first subsection 1181 and the data lines 115 are located on different layers, and the orthographic projections of the first subsection 1181 and the data lines 115 on the substrate 111 do not overlap. This avoids the negative impact of the smaller spacing on wiring and reduces signal interference between the two. The second subsection 1182 intersects the extension direction of the data lines 115 and cannot be located on the same layer. Therefore, the second subsection 1182 and the data lines 115 are located on different layers. The first sub-portion 1181 and the second sub-portion 1182 are located in the same layer, which can reduce the number of film layers in the display panel 1 and reduce the thickness of the display panel 1 .

[0055] In a feasible implementation, as shown in FIG6 , the orthographic projections of the first trace 1141 and the second trace 1142 on the substrate 111 do not overlap.

[0056] In the above embodiment, the first routing line 1141 and the second routing line 1142 are arranged in different conductive layers, and the wiring space is increased within the spatial scope to reduce the wiring space requirement in each plane, so that the fan-out lines 114 can all be arranged in the area opposite to the middle area AA1 of the display area AA, without occupying the arc angle space, and helping to achieve a narrow frame; at the same time, the orthographic projections of the first routing line 1141 and the second routing line 1142 on the substrate 111 do not overlap, that is, the orthographic projections of the first routing line 1141 and the second routing line 1142 on the substrate 111 are alternately arranged, thereby reducing the mutual interference between the first routing line 1141 and the second routing line 1142 in the direction perpendicular to the substrate 111. At the same time, the orthographic projections of the first routing line 1141 and the second routing line 1142 on the substrate 111 are arranged to be alternately arranged, which helps to improve the space utilization of the wiring.

[0057] In a feasible implementation, as shown in FIG6 , at least a portion of the fan-out lines 114 are connected to the data lines 115 via the second connecting portion 129 .

[0058] In the above embodiment, as shown in Figures 8 and 9, the substrate 11 also includes a fifth conductive layer 127 and a sixth conductive layer 128 stacked with the first conductive layer 112 and the second conductive layer 113 and insulated from each other, the second connecting portion 129 is located in the fifth conductive layer 127 or the sixth conductive layer 128, the second connecting portion 129 and the first routing 1141 and the second routing 1142 are arranged in different layers, and the second connecting portion 129 is connected to the fan-out line 114 through a via.

[0059] Specifically, the first conductive layer 112 is provided in the same layer as one of the first metal layer 119, the second metal layer 120, and the third metal layer 121, and the second conductive layer 113 is provided in the same layer as the other of the first metal layer 119, the second metal layer 120, and the third metal layer 121. That is, the first trace 1141 is provided in the same layer as one of the first metal layer 119, the second metal layer 120, and the third metal layer 121, and the second trace 1142 is provided in the same layer as the other of the first metal layer 119, the second metal layer 120, and the third metal layer 121. Specifically, both the first trace 1141 and the second trace 1142 are connected to the data line 115 via the second connection portion 129. The second connection portion 129 is provided in a different layer from the fan-out line 114, thereby preventing interference with the first trace 1141 and the second trace 1142.

[0060] Specifically, as shown in FIG8 and FIG9 , the fifth conductive layer 127 and the third metal layer 121 are located in the same layer, and the sixth conductive layer 128 and the fourth metal layer 122 are located in the same layer.

[0061] In a feasible embodiment, as shown in Figures 8 and 9, the first routing 1141 is arranged on the same layer as the first metal layer 119 and the second metal layer 120, and the second routing 1142 is arranged on the same layer as the other of the first metal layer 119 and the second metal layer 120. At this time, the second connecting portion 129 can be arranged on the fifth conductive layer 127 or the sixth conductive layer 128, that is, on the same layer as the third metal layer 121 or the fourth metal layer 122, to prevent the second connecting portion 129 from interfering with the wiring of the fan-out line 114.

[0062] In another feasible embodiment, the first trace 1141 is disposed on the same layer as one of the first metal layer 119, the second metal layer 120, and the third metal layer 121, and the second trace 1142 is disposed on the same layer as another of the first metal layer 119, the second metal layer 120, and the third metal layer 121. In this case, the second connection portion 129 can be disposed on the sixth conductive layer 128, that is, on the same layer as the fourth metal layer 122, to prevent interference between the second connection portion 129 and the routing of the fan-out line 114. In the above embodiment, the fifth conductive layer 127 is spaced a large distance from the first conductive layer 112 and the second conductive layer 113 in a direction perpendicular to the substrate 111, and the sixth conductive layer 128 is spaced a large distance from the first conductive layer 112 and the second conductive layer 113 in a direction perpendicular to the substrate 111, thereby reducing interference between the second connection portion 129 and the fan-out line 114 located therebelow.

[0063] In a feasible embodiment, as shown in Figure 6, the orthographic projections of the first routing line 1141 and the second routing line 1142 on the substrate 111 are alternately arranged along the second direction y, the fan-out area NA includes a first area NA1 and a second area NA2, the second area NA2 is located on both sides of the first area NA1 along the second direction y, and the fan-out line 114 includes an intermediate fan-out line 1143 and an edge fan-out line 1144, the intermediate fan-out line 1143 is used to connect to the light-emitting unit 101 in the intermediate area AA1, the edge fan-out line 1144 is used to connect to the light-emitting unit 101 in the edge area AA2, and the edge fan-out line 1144 is located in the second area NA2.

[0064] In the above embodiment, the fan-out line 114 includes an intermediate fan-out line 1143 for connecting to the light-emitting unit 101 in the intermediate area AA1 and an edge fan-out line 1144 for connecting to the light-emitting unit 101 in the edge area AA2, wherein part of the intermediate fan-out line 1143 can extend along the first direction x, and the edge fan-out line 1144 and another part of the intermediate fan-out line 1143 can extend along a direction intersecting the first direction x and the second direction y.

[0065] In the above embodiment, the fan-out area NA includes a first region NA1 and a second region NA2 . The second region NA2 is located on both sides of the first region NA1 along the second direction y, and the edge fan-out line 1144 is located in the second region NA2 .

[0066] By setting the edge fan-out line 1144 in the two edge areas of the fan-out area NA along the second direction y to achieve connection with the light-emitting unit 101 in the edge area AA2, compared with connecting the fan-out line 114 at the middle position of the fan-out area NA to the light-emitting unit 101 in the edge area AA2, the length of the edge fan-out line 1144 can be saved, thereby reducing resistance and power consumption, while facilitating wiring.

[0067] In the above embodiment, at least some of the three fan-out lines 114 that are adjacent along the second direction y include an edge fan-out line 1144, where "adjacent along the second direction y" means that the orthographic projections of the fan-out lines 114 on the substrate 111 are adjacent along the second direction y. This arrangement allows the edge fan-out line 1144 to be disposed within the second area NA2, while simultaneously connecting the first light-emitting element group 102 within the edge area AA2 to the first trace 1141 and the second light-emitting element group 103 to the second trace 1142.

[0068] In a feasible implementation, as shown in FIG10 , the substrate 11 further includes a compensation resistor 130 , and the middle fan-out lines 1143 are connected to the compensation resistor 130 in a one-to-one correspondence.

[0069] Because edge fan-out lines 1144 need to be connected to data lines 115 via first connectors 118, the resistance in the circuit corresponding to edge fan-out lines 1144 increases. This can cause differences in the data signals received by light-emitting units 101 in edge area AA2 and those in middle area AA1 of display panel 1, resulting in uneven display. By connecting compensation resistors 130 to middle fan-out lines 1143, which connect to data lines 115 in middle area AA1, these differences in display quality can be reduced, further improving display quality.

[0070] The present application also provides a display device 2 , as shown in FIG11 , which includes any one of the display panels 1 provided in the above embodiments of the present application.

[0071] Since the display device 2 provided in the present application includes the display panel 1 of any of the above embodiments, the display device 2 provided in the present application has the beneficial effects of the display panel 1 of any of the above embodiments, which will not be described in detail here.

[0072] The display device 2 in the embodiment of the present application includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles, and other devices with display functions.

[0073] While the embodiments described above are not exhaustive, they do not limit the invention to specific embodiments. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, comprising a display area and a fan-out area, the display panel comprising: A substrate, the substrate comprising a substrate and a first conductive layer and a second conductive layer stacked on the substrate, a fan-out line formed in the substrate, the fan-out line being located in the fan-out area, the fan-out line comprising a first routing line and a second routing line, the first routing line being located in the first conductive layer, and the second routing line being located in the second conductive layer; A light-emitting layer, comprising a plurality of light-emitting units formed on one side of the substrate, the light-emitting layer comprising a first light-emitting unit group and a second light-emitting unit group, the first light-emitting unit group comprising a plurality of the light-emitting units arranged along a first direction, the second light-emitting unit group comprising a plurality of the light-emitting units arranged along the first direction, the light-emitting units in the first light-emitting unit group and the second light-emitting unit group have different colors, the first light-emitting unit group and the second light-emitting unit group are alternately arranged along a second direction, and the first direction intersects with the second direction; A driver chip, located in the fan-out area; The first wiring is used to electrically connect the light-emitting units in the first light-emitting unit group with the driving chip, and the second wiring is used to electrically connect the light-emitting units in the second light-emitting unit group with the driving chip.

2. The display panel according to claim 1, wherein: The substrate also includes a plurality of data lines, the plurality of data lines include a first data line and a second data line, the first data line is electrically connected to the light-emitting unit in the first light-emitting unit group, the second data line is electrically connected to the light-emitting unit in the second light-emitting unit group, the first routing line corresponds one-to-one to the first data line and is electrically connected, and the second routing line corresponds one-to-one to the second data line and is electrically connected.

3. The display panel according to claim 2, wherein: The substrate comprises a third conductive layer and a fourth conductive layer which are located on a side of the second conductive layer away from the substrate and are stacked, and the data line is located in the third conductive layer or in the fourth conductive layer.

4. The display panel according to claim 3, wherein: The display area includes a middle area and edge areas located on both sides of the middle area along the second direction. Along the first direction, the orthographic projection of the fan-out line in the display area is located in the middle area. The first data line and the fan-out line, and the second data line and the fan-out line in the edge area are respectively connected through a first connecting portion, and the first connecting portion is at least partially located in the display area.

5. The display panel according to claim 4, wherein: The first connection portion is located in the third conductive layer or in the fourth conductive layer, and the first connection portion and the data line are arranged in a different layer.

6. The display panel according to claim 5, wherein: At least part of the fan-out lines are connected to the data lines through a second connecting portion.

7. The display panel according to claim 5, wherein: The first connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is parallel to the first direction, the second sub-portion is parallel to the second direction, and the orthographic projections of the first sub-portion and the data line on the substrate have no overlap.

8. The display panel according to claim 7, wherein: The orthographic projections of the first routing line and the second routing line on the substrate do not overlap.

9. The display panel according to claim 7, wherein: An extending direction of the first section is the same as an extending direction of the data line.

10. The display panel according to claim 7, wherein: The second section and the data line are arranged in different layers.

11. The display panel according to claim 7, wherein: The first subdivision and the second subdivision are located on the same floor.

12. The display panel according to claim 6, wherein: The substrate comprises a substrate and a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer and a sixth metal layer stacked in a direction away from the substrate, and the substrate comprises a transistor and a capacitor, wherein: The first metal layer is located between the substrate and the transistor; The second metal layer is used to form the gate of the transistor and the first plate of the capacitor; The third metal layer is used to form the second electrode plate of the capacitor; The fourth metal layer is used to form the source and drain of the transistor; The fifth metal layer and the sixth metal layer are used to form the data line.

13. The display panel according to claim 12, wherein: The first conductive layer is disposed in the same layer as one of the first metal layer, the second metal layer and the third metal layer, and the second conductive layer is disposed in the same layer as the other one of the first metal layer, the second metal layer and the third metal layer.

14. The display panel according to claim 13, wherein: The third conductive layer is disposed on the same layer as the fifth metal layer, and the fourth conductive layer is disposed on the same layer as the sixth metal layer.

15. The display panel according to claim 14, wherein: The substrate also includes a fifth conductive layer and a sixth conductive layer stacked with the first conductive layer and the second conductive layer and insulated from each other, the second connecting portion is located in the fifth conductive layer or the sixth conductive layer, the second connecting portion and the first routing line and the second routing line are arranged in a different layer, and the second connecting portion is connected to the fan-out line through a via.

16. The display panel according to claim 15, wherein: The fifth conductive layer and the third metal layer are located in the same layer, and the sixth conductive layer and the fourth metal layer are located in the same layer.

17. The display panel according to claim 6, wherein: The orthographic projections of the first routing line and the second routing line on the substrate are alternately arranged along the second direction, the fan-out area includes a first area and a second area, the second area is located on both sides of the first area along the second direction, the fan-out line includes a middle fan-out line and an edge fan-out line, the middle fan-out line is used to connect to the light-emitting unit in the middle area, the edge fan-out line is used to connect to the light-emitting unit in the edge area, and the edge fan-out line is located in the second area.

18. The display panel according to claim 17, wherein: The substrate further includes compensation resistors, and the intermediate fan-out lines are connected to the compensation resistors in a one-to-one correspondence.

19. The display panel according to claim 1, wherein: One of the first light emitting unit group and the second light emitting unit group includes at least two colors of the light emitting units, and the other includes at least one color of the light emitting units.

20. A display device comprising the display panel according to any one of claims 1 to 19.

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