Display substrate, display panel, and display device

Abstract

A display substrate, a display panel, and a display device. The display substrate comprises: a first base substrate (1), the first base substrate (1) comprising: a display area (101) and a peripheral area (102) surrounding the display area (101), and the peripheral area (102) comprising a first peripheral area (1021) located on one side of the display area (101) in a first direction; a plurality of first binding terminals (2), located in the first peripheral area (1021), the plurality of first binding terminals (2) being configured to bind to a driving chip; and a plurality of test terminals (3), in the first peripheral area (1021), the plurality of test terminals (3) and the plurality of first binding terminals (2) being located on the same side of the first base substrate (1). The orthographic projection of the plurality of test terminals (3) on the first base substrate (1) is located on the side, distant from the display area (101), of the orthographic projection of the plurality of first binding terminals (2) on the first base substrate (1).

Description

Display substrate, display panel, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on June 29, 2023, with application number 202310786042.1 and invention name "Display substrate, display panel and display device", the entire content of which is incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0004] During the production process of display products, before binding the driver chip and other structures, the produced panel needs to be tested by electrical means to detect defects in a timely manner to avoid defective products flowing into the subsequent processes and causing waste.

[0005] Prior art testing of display products requires multiple test terminals, each located on either side of the driver chip's binding area. However, for high-resolution, narrow-frame display products, the driver chip's binding area is relatively wide, leaving little free space on either side. If test terminals were still placed on either side of the driver chip's binding area, the narrow-frame requirement would not be met.

[0006] Summary of the Invention

[0007] Embodiments of the present disclosure provide a display substrate, a display panel, and a display device, which are used to realize the arrangement of test terminals without increasing the size of the peripheral area.

[0008] An embodiment of the present disclosure provides a display substrate, the display substrate comprising:

[0009] The first base substrate comprises: a display area and a peripheral area surrounding the display area; the peripheral area comprises a first peripheral area located on one side of the display area in a first direction;

[0010] A plurality of first binding terminals are located in the first peripheral area; the plurality of first binding terminals are used to bind to the driver chip;

[0011] The plurality of test terminals are located on the same side of the first base substrate as the plurality of first binding terminals in the first peripheral area; the orthographic projections of the plurality of test terminals on the first base substrate are located on a side of the orthographic projections of the plurality of first binding terminals on the first base substrate away from the display area.

[0012] In some embodiments, the display substrate further comprises:

[0013] A plurality of second binding terminals are located on the same side of the first base substrate as the plurality of first binding terminals in the first peripheral area; the plurality of second binding terminals are used to bind to the flexible circuit board, and at least some of the second binding terminals are electrically connected to at least some of the first binding terminals; the orthographic projections of the plurality of second binding terminals on the first base substrate are located on a side of the orthographic projections of the plurality of first binding terminals on the first base substrate away from the display area, and in a second direction, the orthographic projections of the plurality of test terminals on the first base substrate are located on one side of the orthographic projections of the plurality of second binding terminals on the first base substrate, and the second direction intersects with the first direction.

[0014] In some embodiments, the plurality of first binding terminals include:

[0015] a plurality of input terminals; at least some of the plurality of input terminals are arranged along the second direction;

[0016] The plurality of test terminals are located on a side of the plurality of input terminals away from the display area;

[0017] The display substrate also includes:

[0018] A plurality of test signal lines are located in a first peripheral area; each of the plurality of test signal lines is electrically connected to a test terminal; the test signal line comprises a first portion, an orthographic projection of the first portion on the first substrate substrate and an orthographic projection of the input terminal on the first substrate substrate do not overlap with each other, and an orthographic projection of the first portion between the orthographic projection of the first substrate substrate and an adjacent input terminal on the first substrate substrate overlaps with each other.

[0019] In some embodiments, the plurality of first binding terminals further include:

[0020] The plurality of output terminals are located on a side of the plurality of input terminals facing the display area; and the test signal lines are electrically connected to the output terminals.

[0021] In some embodiments, the plurality of input terminals include: a plurality of first input terminals, and a plurality of first dummy terminals located on one side of the plurality of first input terminals in a direction in which the plurality of second binding terminals point to one side of the plurality of test terminals;

[0022] The plurality of first input terminals are electrically connected to at least some of the second binding terminals among the plurality of second binding terminals;

[0023] The orthographic projection of the first portion on the first base substrate and the area between the adjacent first input terminal do not overlap with each other, and the orthographic projection of the first portion on the first base substrate and the area between the adjacent first dummy terminal overlap with each other.

[0024] In some embodiments, the first portion includes a plurality of first sub-signal lines arranged along the second direction.

[0025] In some embodiments, the test signal line further includes: a second portion and a third portion respectively connected to both ends of the first portion in the extending direction; the second portion is located on a side of the first portion facing the display area, and the third portion is located on a side of the first portion away from the display area;

[0026] In the second direction, the width of the first sub-signal line is smaller than the width of the second portion connected to the first portion, and the width of the first sub-signal line is smaller than the width of the third portion connected to the first portion.

[0027] In some embodiments, the edge of at least the first sub-signal line extending along the first direction and the edge of the second part extending along the first direction are located in the same straight line, and the edge of at least one first sub-signal line extending along the first direction and the edge of the third part extending along the first direction are located in the same straight line.

[0028] In some embodiments, the plurality of test terminals are sequentially arranged along the second direction;

[0029] The first part of the plurality of test signal lines is sequentially arranged along the second direction, the second part of the plurality of test signal lines is sequentially arranged along the second direction, and the third part of the plurality of test signal lines is sequentially arranged along the second direction.

[0030] In some embodiments, the display substrate further comprises:

[0031] A plurality of transistors are located on the same side of a first substrate as the plurality of first binding terminals in a first peripheral region; the orthographic projections of the plurality of transistors on the first substrate are located between the orthographic projections of the plurality of output terminals on the first substrate and the orthographic projections of the plurality of input terminals on the first substrate; each of the plurality of transistors includes: a control electrode, a first electrode, and a second electrode; the plurality of transistors include: a plurality of first transistors, and a plurality of second transistors located on at least one side of the plurality of first transistors in a second direction;

[0032] The plurality of output terminals include: a plurality of first output terminals, and a plurality of second output terminals located at least on one side of the plurality of first output terminals in the second direction; the first electrode of the first transistor is electrically connected to the first output terminal, and the first electrode of the second transistor is electrically connected to the second output terminal;

[0033] The plurality of test signal lines include: a control signal line, a plurality of first signal lines, and at least one second signal line;

[0034] The plurality of test terminals include: a control terminal, a plurality of first test terminals, and a second test terminal;

[0035] The control terminal is electrically connected to the control electrodes of multiple transistors through a control signal line; the first test terminal is electrically connected to the second electrodes of some first transistors through a first signal line; the second test terminal is electrically connected to the second electrodes of at least some second transistors through a second signal line.

[0036] In some embodiments, in the second direction, the control terminal is located on a side of the remaining test terminals away from the plurality of second binding terminals.

[0037] In some embodiments, the second test terminal includes at least one sub-test terminal; in the second direction, the at least one sub-test terminal is located between the multiple first test terminals and the control terminal, or the at least one sub-test terminal is located on the side of the multiple first test terminals away from the control terminal.

[0038] In some embodiments, the second test terminals include: a first type of second test terminal located between the plurality of first test terminals and the control terminal, and a second type of second test terminal located on a side of the plurality of first test terminals facing away from the control terminal;

[0039] The plurality of second transistors are divided into: a first group located on one side of the plurality of first transistors in a direction in which the plurality of first test terminals point to the first type of second test terminals, and a second group located on one side of the plurality of first transistors in a direction in which the plurality of first test terminals point to the second type of second test terminals;

[0040] The plurality of second output terminals are divided into: a third group located on one side of the plurality of first output terminals in a direction in which the plurality of first test terminals point to the first type of second test terminals, and a fourth group located on one side of the plurality of first output terminals in a direction in which the plurality of first test terminals point to the second type of second test terminals; the second output terminals in the third group are electrically connected to the second transistors of the first group, and the second output terminals in the fourth group are electrically connected to the second transistors of the second group;

[0041] The first type second test terminal is electrically connected to the second pole of the first group through the second signal line, and the second type second test terminal is electrically connected to the second pole of the second group through the second signal line.

[0042] In some embodiments, the test signal line further includes a fourth portion electrically connected to the second portion;

[0043] At least a portion of the fourth portion extends along the second direction, and an orthographic projection of the fourth portion on the first substrate is located between an orthographic projection of the plurality of output terminals on the first substrate and an orthographic projection of the plurality of input terminals on the first substrate;

[0044] The fourth portion of the control signal line is electrically connected to the control electrodes of the plurality of transistors, the fourth portion of the first signal line is electrically connected to the second electrode of the first transistor, and the fourth portion of the second signal line is electrically connected to the second electrode of the second transistor;

[0045] The fourth portion of the first signal line is located on a side of the fourth portion of the control signal line away from the display area, and the fourth portion of the second signal line is located on a side of the fourth portion of the control signal line away from the display area.

[0046] In some embodiments, the second test terminal includes: a first type second test terminal and a second type second test terminal;

[0047] The second signal lines include: a first type of second signal line and a second type of second signal line;

[0048] The fourth portion of the first-type second signal line electrically connected to the first-type second test terminal is located between the fourth portion of the control signal line and the fourth portion of the multiple first signal lines, and the fourth portion of the second-type second signal line electrically connected to the second-type second test terminal is located on the side of the fourth portion of the multiple first signal lines away from the fourth portion of the control signal line.

[0049] In some embodiments, the control signal line further includes: a fifth portion electrically connected to the fourth portion at an end of the fourth portion facing away from the second portion;

[0050] The plurality of first input terminals include: a first ground level signal input terminal; and a fifth portion electrically connected to the first ground level signal input terminal.

[0051] In some embodiments, the peripheral region further includes second peripheral regions located on both sides of the display region in the second direction; and the display substrate further includes:

[0052] A plurality of sub-pixel units are located on the same side of the first base substrate as the plurality of first binding terminals in the display area; the plurality of sub-pixel units include a plurality of sub-pixel units having different light emission colors; the number of the first test signal lines is equal to the number of the sub-pixel units;

[0053] A plurality of scan lines are electrically connected to the plurality of sub-pixel units and extend from the display area to the second peripheral area; the plurality of scan lines are arranged along the first direction and extend along the second direction;

[0054] a plurality of data lines electrically connected to the plurality of sub-pixel units, extending from the display area to the peripheral area; the plurality of data lines are arranged along the second direction and extend along the first direction; each of the plurality of data lines is electrically connected to the first output terminal;

[0055] A plurality of first connecting leads extend from the first peripheral area to the second peripheral area; two ends of each of the plurality of first connecting leads are electrically connected to the second output terminal and the scan line respectively.

[0056] In some embodiments, the display substrate further includes: a common electrode, and a common electrode line electrically connected to the common electrode;

[0057] The first peripheral area includes a first binding area and a second binding area located in the first binding area away from the display area, the orthographic projections of the plurality of first binding terminals on the first base substrate and the orthographic projections of the plurality of transistors on the first base substrate fall into the first binding area, and the orthographic projections of the plurality of second binding terminals on the first base substrate fall into the second binding area;

[0058] In the first peripheral area, the orthographic projection of the common electrode line on the first base substrate extends through the first binding area to the second binding area, and the orthographic projection of the common electrode line on the first base substrate does not overlap with the orthographic projection of the first binding terminal on the first base substrate.

[0059] In some embodiments, the plurality of input terminals include a plurality of first dummy terminals and a plurality of first input terminals; the common electrode line includes: a first common electrode line and a second common electrode line;

[0060] In the first peripheral area, the first common electrode line is located on one side of the plurality of data lines in a direction in which the plurality of second binding terminals point to the plurality of test terminals when an orthographic projection of the first base substrate is formed, and the second common electrode line is located on the other side of the plurality of data lines in a direction in which the plurality of test terminals point to the plurality of second binding terminals when an orthographic projection of the first base substrate is formed.

[0061] The first common electrode line includes a sixth portion, wherein an area between an orthographic projection of the sixth portion on the first substrate and an adjacent first dummy terminal overlaps with an orthographic projection of the sixth portion on the first substrate, and the orthographic projection of the sixth portion on the first substrate is located between an orthographic projection of the first portions of the plurality of test signal lines on the first substrate and an orthographic projection of the plurality of first input terminals on the first substrate;

[0062] The second common electrode line includes a seventh portion. In the second direction, the orthographic projection of the seventh portion on the first base substrate is located on a side of the orthographic projections of the plurality of first input terminals on the first base substrate away from the orthographic projections of the plurality of first dummy terminals on the first base substrate.

[0063] In some embodiments, the sixth portion includes a plurality of first sub-common electrode lines arranged along the second direction.

[0064] In some embodiments, the first common electrode line further includes an eighth portion electrically connected to the sixth portion on a side of the sixth portion close to the display area;

[0065] An orthographic projection of the eighth portion on the first substrate overlaps an orthographic projection of at least a portion of the fourth portion of the test signal line on the first substrate, and the eighth portion and at least a portion of the fourth portion of the test signal line are located on different layers;

[0066] The second common electrode line further includes a ninth portion electrically connected to the seventh portion at a side of the seventh portion close to the display area;

[0067] An orthographic projection of the ninth portion on the first substrate overlaps with an orthographic projection of at least a portion of the fourth portion of the test signal line on the first substrate, and the ninth portion and at least a portion of the fourth portion of the test signal line are located in different layers.

[0068] In some embodiments, the plurality of second output terminals include a third group and a fourth group;

[0069] The plurality of first connecting leads are divided into a fifth group and a sixth group extending to different second peripheral regions; the first connecting leads in the fifth group are electrically connected to the second output terminals in the third group, and the first connecting leads in the sixth group are electrically connected to the second output terminals in the fourth group;

[0070] In the first peripheral area, the orthographic projection of the first common electrode line on the first substrate is located between the orthographic projection of the fifth group on the first substrate and the orthographic projection of the multiple data lines on the first substrate, and the orthographic projection of the second common electrode line on the first substrate is located between the orthographic projection of the sixth group on the first substrate and the orthographic projection of the multiple data lines on the first substrate.

[0071] In some embodiments, the display substrate further includes a first electrostatic unit electrically connected to the test terminal.

[0072] A display panel provided by an embodiment of the present disclosure includes the display substrate provided by an embodiment of the present disclosure.

[0073] In some embodiments, it further includes:

[0074] an opposite substrate, arranged opposite to the display substrate;

[0075] The liquid crystal layer is located between the opposite substrate and the display substrate.

[0076] A display device provided by an embodiment of the present disclosure includes the display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0078] FIG1 is a schematic structural diagram of a display product provided by the related art;

[0079] FIG2 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0080] FIG3 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0081] FIG4 is an enlarged schematic diagram of area A in FIG3 provided by an embodiment of the present disclosure;

[0082] FIG5 is an enlarged schematic diagram of area B in FIG4 provided by an embodiment of the present disclosure;

[0083] FIG6 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0084] FIG7 is an enlarged schematic diagram of area C in FIG3 provided by an embodiment of the present disclosure;

[0085] FIG8 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0086] FIG9 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0087] FIG10 is an enlarged schematic diagram of the D area in FIG9 provided by an embodiment of the present disclosure;

[0088] FIG11 is an enlarged schematic diagram of the E region in FIG9 provided by an embodiment of the present disclosure;

[0089] FIG12 is an enlarged schematic diagram of the G area in FIG10 provided by an embodiment of the present disclosure;

[0090] FIG13 is an enlarged schematic diagram of the F area in FIG9 provided by an embodiment of the present disclosure;

[0091] FIG14 is a schematic structural diagram of a first electrostatic unit provided in an embodiment of the present disclosure;

[0092] FIG15 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0093] FIG16 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0094] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0095] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0096] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0097] In the related art, after part of the manufacturing process of a display product is completed, before the driver chip and the flexible circuit board are bonded, it is necessary to load an electrical signal to the display product and perform a lighting test to determine whether there is any display abnormality in the display area. Typically, as shown in FIG1 , the flexible circuit board FPC, the driver chip IC, and the test terminals are all located in the peripheral area 102 below the display area 101. The flexible circuit board FPC is located directly below the driver chip IC, and the test terminals for testing are located in the areas ET1 and ET2 on both sides of the driver chip IC. For display products with low resolution, for example, the width of the driver chip IC in the second direction X is 15.36 millimeters (mm), which is approximately 1 / 2 of the width of the display panel in the second direction X. There is sufficient space on both sides of the driver chip to set the test terminals. Alternatively, the width of the driver chip in the second direction X is 10.02 mm, which is approximately 2 / 3 of the width of the display panel in the second direction X. The test terminals can be designed in double rows on both sides of the driver chip, that is, there is still space to set the test terminals on both sides of the driver chip. However, for narrow-frame display products with higher resolution, in one solution, the width of the IC in the second direction X is 22.742 mm, and the width of the display panel in the second direction X is 25.1 mm. That is, the width of the driver chip in the second direction X is not much different from the width of the display panel in the second direction X. The remaining space on both sides of the driver chip cannot be used to set test terminals. If test terminals are still set on both sides of the driver chip, the width of the peripheral area in the second direction X will inevitably need to be increased, affecting the user experience.

[0098] An embodiment of the present disclosure provides a display substrate, as shown in FIG2 , comprising:

[0099] The first base substrate 1 includes: a display area 101 and a peripheral area 102 surrounding the display area 101; the peripheral area 102 includes a first peripheral area 1021 located on one side of the display area 101 in the first direction Y;

[0100] A plurality of first binding terminals 2 are located in the first peripheral area 1021 ; the plurality of first binding terminals 2 are used for binding with the driver chip;

[0101] Multiple test terminals 3 are located on the same side of the first base substrate 1 as the multiple first binding terminals 2 in the first peripheral area 1021; the orthographic projections of the multiple test terminals 3 on the first base substrate 1 are located on the side of the orthographic projections of the multiple first binding terminals 2 on the first base substrate 1 away from the display area 101.

[0102] In the display substrate provided by the embodiment of the present disclosure, the test terminal is arranged on a side of the multiple first binding terminals bound to the driver chip away from the display area, thereby avoiding the test terminals being located on both sides of the multiple first binding terminals in a second direction intersecting the first direction, resulting in an increase in the width of the peripheral area in the second direction, thereby avoiding affecting the user experience.

[0103] In some embodiments, as shown in FIG2 , the display substrate further includes:

[0104] A plurality of second binding terminals 4 are located on the same side of the first base substrate 1 as the plurality of first binding terminals 2 in the first peripheral area 1021; the plurality of second binding terminals 4 are used to bind to the flexible circuit board, and at least some of the second binding terminals 4 are electrically connected to at least some of the first binding terminals 2; the orthographic projections of the plurality of second binding terminals 4 on the first base substrate 1 are located on a side of the orthographic projections of the plurality of first binding terminals 2 on the first base substrate 1 away from the display area 101, and in the second direction X, the orthographic projections of the plurality of test terminals 3 on the first base substrate 1 are located on one side of the orthographic projections of the plurality of second binding terminals 4 on the first base substrate 1, and the second direction X intersects with the first direction Y.

[0105] In the display substrate provided by the embodiment of the present disclosure, multiple test terminals and multiple second binding terminals bound to the flexible circuit board are all located on the side of the multiple first binding terminals away from the display area, and the multiple test terminals are located on one side of the multiple second binding terminals in the second direction, so that the setting position of the test terminals will not affect the electrical connection between the second binding terminals and the first binding terminals.

[0106] It should be noted that in Figure 2 , the first direction Y is perpendicular to the second direction X, with the second direction X being the horizontal direction in the figure and the first direction Y being the vertical direction. Furthermore, Figure 2 illustrates the example where the orthographic projections of the multiple test terminals 3 on the first base substrate 1 are located to the left of the orthographic projections of the multiple second binding terminals 4 on the first base substrate 1. In a specific implementation, the orthographic projections of the multiple test terminals on the first base substrate may also be located to the right of the orthographic projections of the multiple second binding terminals on the first base substrate.

[0107] In some embodiments, as shown in Figure 2, the first peripheral area 1021 includes: a first binding area 11 and a second binding area 12 located in the first binding area 11 away from the display area 101, the orthographic projection of multiple first binding terminals 2 on the first base substrate 1 falls into the first binding area 11, and the orthographic projection of multiple second binding terminals 4 on the first base substrate 1 falls into the second binding area 12; the first peripheral area 1021 also includes a test terminal area 13; the first binding area 11 is the area covered by the orthographic projection of the driver chip on the first base substrate 1, and the second binding area 12 is the area covered by the orthographic projection of the flexible circuit board on the first base substrate 1; multiple test terminals 3 are located in the test terminal area 13; the driver chip is bound to the multiple first binding terminals 2 in the first binding area 11, and the flexible circuit board is bound to the multiple second binding terminals 4 in the second binding area 12.

[0108] In some embodiments, as shown in Figure 3, the width h10 of the first binding area 11 in the second direction X is greater than the width h12 of the second binding area 12 in the second direction X, the width h10 of the first binding area 11 in the second direction X is greater than the width h13 of the multiple test terminals 3 in the test terminal area 13 in the second direction X, and the width h10 of the first binding area 11 in the second direction X is greater than the sum of the widths 2 of the second binding area 12 in the second direction X and the width h13 of the multiple test terminals 3 in the test terminal area 13 in the second direction X.

[0109] In a specific implementation, h10 is approximately 22 mm, the width of the first peripheral area in the second direction X is approximately 25 mm, h12 is approximately 15 mm, and h13 is approximately 3.5 mm.

[0110] In some embodiments, as shown in Figure 3, in the first direction Y, the distance from the first binding area 11 to the edge of the first peripheral area 102 away from the display area is h11, the width of the test terminal 3 is h14, and the width of the second binding area 12 is h15, h11 is greater than h14, and h11 is greater than h15.

[0111] In a specific implementation, h11 is approximately 1 mm, h14 is approximately 0.3 mm, and h15 is approximately 0.4 mm.

[0112] In specific implementation, the first binding area, i.e., the area covered by the orthographic projection of the driver chip on the first substrate, is usually rectangular, and the second binding area, i.e., the area covered by the orthographic projection of the flexible circuit board on the first substrate, is also usually rectangular. In the display substrate provided by the embodiment of the present disclosure, the center of the first binding area and the center of the second binding area are located on different straight lines in the first direction. That is, the area bound by the flexible circuit board is not directly opposite to the area bound by the driver chip. Compared with the situation where the center of the flexible circuit board is directly opposite to the center of the driver chip, i.e., the center line connecting the two is parallel to the first direction, the display substrate provided by the embodiment of the present application is equivalent to moving the area bound by the flexible circuit board toward the edge in the second direction, thereby providing sufficient wiring space for the test terminal.

[0113] In some embodiments, as shown in FIG2 , the plurality of first binding terminals 2 include:

[0114] A plurality of input terminals 201; at least some of the input terminals 201 are arranged along the second direction X;

[0115] A plurality of output terminals 202 are located on a side of the plurality of input terminals 201 facing the display area 101;

[0116] The plurality of test terminals 3 are located on a side of the plurality of input terminals 201 facing away from the display area 101 .

[0117] In a specific implementation, the test terminal is electrically connected to the output terminal.

[0118] In some embodiments, as shown in FIG3 , FIG4 , and FIG5 , the display substrate further includes:

[0119] A plurality of test signal lines 5 are located in a first peripheral area; each of the plurality of test signal lines 5 is electrically connected to a test terminal 3; the test signal line 5 comprises: a first portion 501, wherein the orthographic projection of the first portion 501 on the first substrate 1 and the orthographic projection of the input terminal 201 on the first substrate 1 do not overlap with each other, and the orthographic projection of the first portion 501 on the first substrate 1 and the area between the orthographic projection of the adjacent input terminal 201 on the first substrate 1 have an overlapping orthographic projection on the first substrate 1; the test signal line 5 is electrically connected to the output terminal 202.

[0120] In the display substrate provided by the embodiments of the present disclosure, a test signal line is electrically connected to the output terminal and the test terminal, that is, the test signal line needs to extend from the first binding area to the test terminal area. The orthographic projection of the first portion of the test signal line on the first substrate substrate does not overlap with the orthographic projection of the input terminal on the first substrate substrate, and the orthographic projection of the first portion on the first substrate substrate and the area between the adjacent input terminals on the first substrate substrate do overlap, that is, the test signal line passes through the space between the adjacent input terminals to electrically connect to the test terminals, thereby preventing the test signal line from interfering with the input terminals.

[0121] In a specific implementation, the number of test signal lines is equal to the number of test terminals.

[0122] In some embodiments, the display substrate further comprises:

[0123] The plurality of sub-pixel units are located on the same side of the first base substrate in the display area as the plurality of first binding terminals.

[0124] In a specific implementation, at least part of the output terminals are electrically connected to the sub-pixel units arranged in the display area, so that the test terminals are electrically connected to the sub-pixel units through the test signal lines and the output terminals, so as to realize the lighting test of the sub-pixel units through the test terminals.

[0125] It should be noted that Figure 3 is a simple schematic diagram of a portion of the first peripheral area, Figure 4 is an enlarged structural schematic diagram of area A in Figure 3, and Figure 5 is an enlarged structural schematic diagram of area B in Figure 4.

[0126] In some embodiments, as shown in FIG2 and FIG3 , the plurality of input terminals 201 include: a plurality of first input terminals 2011 , and a plurality of first dummy terminals 2012 located on one side of the plurality of first input terminals 2011 in a direction in which the plurality of second binding terminals 4 point to one side of the plurality of test terminals 3 ;

[0127] The plurality of first input terminals 2011 are electrically connected to at least some of the second binding terminals 4 among the plurality of second binding terminals 4 .

[0128] It should be noted that the first dummy terminal does not need to be electrically connected to any conductive structure on the display substrate, but the first dummy terminal still needs to be bonded to the driver chip. The first dummy terminal can support the driver chip and balance the thickness of the structure in the first bonding area. Signals can also be provided to the driver chip from outside the display substrate through the first dummy terminal, or signals from the driver chip can be extracted through the first dummy terminal.

[0129] It should be noted that, as shown in FIG7 , in the area where the multiple first input terminals 2011 are provided, the multiple input terminals 2 may further include multiple second dummy terminals 27 , and at least some of the multiple second dummy terminals 27 may be located between two adjacent first input terminals 2011 . In a specific implementation, the second dummy terminals do not need to be electrically connected to any conductive structure of the display substrate, but the second dummy terminals still need to be bound to the driver chip. The second dummy terminals can support the driver chip and balance the thickness of the structure in the first binding area. Signals can also be provided to the driver chip from outside the display substrate via the second dummy terminals, or signals from the driver chip can be led out via the second dummy terminals.

[0130] It should be noted that FIG7 is an enlarged schematic diagram of area C in FIG3 .

[0131] In some embodiments, as shown in Figures 4 and 5, the orthographic projection of the first portion 501 on the first base substrate and the area between the adjacent first input terminal 2011 do not overlap with each other, and the orthographic projection of the first portion 501 on the first base substrate and the area between the adjacent first dummy terminal 2012 do overlap with each other.

[0132] In the display substrate provided by the embodiments of the present disclosure, a first portion of a test signal line passes through the area between adjacent first dummy terminals and is electrically connected to a test terminal located on a side of the plurality of first dummy terminals facing away from the display area. Because the first dummy terminals do not need to be electrically connected to any conductive structure on the display substrate, the first portion passing through the area between adjacent first dummy terminals does not interfere with other conductive structures. Furthermore, the first portion passes through the area between adjacent first dummy terminals rather than the area between adjacent first input terminals, thereby effectively utilizing the display substrate space while preventing interference from the test signal line on the first input terminals.

[0133] In some embodiments, as shown in FIG4 and FIG5 , the first portion 501 includes a plurality of first sub-signal lines 5011 arranged along the second direction X. That is, the orthographic projection of each first sub-signal line on the first base substrate 1 overlaps with the area between the adjacent first dummy terminal 2012 on the orthographic projection of the first base substrate 1 .

[0134] It should be noted that the test signal line extends from the first binding area through the area between the first dummy terminals to the test terminal area and connects to the test terminals. As shown in Figure 5, in the second direction X, the distance h1 between two adjacent first dummy terminals 2012 is approximately 20 microns. The width h2 of the first sub-signal line 5011 in the area between the two adjacent first dummy terminals 2012 is smaller than the distance h1 between the two adjacent first dummy terminals 2012. Therefore, the width h2 of the first sub-signal line 5011 is relatively small. Therefore, providing only one first sub-signal line results in a higher impedance in the first portion, affecting test signal transmission.

[0135] In the display substrate provided by the embodiment of the present disclosure, the first part of each test signal line includes multiple first sub-signal lines, thereby improving the electrical connection performance between the first part and the remaining parts, reducing the impedance of the test signal line, and avoiding affecting the test signal transmission.

[0136] In some embodiments, in the second direction X, the width h2 of the first sub-signal line in the region between two adjacent first dummy terminals is approximately 10 microns. This can prevent the first sub-signal line from being too close to the first dummy terminal, thereby preventing the driver chip from short-circuiting with the first sub-signal line when the driver chip is bound to the first dummy terminal.

[0137] In specific implementation, the number of the first sub-signal lines included in the first part can be selected according to actual needs. For example, it can be specifically set according to the width of the part connected to the first part in the second direction X.

[0138] In some embodiments, as shown in FIGS. 4 and 5, the test signal line 5 further includes: a second part 502 and a third part 503 respectively connected to two ends of the first part 501 in the extending direction; the second part 502 is located on the side of the first part 501 facing the display area 101, and the third part 503 is located on the side of the first part 501 away from the display area 101.

[0139] In specific implementation, as shown in FIG. 5, both the second part 502 and the third part 503 are single wirings. The second part 502, the third part 503, and the multiple first sub-signal lines 5011 enclose multiple opening areas 14, and the orthographic projection of the first dummy terminal 2012 on the first substrate 1 falls within the orthographic projection of the opening areas 14 on the first substrate 1.

[0140] In some embodiments, as shown in FIG. 5, in the second direction X, the width of the first sub-signal line 5011 is smaller than the width of the second part 502 at the connection with the first part 501, and the width of the first sub-signal line 5011 is smaller than the width of the third part 503 at the connection with the first part 501.

[0141] In some embodiments, as shown in FIG. 5, the edge 15 of at least one first sub-signal line 5011 extending along the first direction Y and the edge 16 of the second part 502 extending along the first direction Y are on the same straight line, and the edge 15 of at least one first sub-signal line 5011 extending along the first direction Y and the edge 17 of the third part 503 extending along the first direction Y are on the same straight line. Thus, the number of the first sub-signal lines connected to the second part and the third part can be set as much as possible, which is beneficial to reducing the impedance of the test signal line.

[0142] In some embodiments, as shown in FIG. 5, in the second direction X, the width h6 of the area where the first part 501 is located is not greater than the width h7 of the second part 502, and the width h6 of the area where the first part 501 is located is not greater than the width h8 of the third part 503. For each test signal line 5, in the second direction X, the width h6 of the area where the first part 501 is located is equal to the width h7 of the second part 502, and / or, the width h6 of the area where the first part 501 is located is equal to the width h8 of the third part 503. That is, for each test signal line 5, it can be h6 = h7, h6 < h8, or it can also be h6 = h8, h6 < h7, or it can also be h6 = h7, h6 = h8.

[0143] It should be noted that in FIG4 , the third portion 503 of each test signal line 3 includes a portion extending along the first direction Y and a portion extending along the second direction X; the second portion 502 of some test signal lines 3 includes a portion extending along the first direction Y and a portion extending along the second direction X, and the second portion 502 of some test signal lines 3 only includes a portion extending along the second direction X. In a specific implementation, the pattern of the second portion and the pattern of the third portion can be designed based on the available wiring space. For example, as shown in FIG6 , the third portion 503 of at least some test signal lines 3 can only include a portion extending along the first direction Y. That is, if the wiring space allows, the test signal line can extend directly from the test signal end upward (i.e., toward the side of the display area) to the first binding area.

[0144] In some embodiments, as shown in FIG2 , FIG3 , and FIG4 , a plurality of test terminals 3 are sequentially arranged along the second direction X;

[0145] As shown in FIG3 and FIG4, the first portion 501 of the plurality of test signal lines 5 is sequentially arranged along the second direction X, the second portion 502 of the plurality of test signal lines 5 is sequentially arranged along the second direction X, and the third portion 503 of the plurality of test signal lines 5 is sequentially arranged along the second direction X.

[0146] In some embodiments, as shown in FIG3 , the display substrate further includes:

[0147] The plurality of transistors 6 are located on the same side of the first substrate 1 as the plurality of first binding terminals 2 in the first peripheral region 1021; the orthographic projections of the plurality of transistors 6 on the first substrate 1 are located between the orthographic projections of the plurality of output terminals 202 on the first substrate 1 and the orthographic projections of the plurality of input terminals 201 on the first substrate 1; the plurality of transistors 6 include: a plurality of first transistors 6-1, and a plurality of second transistors 6-2 located at least on one side of the plurality of first transistors 6-1 in the second direction X;

[0148] The plurality of output terminals 202 include: a plurality of first output terminals 2021, and a plurality of second output terminals 2022 located at least on one side of the plurality of first output terminals 2021 in the second direction X; the plurality of test signal lines 5 include: a control signal line 5-1, a plurality of first signal lines 5-2, and at least one second signal line 5-3;

[0149] The plurality of test terminals 3 include a control terminal 303 , a plurality of first test terminals 301 , and a second test terminal 302 .

[0150] In some embodiments, as shown in FIG. 3 , orthographic projections of the plurality of transistors 6 on the first substrate fall within the first bonding region 11 .

[0151] In some embodiments, as shown in FIG5 , each transistor 6 of the plurality of transistors 6 includes: a control electrode 601 , a first electrode 602 , a second electrode 603 , and an active layer 34 ;

[0152] The first electrode 602 of the first transistor 6 - 1 is electrically connected to the first output terminal 2021 , and the first electrode 602 of the second transistor 6 - 2 is electrically connected to the second output terminal 2022 ;

[0153] The control terminal 303 is electrically connected to the control electrodes 601 of multiple transistors 6 through the control signal line 5-1; the first test terminal 301 is electrically connected to the second electrodes 603 of some first transistors 6-1 through the first signal line 5-2; the second test terminal 302 is electrically connected to the second electrodes 603 of at least some second transistors 6-2 through the second signal line 5-3.

[0154] In a specific implementation, a control signal is applied to the control terminal to control the transistor to turn on, a first test signal is transmitted to the sub-pixel unit through the first signal line, the first transistor and the output terminal electrically connected to the first transistor, and a second test signal is transmitted to the sub-pixel unit through the second signal line, the second transistor and the output terminal electrically connected to the second transistor, so as to light up the sub-pixel unit and determine whether there is a display abnormality.

[0155] In a specific implementation, the transistor is, for example, a thin film transistor, the control electrode of the transistor is the gate of the thin film transistor, one of the first electrode and the second electrode of the transistor is the source of the thin film transistor, and the other of the first electrode and the second electrode of the transistor is the drain of the thin film transistor.

[0156] In a specific implementation, in order to avoid increasing the width of the driver chip in the second direction X and thus the width of the display substrate in the second direction X, the multiple output terminals can be arranged in multiple rows along the first direction Y, and the transistors can also be arranged in multiple rows along the first direction Y. For example, as shown in FIG3 , the multiple output terminals 202 are arranged in two rows along the first direction Y, the multiple first transistors 6 - 1 are arranged in three rows along the first direction Y, and the multiple second transistors 6 - 2 located on one side of the multiple first transistors 6 - 1 are arranged in two rows along the first direction Y.

[0157] In specific implementation, as shown in FIG. 4, the third part 503 is the part located outside the first binding area, the second part 502 is the part located inside the first binding area, and the second part 502 is located between the transistor 6 and the first dummy terminal 2012. As shown in FIG. 5, in the first direction Y, the distance between the second part 502 and the first dummy terminal 2012 is h3, and the distance between the third part 503 and the first dummy terminal 2012 is h4. It can be h3 = h4. Or, it can also be that h3 is not equal to h4. In the first direction Y, the distance h5 between the first dummy terminal 2012 and the test terminal 3 is about 400 microns, and the distance h9 between the first dummy terminal 2012 and the transistor 6 is about 150 microns. That is, the wiring space between the first dummy terminal 2012 and the transistor 6 is small, and the wiring space between the first dummy terminal 2012 and the test terminal 3 is large. Therefore, it can be set as h3 < h4. In some embodiments, in the first direction Y, the distance h3 between the second part 502 and the first dummy terminal 2012 is about 40 microns, and the distance h4 between the third part 503 and the first dummy terminal 2012 is about 80 microns.

[0158] In some embodiments, as shown in FIG. 2, the peripheral area 102 further includes second peripheral areas 1022 respectively located on both sides of the display area 101 in the second direction X; the display substrate further includes:

[0159] Multiple scan lines 7, electrically connected to multiple sub-pixel units (not shown), extending from the display area 101 to the second peripheral area 1022; the multiple scan lines 7 are arranged along the first direction Y and extend along the second direction X;

[0160] Multiple data lines 8, electrically connected to multiple sub-pixel units, extending from the display area 101 to the peripheral area 102; the multiple data lines 8 are arranged along the second direction X and extend along the first direction Y; each data line 8 in the multiple data lines 8 is electrically connected to the first output terminal 2021;

[0161] Multiple first connection leads 9, extending from the first peripheral area 1021 to the second peripheral area 1022; both ends of each first connection lead 9 in the multiple first connection leads 9 are respectively electrically connected to the second output terminal 2022 and the scan line 7.

[0162] In specific implementation, the sub-pixel unit includes a first thin-film transistor, the gate of the first thin-film transistor is electrically connected to the scan line, and the source of the first thin-film transistor is electrically connected to the data line.

[0163] In a specific implementation, the multiple sub-pixel units include multiple sub-pixel units with different light-emitting colors, and the number of first test terminals and the number of first signal lines are equal to the types of sub-pixel units; for example, the multiple sub-pixel units include: multiple red sub-pixel units, multiple blue sub-pixel units, and multiple green sub-pixel units. Accordingly, as shown in FIG3 , the display substrate includes: three first test terminals 301 and three first signal lines 5-2, the three first test terminals 301 are DB, DG, and DR, respectively, and the three first signal lines 5-2 are db, dg, and dr, respectively. The blue image is detected through DB and db, the green image is detected through DG and dg, and the red image is detected through DR and dr.

[0164] In some embodiments, as shown in FIG. 3 , in the second direction X, the control terminal 303 is located on a side of the remaining test terminals 3 away from the plurality of second binding terminals 4 .

[0165] In some embodiments, as shown in Figure 3, the second test terminal 302 includes at least one sub-test terminal 3021; ​​in the second direction X, the at least one sub-test terminal 3021 is located between the multiple first test terminals 301 and the control terminal 303, or, the at least one sub-test terminal 3021 is located on the side of the multiple first test terminals 301 away from the control terminal 303.

[0166] In some embodiments, as shown in FIG2 , the plurality of first connection leads 9 are divided into a fifth group 9 - 1 and a sixth group 9 - 2 extending to different second peripheral regions 1022 ;

[0167] The plurality of second output terminals 2022 are divided into: a third group 202-1 located on one side of the plurality of first output terminals 2021 in a direction in which the plurality of first test terminals 301 point to the first type second test terminal 3021-1, and a fourth group 202-2 located on one side of the plurality of first output terminals 2021 in a direction in which the plurality of first test terminals 301 point to the second type second test terminal 3021-2;

[0168] The first connection leads 9 in the fifth group 9 - 1 are electrically connected to the second output terminals 2022 in the third group 202 - 1 , and the first connection leads 9 in the sixth group 9 - 2 are electrically connected to the second output terminals 2022 in the fourth group 202 - 2 .

[0169] It should be noted that Figure 2 uses the examples in which the fifth group 9-1 extends to the second peripheral area 1022-1 on the left side of the display area 101, the sixth group 9-2 extends to the second peripheral area 1022-2 on the right side of the display area 101, the third group 202-1 is located on the left side of the multiple first output terminals 2021, and the fourth group 202-2 is located on the right side of the multiple first output terminals 2021.

[0170] In a specific implementation, the first connecting leads in the fifth group and the first connecting leads in the sixth group are connected to different rows of scan lines; the first connecting leads in the fifth group are electrically connected to odd-numbered scan lines, and the first connecting leads in the sixth group are electrically connected to even-numbered scan lines; or the first connecting leads in the fifth group are electrically connected to even-numbered scan lines, and the first connecting leads in the sixth group are electrically connected to odd-numbered scan lines. That is, the plurality of first connecting leads electrically connected to the plurality of scan lines are respectively located in two second peripheral areas on either side of the display area, thereby avoiding an increase in the width of the second peripheral area caused by the first connecting leads being located in one of the second peripheral areas, thereby facilitating a narrow-frame display.

[0171] Accordingly, in some embodiments, as shown in FIG3 , the plurality of test terminals 3 include two second test terminals 302 , the two second test terminals 302 being respectively: a first-type second test terminal 3021 - 1 located between the plurality of first test terminals 301 and the control terminal 303 , and a second-type second test terminal 3021 - 2 located on a side of the plurality of first test terminals 301 away from the control terminal 303 ;

[0172] The plurality of signal lines 5 include two second signal lines 5-3, the two second signal lines 5-3 being respectively: a first type second signal line 5-3-1 located between the plurality of first signal lines 5-2 and the control signal line 5-1, and a second type second signal line 5-3-2 located on a side of the plurality of first signal lines 5-2 away from the control signal line 5-1;

[0173] The plurality of second transistors 6-2 are divided into a first group 6-2-1 located on one side of the plurality of first transistors 6-1 in a direction in which the plurality of first test terminals 301 point to the first type of second test terminal 3021-1, and a second group 6-2-2 located on one side of the plurality of first transistors 6-1 in a direction in which the plurality of first test terminals 301 point to the second type of second test terminal 3021-2; the second output terminal 2022 of the third group 202-1 is electrically connected to the second transistor 6-2 of the first group 6-2-1, and the second output terminal 2022 of the fourth group 202-2 is electrically connected to the second transistor 6-2 of the second group 6-2-2;

[0174] The first-type second test terminal 3021-1 is electrically connected to the second pole of the first group 6-2-1 through the first-type second signal line 5-3-1, and the second-type second test terminal 3021-2 is electrically connected to the second pole of the second group 6-2-2 through the second-type second signal line 5-3-2;

[0175] That is, in a specific implementation, a second test signal is loaded on the second test terminal of the first category to transmit the second test signal to the scanning line electrically connected to the first connecting lead in the fifth group through the second signal line of the first category, the first transistor in the first group, the second output terminal in the third group, and the first connecting lead in the fifth group; a second test signal is loaded on the second test terminal of the second category to transmit the second test signal to the scanning line electrically connected to the first connecting lead in the sixth group through the second signal line of the second category, the first transistor in the second group, the second output terminal in the fourth group, and the first connecting lead in the sixth group.

[0176] It should be noted that because the data lines extend directly to the first peripheral area and are electrically connected to the first output terminal, the first connecting leads in the fifth group and the first connecting leads in the sixth group are located on either side of the multiple data lines, respectively. This allows the fifth, third, and first groups to be located on the same side, and the sixth, fourth, and first groups to be located on the same side. This effectively utilizes wiring space while avoiding increased wiring complexity on the display substrate. Accordingly, the control signal terminal is located on the side farthest from the second binding terminal, the first type second signal terminal is located between the control signal terminal and the first signal terminal, and the second type second signal terminal is located on the side of the first signal terminal away from the control signal terminal. This also effectively utilizes wiring space while avoiding increased wiring complexity on the display substrate.

[0177] In some embodiments, as shown in FIG3 , the test signal line 5 further includes a fourth portion 504 electrically connected to the second portion 502 ;

[0178] At least a portion of the fourth portion 504 extends along the second direction X. The orthographic projection of the fourth portion 504 on the first substrate 1 is located between the orthographic projections of the plurality of output terminals 202 on the first substrate 1 and the orthographic projections of the plurality of input terminals 201 on the first substrate 1.

[0179] The fourth portion 504 of the control signal line 5-1 is electrically connected to the control electrodes of the plurality of transistors 6, the fourth portion 504 of the first signal line 5-2 is electrically connected to the second electrode of the first transistor 6-1, and the fourth portion 504 of the second signal line 5-3 is electrically connected to the second electrode of the second transistor 6-2.

[0180] The fourth portion 504 of the first signal line 5-2 is located on a side of the fourth portion 504 of the control signal line 5-1 away from the display area 101 . The fourth portion 504 of the second signal line 5-3 is located on a side of the fourth portion 504 of the control signal line 5-1 away from the display area 101 .

[0181] In a specific implementation, the control signal line is electrically connected to the control level of the first transistor and the control level of the second transistor. The fourth part of the control signal line is closer to the display area than the fourth parts of the remaining test signal lines. The second part, the first part, and the third part of the control signal line are farther away from the second binding terminal than the second part, the first part, and the third part of the remaining test signal lines. This makes the control signal line located outside the remaining test signal lines, which is conducive to the rational use of the space in the first peripheral area and avoids interference between different test signal lines.

[0182] In some embodiments, as shown in FIG3 , when the second test terminal 302 includes a first-type second test terminal 3021 - 1 and a second-type second test terminal 3021 - 2 ;

[0183] The fourth portion 504 of the first-type second signal line 5-3-1 electrically connected to the first-type second test terminal 3021-1 is located between the fourth portion 504 of the control signal line 5-1 and at least part of the fourth portion 504 of the multiple first signal lines 5-2, and the fourth portion 504 of the second-type second signal line 5-3-2 electrically connected to the second-type second test terminal 3021-2 is located on the side of the fourth portion 504 of the multiple first signal lines 5-2 away from the fourth portion 504 of the control signal line 5-1.

[0184] In a specific implementation, as shown in FIG4 , the fourth portion 504 of each test signal line 5 can be divided into a plurality of first sub-portions 5041 extending along the second direction X. At least some of the first sub-portions 5041 extend from the orthographic projections of the first substrate 1 to the region where the orthographic projections of the plurality of transistors 6 are formed on the first substrate 1. The extension lines of different first sub-portions 5041 can lie on different straight lines. The fourth portion 504 can also be divided into second sub-portions 5042 extending in a direction intersecting the second direction X. The second sub-portions 5042 can connect to the first sub-portions 5041, whose extension lines can lie on different straight lines.

[0185] In a specific implementation, in FIG3 , the second transistors 6-2 in the first group 6-2-1 are arranged in two rows, and accordingly, the first type second signal line 5-3-1 includes two first sub-portions 5041, and the two first sub-portions 5041 are electrically connected to the two rows of second transistors 6-2, respectively; as shown in FIG4 , in the first direction Y, one of the first sub-portions 5041 (marked as 5041-1 in the drawing) is located between the other first sub-portion 5041 (marked as 5041-2 in the drawing) and the first sub-portion 5041 of the control signal line 5-1; one end of the extension direction of the two first sub-portions 5041 is connected to the portion of the second portion 502 extending along the first direction Y; the first type second signal line 5-31 also includes a second sub-portion 5042 connected to the two first sub-portions 5041 at one end of the two first sub-portions 5041 away from the connection with the second portion 502.

[0186] In a specific implementation, in FIG4 , each first signal line 5-2 includes two first sub-portions 5041 , one of which (marked as 5041-3 in the drawing) is located between the first group 6-2-1 and the first dummy terminal 2012 , and the orthographic projection of the first sub-portion 5041 (marked as 5041-3 in the drawing) on ​​the first substrate 1 does not overlap with the orthographic projection of the transistor 6 on the first substrate 1 ; the other first sub-portion 5041 (marked as 5041-4 in the drawing) extends to an area where a plurality of first transistors (not shown) are provided.

[0187] In some embodiments, as shown in FIG3 and FIG7 , the control signal line 5 - 1 further includes: a fifth portion 505 , the fifth portion 505 being electrically connected to the fourth portion 504 at an end of the fourth portion 504 facing away from the second portion 502 ;

[0188] The plurality of first input terminals 2011 include: a first ground level signal input terminal gnd; and the fifth portion 505 is electrically connected to the first ground level signal input terminal gnd.

[0189] It should be noted that transistors are not shown in FIG7 .

[0190] In some embodiments, as shown in Figures 3 and 7, the first input terminal 2011 is electrically connected to the second binding terminal 4 through the second connecting lead 18; the multiple second binding terminals 4 include a ground level signal binding terminal GND, and the first ground level signal input terminal gnd is electrically connected to the ground level signal binding terminal GND through the second connecting lead 18.

[0191] That is, in the display substrate provided by the embodiment of the present disclosure, one end of the control signal line is electrically connected to the control signal terminal, and the other end is electrically connected to the ground level signal binding terminal. Therefore, after binding the driver chip and the flexible circuit board, the other end of the control signal line is grounded, so that after binding the driver chip and the flexible circuit board, the potential of the control signal line can be lowered to avoid the transistor electrically connected to the control signal line from being accidentally turned on.

[0192] In some embodiments, as shown in FIG. 7 , the second binding terminal 4 includes a plurality of third dummy terminals 401 .

[0193] It should be noted that the third dummy terminal does not need to be electrically connected to any conductive structure of the display substrate, but the third dummy terminal still needs to be bound to the flexible circuit board. The third dummy terminal can support the flexible circuit board and balance the thickness of the structure of the second binding area.

[0194] In some embodiments, the display substrate provided by the embodiments of the present disclosure may be applied to electroluminescent display, and the sub-pixel unit of the display substrate further includes an electroluminescent device electrically connected to the thin film transistor of the sub-pixel unit.

[0195] Alternatively, in some embodiments, the display substrate provided by the embodiments of the present disclosure may be applied to liquid crystal displays. As shown in FIG8 , the sub-pixel unit further includes a pixel electrode 35 electrically connected to the first thin film transistor TFT1 ; the display substrate further includes a common electrode 36 .

[0196] In a specific implementation, as shown in FIG8 , the first thin-film transistor TFT1 includes a first active layer 37, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1; the first thin-film transistor TFT1 shown in FIG8 is a top-gate structure, that is, the first gate electrode G1 is located on the side of the first active layer 37 away from the first base substrate 1, and the display substrate further includes: a buffer layer 38 located between the first active layer 37 and the first base substrate 1, a gate insulating layer 39 located between the first gate electrode G1 and the first active layer 37, and an interlayer insulating layer 40 located between the first active layer 37 and the first source electrode S1 and the first drain electrode D1.

[0197] In a specific implementation, the display substrate includes a first conductive layer, a second conductive layer located on a side of the first conductive layer facing away from the first base substrate, a third conductive layer located on a side of the second conductive layer facing away from the first conductive layer, and a fourth conductive layer located on a side of the third conductive layer facing away from the second conductive layer. The first conductive layer includes a control electrode of the first transistor, a control electrode of the second transistor, and a gate electrode of the first thin-film transistor, and the second conductive layer includes a source electrode and a drain electrode of the first thin-film transistor. The third and fourth conductive layers are transparent conductive layers, one of which includes a pixel electrode and the other includes a common electrode. FIG8 illustrates an example in which the third conductive layer 20 includes a common electrode 36 and the fourth conductive layer 21 includes a pixel electrode 35. In a specific implementation, as shown in FIG8 , the display substrate also includes a first insulating layer 41 located between the common electrode 36 and the first source electrode S1 and the first drain electrode D1, and a second insulating layer 42 located between the pixel electrode 35 and the common electrode 36.

[0198] In a specific implementation, as shown in Figure 4, the test signal line 5 is located in the first conductive layer 19; the test terminal 3 includes an electrically connected first sublayer 22 and a second sublayer 23, the first sublayer 22 is located in the first conductive layer 19, the second sublayer 23 is located in the fourth conductive layer 21, and the first sublayer 22 is integrally connected to the test signal line 5; of course, the second sublayer can also be located in the third conductive layer; part of the input terminal 201 includes an electrically connected third sublayer 24 and a fourth sublayer 25, the third sublayer 24 is located in the first conductive layer 19, the fourth sublayer 25 is located in the second conductive layer 26, and part of the first dummy terminal 2012 and the second dummy terminal 27 are located in the fourth conductive layer 21; of course, part of the first dummy terminal and the second dummy terminal can also be located in the third conductive layer; in a specific implementation, the binding status of the driver chip can be checked through the first dummy terminal and / or the second dummy terminal located in the third conductive layer or the fourth conductive layer. As shown in FIG5 , the first electrode 602 of transistor 6 includes an electrically connected fifth sublayer 28 and sixth sublayer 29. Fifth sublayer 28 is located in second conductive layer 26, and sixth sublayer 29 is located in fourth conductive layer 21. Sixth sublayer 29 is electrically connected to a first signal line (not shown) or second signal line 5-3. A second electrode 603 of transistor 6 is located in second conductive layer 26. Of course, the sixth sublayer can also be located in the third conductive layer.

[0199] In a specific implementation, as shown in FIG7 , part of the third dummy terminals 401 are located on the fourth conductive layer 21 ; or, part of the third dummy terminals are located on the third conductive layer; thus, the binding condition of the flexible circuit board can be checked through the third dummy terminals located on the third conductive layer or the fourth conductive layer.

[0200] In a specific implementation, the remaining second binding terminals except the third dummy terminal located in the third conductive layer or the fourth conductive layer include the electrically connected seventh sublayer and eighth sublayer, the second connecting lead includes the ninth sublayer and the tenth sublayer, the seventh sublayer and the ninth sublayer are located in the first conductive layer, and the eighth sublayer and the tenth sublayer are located in the second conductive layer.

[0201] In a specific implementation, the second connecting lead may also be wired in a double layer, that is, the second connecting lead includes an eleventh sub-layer located in the first conductive layer and a twelfth sub-layer located in the second conductive layer.

[0202] In some embodiments, as shown in FIG9 , the display substrate further includes: a common electrode line 10 electrically connected to a common electrode (not shown);

[0203] In the first peripheral area 1021 , the orthographic projection of the common electrode line 10 on the first base substrate 1 extends through the first binding area 11 to the second binding area 12 , and the orthographic projection of the common electrode line 10 on the first base substrate 1 does not overlap with the orthographic projection of the first binding terminal 2 on the first base substrate 1 .

[0204] In some embodiments, an orthographic projection of the common electrode line on the first substrate and an orthographic projection of the transistor on the first substrate do not overlap with each other.

[0205] In the display substrate provided by the embodiments of the present disclosure, the common electrode line extends through the first binding region to the second binding region and is electrically connected to the second binding terminal, thereby effectively utilizing the space in the first peripheral region. Furthermore, the orthographic projection of the common electrode line on the first base substrate does not overlap with the first binding terminal or the orthographic projection of the transistor on the first base substrate, thereby preventing interference between the common electrode line and signal transmission at the first binding terminal.

[0206] In some embodiments, as shown in FIG9 , the common electrode line 10 includes: a first common electrode line 1001 and a second common electrode line 1002 ;

[0207] In the first peripheral area 1021, the first common electrode line 1001 is located on one side of the multiple data lines 8 in the direction in which the multiple second binding terminals 4 point to the multiple test terminals 3 on the orthographic projection of the first substrate 1, and the second common electrode line 1002 is located on the other side of the multiple data lines 8 in the direction in which the multiple test terminals 3 point to the multiple second binding terminals 4 on the orthographic projection of the first substrate 1.

[0208] In some embodiments, as shown in Figure 10, the first common electrode line 1001 includes a sixth portion 10011, and the area between the sixth portion 10011 and the adjacent first dummy terminal 2012 on the orthographic projection of the first substrate 1 overlaps with the orthographic projection of the first substrate 1, and the orthographic projection of the sixth portion 10011 on the first substrate 1 is located between the orthographic projection of the first portion 501 of the multiple test signal lines 5 on the first substrate 1 and the orthographic projection of the multiple first input terminals 2011 on the first substrate 1.

[0209] It should be noted that FIG10 is an enlarged schematic diagram of the D area in FIG9 .

[0210] In some embodiments, as shown in Figure 9, the peripheral area 102 also includes a third peripheral area 1023 located on the side of the display area 101 away from the first peripheral area 1021; the common electrode line also includes: a third common electrode line 1003, and a fourth common electrode line 1004, the fourth common electrode line 1004 surrounds the display area and is located on the side of the first connecting lead 9 facing the display area 101, and the third common electrode line 1003 surrounds the display area 101 and is located on the side of the first connecting lead 9 away from the display area 101; the third common electrode line 1003 is led out from one end of the plurality of second binding terminals 4, passes through the second peripheral area 1022 on one side of the display area 101, the third peripheral area 1023, and the second peripheral area 1022 on the other side of the display area 101, and then returns to the first peripheral area 1021 to be electrically connected to the other end of the plurality of second binding terminals 4; the display substrate also includes a ground level lead Gnd', and the ground level lead Gnd' is located on the side of the third common electrode line 1003 away from the display area 101.

[0211] In some embodiments, as shown in Figure 10, the multiple second binding terminals 4 also include multiple common electrode binding terminals vcom; one end of the first common electrode line 1001 and the third common electrode line 1003 are electrically connected to the same common electrode binding terminal vcom (i.e., the common electrode binding terminal vcom marked as vcom1 in the figure); as shown in Figure 13, the other end of the second common electrode line 1002 and the third common electrode line 1003 are electrically connected to the same common electrode binding terminal vcom (i.e., the common electrode binding terminal vcom marked as vcom2 in the figure).

[0212] In some embodiments, as shown in FIG10 , on a side of at least a portion of the first input terminal 2011 away from the first dummy terminal 2012 , some of the second dummy terminals 27 are arranged continuously.

[0213] The second connecting lead 18 electrically connected to the first input terminal 2011 located between the first dummy terminal 2012 and the second dummy terminal 27 includes: a fifteenth portion 1801 electrically connected to the first input terminal 2011 and extending along the first direction Y, a sixteenth portion 1802 electrically connected to the fifteenth portion 1801 and extending along the second direction X, and a seventeenth portion 1803 electrically connected to the sixteenth portion 1802 and the second binding terminal 4.

[0214] It should be noted that because the centers of the second binding area and the first binding area are located on different lines in the first direction, that is, the area bound to the flexible circuit board is not directly opposite the area bound to the driver chip, the wiring space of the second connecting lead electrically connecting the first input terminal to the second binding terminal is also changed. In the display substrate provided by the embodiment of the present disclosure, when wiring space is limited, at least a portion of the second connecting leads are led out from the first input terminal located on the side of the multiple second dummy terminals toward the first dummy terminal, and then electrically connected to the second binding terminal through the fifteenth, sixteenth, and seventeenth portions. This can increase the length of the second connecting leads while reasonably utilizing the wiring space, which is beneficial for reducing the impedance of the second connecting leads. In specific implementations, the length and width of the fifteenth, sixteenth, and seventeenth portions can be set according to the number of second connecting leads and the actual wiring space.

[0215] It should be noted that some of the consecutively arranged second dummy terminals are still provided with first input terminals on the side away from the first dummy terminals, that is, some of the multiple second dummy terminals are consecutively arranged between at least some adjacent first input terminals.

[0216] In some embodiments, as shown in FIG10 , the second connecting lead 18 can be electrically connected to one first input terminal 2011 or multiple first input terminals 2011 ; the second connecting lead 18 can be electrically connected to one second binding terminal 4 or multiple second binding terminals 4 .

[0217] In some embodiments, as shown in FIG. 12 , the sixth portion 10011 includes a plurality of first sub-common electrode lines 100111 arranged along the second direction X.

[0218] It should be noted that FIG12 is an enlarged schematic diagram of the G area in FIG10 .

[0219] In the display substrate provided by the embodiment of the present disclosure, the sixth portion includes a plurality of first sub-common electrode lines, thereby improving the electrical connection performance between the sixth portion and the rest of the first common electrode lines, reducing the impedance of the first common electrode lines, and avoiding affecting signal transmission.

[0220] In some embodiments, as shown in FIG. 10 and FIG. 12 , the first common electrode line 1001 further includes an eighth portion 10012 electrically connected to the sixth portion 10011 on a side of the sixth portion 10011 close to the display area 101 ;

[0221] The orthographic projection of the eighth portion 10012 on the first substrate 1 overlaps with the orthographic projection of at least a portion of the fourth portion 504 of the test signal line 5 on the first substrate 1, and the eighth portion 10012 and at least a portion of the fourth portion 504 of the test signal line 5 are located on different layers. Because the test signal line includes a portion extending along the second direction in the region corresponding to the transistor, the first common electrode line passing through the first binding region inevitably overlaps with the portion of the test signal line extending along the second direction in the region corresponding to the transistor. In the overlapping region, the first common electrode line and the test signal line are located on different layers, thereby preventing interference between the first common electrode line and the test signal line.

[0222] In some embodiments, as shown in Figures 10 and 12, the first common electrode line 1001 further includes: a tenth portion 10013 electrically connected to the sixth portion 10011 and the eighth portion 10012, and an eleventh portion 10014 electrically connected to the eighth portion 10012 at an end of the eighth portion 10012 away from the tenth portion 10013; the orthographic projection of the tenth portion 10013 on the first substrate does not overlap with the orthographic projection of the test signal line 5 on the first substrate, and the orthographic projection of the eleventh portion 10014 on the first substrate does not overlap with the orthographic projection of the test signal line 5 on the first substrate.

[0223] In a specific implementation, the eleventh portion is electrically connected to the fourth common electrode line through a region between the first group and the plurality of first transistors. The eighth portion is, for example, located in the third conductive layer or the fourth conductive layer, and the sixth portion, the tenth portion, and the eleventh portion are, for example, located in the first conductive layer. The eighth portion is electrically connected to the tenth portion and the eleventh portion via a via penetrating through each insulating film layer between the third conductive layer and the first conductive layer, or the eighth portion is electrically connected to the tenth portion and the eleventh portion via a via penetrating through each insulating film layer between the fourth conductive layer and the first conductive layer.

[0224] In some embodiments, as shown in FIG. 10 , the first common electrode line 1001 further includes a twelfth portion 10015 located on a side of the sixth portion 10011 away from the display area; the twelfth portion 10015 is connected to the third common electrode line 1003 .

[0225] In some embodiments, as shown in Figure 11, the second common electrode line 1002 includes a seventh portion 10021. In the second direction X, the orthographic projection of the seventh portion 10021 on the first base substrate 1 is located on a side of the orthographic projection of the multiple first input terminals 2011 on the first base substrate 1 away from the orthographic projection of the multiple first dummy terminals 2012 on the first base substrate 1.

[0226] It should be noted that FIG11 is an enlarged schematic diagram of the F area in FIG9 .

[0227] In some embodiments, as shown in FIG11 , the second common electrode line 1002 further includes a ninth portion 10022 electrically connected to the seventh portion 10021 on a side of the seventh portion 10021 close to the display area 101 ;

[0228] The orthographic projection of the ninth portion 10022 on the first substrate 1 overlaps with the orthographic projection of at least part of the fourth portion 504 of the test signal line 5 on the first substrate 1 , and the ninth portion 10022 and at least part of the fourth portion 504 of the test signal line 5 are located in different layers.

[0229] In some embodiments, as shown in Figure 11, the second common electrode line 1002 further includes: a thirteenth portion 10023 connecting the seventh portion 10021 and the ninth portion 10022, and a fourteenth portion 10024 located on the side of the ninth portion 10022 facing the display area; the thirteenth portion 10023 is connected to the third common electrode line 1003.

[0230] In some embodiments, as shown in FIG. 13 , the seventh portion 10021 is electrically connected to the common electrode binding terminal vcom (the common electrode binding terminal vcom labeled vcom2 ).

[0231] In the display substrate provided by the embodiment of the present disclosure, the seventh portion of the second common electrode line is located on a side of the first base substrate where the orthographic projection of the plurality of first input terminals on the first base substrate is away from the orthographic projection of the plurality of first dummy terminals on the first base substrate, that is, the second common electrode line extends to the edge of the first binding area, passes through the area between the input terminal and the edge of the first binding area, and extends to the second binding area, so that the wiring space can be reasonably utilized to realize the electrical connection between the second common electrode line and the third common electrode line, and to realize the electrical connection between the second common electrode and the second binding terminal.

[0232] In some embodiments, as shown in Figure 9, in the first peripheral area 1021, the orthographic projection of the first common electrode line 1001 on the first substrate substrate 1 is located between the orthographic projection of the fifth group 9-1 on the first substrate substrate 1 and the orthographic projection of the multiple data lines 8 on the first substrate substrate 1, and the orthographic projection of the second common electrode line 1002 on the first substrate substrate 1 is located between the orthographic projection of the sixth group 9-2 on the first substrate substrate 1 and the orthographic projection of the multiple data lines 8 on the first substrate substrate 1.

[0233] In some embodiments, as shown in FIG10 , the display substrate further includes a plurality of first electrostatic units 43 ; the first electrostatic units 43 are electrically connected to the test terminals 3 . A first electrostatic unit 43 is electrically connected between any two test terminals 3 .

[0234] In some embodiments, as shown in Figure 10, the first electrostatic unit 43 is also electrically connected to the third common electrode line 1003. The first electrostatic unit 43 is electrically connected between the third common electrode line 1003 and the test terminal 3, thereby preventing static electricity accumulation.

[0235] In some embodiments, the circuit diagram of the first electrostatic unit is shown in Figure 14. In Figure 14, the first electrostatic unit includes four thin-film transistors, namely M1, M2, M3, and M4. p1 and p2 in Figure 14 can both be test terminals. Of course, p1 and p2 can also be one of the test terminal and the other a common electrode layer.

[0236] In some embodiments, for various signal lines, such as test signal lines, common electrode lines, and ground leads, if their extension direction changes, for example, from a first direction to a second direction, or vice versa, the edge of the signal line pattern at the point where the extension direction changes can include a portion extending along a third direction, where the third direction intersects both the first and second directions. Taking test signal line 3 as an example, as shown in FIG5 , the angle of the contour of test signal line 3 at the point where its extension direction changes in regions J and K is not a right angle. This prevents tip discharges between adjacent signal lines.

[0237] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel, as shown in FIG15 , including a display substrate 36 provided in an embodiment of the present disclosure.

[0238] In some embodiments, as shown in FIG15 , the display panel further includes:

[0239] an opposite substrate 37 disposed opposite to the display substrate 36;

[0240] The liquid crystal layer 38 is located between the counter substrate 37 and the display substrate 36 .

[0241] In some embodiments, the counter substrate includes: a second base substrate, a black matrix and color resists on the side of the second base substrate facing the liquid crystal layer; the black matrix has openings, the openings corresponding one-to-one to the sub-pixel units of the display substrate, and the color resists are located within the openings; and spacers are located on the side of the black matrix facing the liquid crystal layer. The color resists correspond one-to-one to the sub-pixel units. The sub-pixel units include red sub-pixels, blue sub-pixels, and green sub-pixels. Accordingly, the color resists include red resists corresponding to the red sub-pixels, blue resists corresponding to the blue sub-pixels, and green resists corresponding to the green sub-pixels.

[0242] A display device provided by an embodiment of the present disclosure includes the display panel provided by an embodiment of the present disclosure.

[0243] In some embodiments, the display device provided in the embodiment of the present disclosure, as shown in FIG16 , may further include:

[0244] Driver chip IC; the driver chip IC is bound to a plurality of first binding terminals (not shown) in a first binding area (not shown);

[0245] Flexible circuit board FPC; the flexible circuit board FPC is bound to a plurality of second binding terminals (not shown) in a second binding area (not shown).

[0246] In some embodiments, the display device provided in the embodiments of the present disclosure may further include a backlight module located on the light incident side of the display substrate. The backlight module may be a direct-type backlight module or an edge-type backlight module.

[0247] In a specific implementation, the side-entry backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet stacked on the light-emitting side of the matrix light source, a diffuser, and a brightening film, etc. The reflective sheet includes an opening arranged directly opposite the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.). Submillimeter or even micron-scale micro light-emitting diodes are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, it has a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. Moreover, when micro-light-emitting diodes are used as backlight sources, more sophisticated dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0248] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the above-described display panel embodiments, and any repetitive details will not be repeated.

[0249] To sum up, in the display substrate, display panel and display device provided by the embodiments of the present disclosure, the test terminal is arranged on a side away from the display area of ​​the multiple first binding terminals bound to the driving chip, thereby avoiding the test terminal being located on both sides of the multiple first binding terminals in the second direction intersecting the first direction, resulting in an increase in the width of the peripheral area in the second direction, thereby avoiding affecting the user experience.

[0250] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0251] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A display substrate, wherein: The display substrate comprises: The first substrate includes: a display area and a peripheral area surrounding the display area; the peripheral area includes a first peripheral area located at one side of the display area in a first direction; A plurality of first binding terminals, located in the first peripheral area; the plurality of first binding terminals are used to bind to the driver chip; A plurality of test terminals are located on the same side of the first base substrate as the plurality of first binding terminals in the first peripheral area; the orthographic projections of the plurality of test terminals on the first base substrate are located on a side of the orthographic projections of the plurality of first binding terminals on the first base substrate away from the display area.

2. The display substrate according to claim 1, wherein: The display substrate further comprises: A plurality of second binding terminals are located on the same side of the first base substrate as the plurality of first binding terminals in the first peripheral area; the plurality of second binding terminals are used to bind to the flexible circuit board, and at least part of the second binding terminals are electrically connected to at least part of the first binding terminals; the orthographic projections of the plurality of second binding terminals on the first base substrate are located on a side of the orthographic projections of the plurality of first binding terminals on the first base substrate away from the display area, and in a second direction, the orthographic projections of the plurality of test terminals on the first base substrate are located on a side of the orthographic projections of the plurality of second binding terminals on the first base substrate, and the second direction intersects with the first direction.

3. The display substrate according to claim 2, wherein: The plurality of first binding terminals include: A plurality of input terminals; at least some of the plurality of input terminals are arranged along the second direction; The plurality of test terminals are located at a side of the plurality of input terminals away from the display area; The display substrate further comprises: A plurality of test signal lines are located in the first peripheral area; each of the plurality of test signal lines is electrically connected to the test terminal; the test signal line comprises: a first part, the orthographic projection of the first part on the first substrate substrate and the orthographic projection of the input terminal on the first substrate substrate do not overlap each other, and the orthographic projection of the first part on the first substrate substrate and the orthographic projection of the area between the adjacent input terminals on the first substrate substrate have an overlap.

4. The display substrate according to claim 3, wherein: The plurality of first binding terminals further include: A plurality of output terminals are located on a side of the plurality of input terminals facing the display area; and the test signal lines are electrically connected to the output terminals.

5. The display substrate according to claim 4, wherein: The plurality of input terminals include: a plurality of first input terminals, and a plurality of first dummy terminals located at one side of the plurality of first input terminals in a direction in which the plurality of second binding terminals point to one side of the plurality of test terminals; The plurality of first input terminals are electrically connected to at least some of the second binding terminals among the plurality of second binding terminals; The orthographic projection of the first portion on the first base substrate and the area between the adjacent first input terminals on the first base substrate do not overlap, and the orthographic projection of the first portion on the first base substrate and the area between the adjacent first dummy terminals on the first base substrate overlap.

6. The display substrate according to claim 5, wherein: The first portion includes a plurality of first sub-signal lines arranged along the second direction; an orthographic projection of the first sub-signal lines on the first substrate overlaps an orthographic projection of a region between adjacent first dummy terminals on the first substrate.

7. The display substrate according to claim 6, wherein: The test signal line further includes: a second part and a third part respectively connected to two ends of the first part in the extending direction; the second part is located at a side of the first part facing the display area, and the third part is located at a side of the first part away from the display area; In the second direction, the width of the first sub-signal line is smaller than the width of the second portion connected to the first portion, and the width of the first sub-signal line is smaller than the width of the third portion connected to the first portion.

8. The display substrate according to claim 7, wherein: At least one edge of the first signal sub-line extending in the first direction is in the same straight line as the edge of the second portion extending in the first direction, and at least one edge of the first signal sub-line extending in the first direction is in the same straight line as the edge of the third portion extending in the second direction.

9. The display substrate according to any one of claims 3 to 8, wherein: The plurality of test terminals are arranged in sequence along the second direction; The first part of the plurality of test signal lines is sequentially arranged along the second direction, the second part of the plurality of test signal lines is sequentially arranged along the second direction, and the third part of the plurality of test signal lines is sequentially arranged along the second direction.

10. The display substrate according to claim 9, wherein: The display substrate further comprises: A plurality of transistors are located on the same side of the first substrate with the plurality of first binding terminals in the first peripheral region; the orthographic projections of the plurality of transistors on the first substrate are located between the orthographic projections of the plurality of output terminals on the first substrate and the orthographic projections of the plurality of input terminals on the first substrate; each of the plurality of transistors comprises: a control electrode, a first electrode and a second electrode; the plurality of transistors comprises: a plurality of first transistors, and a plurality of second transistors located at least on one side of the plurality of first transistors in the second direction; The plurality of output terminals include: a plurality of first output terminals, and a plurality of second output terminals located at least on one side of the plurality of first output terminals in the second direction; the first electrode of the first transistor is electrically connected to the first output terminal, and the first electrode of the second transistor is electrically connected to the second output terminal; The plurality of test signal lines include: a control signal line, a plurality of first signal lines, and at least one second signal line; The plurality of test terminals include: a control terminal, a plurality of first test terminals, and a second test terminal; The control terminal is electrically connected to the control electrodes of the multiple transistors through the control signal line; the first test terminal is electrically connected to the second electrodes of some of the first transistors through the first signal line; and the second test terminal is electrically connected to the second electrodes of at least some of the second transistors through the second signal line.

11. The display substrate according to claim 10, wherein: In the second direction, the control terminal is located on a side of the remaining test terminals away from the plurality of second binding terminals.

12. The display substrate according to claim 11, wherein: The second test terminal includes at least one sub-test terminal; in the second direction, at least one sub-test terminal is located between the multiple first test terminals and the control terminal, or at least one sub-test terminal is located on the side of the multiple first test terminals away from the control terminal.

13. The display substrate according to claim 12, wherein: The second test terminals include: a first type of second test terminal located between the plurality of first test terminals and the control terminal, and a second type of second test terminal located on a side of the plurality of first test terminals away from the control terminal; The plurality of second transistors are divided into: a first group located at one side of the plurality of first transistors in a direction in which the plurality of first test terminals point to the first type second test terminals, and a second group located at one side of the plurality of first transistors in a direction in which the plurality of first test terminals point to the second type second test terminals; The plurality of second output terminals are divided into: a third group located at one side of the plurality of first output terminals in a direction in which the plurality of first test terminals point to the first type of second test terminals, and a fourth group located at one side of the plurality of first output terminals in a direction in which the plurality of first test terminals point to the second type of second test terminals; the second output terminals in the third group are electrically connected to the second transistors in the first group, and the second output terminals in the fourth group are electrically connected to the second transistors in the second group; The first-type second test terminal is electrically connected to the second pole of the first group through the second signal line, and the second-type second test terminal is electrically connected to the second pole of the second group through the second signal line.

14. The display substrate according to claim 12 or 13, wherein: The test signal line further includes a fourth portion electrically connected to the second portion; At least a portion of the fourth portion extends along the second direction, and an orthographic projection of the fourth portion on the first substrate is located between an orthographic projection of the plurality of output terminals on the first substrate and an orthographic projection of the plurality of input terminals on the first substrate; The fourth portion of the control signal line is electrically connected to the control electrodes of the plurality of transistors, the fourth portion of the first signal line is electrically connected to the second electrode of the first transistor, and the fourth portion of the second signal line is electrically connected to the second electrode of the second transistor; The fourth portion of the first signal line is located at a side of the fourth portion of the control signal line away from the display area, and the fourth portion of the second signal line is located at a side of the fourth portion of the control signal line away from the display area.

15. The display substrate according to claim 14, wherein: The second test terminals include: a first type second test terminal and a second type second test terminal; The second signal lines include: first-type second signal lines and second-type second signal lines; The fourth portion of the first-type second signal line electrically connected to the first-type second test terminal is located between the fourth portion of the control signal line and the fourth portions of the plurality of first signal lines, and the fourth portion of the second-type second signal line electrically connected to the second-type second test terminal is located on the side of the fourth portion of the plurality of first signal lines away from the fourth portion of the control signal line.

16. The display substrate according to claim 14, wherein: The control signal line further includes: a fifth portion, the fifth portion being electrically connected to the fourth portion at an end of the fourth portion away from the second portion; The plurality of first input terminals include: a first ground level signal input terminal; and the fifth portion is electrically connected to the first ground level signal input terminal.

17. The display substrate according to any one of claims 10 to 13, 15 and 16, wherein: The peripheral area further includes second peripheral areas respectively located on both sides of the display area in the second direction; and the display substrate further includes: A plurality of sub-pixel units, wherein the display area and the plurality of first binding terminals are located on the same side of the first substrate; the plurality of sub-pixel units include a plurality of sub-pixel units with different light emission colors; the number of the first test signal lines is equal to the type of the sub-pixel units; A plurality of scan lines, electrically connected to the plurality of sub-pixel units, extending from the display area to the second peripheral area; the plurality of scan lines are arranged along the first direction and extend along the second direction; a plurality of data lines electrically connected to the plurality of sub-pixel units, extending from the display area to the peripheral area; the plurality of data lines are arranged along the second direction and extend along the first direction; each of the plurality of data lines is electrically connected to the first output terminal; A plurality of first connecting leads extend from the first peripheral region to the second peripheral region; two ends of each of the plurality of first connecting leads are electrically connected to the second output terminal and the scan line respectively.

18. The display substrate according to claim 17, wherein: The display substrate further includes: a common electrode, and a common electrode line electrically connected to the common electrode; The first peripheral area includes a first binding area and a second binding area located in the first binding area away from the display area, the orthographic projections of the plurality of first binding terminals on the first substrate and the orthographic projections of the plurality of transistors on the first substrate fall into the first binding area, and the orthographic projections of the plurality of second binding terminals on the first substrate fall into the second binding area; In the first peripheral area, the orthographic projection of the common electrode line on the first base substrate extends through the first binding area to the second binding area, and the orthographic projection of the common electrode line on the first base substrate does not overlap with the orthographic projection of the first binding terminal on the first base substrate.

19. The display substrate according to claim 18, wherein: The plurality of input terminals include a plurality of first dummy terminals and a plurality of first input terminals; The common electrode line comprises: a first common electrode line and a second common electrode line; In the first peripheral area, an orthographic projection of the first common electrode line on the first substrate is located on one side of the plurality of data lines in a direction in which the plurality of second binding terminals point to the plurality of test terminals, and an orthographic projection of the second common electrode line on the first substrate is located on the other side of the plurality of data lines in a direction in which the plurality of test terminals point to the plurality of second binding terminals; The first common electrode line includes a sixth portion, an orthographic projection of the sixth portion on the first substrate overlaps an orthographic projection of a region between adjacent first dummy terminals on the first substrate, and an orthographic projection of the sixth portion on the first substrate is located between an orthographic projection of the first portions of the plurality of test signal lines on the first substrate and an orthographic projection of the plurality of first input terminals on the first substrate; The second common electrode line includes a seventh portion, and in the second direction, the orthographic projection of the seventh portion on the first substrate is located on a side of the orthographic projection of the plurality of first input terminals on the first substrate away from the orthographic projection of the plurality of first dummy terminals on the first substrate.

20. The display substrate according to claim 19, wherein: The sixth portion includes a plurality of first sub-common electrode lines arranged along the second direction.

21. The display substrate according to claim 19 or 20, wherein: The first common electrode line further includes an eighth portion electrically connected to the sixth portion at a side of the sixth portion close to the display area; The orthographic projection of the eighth portion on the first substrate overlaps with the orthographic projection of at least a portion of the fourth portion of the test signal line on the first substrate, and the eighth portion and at least a portion of the fourth portion of the test signal line are located in different layers; The second common electrode line further includes a ninth portion electrically connected to the seventh portion at a side of the seventh portion close to the display area; An orthographic projection of the ninth portion on the first substrate overlaps an orthographic projection of at least a portion of the fourth portion of the test signal line on the first substrate, and the ninth portion and at least a portion of the fourth portion of the test signal line are located in different layers.

22. The display substrate according to claim 19 or 20, wherein: The plurality of second output terminals include a third group and a fourth group; The plurality of first connecting leads are divided into a fifth group and a sixth group extending to different second peripheral areas; the first connecting leads in the fifth group are electrically connected to the second output terminals in the third group, and the first connecting leads in the sixth group are electrically connected to the second output terminals in the third group. The second output terminals in the four groups are electrically connected; In the first peripheral area, the orthographic projection of the first common electrode line on the first substrate is located between the orthographic projection of the fifth group on the first substrate and the orthographic projection of the multiple data lines on the first substrate, and the orthographic projection of the second common electrode line on the first substrate is located between the orthographic projection of the sixth group on the first substrate and the orthographic projection of the multiple data lines on the first substrate.

23. The display substrate according to any one of claims 1 to 8, 10 to 13, 15, 16, 18 to 20, wherein: The display substrate further includes a first electrostatic unit electrically connected to the test terminal.

24. A display panel, wherein: It comprises the display substrate according to any one of claims 1 to 23.

25. The display panel according to claim 24, wherein: Also includes: An opposite substrate, arranged opposite to the display substrate; The liquid crystal layer is located between the opposite substrate and the display substrate.

26. A display device, wherein: Comprising a display panel according to claim 24 or 25.

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