Display device and method for driving same

Abstract

The present application discloses a display device with an internal compensation scheme using an N-channel transistor such as an oxide TFT as an initialization switching element, said display device being capable of displaying good images without defective bright spots or raised blacks. In a pixel circuit of an OLED display device, a holding capacitor is initialized before the voltage of a data signal line is written to the holding capacitor via a drive transistor in a diode connection state. In this initialization period Tini, an initialization signal Vini(i) is given to the holding capacitor via an N-channel initialization transistor in the on state. The initialization signal Vini(i) is configured such that the voltage ViniH in an emission period when the initialization transistor is in the off state and a drive current flows to the OLED element is higher than the voltage ViniL in the initialization period Tini.

Description

Display device and driving method thereof

[0001] The present invention relates to a display device, and more particularly to a current-driven display device including display elements driven by current, such as an organic EL (Electro Luminescence) display device, and a method for driving the same.

[0002] In recent years, organic EL display devices equipped with pixel circuits including organic EL elements (also called organic light-emitting diodes (OLEDs)) have been put to practical use. The pixel circuits of organic EL display devices include, in addition to the organic EL elements, drive transistors, write control transistors, and storage capacitors. Thin-film transistors are used for the drive transistors and write control transistors, and a storage capacitor is connected to a gate terminal serving as a control terminal of the drive transistor. A voltage corresponding to a video signal representing an image to be displayed (more specifically, a voltage indicating the gradation value of a pixel to be formed by the pixel circuit, hereinafter referred to as a "data voltage") is applied to the storage capacitor via a data signal line from the drive circuit. The organic EL elements are self-luminous display elements that emit light at a brightness corresponding to the current flowing through them. The drive transistor is connected in series with the organic EL element and controls the current flowing through the organic EL element according to the voltage stored in the storage capacitor.

[0003] Variations and fluctuations occur in the characteristics of organic EL elements and drive transistors. Therefore, in order to achieve high-quality display in an organic EL display device, it is necessary to compensate for these variations and fluctuations in the characteristics of these elements. For organic EL display devices, there are known methods for compensating for element characteristics internally in the pixel circuit and externally in the pixel circuit. A pixel circuit that corresponds to the former method is known to be configured to initialize the voltage of the gate terminal of the drive transistor, i.e., initialize the voltage held in the hold capacitor, and then charge the hold capacitor with a data voltage via a diode-connected drive transistor. In such a pixel circuit, variations and fluctuations in the threshold voltage of the drive transistor are compensated for internally (hereinafter, this compensation for variations and fluctuations in threshold voltage is referred to as "threshold compensation").

[0004] In organic EL display devices employing a method for performing threshold compensation within a pixel circuit (hereinafter referred to as an "internal compensation method") as described above, a thin-film transistor (hereinafter referred to as an "oxide TFT") having a channel layer formed of an oxide semiconductor may be used as a switching element (hereinafter referred to as an "initialization switching element") for initializing the voltage of the gate terminal of the drive transistor (hereinafter simply referred to as the "gate voltage") in order to suppress fluctuations in the gate voltage due to current leakage during the light-emitting period after initialization. For example, an N-channel oxide TFT (hereinafter referred to as an "IGZO-TFT") using indium gallium zinc oxide (InGaZnO) as the oxide semiconductor may be used. In such pixel circuits, the gate terminal of the drive transistor is connected to an initialization voltage line via an IGZO-TFT, an N-channel thin-film transistor that serves as an initialization switching element. On the other hand, a P-channel thin-film transistor (hereinafter referred to as an "LTPS-TFT") having a channel layer formed of low-temperature polysilicon may be used as the drive transistor in order to enhance the driving capability of the organic EL element.

[0005] Issues related to the current leakage problem of the initialization switching element in the pixel circuit of an organic EL display device using the internal compensation method described above are described, for example, in Patent Document 1. Patent Document 1 discloses an organic EL display device in which a voltage Vini1 for initializing the gate voltage Vg, which is the voltage at the gate terminal of the drive transistor in the pixel circuit, is made different from a voltage Vini2 for initializing the anode voltage Va of the organic EL element serving as the display element, thereby reducing the off-leak current during the light emission period of the P-channel transistor serving as the initialization switching element. This configuration suppresses the occurrence of defective bright dots (bright dots that are not part of the intended display content) due to the off-leak current without increasing the area of ​​the pixel circuit.

[0006] International Publication No. WO2019 / 186765 Pamphlet

[0007] In pixel circuits in organic EL display devices employing the internal compensation method described above, the characteristics of an N-channel IGZO-TFT (hereinafter referred to as the "initialization TFT") serving as an initialization switching element may shift toward depletion when a voltage is applied to the gate terminal, causing its threshold voltage Vth (>0) to become smaller than the difference VGL-Vini (>0) between the voltage VGL to be applied to the gate terminal to turn off the initialization TFT and the voltage Vini of the initialization voltage line. When this threshold shift occurs, current flows through the initialization TFT during the light-emitting period when the initialization TFT should be turned off, lowering the gate voltage of the drive transistor. As a result, the displayed image may exhibit bright spots that are not included in the intended display content, i.e., defective bright spots, or a phenomenon known as "floating black," in which black areas appear brighter than they should.

[0008] Therefore, it is desirable to display good images without defective bright spots or floating blacks in current-driven display devices such as organic EL display devices of an internal compensation type that use N-channel transistors such as oxide TFTs as initialization switching elements.

[0009] a write control transistor as a switching element having a first conduction terminal for receiving a data voltage to be written to the hold capacitor and a second conduction terminal connected to the first conduction terminal of the drive transistor; a threshold compensation transistor as a switching element provided between the second conduction terminal and the control terminal of the drive transistor, the threshold compensation transistor as a switching element providing the drive transistor in a diode-connected state when in an on state; a light-emitting control transistor as a switching element provided in series with the display element and the drive transistor; and a drive circuit for driving the pixel circuits, each pixel circuit including: a display element driven by a current; a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal, the drive transistor being arranged in series with the display element; a storage capacitor having one end connected to the control terminal of the drive transistor for storing a voltage at the control terminal of the drive transistor; a write control transistor as a switching element having a first conduction terminal for receiving a data voltage to be written to the storage capacitor and a second conduction terminal connected to the first conduction terminal of the drive transistor; each pixel circuit is configured such that one first initialization signal of the plurality of first initialization signals is supplied to the holding capacitor via the first initialization transistor, and the drive circuit: during a write period in which the data voltage is to be written to the holding capacitor, turns on the write control transistor and the threshold compensation transistor and turns off the light-emission control transistor and the first initialization transistor; during an initialization period before the write period in which a voltage of the control terminal of the drive transistor is to be initialized, turns on the first initialization transistor and turns off the light-emission control transistor and the threshold compensation transistor; and during an emission period after the write period in which a drive current corresponding to the hold voltage of the hold capacitor is to be supplied from the drive transistor to the display element, turns on the light-emission control transistor and turns off the threshold compensation transistor and the first initialization transistor;The initialization signal generating circuit generates the plurality of first initialization signals so that the voltage of the one first initialization signal is higher in the light emission period than in the initialization period.

[0010] Some other embodiments of the display device of the present invention are related to the display device of the above-mentioned some embodiments, wherein each of the pixel circuits further includes an N-channel second initialization transistor as a switching element, the initialization signal generation circuit further generates a plurality of second initialization signals, the light-emitting control transistor has a first conduction terminal connected to the second conduction terminal of the drive transistor and a second conduction terminal connected to the display element, the second initialization transistor has a first conduction terminal connected to the second conduction terminal of the light-emitting control transistor and a second conduction terminal for receiving one second initialization signal of the plurality of second initialization signals, the drive circuit turns the second initialization transistor on during periods other than the light-emitting period and turns the second initialization transistor off during the light-emitting period, and the initialization signal generation circuit generates the plurality of first initialization signals so that the voltage of the one first initialization signal is higher in periods other than the initialization period than in the initialization period, and generates the plurality of second initialization signals so that the voltage of the one second initialization signal is higher in the light-emitting period than in periods other than the light-emitting period.

[0011] a write control transistor as a switching element having a first conduction terminal for receiving a data voltage to be written to the hold capacitor and a second conduction terminal connected to the first conduction terminal of the drive transistor; a threshold compensation transistor as a switching element provided between the second conduction terminal and the control terminal of the drive transistor, the threshold compensation transistor as a switching element providing the drive transistor in a diode-connected state when in an on state; a light-emitting control transistor as a switching element provided in series with the display element and the drive transistor; and an N-channel first initialization transistor as a switching element; and the driving step includes an initialization signal generation step of generating a plurality of first initialization signals. Each of the pixel circuits is configured such that one first initialization signal of the plurality of first initialization signals is applied to the holding capacitor via the first initialization transistor, and the driving step includes the steps of: during a write period in which the data voltage is to be written to the holding capacitor, turning on the write control transistor and the threshold compensation transistor and turning off the light-emitting control transistor and the first initialization transistor; and during an initialization period before the write period in which the voltage of the control terminal of the driving transistor is to be initialized, turning on the first initialization transistor and turning off the light-emitting control transistor and the threshold compensation transistor.The method further includes a step of turning on the light-emission control transistor and turning off the threshold compensation transistor and the first initialization transistor during an emission period after the writing period in which a drive current corresponding to the holding voltage of the holding capacitor should be supplied from the drive transistor to the display element, wherein the initialization signal generating step generates the plurality of first initialization signals so that the voltage of the one first initialization signal is higher during the light-emission period than during the initialization period.

[0012] In some of the above embodiments of the present invention, the pixel circuit is configured so that a data voltage to be written to the holding capacitor is applied to a first conduction terminal of the drive transistor via a write control transistor, and further applied to the holding capacitor via a drive transistor that is diode-connected by a threshold compensation switching element. During an initialization period prior to the write period in which the data voltage is written, in which the voltage at the control terminal of the drive transistor is to be initialized, the emission control transistor and the threshold compensation transistor are turned off and the first initialization transistor is turned on. As a result, the holding capacitor is initialized via the first initialization transistor by one of a plurality of first initialization signals generated by the initialization signal generation circuit, thereby initializing the voltage at the control terminal of the drive transistor. During an emission period following the write period in which a drive current corresponding to the voltage held by the holding capacitor is to be supplied from the drive transistor to the display element, the emission control transistor is turned on and the threshold compensation transistor and the first initialization transistor are turned off. In driving such a pixel circuit, the initialization signal generation circuit generates the plurality of first initialization signals so that the voltage of the single first initialization signal for initializing the voltage of the control terminal of the drive transistor by initializing the storage capacitor is higher during the light-emitting period than during the initialization period. This single first initialization signal ensures that the off-margin of the first initialization transistor, an N-channel transistor, during the light-emitting period is significantly larger than in conventional technology. Therefore, even if a slight threshold shift occurs in the first initialization transistor, no leakage current is generated in the first initialization transistor during the light-emitting period, and the voltage of the control terminal of the drive transistor is maintained at a voltage corresponding to the data voltage written during the write period. This allows the display element to continue emitting light at a luminance corresponding to the data voltage during the light-emitting period. As a result, the occurrence of defective bright spots and floating blacks due to leakage current in the first initialization transistor is suppressed.

[0013] In some other embodiments of the present invention, as in the above embodiments, during an initialization period before a write period in which a data voltage is written to a storage capacitor via a diode-connected drive transistor, the light-emission control transistor and the threshold compensation transistor are turned off and the first initialization transistor is turned on, thereby initializing the storage capacitor via the first initialization transistor by one of the plurality of first initialization signals, thereby initializing the voltage at the control terminal of the drive transistor. Furthermore, during the light-emission period after the write period, the light-emission control transistor is turned on and the threshold compensation transistor and the first initialization transistor are turned off. In addition, in some other embodiments, during a period other than the light-emission period (a non-light-emission period), the second initialization transistor is turned on, and the display element is initialized via the second initialization transistor by one of the plurality of second initialization signals generated by the initialization signal generation circuit. Meanwhile, during the light-emission period, the second initialization transistor is turned off. In driving such a pixel circuit, the initialization signal generation circuit generates the plurality of first initialization signals so that the voltage of the one first initialization signal is higher in periods other than the initialization period (including the light-emitting period) than in the initialization period, and generates the plurality of second initialization signals so that the voltage of the one second initialization signal is higher in the light-emitting period than in periods other than the light-emitting period (non-light-emitting period). The one first initialization signal prevents leakage current from occurring in periods other than the initialization period even if a slight threshold shift occurs in the first initialization transistor, which is an N-channel transistor. Therefore, the occurrence of defective bright spots and floating blacks due to leakage current in the first initialization transistor is suppressed regardless of the light-emitting duty.Furthermore, with this single second initialization signal, even if a slight threshold shift occurs in the second initialization transistor, which is an N-channel transistor, no leakage current occurs during the light-emitting period, and during periods other than the light-emitting period (non-light-emitting period), a relatively low voltage of the second initialization signal is applied to the display element via the second initialization transistor, thereby reliably initializing the display element, thereby further reducing the possibility of black floating in the display.

[0014] 1 is a block diagram showing an overall configuration of a display device according to a first embodiment. FIG. 2 is a timing chart illustrating a schematic operation of the display device according to the first embodiment. FIG. 3 is a circuit diagram showing a configuration of a pixel circuit in a conventional display device. FIG. 4 is a timing chart illustrating driving of a pixel circuit in the conventional display device. FIG. 5 is a characteristic diagram illustrating an off-margin of a first initialization transistor of a pixel circuit in the conventional display device. FIG. 6 is a signal waveform diagram illustrating operation of a pixel circuit in the conventional display device. FIG. 7 is a circuit diagram showing a configuration of a pixel circuit in the first embodiment. FIG. 8 is a timing chart illustrating driving of a pixel circuit in the first embodiment. FIG. 9 is a characteristic diagram illustrating an off-margin of a first initialization transistor of a pixel circuit in the first embodiment. FIG. 10 is a signal waveform diagram illustrating operation of a pixel circuit in the first embodiment. FIG. 11 is a timing chart illustrating driving of a pixel circuit in a second embodiment. FIG. 12 is a characteristic diagram illustrating an off-margin of a first initialization transistor of a pixel circuit in the display device according to the second embodiment. FIG. 13 is a signal waveform diagram illustrating operation of a pixel circuit in the second embodiment. FIG. 14 is a timing chart illustrating driving of a pixel circuit in a third embodiment. FIG. 15 is a characteristic diagram illustrating an off-margin of a first initialization transistor of a pixel circuit in the display device according to the third embodiment. FIG. 16 is a signal waveform diagram illustrating operation of a pixel circuit in the third embodiment. Fig. 10 is a block diagram showing the overall configuration of a display device according to a fourth embodiment. Fig. 11 is a circuit diagram showing the configuration of a pixel circuit in the fourth embodiment. Fig. 12 is a timing chart for explaining driving of the pixel circuit in the fourth embodiment. Fig. 13 is a characteristic diagram for explaining the off-margin of a first initialization transistor of the pixel circuit in the fourth embodiment. Fig. 14 is a signal waveform diagram for explaining the operation of the pixel circuit in the fourth embodiment.

[0015] Each embodiment will be described below with reference to the accompanying drawings. In each transistor described below, the gate terminal corresponds to the control terminal, one of the drain terminal and the source terminal corresponds to the first conduction terminal, and the other corresponds to the second conduction terminal. The transistor in each embodiment is, for example, a thin-film transistor, but the present invention is not limited thereto. Furthermore, in this specification, "connection" means "electrical connection" unless otherwise specified, and includes not only direct connection but also indirect connection via another element, within the scope of the present invention.

[0016] 1 is a block diagram showing the overall configuration of an organic EL display device 10 according to a first embodiment. This display device 10 is an organic EL display device that performs internal compensation. That is, in this display device 10, when a data voltage as pixel data is written to each pixel circuit, a storage capacitor is charged with the voltage of a data signal (data voltage) via a diode-connected drive transistor in the pixel circuit, thereby compensating for variations and fluctuations in the threshold voltage of the drive transistor (details will be described later).

[0017] As shown in FIG. 1 , this display device 10 includes a display unit 11, a display control circuit 20, a data-side drive circuit 30, a scanning-side drive circuit 40, and a power supply circuit 50. The data-side drive circuit functions as a data signal line drive circuit (also referred to as a “data driver”). The scanning-side drive circuit 40 functions as a scan signal line drive circuit (also referred to as a “gate driver”), a light-emission control circuit (also referred to as an “emission driver”), and an initialization signal generation circuit. In the configuration shown in FIG. 1 , these three drive circuits are implemented as a single scanning-side drive circuit 40. However, these three drive circuits in the scanning-side drive circuit 40 may be appropriately separated, or may be arranged separately on one side and the other side of the display unit 11. Furthermore, the scanning-side drive circuit 40 may be formed integrally with the display unit 11. These points also apply to other embodiments and modifications described below. The power supply circuit 50 generates a high-level power supply voltage ELVDD, a low-level power supply voltage ELVSS, a high-level initialization voltage ViniH, and a low-level initialization voltage ViniL, which will be described later, to be supplied to the display unit 11, as well as power supply voltages (not shown) to be supplied to the display control circuit 20, the data-side drive circuit 30, and the scan-side drive circuit 40. The high-level initialization voltage ViniH may be common to a gate high voltage VGH, which will be described later. In the following description of this embodiment, it is assumed that the high-level initialization voltage VniH is common to the gate high voltage VGH.

[0018] The display unit 11 is provided with m (m is an integer of 2 or greater) data signal lines D1, D2, ..., Dm, n (n is an integer of 2 or greater) first scanning signal lines PS1, PS2, ..., PSn, and n+2 second scanning signal lines NS-1, NS0, NS1, ..., NSn that intersect with the data signal lines D1, D2, ..., Dm. Furthermore, n light-emission control lines (emission lines) EM1 to EMn are provided along the n first scanning signal lines PS1 to PSn, respectively. Furthermore, n initialization signal lines INI1 to INIn are provided along the n first scanning signal lines PS1 to PSn, respectively. The display unit 11 is also provided with m x n pixel circuits 15 arranged in a matrix along the m data signal lines D1 to Dm and the n first scanning signal lines PS1 to PSn. Each pixel circuit 15 corresponds to one of the m data signal lines D1 to Dm and one of the n first scanning signal lines PS1 to PSn (hereinafter, when distinguishing between the pixel circuits 15, the pixel circuit corresponding to the ith first scanning signal line PSi and the jth data signal line Dj is also referred to as the "pixel circuit in the ith row and jth column" and is indicated by the symbol "Pix(i, j)"). Each pixel circuit 15 also corresponds to one of the n second scanning signal lines NS1 to NSn and one of the n light emission control lines EM1 to EMn. Furthermore, each pixel circuit 15 also corresponds to one of the n initialization signal lines INI1 to INIn. The data-side drive circuit 30 that drives the n data signal lines D1 to Dm, and the scan-side drive circuit 40 that drives the n first scanning signal lines PS1 to PSn, the n+2 second scanning signal lines NS-1 to NSn, the n light-emitting control lines EM1 to EMn, and the n initialization signal lines INI1 to INIn constitute a drive circuit that drives the m×n pixel circuits 15 in the display unit 11 (see Figure 1).

[0019] The display unit 11 is also provided with power supply lines (not shown) that are common to each pixel circuit 15. That is, a power supply line (hereinafter referred to as a "high-level power supply line" and denoted by the symbol "ELVDD" like the high-level power supply voltage) as a fixed voltage line for supplying a high-level power supply voltage ELVDD for driving an organic EL element (described later), and a power supply line (hereinafter referred to as a "low-level power supply line" and denoted by the symbol "ELVSS" like the low-level power supply voltage) as a fixed voltage line for supplying a low-level power supply voltage ELVSS for driving the organic EL element are provided. The high-level power supply voltage ELVDD and the low-level power supply voltage ELVSS are supplied from a power supply circuit 50 shown in FIG. 1 .

[0020] The display control circuit 20 receives an input signal Sin from outside the display device 10, which includes image information representing the image to be displayed and timing control information for image display, generates a data-side control signal Scd and a scanning-side control signal Scs based on this input signal Sin, and outputs the data-side control signal Scd to a data-side drive circuit (data signal line drive circuit) 30 and the scanning-side control signal Scs to a scanning-side drive circuit (scanning signal line drive / light emission control / initialization signal generation circuit) 40.

[0021] The data side drive circuit 30 drives the data signal lines D1 to Dm based on a data side control signal Scd from the display control circuit 20. That is, based on the data side control signal Scd, the data side drive circuit 30 outputs m data signals D(1) to D(m) in parallel, which represent an image to be displayed, and applies them to the data signal lines D1 to Dm, respectively.

[0022] The scanning-side drive circuit 40 functions as a scanning signal line drive circuit that drives the n first scanning signal lines PS1 to PSn and the n+2 second scanning signal lines NS-1 to NSn, an emission control circuit that drives the emission control lines EM1 to EMn, and an initialization signal generation circuit that drives the initialization signal lines INI1 to INIn, based on the scanning-side control signal Scs from the display control circuit 20. That is, in each frame period Tf, the scanning-side drive circuit 40, as a scanning signal line drive circuit, sequentially selects the n first scanning signal lines PS1 to PSn for a predetermined period corresponding to one horizontal period (1H), and sequentially selects the n+2 second scanning signal lines NS-1 to NSn for a predetermined period corresponding to two horizontal periods, with partial overlapping periods. Furthermore, in each frame period Tf, the scanning-side drive circuit 40, as a light-emission control circuit, drives the light-emission control lines EM1 to EMn so that they are selectively inactivated in conjunction with the driving of the first scanning signal lines PS1 to PSn and the second scanning signal lines NS-1 to NSn. Furthermore, in each frame period Tf, the scanning-side drive circuit 40, as an initialization signal generation circuit, generates initialization signals Vini(1) to Vini(i) and applies them to the initialization signal lines INI1 to INIn, respectively.

[0023] Note that the period during which the i-th emission control line EMi is in an activated state is the emission period of the i-th row's pixel circuits Pix(i,1) to Pix(i,m), and the period during which the i-th emission control line EMi is in an inactivated state is the non-emission period of the i-th row's pixel circuits Pix(i,1) to Pix(i,m). Also, as shown in FIG. 7 (described later), in this embodiment, the first scanning signal line PSi1 is connected to the gate terminal of the P-channel (hereinafter also referred to as "P-type") transistor T3 in the pixel circuit 15 (i1 = 1 to n), and the second scanning signal line NSi2 is connected to the gate terminal of the N-channel (hereinafter also referred to as "N-type") transistor T2 in the pixel circuit 15 (i2 = -1 to n). Therefore, a low-level (L-level) voltage is applied as an active signal to the selected first scanning signal line PSi1, and a high-level (H-level) voltage is applied as an active signal to the selected second scanning signal line NSi2.

[0024] <1.2 Outline of Operation> Hereinafter, an outline of the operation of the display device 10 according to this embodiment will be described with reference to FIG.

[0025] 2 is a timing chart for explaining the general operation of the display device 10 according to this embodiment. Based on the scanning control signal Scs from the display control circuit 20, the scanning-side drive circuit 40 generates first scanning signals PS(1), PS(2), ..., PS(n) and second scanning signals NS(-1), NS(0), NS(1), ..., NS(n) as shown in FIG. 2, and applies the first scanning signals PS(1) to PS(n) to the first scanning signal lines PS1 to PSn, respectively, and the second scanning signals NS(-1) to NS(n) to the second scanning signal lines NS-1 to NSn, respectively. Based on the scanning control signal Scs, the scanning-side drive circuit 40 also generates light-emission control signals EM(1) to EM(n) as shown in FIG. 2 and applies them to the light-emission control lines EM1 to EMn, respectively. Furthermore, the scanning-side drive circuit 40 generates initialization signals Vini(1) to Vini(n) as shown in FIG. 2 based on the scanning-side control signal Scs and applies them to the initialization signal lines INI1 to INIn, respectively. Meanwhile, the data-side drive circuit 30 generates data signals D(1) to D(m) that change in conjunction with the first scanning signals PS(1) to PS(n), as shown in FIG. 2, based on the data-side control signal Scd from the display control circuit 20, and applies them to the data signal lines D1 to Dm, respectively. By driving the first scanning signal lines PS1 to PSn, the second scanning signal lines NS-1 to NSn, the emission control lines EM1 to EMn, the initialization signal lines INI1 to INIn, and the data signal lines D1 to Dm in the display unit 11 in this manner, in each pixel circuit Pix(i, j), initialization and writing of data voltages are performed during the non-emission period, and the display element emits light at a luminance corresponding to the written data voltage during the emission period.

[0026] In this embodiment, during each frame period Tf, a data write operation is performed for each pixel circuit Pix(i,j) when the corresponding first scanning signal line PSi and second scanning signal line NSi are in a selected state, and an initialization operation is performed when the second scanning signal line NSi-2, which is two lines before the corresponding second scanning signal line NSi, is in a selected state. The light-emission control line EMi is driven (i = 1 to n) (see FIG. 2) so that each pixel circuit Pix(i,j) is in an extinguished state during the data write operation and initialization operation. As will be described later, in this embodiment, P-type transistors are used as the power supply control transistor T5 and the light-emission control transistor T6 in the pixel circuit Pix(i,j). Therefore, each light-emission control line EMi is activated when a low-level (L-level) voltage is applied, and is inactivated when a high-level (H-level) voltage is applied.

[0027] 1.3 Configuration and Operation of Pixel Circuit in Conventional Example Before describing the configuration and operation of pixel circuit 15 in this embodiment, the configuration and operation of pixel circuit 15a in a conventional organic EL display device (hereinafter referred to as the "conventional example") will be described below with reference to FIGS. 3 to 6 as a pixel circuit for comparison with pixel circuit 15. Note that this conventional example differs from the configuration shown in FIG. 1 in that, in the display unit 11, instead of the initialization signal lines INI1 to INIn, an initialization voltage line INI common to each pixel circuit Pix(i,j) is provided, and an initialization voltage Vini, which is a fixed voltage, is supplied to this initialization voltage line INI from power supply circuit 50. Other parts of the overall configuration of this conventional example are similar to the configuration shown in FIG. 1.

[0028] 3 is a circuit diagram showing the configuration of pixel circuit 15a in the above-mentioned conventional example, and more specifically, the configuration of pixel circuit 15a corresponding to the ith first scanning signal line PSi and the jth data signal line Dj, i.e., pixel circuit Pix(i,j) in the ith row and jth column (1≦i≦n, 1≦j≦m). This pixel circuit 15a includes one organic EL element OL as a display element, seven transistors T1 to T7 (hereinafter referred to as the “first initialization transistor T1,” “threshold compensation transistor T2,” “write control transistor T3,” “drive transistor T4,” “power supply control transistor T5,” “emission control transistor T6,” and “second initialization transistor T7”), and one storage capacitor Cst.

[0029] In this pixel circuit 15a, transistors T1, T2, and T7 are N-type transistors, and transistors T3 to T6 are P-type transistors. In this embodiment, N-type transistors T1, T2, and T7 are thin-film transistors (hereinafter referred to as "oxide TFTs") whose channel layers are formed from an oxide semiconductor. More specifically, they are oxide TFTs, i.e., IGZO-TFTs, that use indium gallium zinc oxide (InGaZnO) as the oxide semiconductor. Oxide TFTs have a small off-leakage current, making them suitable as switching elements in pixel circuits and the like. Furthermore, P-type transistors T3 to T6 are thin-film transistors, i.e., LTPS-TFTs, whose channel layers are formed from low-temperature polysilicon. Because low-temperature polysilicon has high mobility, using LTPS-TFTs as driving transistors improves the driving capability for organic EL elements in pixel circuits, and using them as switching elements reduces on-resistance. However, the transistors that can be used in pixel circuit 15a are not limited to IGZO-TFTs or LTPS-TFTs. In the pixel circuit 15a, the transistors T1 to T3 and T5 to T7 other than the drive transistor T4 operate as switching elements (the same applies to each embodiment).

[0030] As shown in FIGS. 1 and 3, each pixel circuit Pix(i, j) (1≦i≦n, 1≦j≦m) in the conventional example has a corresponding first scanning signal line PSi (hereinafter, also referred to as a “corresponding first scanning signal line” in the description focusing on the pixel circuit), a corresponding second scanning signal line NSi (hereinafter, also referred to as a “corresponding second scanning signal line” in the description focusing on the pixel circuit), and a corresponding light-emission control line E Mi, its corresponding data signal line (hereinafter, also referred to as the "corresponding data signal line" in the description focusing on the pixel circuit) Dj, the second scanning signal line NSi two before the corresponding second scanning signal line NSi (the scanning signal line two before in the scanning order of the second scanning signal lines NS-1 to NSn, hereinafter, also referred to as the "preceding second scanning signal line" in the description focusing on the pixel circuit) NSi-2, the initialization voltage line INI, the high-level power supply line ELVDD, and the low-level power supply line ELVSS are connected.

[0031] In the following description of such a pixel circuit Pix(i, j), the signal PS(i) of the corresponding first scanning signal line PSi, the signal NS(i) of the corresponding second scanning signal line NSi, the signal NS(i-2) of the preceding second scanning signal line NSi-2, the signal EM(i) of the corresponding light-emission control line EMi, and the signal D(j) of the corresponding data signal line Dj will be referred to as the corresponding first scanning signal PS(i), the corresponding second scanning signal NS(i), the preceding second scanning signal NS(i-2), the corresponding light-emission control signal EM(i), and the corresponding data signal D(j), respectively.

[0032] As shown in Figure 3, in pixel circuit Pix(i, j), the source terminal of the drive transistor T4 is connected to the corresponding data signal line Dj via a write control transistor T3 and to a high-level power line ELVDD via a power supply control transistor T5. The drain terminal of the drive transistor T4 is connected to an anode (first terminal) of an organic EL element OL via an emission control transistor T6, and the cathode (second terminal) of the organic EL element OL is connected to a low-level power line ELVSS. The gate terminal of the drive transistor T4 is connected to the drain terminal of the drive transistor T4 via a threshold compensation transistor T2, to the high-level power line ELVDD via a storage capacitor Cst, and to an initialization voltage line INI via a first initialization transistor T1. The anode of the organic EL element OL is connected to the initialization voltage line INI via a second initialization transistor T7. The gate terminal of the write control transistor T3 is connected to the corresponding first scanning signal line PSi, the gate terminal of the threshold compensation transistor T2 is connected to the corresponding second scanning signal line NSi, the gate terminals of the power supply control transistor T5 and the light-emitting control transistor T6 are both connected to the corresponding light-emitting control line EMi, and the gate terminals of the first initialization transistor T1 and the second initialization transistor T7 are both connected to the preceding second scanning signal line NSi-2.

[0033] The driving transistor T4 operates in a saturation region, and the driving current I1 flowing through the organic EL element OL during the light emission period is given by the following equation (1). The gain β of the driving transistor T4 included in equation (1) is given by the following equation (2): I1=(β / 2)(|Vgs|-|Vth|). 2 = (β / 2) (|Vg-ELVDD|-|Vth|) 2 ... (1) β = μ × (W / L) × Cox ... (2) However, in the above formulas (1) and (2), Vgs, Vth, Vg, μ, W, L, and Cox represent the gate-source voltage, threshold voltage, gate voltage, mobility, gate width, gate length, and gate insulating film capacitance per unit area of ​​the driving transistor T4, respectively.

[0034] FIG. 4 is a timing chart for explaining the driving of pixel circuit 15a in the above-described conventional example, showing changes in the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), initialization voltage Vini, and corresponding data signal D(j) during the initialization operation, writing operation, and lighting operation of pixel circuit Pix(i,j) in the i-th row and j-th column shown in FIG. Note that the initialization voltage Vini in the above-described conventional example is a fixed voltage (-5.5 V). In FIG. 4, the period from time t1 to t7 is a non-emission period for pixel circuits Pix(i,1) to Pix(i,m) in the i-th row. The period from time t2 to t3 is a selection period for preceding second scanning signal line Ni-2, which corresponds to the initialization period Tini for pixel circuits Pix(i,1) to Pix(i,m) in the i-th row. The period from time t3 to t6 is a selection period of the corresponding second scanning signal line NSi. The period from time t4 to t5 is a selection period of the corresponding first scanning signal line PSi, which is included in the selection period of the corresponding second scanning signal line NSi and corresponds to the writing period Tw of the pixel circuits Pix(i,1) to Pix(i,m) in the i-th row.

[0035] In the pixel circuit Pix(i,j) in the i-th row and j-th column, when the voltage of the corresponding light-emission control signal EM(i) changes from the L level to the H level at time t1, the power supply control transistor T5 and the light-emission control transistor T6 change from the ON state to the OFF state, and the organic EL element OL enters a non-light-emitting state, as shown in Figure 4. At the start time t1 of this non-light-emitting state period (non-light-emitting period), the preceding second scanning signal NS(i-2) and the corresponding second scanning signal NS(i) are at the L level, and the corresponding first scanning signal PS(i) is at the H level.

[0036] At time t2 in this non-light emitting period, the preceding second scanning signal NS(i-2) changes from L level to H level, so that the preceding second scanning signal line NSi-2 is selected, and the first initialization transistor T1 changes to the ON state.

[0037] The period from time t2 to t3 is the initialization period Tini for the pixel circuits Pix(i,1) to Pix(i,m) in the i-th row. In the pixel circuit Pix(i,j), the first initialization transistor T1 is on during this initialization period Tini, which initializes the storage capacitor Cst and initializes the gate voltage (the voltage at the gate terminal of the drive transistor T4) Vg to the initialization voltage Vini. The initialization voltage Vini is a voltage sufficient to maintain the drive transistor T4 in the on state when writing a data voltage to the pixel circuit Pix(i,j). However, the initialization voltage Vini is also used to initialize the anode of the organic EL element OL, and is selected to be at a level such that the anode-cathode voltage of the organic EL element OL does not exceed the light-emission threshold voltage. Note that the initialization voltage Vini may be equal to or lower than the low-level power supply voltage ELVSS. That is, during this initialization period Tini, the second initialization transistor T7 is also in the on state, so that the accumulated charge in the parasitic capacitance of the organic EL element OL is discharged and the anode voltage (voltage of the anode of the organic EL element OL) Va is initialized to the initialization voltage Vini.

[0038] At time t3, the preceding second scanning signal NS(i-2) changes to the L level, deselecting the preceding second scanning signal line NSi-2, thereby turning off the first initialization transistor T1 and the second initialization transistor T7. Also at time t3, the corresponding second scanning signal NS(i) changes from the L level to the H level, selecting the corresponding second scanning signal line NSi. This causes the threshold compensation transistor T2 to change from the OFF state to the ON state.

[0039] At time t4 during the period in which the corresponding second scanning signal line NSi is in the selected state, the corresponding first scanning signal PS(i) changes from H level to L level, thereby selecting the corresponding first scanning signal line PSi. This causes the write control transistor T3 to change from OFF state to ON state, and the write control transistor T3 remains ON until time t5, when the corresponding first scanning signal PS(i) changes to H level and the corresponding first scanning signal PS(i) is in the unselected state. As shown in FIG. 4 , during the period from t4 to t5 during which the corresponding first scanning signal PS(i) is in the selected state, i.e., by the start of the write period Tw, the data-side drive circuit 30 begins applying the voltage Dj(i) of the data signal D(j) to the data signal line Dj as the data voltage for the pixel circuit Pix(i,j) in the ith row and jth column, and continues applying the data voltage Dj(i) until at least the end of the write period Tw, i.e., time t5.

[0040] As described above, during the write period Tw, the write control transistor T3 is in an ON state, and a data voltage Vdata=Dj(i) is applied to the corresponding data signal line Dj. Furthermore, during the selection period t3 to t6 of the corresponding second scanning signal line NSi, which includes the write period Tw, the threshold compensation transistor T2 is also in an ON state, and the drive transistor T4 is in a diode-connected state, with its gate terminal and drain terminal connected. As a result, the voltage of the corresponding data signal D(j) is applied as a data voltage Vdata=Dj(i) to the holding capacitor Cst via the diode-connected drive transistor T4. As a result, the gate voltage Vg changes toward the value given by the following equation (3): Vg=Vdata-|Vth| (3) At the end time t5 of the data write period Tw, the data voltage that has been subjected to threshold compensation as described above is held in the holding capacitor Cst, and the gate voltage Vg becomes the value given by the above equation (3).

[0041] At time t7 after the end of the writing period Tw, the corresponding light-emission control signal line EM(i) changes to the L level. Accordingly, the power supply control transistor T5 and the light-emission control transistor T6 change to the ON state. As a result, from time t7 onwards, a current I1 flows from the high-level power supply line ELVDD to the low-level power supply line ELVSS via the power supply control transistor T5, the driving transistor T4, the light-emission control transistor T6 and the organic EL element OL. This current I1 is given by the above formula (1). Considering that the driving transistor T4 is a P-channel type and ELVDD>Vg, from the above formulas (1) and (3), this current I1 is given by the following formula: I1=(β / 2)(ELVDD-Vg-|Vth|) 2 =(β / 2)(ELVDD-Vdata) 2 ...(4) From the above, after time t7, the organic EL element OL emits light with a luminance corresponding to the data voltage Vdata=Dj(i), which is the voltage of the corresponding data signal line Dj in the i-th selection scanning period, regardless of the threshold voltage Vth of the drive transistor T4.

[0042] Here, the off margin of the first initialization transistor T1, which is related to the problem in the conventional example, will be described. Hereinafter, the "off margin of the first initialization transistor T1 (more generally, the off margin of an N-type transistor)" refers to the amount of voltage that must be increased from the gate-source voltage Vgs (OFF) of the transistor in the off state to achieve a gate-source voltage Vgs (e.g., Vgs = 0 V) ​​at which the transistor is turned on and the source-drain current Ids increases (the same applies to other embodiments).

[0043] 5 is a characteristic diagram illustrating the off margin of the first initialization transistor T1 of the pixel circuit in the above-described conventional example. As described above, in the above-described conventional example, an N-type transistor (more precisely, an N-type oxide TFT) is used as the first initialization transistor T1, and this first initialization transistor T1 has a gate terminal connected to the preceding second scanning signal line NSi-2 and a source terminal connected to the initialization voltage line INI. In the above-described conventional example, for example, the L-level voltage VGL of the second scanning signal NS(i) (-1≦i≦n) is −8 V, and the voltage of the initialization voltage line INI, i.e., the initialization voltage Vini, is −5.5 V (see FIG. 6 described below). In this case, the gate-source voltage Vgs(OFF) when the first initialization transistor T1 is in the off state is given by the following equation: Vgs(OFF)=VGL-Vini=-8-(-5.5)=-2.5 [V] Therefore, the off margin Vmg(OFF) of the first initialization transistor T1 is Vmg(OFF)=0-Vgs(OFF)=2.5 [V].

[0044] Because the off-margin Vmg(OFF) of the first initialization transistor T1 in the above-described conventional example is relatively small, considering the characteristics diagram of FIG. 5, the first initialization transistor T1, which is an N-type oxide TFT, becomes a depletion type due to a threshold shift, and leakage current may occur in the first initialization transistor T1, which should be in the off state. If leakage current occurs due to such a threshold shift, problems with display will occur. This point will be explained below with reference to FIGS. 4 and 6.

[0045] FIG. 6 is a signal waveform diagram for explaining the operation of pixel circuit 15 a ( FIG. 3 ) in the above-described conventional example, and shows changes in the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i−2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), initialization voltage Vini, corresponding data signal D(j), gate voltage Vg, and luminance L(i, j) of organic EL element OL during the operation of pixel circuit Pix(i, j) in the i-th row and j-th column in the above-described conventional example over two frame periods. 6, the initialization voltage Vini is a fixed voltage of −5.5 V, the H-level voltage (hereinafter referred to as the “gate high voltage”) VGH and the L-level voltage (hereinafter referred to as the “gate low voltage”) VGL of the light-emission control signals EM(1) to EM(n), first scanning signals PS(1) to PS(n), and second scanning signals NS(−1) to NS(n) are 9 V and −8 V, respectively, and the voltage of the corresponding data signal D(j), i.e., the data voltage Vdata to be written to the pixel circuit Pix(i, j), is set to Dj(i) = D(j) = 7 V. Note that the timing chart shown in FIG. 4 corresponds to the portion surrounded by the dashed ellipse in FIG. 6.

[0046] As shown in Fig. 6, at time t11 (t13, t14), which corresponds to time t1 in Fig. 4, the corresponding light-emission control signal EM(i) changes to H level, starting a non-light-emitting period. When the non-light-emitting period starts, the gate voltage Vg (the voltage at the gate terminal of the driving transistor T4) of the pixel circuit Pix(i,j) is initialized to the initialization voltage Vini during the initialization period Tini, and then becomes Vdata - |Vth| during the writing period Tw (see equation (3) above). Here, Vdata = Dj(i), and Vth is the threshold voltage of the driving transistor T4.

[0047] 4, the non-light-emitting period for the pixel circuit Pix(i,j) ends and the light-emitting period begins. This light-emitting period continues until time t13 in the next frame period, when the non-light-emitting period for the pixel circuit Pix(i,j) begins. During this light-emitting period, the first initialization transistor T1 is in the off state.

[0048] As described above, in the pixel circuit 15a of the conventional example, the first initialization transistor T1 has an off-margin Vmg (OFF) of 2.5 V, as shown in FIG. 5 . Therefore, during the light-emitting period, the first initialization transistor T1 becomes a depletion-mode transistor due to a relatively small threshold shift, and a leakage current may occur along a path from the node Ng including the gate terminal of the drive transistor T4 to the first initialization transistor T1 to the initialization voltage line INI. When such a leakage current occurs, as shown in FIG. 6 , the gate voltage Vg gradually decreases during the light-emitting period (t12 to t13), resulting in a gradual increase in the drive current I1 of the organic EL element OL, and a corresponding gradual increase in the luminance of the organic EL element OL. When one frame period has elapsed since time t11 (at time t13), the light-emitting period ends, and the non-light-emitting period of the next frame period begins. During the light-emitting period from the start time t13 of this non-light-emitting period to the start time t14 of the next frame period, the gate voltage Vg changes in the same manner as above, and the light-emitting luminance L(i, j) of the organic EL element OL gradually increases. This phenomenon is repeated every frame period, causing defective bright spots or floating blacks, making it impossible to display an image properly.

[0049] 1.4 Configuration and Operation of Pixel Circuit in This Embodiment Next, the configuration and operation of pixel circuit 15 in this embodiment will be described with reference to Fig. 7 to Fig. 10. Note that the configuration and operation of pixel circuit 15 in this embodiment that are not newly described below are the same as those of pixel circuit 15a in the conventional example.

[0050] 7 is a circuit diagram showing the configuration of a pixel circuit 15 corresponding to the ith first scanning signal line PSi and the jth data signal line Dj in this embodiment, i.e., the pixel circuit Pix(i, j) in the ith row and jth column (1≦i≦n, 1≦j≦m). Similar to the pixel circuit 15a in the conventional example (FIG. 3), this pixel circuit 15 includes an organic EL element OL as a display element, a drive transistor T4, a write control transistor T3, a threshold compensation transistor T2, a first initialization transistor T1, a power supply control transistor T5, a light-emission control transistor T6, a second initialization transistor T7, and a storage capacitor Cst.

[0051] As shown in FIG. 7 , in the pixel circuit 15 of this embodiment, the circuit elements (organic EL element OL, transistors T1 to T7, and storage capacitor Cst) as components are connected in the same manner as in the pixel circuit 15 a of the conventional example ( FIG. 3 ). Furthermore, the corresponding first scanning signal line PSi, the corresponding second scanning signal line NSi, the preceding second scanning signal line NSi-2, the corresponding light-emission control line EMi, the corresponding data signal line Dj, the high-level power supply line ELVDD, and the low-level power supply line ELVSS are also connected to the pixel circuit 15 of this embodiment in the same manner as in the pixel circuit 15 a of the conventional example. However, instead of the initialization voltage line INI ( FIG. 3 ) commonly connected to each pixel circuit 15 a of the conventional example, each pixel circuit 15 of this embodiment is connected to an initialization signal line INIi (hereinafter referred to as the “corresponding initialization signal line”) corresponding to that pixel circuit 15 among n initialization signal lines INI1 to INIn provided in the display unit 11 (see FIGS. 1 and 7 ). In the following description, the initialization signal Vini(i) applied to the corresponding initialization signal line INIi will be referred to as the corresponding initialization signal Vini(i).

[0052] FIG. 8 is a timing chart for explaining the driving of pixel circuit 15 in this embodiment, showing changes in the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), corresponding initialization signal Vini(i), and corresponding data signal D(j) during the initialization operation, writing operation, and lighting operation of pixel circuit Pix(i,j) in the i-th row and j-th column shown in FIG. 7. In FIG. 8, the period from time t1 to t7 is a non-emission period for pixel circuits Pix(i,1) to Pix(i,m) in the i-th row. The period from time t2 to t3 is a selection period for preceding second scanning signal line Ni-2, which corresponds to the initialization period Tini for pixel circuits Pix(i,1) to Pix(i,m) in the i-th row. The period from time t3 to t6 is a selection period for corresponding second scanning signal line NSi. The period from time t4 to t5 is the selection period of the corresponding first scanning signal line PSi, is included in the selection period of the corresponding second scanning signal line NSi, and corresponds to the writing period Tw of the pixel circuits Pix(i,1) to Pix(i,m) in the i-th row.

[0053] 8 with FIG. 4, the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), and corresponding data signal D(j) in this embodiment change at the same timing as the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), and corresponding data signal D(j) in the above-described conventional example. However, the voltage level of the corresponding initialization signal Vini(i) in this embodiment is ViniL (-4 V in the example of FIG. 8) during the non-light-emission period (t1 to t3) and ViniH (9 V in the example of FIG. 8) during the light-emission period, which is different from the above-described conventional example in that the initialization voltage Vini is a fixed voltage (-5.5 V in the example of FIG. 4).

[0054] 9 is a characteristics diagram illustrating the off margin of the first initialization transistor T1 of the pixel circuit in this embodiment. As described above, in this embodiment as well, an N-type transistor (more precisely, an N-type oxide TFT) is used as the first initialization transistor T1, and as shown in FIG. 7 , this first initialization transistor T1 has a gate terminal connected to the preceding second scanning signal line NSi-2 and a source terminal connected to the corresponding initialization signal line INIi. In this embodiment, for example, the L-level voltage (gate low voltage VGL) of the second scanning signal NS(i) (-1≦i≦n) is −8 V, but the voltage of the corresponding initialization signal line INIi (the voltage of the corresponding initialization signal Vini(i)) is ViniL = −4 V during the non-emission period and ViniH = 9 V during the emission period. In this case, the gate-source voltage Vgs(OFF) of the first initialization transistor T1 during the light emission period is Vgs(OFF) = VGL - ViniH = -8 - 9 = -17 [V], and therefore the off-margin Vmg(OFF) of the first initialization transistor T1 is Vmg(OFF) = 0 - Vgs(OFF) = 17 [V].

[0055] Therefore, as can be seen from the characteristic diagram of the first initialization transistor T1 shown in FIG. 9, in this embodiment, the off-margin Vmg(OFF) of the first initialization transistor T1 is sufficiently larger than the off-margin Vmg(OFF) = 2.5 V of the first initialization transistor T1 in the above-mentioned conventional example (see FIG. 5). For this reason, even if a slight threshold shift occurs in the N-type oxide TFT used as the first initialization transistor T1, no leakage current occurs in the first initialization transistor T1 during the light-emitting period. As a result, in this embodiment, the occurrence of defective bright spots and floating blacks caused by leakage current occurring in the first initialization transistor T1 in the above-mentioned conventional example is suppressed. This point will be explained below with reference to FIG. 10.

[0056] FIG. 10 is a signal waveform diagram for explaining the operation of pixel circuit 15 (FIG. 7) in this embodiment, and shows changes in the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), corresponding initialization signal Vini(i), corresponding data signal D(j), gate voltage Vg, and luminance L(i, j) of organic EL element OL during the operation of pixel circuit Pix(i, j) in the i-th row and j-th column in this embodiment over two frame periods. In the example of FIG. 10 , as in the conventional example described above (see FIG. 6 ), the gate high voltage VGH and gate low voltage VGL of the light-emission control signals EM(1) to EM(n), first scanning signals PS(1) to PS(n), and second scanning signals NS(−1) to NS(n) are 9 V and −8 V, respectively, and the voltage of the corresponding data signal D(j), i.e., the data voltage Vdata to be written to the pixel circuit Pix(i, j), is Dj(i) = D(j) = 7 V. However, the voltage of the corresponding initialization signal Vini(i) is ViniL = −4 V during the non-light-emission period and ViniH = VGH = 9 V during the light-emission period. Note that the timing chart shown in FIG. 8 corresponds to the portion enclosed by the dashed ellipse in FIG. 10 .

[0057] 10, at time t11 (t13, t14), which corresponds to time t1 in FIG. 8, when the corresponding light-emission control signal EM(i) changes to H level and the non-light-emitting period begins, the gate voltage Vg (the voltage at the gate terminal of the drive transistor T4) of the pixel circuit Pix(i, j) is initialized to a low-level initialization voltage ViniL during the initialization period Tini, and then becomes Vdata-|Vth| during the write period Tw, where Vdata=Dj(i), and Vth is the threshold voltage of the drive transistor T4.

[0058] 8, the non-light-emitting period ends and the light-emitting period begins for the pixel circuit Pix(i, j). This light-emitting period continues until time t13, when the non-light-emitting period begins in the next frame period, and during this light-emitting period, the first initialization transistor T1 is in the off state.

[0059] As described above, in the pixel circuit 15 of this embodiment, as shown in FIG. 9 , the off margin Vmg(OFF) of the first initialization transistor T1 is 17 V, which is significantly larger than that of the conventional example ( FIG. 5 ). Therefore, even if a slight threshold shift occurs in the N-type oxide TFT used as the first initialization transistor T1 during the light-emitting period when the first initialization transistor T1 is in the off state, no leakage current occurs. Therefore, unlike the conventional example in which the gate voltage Vg gradually decreases during the light-emitting period (t12 to t13) as shown in FIG. 6 , in this embodiment, the gate voltage Vg is maintained at Vdata−|Vth| during the light-emitting period (t12 to t13) as shown in FIG. 10 (in the waveform of the gate voltage Vg shown in FIG. 10 , the solid line indicates the waveform of the gate voltage Vg in this embodiment, and the dashed-dotted line indicates the waveform of the gate voltage Vg in the conventional example. This also applies to FIGS. 16 and 21 , which will be described later). In this manner, in this embodiment, the gate voltage Vg is maintained at Vdata−|Vth| during the light emission period, so that the organic EL element OL continues to emit light at a luminance according to the data voltage Vdata written to the pixel circuit 15.

[0060] <1.5 Effects> As described above, according to the present embodiment, in the pixel circuit 15, by setting the voltage of the corresponding initialization signal Vini(i) during the light-emitting period to a voltage ViniH (e.g., 9 V) that is higher than the voltage ViniL (e.g., −4 V) during the non-light-emitting period, the off-margin Vmg (OFF) of the first initialization transistor T1 during the light-emitting period becomes sufficiently larger than that of the conventional example ( FIG. 5 ) (see FIG. 9 ). As a result, no leakage current is generated in the first initialization transistor T1 during the light-emitting period, and the gate voltage Vg is maintained at Vdata−|Vth|. Therefore, the organic EL element OL continues to emit light at a luminance corresponding to the data voltage Vdata written to the pixel circuit 15 during the light-emitting period. As a result, unlike the conventional example, the occurrence of defective bright spots and floating blacks due to leakage current generated in the first initialization transistor T1 is suppressed. It should be noted that the voltage of the corresponding initialization signal Vini(i) during the initialization period Tini is a low-level initialization voltage ViniL (for example, −4 V), so that the same appropriate initialization operation as in the prior art is maintained.

[0061] 2. Second Embodiment Next, an organic EL display device according to a second embodiment will be described with reference to Figures 11 to 13. In this embodiment, the overall configuration of the display device and the configuration of the pixel circuit are the same as those in the first embodiment (see Figures 1 and 7), and the same or corresponding parts are designated by the same reference numerals. Note that the configuration and operation of this embodiment that are not newly described below are the same as those in the first embodiment.

[0062] The scanning side drive circuit 40 in this embodiment operates in the same manner as the first embodiment as a scanning signal line drive circuit and a light emission control circuit, but is configured to operate differently as an initialization signal line generation circuit from the first embodiment. This embodiment will be described below, focusing on this point.

[0063] FIG. 11 is a timing chart for explaining the driving of pixel circuit 15 in this embodiment, and shows changes in the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), corresponding initialization signal Vini(i), and corresponding data signal D(j) during the initialization operation, writing operation, and lighting operation of pixel circuit Pix(i, j) in the i-th row and j-th column shown in FIG.

[0064] 11 with FIG. 8, the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), and corresponding data signal D(j) in this embodiment change at the same timing as the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), and corresponding data signal D(j) in the first embodiment. However, the corresponding initialization signal Vini(i) in this embodiment differs from the corresponding initialization signal Vini(i) in the first embodiment in the period during which its voltage is the low-level initialization voltage ViniL. That is, while the voltage of the corresponding initialization signal Vini(i) in the first embodiment is a low-level initialization voltage ViniL (-4 V in the example shown in FIG. 8) during the non-light-emitting period and a high-level initialization voltage ViniH (9 V in the example shown in FIG. 8) during the light-emitting period, the voltage of the corresponding initialization signal Vini(i) in this embodiment is a low-level initialization voltage ViniL (-4 V in the example shown in FIG. 11) during the initialization period Tini (t2 to t3) within the non-light-emitting period (t1 to t7) and a high-level initialization voltage ViniH (9 V in the example shown in FIG. 11) during the other periods.

[0065] According to this embodiment, the off-margin Vmg(OFF) of the first initialization transistor T1 in the pixel circuit Pix(i, j) is given by the following equation not only during the light-emitting period but also during the non-light-emitting period other than the initialization period Tini: Vmg(OFF)=0-Vgs(OFF)=ViniH-VGL=17 [V]. Therefore, in this embodiment as well, the first initialization transistor T1 has the operating characteristics shown in FIG. 12. As can be seen from FIG. 12, in this embodiment, as in the first embodiment, the off-margin Vmg(OFF) of the first initialization transistor T1 is sufficiently larger than the off-margin Vmg(OFF)=2.5 V of the first initialization transistor T1 in the conventional example (see FIG. 5). Therefore, even if a slight threshold shift occurs in the N-type oxide TFT used as the first initialization transistor T1, no leakage current occurs in the first initialization transistor T1 during the light-emitting period. As a result, this embodiment also suppresses the occurrence of defective bright spots and black floating caused by leakage current generated in the first initialization transistor T1, as will be described below with reference to FIG.

[0066] 13 is a signal waveform diagram for explaining the operation of pixel circuit 15 (FIG. 7) in this embodiment, and shows changes in the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), corresponding initialization signal Vini(i), corresponding data signal D(j), gate voltage Vg, and luminance L(i,j) of organic EL element OL during operation of pixel circuit Pix(i,j) in the i-th row and j-th column in this embodiment over two frame periods. In the example of FIG. 13, as in the example of FIG. 10, the gate high voltage VGH and gate low voltage VGL are 9 V and −8 V, respectively, and the voltage of the corresponding data signal D(j), i.e., the data voltage Vdata to be written to pixel circuit Pix(i,j), is set to Dj(i)=D(j)=7 V. The voltage of the corresponding initialization signal Vini(i) is ViniL = -4 V in the initialization period Tini, and ViniH = VGH = 9 V in the light-emitting period and the non-light-emitting period other than the initialization period Tini. The timing chart shown in FIG. 11 corresponds to the portion surrounded by the dashed ellipse in FIG. 13.

[0067] As shown in Figure 13, at time t11 (t13, t14), which corresponds to time t1 in Figure 11, when the corresponding light-emitting control signal EM(i) changes to H level and a non-light-emitting period begins, the gate voltage Vg (the voltage at the gate terminal of the driving transistor T4) of the pixel circuit Pix(i, j) is initialized to a low-level initialization voltage ViniL during the initialization period Tini, and then becomes Vdata-|Vth| during the write period Tw.

[0068] 11, the non-light-emitting period ends and the light-emitting period begins for the pixel circuit Pix(i, j). This light-emitting period continues until time t13, when the non-light-emitting period begins in the next frame period, and during this light-emitting period, the first initialization transistor T1 is in the off state.

[0069] As described above, in the pixel circuit 15 of this embodiment, the off margin Vmg(OFF) of the first initialization transistor T1 is 17 V, as shown in FIG. 12 , which is significantly larger than that of the conventional example ( FIG. 5 ). Therefore, even if a slight threshold shift occurs in the N-type oxide TFT used as the first initialization transistor T1 during the light-emitting period when the first initialization transistor T1 is in the off state, no leakage current occurs. Therefore, in this embodiment, as in the first embodiment, the gate voltage Vg is maintained at Vdata−|Vth| during the light-emitting period, as shown in FIG. 13 . Thus, in this embodiment, as in the first embodiment, the gate voltage Vg is maintained at Vdata−|Vth| during the light-emitting period, so that the organic EL element OL continues to emit light at a luminance corresponding to the data voltage Vdata written to the pixel circuit 15. As a result, as in the first embodiment, the occurrence of defective bright spots and floating blacks due to leakage current occurring in the first initialization transistor T1 during the light-emitting period is suppressed.

[0070] Furthermore, in this embodiment, unlike the first embodiment, even in non-light-emitting periods other than the initialization period Tini, the voltage level of the corresponding initialization signal Vini(i) is ViniH (=9V), and the off-margin Vmg (OFF) of the first initialization transistor T1 is sufficiently large. Therefore, even when brightness is adjusted by the light-emitting duty, the gate voltage Vg is maintained at Vdata-|Vth| from the time when the data voltage Vdata is written until the time when writing of the data voltage Vdata in the next frame period begins, regardless of the light-emitting duty. Therefore, the occurrence of defective bright spots and floating blacks caused by leakage current in the first initialization transistor T1 is reliably suppressed, regardless of the light-emitting duty.

[0071] 3. Third Embodiment Next, an organic EL display device according to a third embodiment will be described with reference to Figures 14 to 16. In this embodiment, the overall configuration of the display device and the configuration of the pixel circuit are the same as those in the first embodiment (see Figures 1 and 7), and the same or corresponding parts are designated by the same reference numerals. Note that the configuration and operation of this embodiment that are not newly described below are the same as those in the first embodiment.

[0072] 14 is a timing chart for explaining the driving of pixel circuit 15 in this embodiment, and shows changes in the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), corresponding initialization signal Vini(i), and corresponding data signal D(j) during the initialization operation, writing operation, and lighting operation of pixel circuit Pix(i,j) in the i-th row and j-th column shown in FIG.

[0073] 11 , the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), corresponding data signal D(j), and corresponding initialization signal Vini(i) in this embodiment change at the same timing as the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), corresponding data signal D(j), and corresponding initialization signal Vini(i) in the second embodiment. Here, the voltage of the initialization signal Vini(i) in this embodiment is a high-level initialization voltage ViniH in periods other than the initialization period Tini (including the light-emission period), and is a low-level initialization voltage ViniL (-4 V in the example shown in FIGS. 14 and 11 ) in other periods, as in the second embodiment.

[0074] However, this embodiment differs from the second embodiment in the value of the high-level initialization voltage ViniH, which is the voltage of the corresponding initialization signal Vini(i) during periods other than the initialization period Tini. That is, while the high-level initialization voltage ViniH in the second embodiment is 9 V, which is equal to the gate high-level voltage VGH used to turn on N-type transistors such as the first initialization transistor T1 and the second initialization transistor T7 (see FIG. 11), the high-level initialization voltage ViniH in this embodiment is −1 V, which is lower than the gate high-level voltage VGH (see FIG. 14). This is to prevent current from flowing from the corresponding initialization signal line INIi to the gate terminal (node ​​Ng) of the drive transistor T4 during periods such as a light-emission period in which the voltage written to the holding capacitor Cst should be held.

[0075] On the other hand, from the viewpoint of suppressing the off-current Ids(OFF) of the first initialization transistor T1, it is preferable to reduce the potential difference between its source and drain during the light-emitting period, regardless of whether its source and drain are inverted. To achieve this, the voltage of the initialization signal Vini(i) during the light-emitting period, i.e., the high-level initialization voltage ViniH, should be set as close as possible to the voltage of the gate terminal of the drive transistor T4, i.e., the gate voltage Vg (see FIG. 7 ). This gate voltage Vg depends on the gradation of the pixel to be formed by the pixel circuit Pix(i, j). In the configuration of FIG. 7 , when the gradation is black (the lowest gradation level), for example, the data voltage Vdata is 7 V and the gate voltage Vg is 4 V. When the gradation is white (the highest gradation level), for example, the data voltage Vdata is 2 V and the gate voltage Vg is −1 V. Therefore, it is preferable to generate the corresponding initialization signal Vini(i) so that the value of the high-level initialization voltage ViniH is equal to or greater than the gate voltage Vg (e.g., −1 V) when the gradation is at the white level and equal to or less than the gate voltage Vg (e.g., 4 V) when the gradation is at the black level, or more generally, so that the value of the high-level initialization voltage ViniH is equal to or greater than the minimum value of the gate voltage Vg during the light-emission period and equal to or less than the maximum value. When the potential difference between the source and drain of the first initialization transistor T1 is reduced in this manner, its off-current Ids(OFF) decreases, and current inflow to or current outflow from the gate terminal (node ​​Ng) of the drive transistor T4 is suppressed during light-emission periods, etc., when the voltage written to the storage capacitor Cst of the pixel circuit Pix(i, j) should be maintained.

[0076] In general, black out, where low-brightness areas of the screen appear brighter than they should be, is more noticeable than white out, where high-brightness areas of the screen appear darker than they should be. In order to suppress the off-current Ids(OFF) of the first initialization transistor T1, it is ideal for its drain-source voltage Vds to be zero. Therefore, from the perspective of prioritizing the prevention of black out, it is preferable to generate the corresponding initialization signal Vini(i) so that the value of the high-level initialization voltage ViniH is as close as possible to the gate voltage Vg (e.g., 4 V) at the black level during a light-emission period or the like in which the voltage written to the storage capacitor Cst should be maintained.

[0077] According to this embodiment, the off-margin Vmg(OFF) of the first initialization transistor T1 is given by the following equation not only during the light-emitting period but also during the non-light-emitting period other than the initialization period Tini: Vmg(OFF)=0-Vgs(OFF)=ViniH-VGL=-1-(-8)=7[V] Therefore, in this embodiment, the first initialization transistor T1 has the operating characteristics shown in Fig. 15. As can be seen from Fig. 15, the off-margin Vmg(OFF) of the first initialization transistor T1 in this embodiment is smaller than the off-margin Vmg(OFF)=17 V of the first initialization transistor T1 in the first and second embodiments (see Figs. 9 and 12), but is still sufficiently larger than the off-margin Vmg(OFF)=2.5 V of the first initialization transistor T1 in the conventional example (see Fig. 5). Therefore, even if a slight threshold shift occurs in the N-type oxide TFT used as the first initialization transistor T1, no leakage current occurs in the first initialization transistor T1 not only during the light-emitting period but also during periods other than the initialization period Tini in the non-light-emitting period.

[0078] 16 is a signal waveform diagram for explaining the operation of pixel circuit 15 (FIG. 7) in this embodiment, and shows changes in the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), corresponding initialization signal Vini(i), corresponding data signal D(j), gate voltage Vg, and luminance L(i,j) of organic EL element OL during the operation of pixel circuit Pix(i,j) in the i-th row and j-th column in this embodiment over two frame periods. In the example of FIG. 16, as in the example of FIG. 13, the gate high voltage VGH and gate low voltage VGL are 9 V and −8 V, respectively, and the voltage of the corresponding data signal D(j), i.e., the data voltage Vdata to be written to pixel circuit Pix(i,j), is set to Dj(i)=D(j)=7 V. However, for the corresponding initialization signal Vini(i), the low-level initialization voltage ViniL is −4V, but the high-level initialization voltage ViniH is −1V.

[0079] As described above, the off margin Vmg(OFF) of the first initialization transistor T1 in this embodiment is 7 V, which is significantly larger than that of the conventional example ( FIG. 5 ). Therefore, even if a slight threshold shift occurs in the N-type oxide TFT used as the first initialization transistor T1 during the light-emitting period when the first initialization transistor T1 is in the off state, no leakage current occurs. Therefore, in this embodiment, as in the first embodiment, the gate voltage Vg is maintained at Vdata−|Vth| during the light-emitting period, as shown in FIG. 16 . Thus, in this embodiment, as in the first embodiment, the gate voltage Vg is maintained at Vdata−|Vth| during the light-emitting period, so that the organic EL element OL continues to emit light at a luminance corresponding to the data voltage Vdata written to the pixel circuit 15 during the light-emitting period. As a result, as in the first embodiment, the occurrence of defective bright spots and floating blacks due to leakage current occurring in the first initialization transistor T1 during the light-emitting period is suppressed.

[0080] Furthermore, in this embodiment, even in non-light-emitting periods other than the initialization period Tini, the voltage level of the corresponding initialization signal Vini(i) is ViniH (=-1V), and the off margin Vmg (OFF) of the first initialization transistor T1 is sufficiently large (see FIG. 15). Therefore, as in the second embodiment (FIG. 13), even when brightness is adjusted by the light-emitting duty, the gate voltage Vg is maintained at Vdata-|Vth| from the time when the data voltage Vdata is written until the time when writing of the data voltage Vdata in the next frame period begins, regardless of the light-emitting duty. This reliably suppresses the occurrence of defective bright spots and floating blacks caused by leakage current in the first initialization transistor T1, regardless of the light-emitting duty, as in the second embodiment.

[0081] Furthermore, in this embodiment, the high-level initialization voltage ViniH is set to -1 V, which is lower than the high-level initialization voltage ViniH (=VGH=9 V) in the second embodiment. This reduces the off-current Ids(OFF) of the first initialization transistor T1, thereby preventing a problem in which a current flows into or out of the gate terminal (node ​​Ng) of the drive transistor T4. As a result, a better display can be achieved more reliably than in the first and second embodiments.

[0082] 4. Fourth Embodiment Next, an organic EL display device according to a fourth embodiment will be described with reference to Figures 17 to 21. In this embodiment, the overall configuration of the display device and the configuration of the pixel circuit are basically the same as those in the first embodiment (see Figures 1 and 7), and the same or corresponding parts are designated by the same reference numerals. Note that the configuration and operation of this embodiment that are not newly described below are the same as those in the first embodiment.

[0083] 17 is a block diagram showing the overall configuration of an organic EL display device 10 according to this embodiment. This display device 10b is also an organic EL display device that performs internal compensation, similar to the display devices 10 according to the first to third embodiments.

[0084] 1, a display device 10b according to this embodiment also includes a display unit 11, a display control circuit 20, a data-side drive circuit 30, a scanning-side drive circuit 40, and a power supply circuit 50, similar to the first embodiment. However, instead of the n initialization signal lines INI1 to INIn, the display unit 11 according to this embodiment is provided with n first initialization signal lines INIA1 to INIAn and n second initialization signal lines INIB1 to INIBn. Correspondingly, the initialization signal generation circuit included in the scanning-side drive circuit 40 according to this embodiment is configured to generate first initialization signals ViniA(1) to ViniA(n) and apply them to the first initialization signal lines INIA1 to INIAn, respectively, and to generate second initialization signals ViniB(1) to ViniB(n) and apply them to the second initialization signal lines INIB1 to INIBn, respectively. In this embodiment, each pixel circuit Pix(i, j) corresponds to one first initialization signal line INIAi among the n first initialization signal lines INIA1 to INIAn, and also corresponds to one second initialization signal line INIBi among the n second initialization signal lines INIB1 to INIBn.

[0085] 18 is a circuit diagram showing the configuration of pixel circuit 15b corresponding to the ith first scanning signal line PSi and the jth data signal line Dj in this embodiment, i.e., pixel circuit Pix(i, j) in the ith row and jth column (1≦i≦n, 1≦j≦m). Like pixel circuit 15 in the first embodiment (FIG. 7), pixel circuit 15b also includes an organic EL element OL as a display element, a drive transistor T4, a write control transistor T3, a threshold compensation transistor T2, a first initialization transistor T1, a power supply control transistor T5, a light-emission control transistor T6, a second initialization transistor T7, and a storage capacitor Cst.

[0086] As shown in FIG. 18 , in the pixel circuit 15 b of this embodiment, the circuit elements (organic EL element OL, transistors T1 to T7, and storage capacitor Cst) as components are connected in the same manner as in the pixel circuit 15 of the first embodiment ( FIG. 7 ). Also, as shown in FIGS. 17 and 18 , in the pixel circuit 15 b of this embodiment, the corresponding first scanning signal line PSi, the corresponding second scanning signal line NSi, the preceding second scanning signal line NSi-2, the corresponding light-emission control line EMi, the corresponding data signal line Dj, the high-level power supply line ELVDD, and the low-level power supply line ELVSS are also connected in substantially the same manner as in the pixel circuit 15 of the first embodiment. However, in this pixel circuit 15 b ( FIG. 18 ), the corresponding light-emission control signal line EMi is connected to the gate terminal of the second initialization transistor T7 instead of the preceding second scanning signal line NSi-2. In this respect, the pixel circuit 15 b differs from the pixel circuit 15 of the first embodiment ( FIG. 7 ).

[0087] 18, the gate terminal of the driving transistor T4 is connected to the corresponding first initialization signal line INIAi via the first initialization transistor T1, and the anode of the organic EL element OL is connected to the corresponding second initialization signal line INIBi via the second initialization transistor T7. In the following, the first initialization signal ViniA(i) applied to the corresponding first initialization signal line INIAi will be referred to as the corresponding first initialization signal ViniA(i), and the second initialization signal ViniB(i) applied to the corresponding second initialization signal line INIBi will be referred to as the corresponding second initialization signal ViniB(i).

[0088] Figure 19 is a timing chart for explaining the driving of pixel circuit 15b in this embodiment, and shows changes in the corresponding light-emitting control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), corresponding first initialization signal ViniA(i), corresponding second initialization signal ViniB(i), and corresponding data signal D(j) during the initialization operation, writing operation, and lighting operation of pixel circuit Pix(i,j) in the i-th row and j-th column shown in Figure 18.

[0089] 19 with FIG. 8 and FIG. 14, the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), and corresponding data signal D(j) in this embodiment change at the same timing as the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), and corresponding data signal D(j) in the first and third embodiments. Furthermore, the corresponding first initialization signal ViniA(i) in this embodiment changes at the same timing as the corresponding initialization signal Vini(i) in the third embodiment (see FIG. 14), and the corresponding second initialization signal ViniB(i) in this embodiment changes at the same timing as the corresponding initialization signal Vini(i) in the first embodiment (see FIG. 8). 19 , for both the first initialization signal ViniA(i) and the second initialization signal ViniB(i) (i = 1 to n), the high-level initialization voltage ViniH is −1 V (<VGH), and the low-level initialization voltage ViniL is −4 V. Here, the high-level initialization voltage ViniH is selected to be lower than the high-level initialization voltage ViniH of 9 V in the first embodiment, based on the same reasoning as for selecting −1 V as the high-level initialization voltage ViniH in the third embodiment. As a result, when a high-level initialization voltage ViniH is applied to the corresponding first initialization signal line INIAi, the potential difference between the source and drain of the first initialization transistor T1 is reduced, thereby suppressing current flow into the gate terminal (node ​​Ng) of the drive transistor T4 during the period in which the voltage held in the holding capacitor Cst should be maintained (the period in which the gate voltage Vg should be maintained) when the data voltage Vdata is written to the pixel circuit Pix(i, j), and when a high-level initialization voltage ViniH is applied to the corresponding second initialization signal line INIBi, the off-current Ids(OFF) in the second initialization transistor T7 is reduced, thereby suppressing current flow into or current flow out of the anode of the organic EL element OL during the light-emitting period.

[0090] According to this embodiment, the off-margin Vmg(OFF) of the first initialization transistor T1 is given by the following equation not only during the light-emitting period but also during the non-light-emitting period, other than the initialization period Tini: Vmg(OFF)=0-Vgs(OFF)=ViniH-VGL=-1-(-8)=7[V] Therefore, in this embodiment as well, the first initialization transistor T1 has the operating characteristics shown in Fig. 20. As can be seen from Fig. 20, the off-margin Vmg(OFF) of the first initialization transistor T1 in this embodiment is smaller than the off-margin Vmg(OFF) of the first initialization transistor T1 in the first and second embodiments (see Figs. 9 and 12), but is sufficiently larger than the off-margin Vmg(OFF)=2.5V of the first initialization transistor T1 in the conventional example (see Fig. 5), not only during the light-emitting period but also during the non-light-emitting period, other than the initialization period Tini. Therefore, as in the third embodiment described above, even when the brightness is adjusted by the light-emitting duty, regardless of the light-emitting duty, after the data voltage Vdata is written, no leakage current occurs in the first initialization transistor T1 until the writing of the data voltage Vdata in the next frame period begins, and the gate voltage Vg is maintained at Vdata-|Vth|.

[0091] Furthermore, the off margin Vmg(OFF) of the second initializing transistor T7 is given by the above formula during the light emission period, Vmg(OFF) = 7 V. Therefore, even if a slight threshold shift occurs in the N-type oxide TFT used as the second initializing transistor T7, no leakage current occurs in the second initializing transistor T7 during the light emission period.

[0092] 21 is a signal waveform diagram for explaining the operation of pixel circuit 15b (FIG. 18) in this embodiment, and shows changes in the corresponding light-emission control signal EM(i), preceding second scanning signal NS(i-2), corresponding second scanning signal NS(i), corresponding first scanning signal PS(i), corresponding first initialization signal ViniA(i), corresponding second initialization signal ViniB(i), corresponding data signal D(j), gate voltage Vg, and luminance L(i,j) of organic EL element OL during operation of pixel circuit Pix(i,j) in the i-th row and j-th column in this embodiment over two frame periods. In the example of FIG. 21, as in the example of FIG. 16, the gate high voltage VGH and gate low voltage VGL are 9 V and −8 V, respectively, and the voltage of the corresponding data signal D(j), i.e., the data voltage Vdata to be written to pixel circuit Pix(i,j), is set to Dj(i)=D(j)=7 V. As described above, for both the corresponding first initialization signal ViniA(i) and the corresponding second initialization signal ViniB(i), the low-level initialization voltage ViniL is −4V, but the high-level initialization voltage ViniH is −1V.

[0093] As described above, the off-margin Vmg(OFF) of the first initialization transistor T1 in this embodiment is 7 V, which is significantly larger than that of the conventional example ( FIG. 5 ). Therefore, even if a slight threshold shift occurs in the N-type oxide TFT used as the first initialization transistor T1 during periods when the first initialization transistor T1 is in the off state (not only during light-emitting periods but also during non-light-emitting periods other than the initialization period Tini), no leakage current occurs. Therefore, according to this embodiment, the gate voltage Vg of the pixel circuit Pix(i, j) is maintained at Vdata−|Vth| regardless of the light-emitting duty (see FIG. 21 ). Furthermore, in this embodiment, the high-level initialization voltage ViniH is set to −1 V, which is lower than the high-level initialization voltage ViniH (=VGH=9 V) in the second embodiment. This reduces the off-current Ids(OFF) of the first initialization transistor T1, thereby preventing a problem in which current flows into the gate terminal (node ​​Ng) of the drive transistor T4. Therefore, according to this embodiment, similar to the third embodiment described above, the occurrence of defective bright spots and black floating caused by leakage current generated in the first initialization transistor T1 is suppressed regardless of the light-emitting duty, and a good display is reliably achieved by reducing the off-current Ids(OFF) in the first initialization transistor T1.

[0094] Furthermore, according to this embodiment, as shown in FIG. 19 , the corresponding second initialization signal ViniB(i) changes in synchronization with the corresponding light-emission control signal EM(i), and the off-margin Vmg(OFF) of the second initialization transistor T7 is also sufficiently large at 7 V during the light-emission period. Therefore, even if a slight threshold shift occurs in the N-type oxide TFT used as the second initialization transistor T7 during the light-emission period when the second initialization transistor T7 is in the off state, no leakage current occurs. Furthermore, in this embodiment, the second initialization transistor T7 is in the on state during the non-light-emission period, and a low-level initialization voltage ViniL (−4 V) is applied to the anode of the organic EL element OL via the second initialization transistor T7. This ensures that the organic EL element OL is reliably initialized, further reducing the possibility of black floating in the display.

[0095] 5. Modifications The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

[0096] For example, in the pixel circuit Pix(i, j) in each of the above embodiments, a P-type transistor is used as the drive transistor T4, but even in a configuration in which an N-type drive transistor is used, the present invention can be applied if an N-type transistor is used as the first initialization transistor T1.

[0097] Although the above describes each embodiment and its modified examples using an organic EL display device as an example, the present invention is not limited to organic EL display devices and can be applied to any internal compensation type display device using a current-driven display element. Display elements that can be used here are display elements whose brightness or transmittance is controlled by current, and examples of such display elements include organic EL elements, i.e., organic light-emitting diodes (OLEDs), inorganic light-emitting diodes, quantum dot light-emitting diodes (QLEDs), and the like.

[0098] In addition, the features of the display device described above may be combined in any manner within the scope that does not contradict the nature of the display device and does not deviate from the spirit of the present invention, to form a display device that combines the features of several of the first to fourth embodiments described above.

[0099] DESCRIPTION OF SYMBOLS 10, 10b... Display device 11... Display unit 15, 15b... Pixel circuit Pix (i, j)... Pixel circuit (i = 1 to n, j = 1 to m) 20... Display control circuit 30... Data side drive circuit (data signal line drive circuit) 40... Scanning side drive circuit (scanning signal line drive / light emission control / initialization signal generation circuit) PSi... First scan signal line (i = 1, 2, ..., n) NSi... Second scan signal line (i = -1, 0, 1, ..., n) EMi... Light emission control line (i = 1 to n) INIi... Initialization signal line (i = 1 to n) INIAi... First initialization signal line (i = 1 to n) INIBi... Second initialization signal line (i = 1 to n) ViniH... High level initialization voltage ViniL... Low level initialization voltage Dj... Data signal line (j = 1 to m) ELVDD...High-level power supply line, high-level power supply voltage ELVSS...Low-level power supply line, low-level power supply voltage OL...Organic EL element (display element) Cst...Retention capacitor T1...First initialization transistor T2...Threshold voltage compensation transistor T3...Data write control transistor T4...Drive transistor T5...Power supply control transistor T6...Light emission control transistor T7...Second initialization transistor Tini...Initialization period Tw...Write period

Claims

1. A display unit including a plurality of pixel circuits; and a drive circuit for driving the plurality of pixel circuits, each pixel circuit including: a display element driven by a current; a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal, and arranged in series with the display element; a retention capacitor having one end connected to the control terminal of the drive transistor for retaining a voltage at the control terminal of the drive transistor; a write control transistor as a switching element having a first conduction terminal for receiving a data voltage to be written to the retention capacitor and a second conduction terminal connected to the first conduction terminal of the drive transistor; a threshold compensation transistor as a switching element arranged between the second conduction terminal and the control terminal of the drive transistor, and putting the drive transistor into a diode-connected state when in an on state; a light-emitting control transistor as a switching element arranged in series with the display element and the drive transistor; and an N-channel first initialization transistor as a switching element, and the drive circuit includes an initialization signal generation circuit for generating a plurality of first initialization signals, each of the pixel circuits is configured such that one first initialization signal of the plurality of first initialization signals is provided to the holding capacitor via the first initialization transistor, and the drive circuit: during a write period in which the data voltage is to be written to the holding capacitor, turns on the write control transistor and the threshold compensation transistor and turns off the light emission control transistor and the first initialization transistor; during an initialization period before the write period in which a voltage of the control terminal of the drive transistor is to be initialized, turns on the first initialization transistor and turns off the light emission control transistor and the threshold compensation transistor; and during an emission period after the write period in which a drive current according to the held voltage of the holding capacitor is to be supplied from the drive transistor to the display element, turns on the light emission control transistor and turns off the threshold compensation transistor and the first initialization transistor;The display device, wherein the initialization signal generation circuit generates the plurality of first initialization signals such that a voltage of the one first initialization signal is higher in the light emission period than in the initialization period.

2. The display device according to claim 1, wherein the initialization signal generating circuit generates the plurality of first initialization signals so that the voltage of the one first initialization signal is higher during the light emission period than during periods other than the light emission period.

3. The display device according to claim 1, wherein the initialization signal generating circuit generates the plurality of first initialization signals so that the voltage of the one first initialization signal is higher in periods other than the initialization period than in the initialization period.

4. The display device of claim 3, wherein the first initialization transistor has a first conductive terminal connected to the holding capacitor and a second conductive terminal that receives the one initialization signal, and the initialization signal generating circuit generates the multiple first initialization signals so that the voltage of the one first initialization signal is not higher than the voltage of the first conductive terminal of the first initialization transistor.

5. The display device described in claim 3, wherein the initialization signal generating circuit generates the plurality of first initialization signals so that the voltage of the one first initialization signal during the light emission period is greater than or equal to the minimum value and less than or equal to the maximum value of the voltage of the control terminal of the driving transistor during the light emission period.

6. The display device described in claim 3, wherein the initialization signal generating circuit generates the plurality of first initialization signals so that the voltage of the one first initialization signal during the light emission period is approximately equal to the voltage of the control terminal of the driving transistor when the gradation of the pixel to be formed by each of the pixel circuits is at a black level.

7. The display device of claim 1, wherein each of the pixel circuits further includes an N-channel second initialization transistor as a switching element, the light-emitting control transistor has a first conduction terminal connected to the second conduction terminal of the drive transistor and a second conduction terminal connected to the display element, the second initialization transistor has a first conduction terminal connected to the second conduction terminal of the light-emitting control transistor and a second conduction terminal for receiving the one first initialization signal, and the drive circuit keeps the second initialization transistor in an on state during the initialization period and keeps the second initialization transistor in an off state during periods other than the initialization.

8. The display device according to claim 1, wherein each of the pixel circuits further includes an N-channel second initialization transistor as a switching element, the initialization signal generation circuit further generates a plurality of second initialization signals, the light emission control transistor has a first conduction terminal connected to the second conduction terminal of the drive transistor and a second conduction terminal connected to the display element, the second initialization transistor has a first conduction terminal connected to the second conduction terminal of the light emission control transistor and a second conduction terminal for receiving one second initialization signal of the plurality of second initialization signals, the drive circuit keeps the second initialization transistor in an on state during a period other than the light emission period and keeps the second initialization transistor in an off state during the light emission period, and the initialization signal generation circuit generates the plurality of first initialization signals such that a voltage of the one first initialization signal is higher in the period other than the initialization period than in the initialization period, and generates the plurality of second initialization signals such that a voltage of the one second initialization signal is higher in the light emission period than in the period other than the light emission period.

9. The display device of claim 8, wherein the initialization signal generating circuit generates the plurality of second initialization signals so that the voltage of the one second initialization signal during the light emission period is lower than the voltage used to turn on the second initialization transistor.

10. The display unit further includes a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of light emission control lines, a plurality of first initialization signal lines, and a plurality of data signal lines, and the drive circuit further includes: a scanning signal line drive circuit selectively driving the plurality of first scanning signal lines and selectively driving the plurality of second scanning signal lines, a light emission control circuit driving the plurality of light emission control lines so that the plurality of light emission control lines are selectively inactivated, and a data signal line drive circuit driving the plurality of data signal lines, and the first conduction terminal of the drive transistor is connected to one data signal line of the plurality of data signal lines via the write control transistor, and the control terminal of the drive transistor is connected to one first initialization signal line of the plurality of first initialization signal lines via the first initialization transistor, and the write control transistor further has a control terminal connected to one first scanning signal line of the plurality of first scanning signal lines, 5. The display device according to claim 1 , wherein the threshold compensation transistor is an N-channel transistor and has a control terminal connected to one second scanning signal line of the plurality of second scanning signal lines, the first initialization transistor has a control terminal connected to a preceding second scanning signal line selected before the one second scanning signal line of the plurality of second scanning signal lines, the light emission control transistor has a control terminal connected to one light emission control line of the plurality of light emission control lines, the scanning signal line drive circuit drives the plurality of first scanning signal lines and the plurality of second scanning signal lines such that the one first scanning signal line and the one second scanning signal line are in a selected state during the write period and the preceding second scanning signal line is in a selected state during the initialization period, and the light emission control circuit drives the plurality of light emission control lines such that the one light emission control line is in an activated state during the light emission period and in an inactivated state during the initialization period and the write period.

11. The display device of claim 10, wherein each of the pixel circuits further includes an N-channel second initialization transistor as a switching element having a control terminal connected to the preceding second scanning signal line, the light emission control transistor has a first conduction terminal connected to the second conduction terminal of the drive transistor and a second conduction terminal connected to the display element, and the second conduction terminal of the light emission control transistor is connected to the one first initialization signal line via the second initialization transistor.

12. The display device of claim 10, wherein the display unit further includes a plurality of second initialization signal lines, the initialization signal generating circuit further generates a plurality of second initialization signals and applies them to the plurality of second initialization signal lines, each of the pixel circuits further includes an N-channel type second initialization transistor as a switching element having a control terminal connected to the one of the light-emitting control lines, the light-emitting control transistor is a P-channel type transistor and has a first conduction terminal connected to the second conduction terminal of the drive transistor and a second conduction terminal connected to the display element, and the second conduction terminal of the light-emitting control transistor is connected to one of the plurality of second initialization signal lines via the second initialization transistor, and the initialization signal generating circuit generates the plurality of first initialization signals such that a voltage of the one of the first initialization signals is higher in a period other than the initialization period than in the initialization period, and generates the plurality of second initialization signals such that a voltage of the one of the second initialization signal lines is higher in the light-emitting period than in a period other than the light-emitting period.

13. A display device described in any one of claims 1 to 9, wherein the drive transistor is a thin-film transistor having a channel layer formed from low-temperature polysilicon, and the first initialization transistor and the threshold compensation transistor are thin-film transistors having channel layers formed from an oxide semiconductor.

14. A method for driving a display device having a display unit including a plurality of pixel circuits, comprising: a driving step for driving the plurality of pixel circuits, each pixel circuit comprising: a display element driven by a current; a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal, and arranged in series with the display element; a retention capacitor having one end connected to the control terminal of the drive transistor for retaining a voltage at the control terminal of the drive transistor; a write control transistor as a switching element having a first conduction terminal for receiving a data voltage to be written to the retention capacitor and a second conduction terminal connected to the first conduction terminal of the drive transistor; a threshold compensation transistor as a switching element arranged between the second conduction terminal and the control terminal of the drive transistor, and putting the drive transistor into a diode-connected state when in an on state; a light-emitting control transistor as a switching element arranged in series with the display element and the drive transistor; and an N-channel first initialization transistor as a switching element, the driving step comprising an initialization signal generating step for generating a plurality of first initialization signals, each of the pixel circuits is configured such that one first initialization signal of the plurality of first initialization signals is provided to the holding capacitor via the first initialization transistor, and the driving step further includes the steps of: during a write period in which the data voltage is to be written to the holding capacitor, turning on the write control transistor and the threshold compensation transistor and turning off the light emission control transistor and the first initialization transistor; during an initialization period before the write period in which a voltage of the control terminal of the drive transistor is to be initialized, turning on the first initialization transistor and turning off the light emission control transistor and the threshold compensation transistor; and during a light emission period after the write period in which a drive current corresponding to the hold voltage of the hold capacitor is to be supplied from the drive transistor to the display element, turning on the light emission control transistor and turning off the threshold compensation transistor and the first initialization transistor,The initialization signal generating step generates the plurality of first initialization signals so that a voltage of the one first initialization signal is higher in the light emission period than in the initialization period.

15. The driving method according to claim 14, wherein each of the pixel circuits further includes an N-channel second initialization transistor as a switching element, the initialization signal generating step further generates a plurality of second initialization signals, the light emission control transistor has a first conduction terminal connected to the second conduction terminal of the drive transistor and a second conduction terminal connected to the display element, the second initialization transistor has a first conduction terminal connected to the second conduction terminal of the light emission control transistor and a second conduction terminal for receiving one second initialization signal of the plurality of second initialization signals, the driving step further includes a step of turning on the second initialization transistor during a period other than the light emission period and turning off the second initialization transistor during the light emission period, and the initialization signal generating step generates the plurality of first initialization signals such that a voltage of the one first initialization signal is higher in the period other than the initial period than in the initialization period, and generates the plurality of second initialization signals such that a voltage of the one second initialization signal is higher and greater in the light emission period than in the period other than the light emission period.

16. The driving method described in claim 14 or 15, wherein the first initialization transistor has a first conduction terminal connected to the holding capacitor and a second conduction terminal that receives the one initialization signal, and the initialization signal generating step generates the plurality of first initialization signals so that a voltage of the one first initialization signal is not higher than a voltage of the first conduction terminal of the first initialization transistor.

17. A driving method as described in claim 14 or 15, wherein the initialization signal generation step generates the plurality of first initialization signals so that the voltage of the one first initialization signal during the light emission period is equal to or greater than the minimum value and equal to or less than the maximum value of the voltage of the control terminal of the driving transistor during the light emission period.

18. A driving method as described in claim 14 or 15, wherein the initialization signal generation step generates the plurality of first initialization signals so that the voltage of the one first initialization signal during the light emission period is approximately equal to the voltage of the control terminal of the driving transistor when the gradation of the pixel to be formed by each of the pixel circuits is at a black level.

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