Shift register, gate driving circuit, and driving method for shift register

Abstract

A shift register, a gate driving circuit, and a driving method for a shift register. The shift register comprises: a cascade output sub-circuit, an output control sub-circuit, and a scanning output sub-circuit, wherein the cascade output sub-circuit is configured to provide a signal of a first power supply end or a second power supply end to a cascade output end under the control of signals of an input end, a first clock signal end, a second clock signal end, a first node, a second node and a third node; the output control sub-circuit is configured to provide the signal of the first node to a fourth node and the signal of the second node to a fifth node under the control of signals of the first node, the third node and a first control signal end to a third control signal end; and the scanning output sub-circuit is configured to output the signal of the first power supply end or the second power supply end to a scanning signal output end under the control of signals of the fourth node and the fifth node.

Description

A shift register, a gate drive circuit and a shift register driving method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 11, 2023, with application number 202310849051.0 and invention name “A shift register, a gate drive circuit and a driving method for a shift register”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, display technology, and in particular to a shift register, a gate driving circuit, and a driving method of the shift register. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0006] In a first aspect, an embodiment of the present disclosure provides a shift register, comprising: a cascade output subcircuit, an output control subcircuit, and a scan output subcircuit;

[0007] The cascade output sub-circuit is electrically connected to the input terminal, the first clock signal terminal, the second clock signal line, the first power supply terminal, the second power supply terminal, the cascade output terminal, the first node, the second node, and the third node, respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of the signals from the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node;

[0008] The output control subcircuit is electrically connected to the first control signal terminal to the third control signal terminal, the first node, the second node, the third node, the fourth node, and the fifth node, respectively, and is configured to provide the signal of the first node to the fourth node and the signal of the second node to the fifth node under the control of the signals of the first node, the third node, and the first control signal terminal to the third control signal terminal;

[0009] The scan output sub-circuit is electrically connected to the fourth node, the fifth node, the scan signal output terminal, the first power supply terminal and the second power supply terminal, respectively, and is configured to output the signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of the signal of the fourth node and the fifth node.

[0010] In some possible implementations, the output control subcircuit includes: a first control subcircuit, a second control subcircuit, and a third control subcircuit;

[0011] The first control subcircuit is electrically connected to the first node, the third node, the sixth node, and the first control signal terminal to the third control signal terminal, respectively, and is configured to provide a signal from the second control signal terminal or the third control signal terminal to the sixth node under the control of the signals from the first node, the third node, and the first control signal terminal;

[0012] The second control subcircuit is electrically connected to the first node, the fourth node, and the sixth node, respectively, and is configured to provide the signal of the first node to the fourth node under the control of the signal of the sixth node;

[0013] The third control subcircuit is electrically connected to the second node, the fifth node, and the sixth node, respectively, and is configured to provide the signal of the second node to the fifth node under the control of the signal of the sixth node.

[0014] In some possible implementations, the first control subcircuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0015] The control electrode of the first transistor is electrically connected to the first control signal terminal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the third control signal terminal;

[0016] The control electrode of the second transistor is electrically connected to the third node, and the first electrode of the second transistor is electrically connected to the sixth node;

[0017] The control electrode of the third transistor is electrically connected to the first control signal terminal, the first electrode of the third transistor is electrically connected to the second control signal terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor;

[0018] A control electrode of the fourth transistor is electrically connected to the first node, and a second electrode of the fourth transistor is electrically connected to the sixth node.

[0019] In some possible implementations, the second control subcircuit includes: a fifth transistor;

[0020] The control electrode of the fifth transistor is electrically connected to the sixth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0021] In some possible implementations, the third control subcircuit includes: a sixth transistor;

[0022] The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0023] In some possible implementations, the output control subcircuit further includes: a storage subcircuit;

[0024] The storage sub-circuit is electrically connected to the fourth node and the sixth node, respectively, and is configured to store a voltage difference between the signal at the sixth node and the signal at the fourth node.

[0025] In some possible implementations, the storage subcircuit includes: a first capacitor including a first plate and a second plate;

[0026] The first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the fourth node.

[0027] In some possible implementations, the scan output subcircuit includes: a seventh transistor and an eighth transistor;

[0028] a control electrode of the seventh transistor electrically connected to the fourth node, a first electrode of the seventh transistor electrically connected to the first power supply terminal, and a second electrode of the seventh transistor electrically connected to the scan signal output terminal;

[0029] The control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the scan signal output terminal, and the second electrode of the eighth transistor is electrically connected to the second power supply terminal.

[0030] In some possible implementations, the scan output subcircuit further includes: a second capacitor, the second capacitor including a first plate and a second plate;

[0031] The first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

[0032] In some possible implementations, the cascade output subcircuit includes: ninth to twenty-fifth transistors, and third to sixth capacitors;

[0033] The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output terminal;

[0034] The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade output terminal;

[0035] a control electrode of the eleventh transistor electrically connected to the second power supply terminal, a first electrode of the eleventh transistor electrically connected to the seventh node, and a second electrode of the eleventh transistor electrically connected to the ninth node;

[0036] The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the second node, and the second electrode of the twelfth transistor is electrically connected to the third node;

[0037] The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second node;

[0038] A control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourteenth transistor is electrically connected to the input terminal, and a second electrode of the fourteenth transistor is electrically connected to the eighth node;

[0039] a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to the eighth node, and a second electrode of the fifteenth transistor electrically connected to the twelfth node;

[0040] a control electrode of the sixteenth transistor electrically connected to the twelfth node, a first electrode of the sixteenth transistor electrically connected to the third node, and a second electrode of the sixteenth transistor electrically connected to the twelfth node;

[0041] The control electrode of the seventeenth transistor is electrically connected to the first clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the input terminal, and the second electrode of the seventeenth transistor is electrically connected to the second node;

[0042] A control electrode of the eighteenth transistor is electrically connected to the second node, a first electrode of the eighteenth transistor is electrically connected to the first clock signal terminal, and a second electrode of the eighteenth transistor is electrically connected to the seventh node;

[0043] A control electrode of the nineteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the nineteenth transistor is electrically connected to the second power supply terminal, and a second electrode of the nineteenth transistor is electrically connected to the seventh node;

[0044] a control electrode of the twentieth transistor electrically connected to the second node, a first electrode of the twentieth transistor electrically connected to the second clock signal terminal, and a second electrode of the twentieth transistor electrically connected to the eleventh node;

[0045] a control electrode of the twenty-first transistor electrically connected to the seventh node, a first electrode of the twenty-first transistor electrically connected to the first power supply terminal, and a second electrode of the twenty-first transistor electrically connected to the eleventh node;

[0046] A control electrode of the twenty-second transistor is electrically connected to the ninth node, a first electrode of the twenty-second transistor is electrically connected to the second clock signal terminal, and a second electrode of the twenty-second transistor is electrically connected to the tenth node;

[0047] A control electrode of the twenty-third transistor is electrically connected to the second clock signal terminal, a first electrode of the twenty-third transistor is electrically connected to the tenth node, and a second electrode of the twenty-third transistor is electrically connected to the first node;

[0048] A control electrode of the twenty-fourth transistor is electrically connected to the second node, a first electrode of the twenty-fourth transistor is electrically connected to the first power supply terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the first node;

[0049] a control electrode of the twenty-fifth transistor electrically connected to the twelfth node, a first electrode of the twenty-fifth transistor electrically connected to the twelfth node, and a second electrode of the twenty-fifth transistor electrically connected to the fifth node;

[0050] The third capacitor includes a first plate and a second plate, the first plate of the third capacitor is electrically connected to the third node, and the second plate of the third capacitor is electrically connected to the eleventh node;

[0051] The fourth capacitor includes a first plate and a second plate, the first plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second plate of the fourth capacitor is electrically connected to the cascade output terminal;

[0052] The fifth capacitor includes a first plate and a second plate, the first plate of the fifth capacitor is electrically connected to the ninth node, and the second plate of the fifth capacitor is electrically connected to the tenth node;

[0053] The sixth capacitor includes a first plate and a second plate. The first plate of the sixth capacitor is electrically connected to the first node, and the second plate of the sixth capacitor is electrically connected to the first power supply terminal.

[0054] In some possible implementations, the cascade output subcircuit includes: ninth to twenty-fifth transistors, and third to sixth capacitors; the output control subcircuit includes: first to sixth transistors and a first capacitor; and the scan output subcircuit includes: a seventh transistor, an eighth transistor, and a second capacitor.

[0055] The control electrode of the first transistor is electrically connected to the first control signal terminal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the third control signal terminal;

[0056] The control electrode of the second transistor is electrically connected to the third node, and the first electrode of the second transistor is electrically connected to the sixth node;

[0057] The control electrode of the third transistor is electrically connected to the first control signal terminal, the first electrode of the third transistor is electrically connected to the second control signal terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor;

[0058] The control electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the sixth node;

[0059] a control electrode of the fifth transistor electrically connected to the sixth node, a first electrode of the fifth transistor electrically connected to the first node, and a second electrode of the fifth transistor electrically connected to the fourth node;

[0060] a control electrode of the sixth transistor electrically connected to the sixth node, a first electrode of the sixth transistor electrically connected to the second node, and a second electrode of the sixth transistor electrically connected to the fifth node;

[0061] a control electrode of the seventh transistor electrically connected to the fourth node, a first electrode of the seventh transistor electrically connected to the first power supply terminal, and a second electrode of the seventh transistor electrically connected to the scan signal output terminal;

[0062] a control electrode of the eighth transistor electrically connected to the fifth node, a first electrode of the eighth transistor electrically connected to the scan signal output terminal, and a second electrode of the eighth transistor electrically connected to the second power supply terminal;

[0063] The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output terminal;

[0064] The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade output terminal;

[0065] a control electrode of the eleventh transistor electrically connected to the second power supply terminal, a first electrode of the eleventh transistor electrically connected to the seventh node, and a second electrode of the eleventh transistor electrically connected to the ninth node;

[0066] The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the second node, and the second electrode of the twelfth transistor is electrically connected to the third node;

[0067] The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second node;

[0068] A control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourteenth transistor is electrically connected to the input terminal, and a second electrode of the fourteenth transistor is electrically connected to the eighth node;

[0069] a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to the eighth node, and a second electrode of the fifteenth transistor electrically connected to the twelfth node;

[0070] a control electrode of the sixteenth transistor electrically connected to the twelfth node, a first electrode of the sixteenth transistor electrically connected to the third node, and a second electrode of the sixteenth transistor electrically connected to the twelfth node;

[0071] The control electrode of the seventeenth transistor is electrically connected to the first clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the input terminal, and the second electrode of the seventeenth transistor is electrically connected to the second node;

[0072] A control electrode of the eighteenth transistor is electrically connected to the second node, a first electrode of the eighteenth transistor is electrically connected to the first clock signal terminal, and a second electrode of the eighteenth transistor is electrically connected to the seventh node;

[0073] A control electrode of the nineteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the nineteenth transistor is electrically connected to the second power supply terminal, and a second electrode of the nineteenth transistor is electrically connected to the seventh node;

[0074] a control electrode of the twentieth transistor electrically connected to the second node, a first electrode of the twentieth transistor electrically connected to the second clock signal terminal, and a second electrode of the twentieth transistor electrically connected to the eleventh node;

[0075] a control electrode of the twenty-first transistor electrically connected to the seventh node, a first electrode of the twenty-first transistor electrically connected to the first power supply terminal, and a second electrode of the twenty-first transistor electrically connected to the eleventh node;

[0076] A control electrode of the twenty-second transistor is electrically connected to the ninth node, a first electrode of the twenty-second transistor is electrically connected to the second clock signal terminal, and a second electrode of the twenty-second transistor is electrically connected to the tenth node;

[0077] A control electrode of the twenty-third transistor is electrically connected to the second clock signal terminal, a first electrode of the twenty-third transistor is electrically connected to the tenth node, and a second electrode of the twenty-third transistor is electrically connected to the first node;

[0078] A control electrode of the twenty-fourth transistor is electrically connected to the second node, a first electrode of the twenty-fourth transistor is electrically connected to the first power supply terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the first node;

[0079] a control electrode of the twenty-fifth transistor electrically connected to the twelfth node, a first electrode of the twenty-fifth transistor electrically connected to the twelfth node, and a second electrode of the twenty-fifth transistor electrically connected to the fifth node;

[0080] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the fourth node;

[0081] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal;

[0082] The third capacitor includes a first plate and a second plate, the first plate of the third capacitor is electrically connected to the third node, and the second plate of the third capacitor is electrically connected to the eleventh node;

[0083] The fourth capacitor includes a first plate and a second plate, the first plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second plate of the fourth capacitor is electrically connected to the cascade output terminal;

[0084] The fifth capacitor includes a first plate and a second plate, the first plate of the fifth capacitor is electrically connected to the ninth node, and the second plate of the fifth capacitor is electrically connected to the tenth node;

[0085] The sixth capacitor includes a first plate and a second plate. The first plate of the sixth capacitor is electrically connected to the first node, and the second plate of the sixth capacitor is electrically connected to the first power supply terminal.

[0086] In some possible implementations, the shift register is disposed on a display substrate, the display substrate includes: a plurality of scan signal lines, an operation process of the display substrate includes: a display phase and a blank phase located between the display phases; the display substrate includes: a plurality of display areas, refresh frequencies of different display areas include a first refresh frequency and a second refresh frequency, and the first refresh frequency is greater than the second refresh frequency;

[0087] When the working process of the display substrate is in a blank stage, when the signal of the first control signal terminal is a low level signal, the signals of the second control signal terminal and the third control signal terminal are low level signals;

[0088] When the display substrate is in a display phase and the shift register is connected to a scanning signal line in a display area at a first refresh frequency, when the signal at the first control signal terminal is a low-level signal, the signals at the second control signal terminal and the third control signal terminal are low-level signals;

[0089] When the operation process of the display substrate is in the display stage, the shift register is connected to the scanning signal line located in the display area of ​​the second refresh frequency, and the cascade output terminal of the shift register outputs a low-level signal, when the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal;

[0090] When the operation process of the display substrate is in the display phase, the shift register is connected to the scanning signal line located in the display area of ​​the second refresh frequency, and the cascade output terminal of the shift register outputs a high-level signal, when the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal;

[0091] When the operation process of the display substrate is in the display stage, the shift register is connected to the scanning signal line located in the display area of ​​the second refresh frequency, and the cascade output terminal of the shift register outputs a low-level signal, when the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal;

[0092] The duration of the signal at the first control signal terminal being a low level signal is shorter than the duration of the signal at any one of the second control signal terminal and the third control signal terminal being a low level signal.

[0093] In a second aspect, an embodiment of the present disclosure provides a gate drive circuit, comprising: a plurality of cascaded shift registers as described in any one of the first aspects;

[0094] The cascade output terminal of the i-th stage shift register is electrically connected to the input terminal of the i+1-th stage shift register, 1≤i≤M-1, and M is the total number of stages of the shift register.

[0095] In a third aspect, an embodiment of the present disclosure provides a method for driving a shift register, configured to drive the shift register according to any one of the first aspects, the method comprising:

[0096] The cascade output subcircuit provides a signal from the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of the signals from the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node;

[0097] The output control subcircuit provides the signal of the first node to the fourth node and the signal of the second node to the fifth node under the control of the first node, the third node and the signals from the first control signal terminal to the third control signal terminal;

[0098] The scan output sub-circuit outputs the signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of the signals of the fourth node and the fifth node.

[0099] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0100] Summary of the Figures

[0101] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0102] FIG1A is a schematic structural diagram of a shift register provided in an exemplary embodiment of the present disclosure;

[0103] FIG1B is a schematic structural diagram of a shift register provided in an exemplary embodiment of the present disclosure;

[0104] FIG2 is an equivalent circuit diagram of an output control subcircuit provided by an exemplary embodiment;

[0105] FIG3 is an equivalent circuit diagram of a first control subcircuit provided by an exemplary embodiment;

[0106] FIG4 is an equivalent circuit diagram of a second control subcircuit provided by an exemplary embodiment;

[0107] FIG5 is an equivalent circuit diagram of a third control subcircuit provided by an exemplary embodiment;

[0108] FIG6 is an equivalent circuit diagram of an output control subcircuit provided by an exemplary embodiment;

[0109] FIG7 is an equivalent circuit diagram of a storage sub-circuit provided by an exemplary embodiment;

[0110] FIG8 is an equivalent circuit diagram of a scan output subcircuit provided by an exemplary embodiment;

[0111] FIG9 is an equivalent circuit diagram of a scan output subcircuit provided by an exemplary embodiment;

[0112] FIG10 is an equivalent circuit diagram of a cascade output sub-circuit provided by an exemplary embodiment;

[0113] FIG11 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0114] FIG12A is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0115] FIG12B is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0116] FIG13 is an output waveform diagram of a shift register provided by an exemplary embodiment;

[0117] FIG14 is an operation timing diagram of a cascade output sub-circuit provided by an exemplary embodiment;

[0118] FIG15A is a schematic diagram of an equivalent circuit of a pixel circuit;

[0119] FIG15B is an operating timing diagram of the pixel circuit provided in FIG15A ;

[0120] FIG16A is a schematic diagram of an equivalent circuit of another pixel circuit;

[0121] FIG16B is an operation timing diagram of the pixel circuit provided in FIG16A .

[0122] Details

[0123] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0124] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0125] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0126] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0127] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0128] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0129] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0130] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0131] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0132] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0133] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0134] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0135] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0136] OLED display technology has the advantages of high contrast, fast response, and low power consumption. In order to reduce power consumption, low-temperature polysilicon (LTPS) and indium gallium zinc oxide (IGZO) are combined to realize low-temperature polycrystalline oxide (LTPO) display technology. LTPO can achieve low frame rate display and reduce driving power consumption by reducing the repeated refresh of static images. However, when the OLED display updates the screen, it is necessary to initialize and write all pixel voltages within one frame. In some special screens, such as always on display (AOD), static screens, or screens that are rarely updated, the voltages of most pixels on the entire screen do not need to be updated. At this time, the repeated writing of these pixels makes the display power consumption higher.

[0137] Figure 1A is a schematic diagram of the structure of a shift register provided in an exemplary embodiment of the present disclosure, and Figure 1B is a schematic diagram of the structure of a shift register provided in an exemplary embodiment of the present disclosure. As shown in Figures 1A and 1B, the shift register provided in an exemplary embodiment of the present disclosure may include: a cascade output subcircuit GOA, an output control subcircuit HRD, and a scan output subcircuit NGOA.

[0138] The cascade output sub-circuit is electrically connected to the input terminal SIN, the first clock signal terminal CK1, the second clock signal line CK2, the first power supply terminal V1, the second power supply terminal V2, the cascade output terminal SOUT, the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide the signal of the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of the signals of the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node and the third node.

[0139] The output control subcircuit is electrically connected to the first control signal terminal MS1 to the third control signal terminal MS3, the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5, respectively, and is configured to provide the signal of the first node to the fourth node and the signal of the second node to the fifth node under the control of the first node, the third node and the signals from the first control signal terminal to the third control signal terminal.

[0140] The scan output sub-circuit is electrically connected to the fourth node N4, the fifth node N5, the scan signal output terminal OUT, the first power supply terminal V1 and the second power supply terminal V2, respectively, and is configured to output the signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of the signal of the fourth node and the fifth node.

[0141] The cascade output sub-circuit GOA, under the control of the input terminal SIN, the first clock signal terminal CK1, and the second clock signal line CK2, outputs a cascade output terminal SOUT signal. The cascade output terminal SOUT signal is the first power supply terminal V1 or the second power supply terminal V2. The output control sub-circuit HRD, under the control of the first to third control signal terminals MS1 to MS3, can select whether to transmit the first power supply terminal V1 or the second power supply terminal V2 signal. If the first to third control signal terminals MS1 to MS3 select the first power supply terminal V1 signal to be transmitted, the first power supply terminal V1 signal is input to the scan output sub-circuit NGOA, and the scan signal output terminal OUT signal output by the scan output sub-circuit NGOA is the first power supply terminal V1. If the second power supply terminal V2 signal is transmitted under the control of the first to third control signal terminals MS1 to MS3, the cascade output terminal SOUT signal of the second power supply terminal V2 is input to the scan output sub-circuit NGOA, and the scan signal output terminal OUT signal output by the scan output sub-circuit NGOA is the second power supply terminal V2.

[0142] In an exemplary embodiment, the first power supply terminal V1 continuously provides a high-level signal, and the second power supply terminal V2 continuously provides a low-level signal.

[0143] In an exemplary embodiment, the first clock signal terminal CK1 and the second clock signal line CK2 may be periodic pulse signals.

[0144] The shift register provided in the embodiments of the present disclosure includes: a cascade output subcircuit, an output control subcircuit, and a scan output subcircuit. The shift register is electrically connected to an input terminal SIN, a first clock signal terminal CK1, a second clock signal line CK2, a first power supply terminal V1, a second power supply terminal V2, a scan signal output terminal OUT, and first to third control signal terminals MS1 to MS3. The cascade output subcircuit provides a signal from the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of signals from the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node. The output control subcircuit provides a signal from the first node to the fourth node and a signal from the second node to the fifth node under the control of signals from the first node, the third node, and the first to third control signal terminals. The scan output subcircuit outputs a signal from the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of signals from the fourth and fifth nodes. By providing the output control subcircuit, the embodiments of the present disclosure can control whether the scan signal output terminal of the scan output subcircuit outputs, thereby reducing power consumption.

[0145] Figure 2 is an equivalent circuit diagram of an output control subcircuit provided by an exemplary embodiment. As shown in Figure 2, in an exemplary embodiment, the output control subcircuit may include: a first control subcircuit, a second control subcircuit, and a third control subcircuit.

[0146] In an exemplary embodiment, as shown in FIG2 , a first control subcircuit is electrically connected to a first node N1, a third node N3, a sixth node N6, and first to third control signal terminals MS1 to MS3, respectively, and is configured to provide a signal from a second control signal terminal MS2 or a third control signal terminal MS3 to the sixth node under control of signals from the first node, the third node, and the first control signal terminal. A second control subcircuit is electrically connected to a first node N1, a fourth node N4, and a sixth node N6, respectively, and is configured to provide a signal from the first node to the fourth node under control of a signal from the sixth node. A third control subcircuit is electrically connected to a second node N2, a fifth node N5, and a sixth node N6, respectively, and is configured to provide a signal from the second node to the fifth node under control of a signal from the sixth node.

[0147] An exemplary structure of the output control subcircuit is shown in Figure 2. Those skilled in the art will readily appreciate that the implementation of the output control subcircuit is not limited thereto.

[0148] Figure 3 is an equivalent circuit diagram of a first control subcircuit provided by an exemplary embodiment. As shown in Figure 3, in an exemplary embodiment, the first control subcircuit may include: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0149] In an exemplary embodiment, as shown in FIG3 , the control electrode of the first transistor T1 is electrically connected to the first control signal terminal MS1, the first electrode of the first transistor T1 is electrically connected to the second electrode of the second transistor T2, and the second electrode of the first transistor T1 is electrically connected to the third control signal terminal MS3. The control electrode of the second transistor T2 is electrically connected to the third node N3, and the first electrode of the second transistor T2 is electrically connected to the sixth node N6. The control electrode of the third transistor T3 is electrically connected to the first control signal terminal MS1, the first electrode of the third transistor T3 is electrically connected to the second control signal terminal MS2, and the second electrode of the third transistor T3 is electrically connected to the first electrode of the fourth transistor T4. The control electrode of the fourth transistor is electrically connected to the first node N1, and the second electrode of the fourth transistor is electrically connected to the sixth node N6.

[0150] An exemplary structure of the first control sub-circuit is shown in Figure 3. Those skilled in the art will readily appreciate that the implementation of the first control sub-circuit is not limited thereto.

[0151] Fig. 4 is an equivalent circuit diagram of a second control subcircuit provided by an exemplary embodiment. As shown in Fig. 4, in an exemplary embodiment, the second control subcircuit may include: a fifth transistor T5.

[0152] In an exemplary embodiment, as shown in FIG4 , the control electrode of the fifth transistor T5 is electrically connected to the sixth node N6 , the first electrode of the fifth transistor T5 is electrically connected to the first node N1 , and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4 .

[0153] An exemplary structure of the second control sub-circuit is shown in Figure 4. Those skilled in the art will readily appreciate that the implementation of the second control sub-circuit is not limited thereto.

[0154] Fig. 5 is an equivalent circuit diagram of a third control sub-circuit provided in an exemplary embodiment. As shown in Fig. 5 , in an exemplary embodiment, the third control sub-circuit includes: a sixth transistor T6.

[0155] In an exemplary embodiment, as shown in FIG5 , the control electrode of the sixth transistor T6 is electrically connected to the sixth node N6 , the first electrode of the sixth transistor T6 is electrically connected to the second node N2 , and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5 .

[0156] An exemplary structure of the third control sub-circuit is shown in Figure 5. Those skilled in the art will readily appreciate that the implementation of the third control sub-circuit is not limited thereto.

[0157] Fig. 6 is an equivalent circuit diagram of an output control subcircuit provided by an exemplary embodiment. As shown in Fig. 6, in an exemplary embodiment, the output control subcircuit may further include: a storage subcircuit.

[0158] In an exemplary embodiment, as shown in FIG. 6 , the storage sub-circuit is electrically connected to the fourth node N4 and the sixth node N6 , respectively, and is configured to store a voltage difference between the signals at the sixth node and the fourth node.

[0159] An exemplary structure of the output control subcircuit is shown in Figure 6. Those skilled in the art will readily appreciate that the implementation of the output control subcircuit is not limited thereto.

[0160] Figure 7 is an equivalent circuit diagram of a storage sub-circuit provided by an exemplary embodiment. As shown in Figure 7, in an exemplary embodiment, the storage sub-circuit may include: a first capacitor C1, the first capacitor including a first plate C11 and a second plate C12.

[0161] In an exemplary embodiment, as shown in FIG7 , the first plate C11 of the first capacitor C1 is electrically connected to the sixth node N6 , and the second plate C12 of the first capacitor C1 is electrically connected to the fourth node N4 .

[0162] Fig. 8 is an equivalent circuit diagram of a scan output sub-circuit provided by an exemplary embodiment. As shown in Fig. 8 , in an exemplary embodiment, the scan output sub-circuit may include: a seventh transistor T7 and an eighth transistor T8.

[0163] In an exemplary embodiment, as shown in FIG8 , a control electrode of the seventh transistor T7 is electrically connected to the fourth node N4, a first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1, and a second electrode of the seventh transistor T7 is electrically connected to the scan signal output terminal OUT. A control electrode of the eighth transistor T8 is electrically connected to the fifth node N5, a first electrode of the eighth transistor T8 is electrically connected to the scan signal output terminal OUT, and a second electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2.

[0164] An exemplary structure of the scan output sub-circuit is shown in Figure 8. Those skilled in the art will readily appreciate that the implementation of the scan output sub-circuit is not limited thereto.

[0165] Figure 9 is an equivalent circuit diagram of a scan output subcircuit provided by an exemplary embodiment. As shown in Figure 9, in an exemplary embodiment, the scan output subcircuit may further include: a second capacitor C2, the second capacitor including a first plate C21 and a second plate C22.

[0166] In an exemplary embodiment, as shown in FIG9 , the first plate C21 of the second capacitor C2 is electrically connected to the fourth node N4 , and the second plate C22 of the second capacitor C2 is electrically connected to the first power terminal V1 .

[0167] An exemplary structure of the scan output sub-circuit is shown in Figure 9. Those skilled in the art will readily appreciate that the implementation of the scan output sub-circuit is not limited thereto.

[0168] Figure 10 is an equivalent circuit diagram of a cascade output sub-circuit provided by an exemplary embodiment. As shown in Figure 10, in an exemplary embodiment, the cascade output sub-circuit may include: ninth transistor T9 to twenty-fifth transistor T25, and third capacitor C3 to sixth capacitor C6.

[0169] In an exemplary embodiment, as shown in FIG10 , the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade output terminal SOUT. The control electrode of the tenth transistor T10 is electrically connected to the third node N3, the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the cascade output terminal SOUT. The control electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal V2, the first electrode of the eleventh transistor T11 is electrically connected to the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected to the ninth node N9. The control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2, the first electrode of the twelfth transistor T12 is electrically connected to the second node N2, and the second electrode of the twelfth transistor T12 is electrically connected to the third node N3. The control electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal V3, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1, and the second electrode of the thirteenth transistor T13 is electrically connected to the second node N2. The control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK1, the first electrode of the fourteenth transistor T14 is electrically connected to the input terminal SIN, and the second electrode of the fourteenth transistor T14 is electrically connected to the eighth node N8. The control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal V2, the first electrode of the fifteenth transistor T15 is electrically connected to the eighth node N8, and the second electrode of the fifteenth transistor T15 is electrically connected to the twelfth node N12. The control electrode of the sixteenth transistor T16 is electrically connected to the twelfth node N12, the first electrode of the sixteenth transistor T16 is electrically connected to the third node N3, and the second electrode of the sixteenth transistor T16 is electrically connected to the twelfth node N12. The control electrode of the seventeenth transistor T17 is electrically connected to the first clock signal terminal CK1, the first electrode of the seventeenth transistor T17 is electrically connected to the input terminal SIN, and the second electrode of the seventeenth transistor T17 is electrically connected to the second node N2. The control electrode of the eighteenth transistor T18 is electrically connected to the second node N2, the first electrode of the eighteenth transistor T18 is electrically connected to the first clock signal terminal CK1, and the second electrode of the eighteenth transistor T18 is electrically connected to the seventh node N7. The control electrode of the nineteenth transistor T19 is electrically connected to the first clock signal terminal CK1, the first electrode of the nineteenth transistor T19 is electrically connected to the second power supply terminal V2, and the second electrode of the nineteenth transistor T19 is electrically connected to the seventh node N7. The control electrode of the twentieth transistor T20 is electrically connected to the second node N2, the first electrode of the twentieth transistor T20 is electrically connected to the second clock signal terminal CK2, and the second electrode of the twentieth transistor T20 is electrically connected to the eleventh node N11. A control electrode of the twenty-first transistor T21 is electrically connected to the seventh node N7 , a first electrode of the twenty-first transistor T21 is electrically connected to the first power supply terminal V1 , and a second electrode of the twenty-first transistor T21 is electrically connected to the eleventh node N11 .The control electrode of the twenty-second transistor T22 is electrically connected to the ninth node N9, the first electrode of the twenty-second transistor T22 is electrically connected to the second clock signal terminal CK2, and the second electrode of the twenty-second transistor T22 is electrically connected to the tenth node N10. The control electrode of the twenty-third transistor T23 is electrically connected to the second clock signal terminal CK2, the first electrode of the twenty-third transistor T23 is electrically connected to the tenth node N10, and the second electrode of the twenty-third transistor T23 is electrically connected to the first node N1. The control electrode of the twenty-fourth transistor T24 is electrically connected to the second node N2, the first electrode of the twenty-fourth transistor T24 is electrically connected to the first power supply terminal V1, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the first node N1. The control electrode of the twenty-fifth transistor T25 is electrically connected to the twelfth node N12, the first electrode of the twenty-fifth transistor T25 is electrically connected to the twelfth node N12, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the fifth node N5. The first plate C31 of the third capacitor C3 is electrically connected to the third node N3, and the second plate C32 of the third capacitor C3 is electrically connected to the eleventh node N11. The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 of the fourth capacitor C4 is electrically connected to the second power supply terminal V2, and the second plate C42 of the fourth capacitor C4 is electrically connected to the cascade output terminal SOUT. The first plate C51 of the fifth capacitor C5 is electrically connected to the ninth node N9, and the second plate C52 of the fifth capacitor C5 is electrically connected to the tenth node N10. The first plate C61 of the sixth capacitor C6 is electrically connected to the first node N1, and the second plate C62 of the sixth capacitor C6 is electrically connected to the first power supply terminal V1.

[0170] An exemplary structure of a cascade output subcircuit with a shift register model of 16T3C is shown in Figure 10. Those skilled in the art will readily appreciate that the implementation of the cascade output subcircuit is not limited thereto.

[0171] In an exemplary embodiment, the shift register model may be 12T3C. When the shift register model is 12T3C, the cascade output subcircuit may include the ninth transistor T9 to the thirteenth transistor T13 and the seventeenth transistor T17 to the twenty-third transistor T23 in FIG. 10 or FIG. 11 .

[0172] In an exemplary embodiment, the shift register model may be 10T3C. When the shift register model is 10T3C, the cascade output sub-circuit may include: a ninth transistor T9 to a twelfth transistor T12, and a seventeenth transistor T17 to a twenty-second transistor T22.

[0173] In an exemplary embodiment, the first transistor T1 to the twenty-fifth transistor T25 may be hexagonal transistors or N-type transistors.

[0174] In an exemplary embodiment, the first power supply terminal V1 continuously provides a high level signal and the second power supply terminal V2 continuously provides a low level signal. Since the second power supply terminal V2 continuously provides a low level signal, the eleventh transistor T11, the twelfth transistor T12 and the fifteenth transistor T15 are continuously turned on.

[0175] In one exemplary embodiment, the third power supply terminal V3 provides a low-level signal during the power-on initialization phase to prevent the ninth transistor T9 and the tenth transistor T10 of the final-stage control shift register from being simultaneously turned on due to output signal delay. Alternatively, the third power supply terminal V3 provides a low-level signal during an abnormal shutdown phase to prevent the ninth transistor T9 and the tenth transistor T10 from being simultaneously turned on. The third power supply terminal V3 continuously provides a high-level signal during the normal display phase, meaning that the thirteenth transistor T13 is continuously turned off during the normal display phase.

[0176] Figure 11 is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment. As shown in Figure 11 , in one exemplary embodiment, the shift register may include a cascade output subcircuit, an output control subcircuit, and a scan output subcircuit. The cascade output subcircuit may include transistors T9 through T25, and capacitors C3 through C6; the output control subcircuit may include transistors T1 through T6, and a first capacitor C1; and the scan output subcircuit may include transistors T7, T8, and C2.

[0177] In an exemplary embodiment, as shown in FIG11 , the control electrode of the first transistor T1 is electrically connected to the first control signal terminal MS1, the first electrode of the first transistor T1 is electrically connected to the second electrode of the second transistor T2, and the second electrode of the first transistor T1 is electrically connected to the third control signal terminal MS3. The control electrode of the second transistor T2 is electrically connected to the third node N3, and the first electrode of the second transistor T2 is electrically connected to the sixth node N6. The control electrode of the third transistor T3 is electrically connected to the first control signal terminal MS1, the first electrode of the third transistor T3 is electrically connected to the second control signal terminal MS2, and the second electrode of the third transistor T3 is electrically connected to the first electrode of the fourth transistor T4. The control electrode of the fourth transistor is electrically connected to the first node N1, and the second electrode of the fourth transistor is electrically connected to the sixth node N6. The control electrode of the fifth transistor T5 is electrically connected to the sixth node N6, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. The control electrode of the sixth transistor T6 is electrically connected to the sixth node N6, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. The control electrode of the seventh transistor T7 is electrically connected to the fourth node N4, the first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1, and the second electrode of the seventh transistor T7 is electrically connected to the scan signal output terminal OUT. The control electrode of the eighth transistor T8 is electrically connected to the fifth node N5, the first electrode of the eighth transistor T8 is electrically connected to the scan signal output terminal OUT, and the second electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2. The control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade output terminal SOUT. The control electrode of the tenth transistor T10 is electrically connected to the third node N3, the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the cascade output terminal SOUT. The control electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal V2, the first electrode of the eleventh transistor T11 is electrically connected to the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected to the ninth node N9. The control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2, the first electrode of the twelfth transistor T12 is electrically connected to the second node N2, and the second electrode of the twelfth transistor T12 is electrically connected to the third node N3. The control electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal V3, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1, and the second electrode of the thirteenth transistor T13 is electrically connected to the second node N2. The control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK1, the first electrode of the fourteenth transistor T14 is electrically connected to the input terminal SIN, and the second electrode of the fourteenth transistor T14 is electrically connected to the eighth node N8.A control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal V2, a first electrode of the fifteenth transistor T15 is electrically connected to the eighth node N8, and a second electrode of the fifteenth transistor T15 is electrically connected to the twelfth node N12. A control electrode of the sixteenth transistor T16 is electrically connected to the twelfth node N12, a first electrode of the sixteenth transistor T16 is electrically connected to the third node N3, and a second electrode of the sixteenth transistor T16 is electrically connected to the twelfth node N12. A control electrode of the seventeenth transistor T17 is electrically connected to the first clock signal terminal CK1, a first electrode of the seventeenth transistor T17 is electrically connected to the input terminal SIN, and a second electrode of the seventeenth transistor T17 is electrically connected to the second node N2. A control electrode of the eighteenth transistor T18 is electrically connected to the second node N2, a first electrode of the eighteenth transistor T18 is electrically connected to the first clock signal terminal CK1, and a second electrode of the eighteenth transistor T18 is electrically connected to the seventh node N7. The control electrode of the nineteenth transistor T19 is electrically connected to the first clock signal terminal CK1, the first electrode of the nineteenth transistor T19 is electrically connected to the second power supply terminal V2, and the second electrode of the nineteenth transistor T19 is electrically connected to the seventh node N7. The control electrode of the twentieth transistor T20 is electrically connected to the second node N2, the first electrode of the twentieth transistor T20 is electrically connected to the second clock signal terminal CK2, and the second electrode of the twentieth transistor T20 is electrically connected to the eleventh node N11. The control electrode of the twenty-first transistor T21 is electrically connected to the seventh node N7, the first electrode of the twenty-first transistor T21 is electrically connected to the first power supply terminal V1, and the second electrode of the twenty-first transistor T21 is electrically connected to the eleventh node N11. The control electrode of the twenty-second transistor T22 is electrically connected to the ninth node N9, the first electrode of the twenty-second transistor T22 is electrically connected to the second clock signal terminal CK2, and the second electrode of the twenty-second transistor T22 is electrically connected to the tenth node N10. The control electrode of the twenty-third transistor T23 is electrically connected to the second clock signal terminal CK2, the first electrode of the twenty-third transistor T23 is electrically connected to the tenth node N10, and the second electrode of the twenty-third transistor T23 is electrically connected to the first node N1. The control electrode of the twenty-fourth transistor T24 is electrically connected to the second node N2, the first electrode of the twenty-fourth transistor T24 is electrically connected to the first power supply terminal V1, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the first node N1. The control electrode of the twenty-fifth transistor T25 is electrically connected to the twelfth node N12, the first electrode of the twenty-fifth transistor T25 is electrically connected to the twelfth node N12, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the fifth node N5. The first plate C11 of the first capacitor C1 is electrically connected to the sixth node N6, and the second plate C12 of the first capacitor C1 is electrically connected to the fourth node N4. The first plate C21 of the second capacitor C2 is electrically connected to the fourth node N4, and the second plate C22 of the second capacitor C2 is electrically connected to the first power supply terminal V1.The first plate C31 of the third capacitor C3 is electrically connected to the third node N3, and the second plate C32 of the third capacitor C3 is electrically connected to the eleventh node N11. The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 of the fourth capacitor C4 is electrically connected to the second power supply terminal V2, and the second plate C42 of the fourth capacitor C4 is electrically connected to the cascade output terminal SOUT. The first plate C51 of the fifth capacitor C5 is electrically connected to the ninth node N9, and the second plate C52 of the fifth capacitor C5 is electrically connected to the tenth node N10. The first plate C61 of the sixth capacitor C6 is electrically connected to the first node N1, and the second plate C62 of the sixth capacitor C6 is electrically connected to the first power supply terminal V1.

[0178] An exemplary structure of a shift register model 16T3C is shown in Figure 11. Those skilled in the art will readily appreciate that the implementation of the shift register is not limited thereto.

[0179] In an exemplary embodiment, the shift register model may be 12T3C. When the shift register model is 12T3C, the cascade output subcircuit may include the ninth transistor T9 to the thirteenth transistor T13 and the seventeenth transistor T17 to the twenty-third transistor T23 in FIG. 10 or FIG. 11 .

[0180] In an exemplary embodiment, the shift register model may be 10T3C. When the shift register model is 10T3C, the cascade output sub-circuit may include: a ninth transistor T9 to a twelfth transistor T12, and a seventeenth transistor T17 to a twenty-second transistor T22.

[0181] In an exemplary embodiment, a shift register is arranged on a display substrate, and the display substrate may include: a plurality of scanning signal lines, and the working process of the display substrate may include: a display stage and a blank stage located between the display stages; the display substrate may include: a plurality of display areas, and the refresh frequencies of different display areas include a first refresh frequency and a second refresh frequency, and the first refresh frequency is greater than the second refresh frequency.

[0182] When the working process of the display substrate is in a blank stage, when the signal of the first control signal terminal MS1 is a low level signal, the signals of the second control signal terminal MS2 and the third control signal terminal MS3 are low level signals.

[0183] When the working process of the display substrate is the display stage and the shift register is connected to the scanning signal line of the display area located at the first refresh frequency, when the signal of the first control signal terminal MS1 is a low level signal, the signals of the second control signal terminal MS2 and the third control signal terminal MS3 are low level signals.

[0184] When the working process of the display substrate is the display stage, the shift register is connected to the scanning signal line of the display area located at the second refresh frequency, and the cascade output terminal SOUT of the shift register outputs a low-level signal, when the signal of the first control signal terminal MS1 is a low-level signal, the signal of the second control signal terminal MS2 is a high-level signal, and the signal of the third control signal terminal MS3 is a low-level signal.

[0185] When the working process of the display substrate is the display stage, the shift register is connected to the scanning signal line of the display area located at the second refresh frequency, and the cascade output terminal SOUT of the shift register outputs a high-level signal, when the signal of the first control signal terminal MS1 is a low-level signal, the signal of the second control signal terminal MS2 is a high-level signal, and the signal of the third control signal terminal is a low-level signal.

[0186] When the working process of the display substrate is the display stage, the shift register is connected to the scanning signal line of the display area located at the second refresh frequency, and the cascade output end of the shift register outputs a low-level signal, when the signal at the first control signal end is a low-level signal, the signal at the second control signal end is a high-level signal, and the signal at the third control signal end is a low-level signal.

[0187] The duration of the signal at the first control signal terminal MS1 being a low level signal is shorter than the duration of the signal at any one of the second control signal terminal MS2 and the third control signal terminal MS3 being a low level signal.

[0188] Figure 12A is an operating timing diagram of a shift register provided by an exemplary embodiment. The exemplary embodiment of the present disclosure is illustrated below through the operating process of the shift register illustrated in Figure 11, taking the first transistor T1 to the eighth transistor T8, the first capacitor C1, the second capacitor C2, the first control signal terminal MS1 to the third control signal terminal MS3, the first node N1 to the fourth node N4 and the scan signal output terminal OUT in the shift register provided in Figure 11 as an example.

[0189] In an exemplary embodiment, as shown in FIG12A , the operation process of the shift register may include:

[0190] Phase S1 (initialization phase): The signal at the first node N1 is a high-level signal, while the signals at the third node N3, the first control signal MS1, the second control signal MS2, and the third control signal MS3 are low-level signals. The signal at the first control signal MS1 is a low-level signal, the first transistor T1 is turned on, the signal at the third node N3 is a low-level signal, the second transistor T2 is turned on, and the low-level signal of the third control signal MS3 is written to the sixth node N6 via the turned-on first and second transistors T1 and T2. The signal at the sixth node N6 is a low-level signal and is maintained by the first capacitor C1. The fifth and sixth transistors T5 and T6 are turned on. The high-level signal at the first node N1 is written to the fourth node N4 via the turned-on fifth transistor T5. At this time, the seventh transistor T7 is turned off, and the low-level signal at the third node N3 is written to the fifth node N5 via the turned-on sixth transistor T6. At this time, the eighth transistor T8 is turned on, and the low-level signal V2 is written to the scan signal output terminal OUT. The output signal of the scan signal output terminal OUT is a low-level signal.

[0191] Phase S21 (low-frequency region cascade output terminal SOUT output is low): The signals of the first node N1 and the second control signal MS2 are high-level signals, and the signals of the third node N3, the first control signal MS1, and the third control signal MS3 are low-level signals. The first control signal MS1 is a low-level signal, the first transistor T1 is turned on, the third node N3 is low-level, the second transistor T2 is turned on, and the low-level signal of the third control signal MS3 is written to the sixth node N6 through the turned-on first transistor T1 and second transistor T2. The signal of the sixth node N6 is a low-level signal and is maintained by the first capacitor C1. The fifth transistor T5 and the sixth transistor T6 are turned on. The high-level signal of the first node N1 is written to the fourth node N4 through the turned-on fifth transistor T5. At this time, the seventh transistor T7 is turned off, and the low-level signal of the third node N3 is written to the fifth node N5 through the turned-on sixth transistor T6. At this time, the eighth transistor T8 is turned on, and the low-level signal of V2 is written to the scan signal output terminal OUT. The output signal of the scan signal output terminal OUT is a low-level signal.

[0192] Phase S22 (low-frequency region cascade output terminal SOUT output is high): The signals of the first node N1, the first control signal MS1, and the third control signal MS3 are low-level signals, and the signals of the third node N3 and the second control signal MS2 are high-level signals. The signal of the first control signal MS1 is a low-level signal, the third transistor T3 is turned on, the signal of the first node N1 is a low-level signal, the fourth transistor T4 is turned on, and the high-level signal of the second control signal MS2 is written to the sixth node N6 through the turned-on third transistor T3 and fourth transistor T4. The signal of the sixth node N6 is a high-level signal and is maintained by the first capacitor C1. The fourth node N4 is maintained at the high-level signal of the previous stage by the second capacitor C2. At this time, the seventh transistor T7 is turned off. The fifth node N5 maintains a low-level signal. At this time, the eighth transistor T8 is turned on, and the low-level signal of V2 is written to the scan signal output terminal OUT. The output signal of the scan signal output terminal OUT is a low-level signal.

[0193] Phase S31 (high-frequency region cascade output terminal SOUT output is high): The signals at the first node N1, the first control signal MS1, the second control signal MS2, and the third control signal MS3 are low-level signals, and the signal at the third node N3 is high-level. The first control signal MS1 is low-level, the third transistor T3 is turned on, the first node N1 is low-level, the fourth transistor T4 is turned on, and the low-level signal of the second control signal MS2 is written to the sixth node N6 through the turned-on third and fourth transistors T3 and T4. The signal at the sixth node N6 is low-level and maintained by the first capacitor C1. The fifth and sixth transistors T5 and T6 are turned on. The high-level signal at the third node N3 is written to the fifth node N5 through the turned-on sixth transistor T6. At this time, the eighth transistor T8 is turned off. The low-level signal at the first node N1 is written to the fourth node N4 through the turned-on fifth transistor T5. At this time, the seventh transistor T7 is turned on, and the high-level signal at the first power supply terminal V1 is written to the scan signal output terminal OUT. The output signal of the scan signal output terminal OUT is a high-level signal.

[0194] Phase S32 (high-frequency region cascade output terminal SOUT outputs a low level): The signal at the first node N1 is a high-level signal, while the signals at the third node N3, the first control signal MS1, the second control signal MS2, and the third control signal MS3 are low-level signals. The first control signal MS1 is a low-level signal, the first transistor T1 is turned on, the third node N3 is low-level, the second transistor T2 is turned on, and the low-level signal of the third control signal MS3 is written to the sixth node N6 through the turned-on first transistor T1 and the second transistor T2. The signal at the sixth node N6 is a low-level signal and is maintained by the first capacitor C1. The fifth transistor T5 and the sixth transistor T6 are turned on. The high-level signal at the first node N1 is written to the fourth node N4 through the turned-on fifth transistor T5. At this time, the seventh transistor T7 is turned off, and the low-level signal at the third node N3 is written to the fifth node N5 through the turned-on sixth transistor T6. At this time, the eighth transistor T8 is turned on, and the low-level signal of V2 is written to the scan signal output terminal OUT. The output signal of the scan signal output terminal OUT is a low-level signal.

[0195] Figure 12B is a working timing diagram of a shift register provided by an exemplary embodiment. The exemplary embodiment of the present disclosure is illustrated below through the working process of the shift register illustrated in Figure 11. Taking the first transistor T1 to the eighth transistor T8, the first capacitor C1, the second capacitor C2, the first control signal terminal MS1 to the third control signal terminal MS3 and the scan signal output terminal OUT in the shift register provided in Figure 11 as an example, the scan signal output terminal OUT includes scan signal output terminals Nout1...Noutn, Noutn+1, Nout...Nout m, Nout m+1, Nout m+2...Nout k of different frames.

[0196] In one exemplary embodiment, as shown in FIG12B , by varying the voltage of control signals MS (first control signal MS1, second control signal MS2, and third control signal MS3), it is possible to control whether a low-level scan signal output terminal OUT is output. This allows for controlling the high-level output of the scan signal output terminal within a frame, updating the data voltage Vdata for some rows, and controlling partial image refreshes across different frames, thereby reducing power consumption of the display panel. The scan signal output terminals for other rows remain at a low level, preventing repeated charging and discharging of the initial signal line and data voltage Vdata, thus saving power.

[0197] In an exemplary embodiment, as shown in FIG12B , the operation process of the shift register can be divided into three stages:

[0198] Initialization Phase: During the second-to-last row of the initialization frame, the first pulse of the first control signal terminal MS1 is turned on. At this point, the third node N3 is at a low level, and the first node N1 is at a high level. The first and second transistors T1 and T2 are turned on, and the fourth transistor T4 is turned off. The low level signal from the third control signal terminal MS3 is written to the third node N3 and maintained by the first capacitor C1. The fifth and sixth transistors T5 and T6 are turned on, connecting the first node N1 to the fourth node N4, and the second node N2 to the fifth node N5. Scan signal output terminals Nout1…Noutn, Noutn+1, Nout…Noutm, Noutm+1, Noutm+2…Noutk for different frames can then be output normally.

[0199] High-Frequency to Low-Frequency Phase: During the last line of the high-frequency region frame, the second pulse of the first control signal MS1 is on. If the cascade output terminal Sout outputs a low-level signal, that is, the first node N1 is a high-level signal and the third node N3 is a low-level signal, the first transistor T1 and the second transistor T2 are turned on, and the high-level signal of the third control signal MS3 is written to the sixth node N6. The fifth transistor T5 and the sixth transistor T6 are turned off, the fourth node N4 maintains a high-level signal, and the fifth node N5 maintains a low-level signal. This maintains the corresponding scanning signal output terminals Nout1...Noutn, Noutn+1, Nout...Noutm, Noutm+1, Noutm+2,...Noutk of different frames at low-level signals. If the cascade output terminal Sout outputs a high-level signal, that is, the first node N1 is a low-level signal and the third node N3 is a high-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the low-level signal of the second control signal MS2 is written to the sixth node N6, which is held by the first capacitor C1. The fifth transistor T5 and the sixth transistor T6 are turned on, the fourth node N4 still maintains a low-level signal, and the fifth node N5 still maintains a high-level signal. The scanning signal output terminals Nout1...Noutn, Noutn+1, Nout...Nout m, Nout m+1, Nout m+2...Nout k of different frames can still output high-level signals. When the cascade output terminal Sout output switches to a low level, the scanning signal output terminals Nout1...Noutn, Noutn+1, Nout...Nout m, Nout m+1, Nout m+2...Nout k of different frames can output low-level signals. In other words, at this time, the corresponding scanning signal output terminals Nout1...Noutn, Noutn+1, Nout...Nout m, Nout m+1, Nout m+2...Nout k of different frames can maintain outputting a complete high-level waveform and then maintain outputting a low-level signal.

[0200] Low-Frequency to High-Frequency Phase: In the last line of the low-frequency region frame, the third pulse of the first control signal MS1 is on. If the cascade output terminal Sout is outputting a low-level signal at this time, the timing sequence is the same as in the initialization phase, and the scan signal output terminals Nout1…Noutn, Noutn+1, Nout…Noutm, Noutm+1, Noutm+2…Noutk of different frames can output normally. If the cascade output terminal Sout is outputting a high-level signal at this time, that is, the first node N1 is at a low-level signal and the third node N3 is at a high-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the high-level signal of the second control signal MS2 is written to the sixth node N6 and maintained by the first capacitor C1. The fourth node N4 is maintained at the high-level signal of the previous phase by the second capacitor C2, and the fifth node N5 is maintained at a low-level signal. This maintains the low-level output waveforms of the corresponding scan signal output terminals Nout1…Noutn, Noutn+1, Nout…Noutm, Noutm+1, Noutm+2…Noutk of different frames.

[0201] FIG13 is an output waveform diagram of a shift register according to an exemplary embodiment. As shown in FIG13 , the control of the scanning signal output terminals OUT1 to OUT13 of thirteen rows of pixels can be achieved by switching the voltages of the first control signal MS1, the first control signal MS2, and the third control signal MS3. The abscissa in FIG13 represents time, in microseconds (µs, also referred to as u).

[0202] Figure 14 is an operating timing diagram of a cascade output sub-circuit provided by an exemplary embodiment. The following illustrates an exemplary embodiment of the present disclosure through the operating process of the cascade output sub-circuit illustrated in Figure 10 or Figure 11, taking the ninth transistor T9 to the twenty-fifth transistor T25, the third capacitor C3 to the sixth capacitor C6, the input terminal SIN, the first clock signal terminal CK1, the second clock signal terminal CK2 and the cascade output terminal SOUT in the cascade output sub-circuit provided in Figure 10 or Figure 11 as an example.

[0203] In an exemplary embodiment, as shown in FIG14 , the operation process of the cascade output sub-circuit may include:

[0204] In the first phase E1, the signal at the second clock signal terminal CK2 is a high-level signal, and the signal at the first clock signal terminal CK1 is a low-level signal. The signal at the first clock signal terminal CK1 is a low-level signal, and the seventeenth transistor T17, the nineteenth transistor T19, the twelfth transistor T12, and the fourteenth transistor T14 are turned on. The seventeenth transistor T17 is turned on and transmits the high-level signal at the input terminal SIN to the second node N2, and the signal at the second node N2 becomes a high-level signal. The twelfth transistor T12 is turned on and transmits the high-level signal at the second node N2 to the third node N3. The fourteenth transistor T14 is turned on and transmits the high-level signal at the input terminal SIN to the eighth node N8, and the signal at the eighth node N8 becomes a high-level signal. The fifteenth transistor T15 is turned on and transmits the high-level signal at the eighth node N8 to the twelfth node N12. The eighteenth transistor T18, the twentieth transistor T20, the twenty-fourth transistor T24, and the tenth transistor T10 are turned off. In addition, the turned-on nineteenth transistor T19 transmits the low-level signal from the second power supply terminal V2 to the seventh node N7, causing the signal at the seventh node N7 to become a low-level signal. The turned-on eleventh transistor T11 transmits the low-level signal from the seventh node N7 to the ninth node N9, causing the signal at the ninth node N9 to become a low-level signal. The twenty-first transistor T21 and the twenty-second transistor T22 are turned on. The signal at the second clock signal terminal CK2 is a high-level signal, and the twenty-third transistor T23 is turned off. In addition, under the action of the third capacitor C3, the ninth transistor T9 is turned off. In the first phase E1, since both the ninth transistor T9 and the tenth transistor T10 are turned off, the signal at the cascade output terminal SOUT remains at the previous low level.

[0205] In the second phase E2, the signal at the second clock signal terminal CK2 is a low-level signal, and the signal at the first clock signal terminal CK1 is a high-level signal. The signal at the second clock signal terminal CK2 is a low-level signal, and the twenty-third transistor T23 is turned on. The signal at the first clock signal terminal CK1 is a high-level signal, and the seventeenth transistor T17 and the nineteenth transistor T19 are turned off. Under the action of the third capacitor C3, the second node N2, the third node N3, the eighth node N8, and the twelfth node N12 can continue to maintain the high-level signals of the previous phase. Under the action of the fifth capacitor C5, the ninth node N9 can continue to maintain the low-level signal of the previous phase, so the twenty-first transistor T21 and the twenty-second transistor T22 are turned on. The eighteenth transistor T18, the twentieth transistor T20, the twenty-fourth transistor T24, and the tenth transistor T10 are turned off. In addition, the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the turned-on twenty-second transistor T22 and the twenty-third transistor T23, and the ninth transistor T9 is turned on. The turned-on ninth transistor T9 outputs the high-level signal of the first power supply terminal V1, and the signal of the cascade output terminal SOUT is a high-level signal.

[0206] In the third phase E3, the signal at the first clock signal terminal CK1 is a low-level signal, and the signal at the second clock signal terminal CK2 is a high-level signal. The signal at the second clock signal terminal CK2 is a high-level signal, and the twenty-third transistor T23 is turned off. The eighteenth transistor T18, the twentieth transistor T20, the twenty-fourth transistor T24, and the tenth transistor T10 are turned off. The signal at the first clock signal terminal CK1 is a low-level signal, and the seventeenth transistor T17 and the nineteenth transistor T19 are turned on. Under the action of the third capacitor C3, the ninth transistor T9 remains on. The turned-on ninth transistor T9 outputs the high-level signal from the first power supply terminal V1, and the signal at the cascade output terminal SOUT remains a high-level signal.

[0207] In the fourth stage E4, the signal at the second clock signal terminal CK2 is a low-level signal, and the signal at the first clock signal terminal CK1 is a high-level signal. The signal at the first clock signal terminal CK1 is a high-level signal, and the seventeenth transistor T17 and the nineteenth transistor T19 are turned off. The signal at the second clock signal terminal CK2 is a low-level signal, and the twenty-third transistor T23 is turned on. Due to the storage function of the third capacitor C3, the signals at the second node N2, the third node N3, the eighth node N8, and the twelfth node N12 remain high-level signals from the previous stage, and the eighteenth transistor T18, the twentieth transistor T20, the twenty-fourth transistor T24, and the tenth transistor T10 are turned off. Due to the storage function of the fifth capacitor C5, the ninth node N9 continues to maintain the low level from the previous stage, and the twenty-first transistor T21 and the twenty-second transistor T22 are turned on. In addition, the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the turned-on twenty-second transistor T22 and the twenty-third transistor T23, and the turned-on ninth transistor T9 outputs the high-level signal of the first power supply terminal V1, and the signal of the cascade output terminal SOUT is still a high-level signal.

[0208] In the fifth phase E5, the signal at the second clock signal terminal CK2 is a high-level signal, and the signal at the first clock signal terminal CK1 is a low-level signal. The signal at the first clock signal terminal CK1 is a low-level signal, and the seventeenth transistor T17, the nineteenth transistor T19, and the fourteenth transistor T14 are turned on. The signal at the second clock signal terminal CK2 is a high-level signal, and the twenty-third transistor T23 is turned off. The turned-on seventeenth transistor T17 transmits the low-level signal of the input terminal SIN to the second node N2, causing the signal of the second node N2 to become a low-level signal. The turned-on twelfth transistor T12 transmits the low-level signal of the second node N2 to the third node N3, causing the signal of the third node N3 to become a low-level signal. The turned-on fourteenth transistor T14 transmits the low-level signal of the input terminal SIN to the eighth node N8, causing the signal of the eighth node N8 to become a low-level signal. The turned-on fifteenth transistor T15 transmits the low-level signal of the eighth node N8 to the twelfth node N12, causing the signal of the twelfth node N12 to become a low-level signal. The eighteenth transistor T18, the twentieth transistor T20, the twenty-fourth transistor T24, and the tenth transistor T10 are turned on. The turned-on eighteenth transistor T18 transmits the low-level signal of the first clock signal terminal CK1 to the seventh node N7, thereby pulling down the level of the seventh node N7. Therefore, the seventh node N7 and the ninth node N9 continue to maintain the low level of the previous stage. The twenty-first transistor T21 and the twenty-second transistor T22 are turned on. The signal at the second clock signal terminal CK2 is high, and the twenty-third transistor T23 is turned off. Furthermore, the turned-on twenty-fourth transistor T24 transmits the high-level signal at the first power supply terminal V1 to the first node N1, and the ninth transistor T9 is turned off. The turned-on tenth transistor T10 outputs the low-level signal at the second power supply terminal V2, and the signal at the cascade output terminal SOUT becomes low.

[0209] An embodiment of the present disclosure also provides a gate drive circuit, comprising: a plurality of cascaded shift registers; the signal output end of the i-th shift register is electrically connected to the signal input end of the i+1-th shift register, 1≤i≤M-1, and M is the total number of shift registers.

[0210] The shift register may be the shift register provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be described in detail here.

[0211] The cascade relationship of multiple shift registers in the gate drive circuit may vary for different display products. Regardless of the cascade relationship of the multiple shift registers, each shift register drives several rows of sub-pixels. As long as a large-area device such as this is modified, and the additional space created by this modification, the simple translation or stretching of small devices is within the scope of protection of this disclosure.

[0212] The gate driving circuit provided by the embodiment of the present disclosure is located in a display device, wherein the display device is further provided with a pixel circuit and a gate line, the pixel circuit is electrically connected to at least one gate line, and the scan output signal terminal of the shift register in the gate driving circuit is electrically connected to the gate line.

[0213] The gate drive circuit provided in the embodiment of the present disclosure can drive the pixel circuit, and through the first control signal MS1 to the third control signal MS3, it can update the partial screen image, while the remaining images do not need to be charged and discharged multiple times, thereby reducing the power consumption of the OLED display; or achieve ultra-low power consumption of OLED products such as wearables, mobile phones, and laptop computers (NB) by partially updating the display image.

[0214] In one exemplary embodiment, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. FIG15A is a schematic diagram of an equivalent circuit of a pixel circuit. As shown in FIG15A , the pixel circuit may include seven control transistors (first control transistor M1 to seventh control transistor M7) and one capacitor C.

[0215] As shown in FIG15A , a gate electrode of the first control transistor M1 is electrically connected to the reset signal line Reset, a first electrode of the first control transistor M1 is electrically connected to the first initial signal line INIT1, and a second electrode of the first control transistor M1 is electrically connected to the first node E1; a gate electrode of the second control transistor M2 is electrically connected to the second scan signal line Gate2, a first electrode of the second control transistor M2 is electrically connected to the first node E1, and a second electrode of the second control transistor M2 is electrically connected to the third node E3; a gate electrode of the third control transistor M3 is electrically connected to the first node E1, a first electrode of the third control transistor M3 is electrically connected to the second node E2, and a second electrode of the third control transistor M3 is electrically connected to the third node E3; a gate electrode of the fourth control transistor M4 is electrically connected to the first scan signal line Gate1, and a first electrode of the fourth control transistor M4 is electrically connected to the data signal line Data. A second electrode of the fourth control transistor M4 is electrically connected to the second node E2; a gate electrode of the fifth control transistor M5 is electrically connected to the light-emitting signal line EM, a first electrode of the fifth control transistor M5 is electrically connected to the high-level power supply line VDD, and a second electrode of the fifth control transistor M5 is electrically connected to the second node E2; a gate electrode of the sixth control transistor M6 is electrically connected to the light-emitting signal line EM, a first electrode of the sixth control transistor M6 is electrically connected to the third node E3, and a second electrode of the sixth control transistor M6 is electrically connected to the fourth node E4; a gate electrode of the seventh control transistor M7 is electrically connected to the first scanning signal line Gate1, a first electrode of the seventh control transistor M7 is electrically connected to the second initial signal line INIT2, and a second electrode of the seventh control transistor M7 is electrically connected to the fourth node E4; a first plate of the capacitor C is electrically connected to the first node E1, and a second plate of the capacitor C is electrically connected to the high-level power supply line VDD.

[0216] In an exemplary embodiment, the first control transistor M1 to the seventh control transistor M7 may be low-temperature polysilicon thin film control transistors, or may be oxide thin film control transistors, or may be low-temperature polysilicon thin film control transistors and oxide thin film control transistors. The active layer of the low-temperature polysilicon thin film control transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film control transistor is made of oxide semiconductor (Oxide). The low-temperature polysilicon thin film control transistor has advantages such as high mobility and fast charging, while the oxide thin film control transistor has advantages such as low leakage current. Integrating the low-temperature polysilicon thin film control transistor and the oxide thin film control transistor on a display substrate to form an LTPO display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0217] In an exemplary embodiment, the first control transistor M1 and the second control transistor M2 are of opposite control transistor types to the third control transistor M3 to the seventh control transistor M7. For example, the first control transistor M1 and the second control transistor M2 may be N-type control transistors, and the third control transistor M3 to the seventh control transistor M7 may be P-type control transistors.

[0218] In an exemplary embodiment, the first control transistor M1 and the second control transistor M2 may be oxide control transistors, and the third control transistor M3 to the seventh control transistor M7 may be low-temperature polysilicon control transistors.

[0219] In an exemplary embodiment, the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal. The voltage value of the signal of the first initial signal line INIT1 may be -3V.

[0220] In an exemplary embodiment, the voltage value of the signal of the second initial signal line INIT2 is constant and is a DC signal. The voltage value of the signal of the second initial signal line INIT2 may be 0V.

[0221] In an exemplary embodiment, the light emitting device L′ may be electrically connected to the fourth node E4 and the low-level power line VSS, respectively.

[0222] In an exemplary embodiment, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0223] FIG15B is a timing diagram of the operation of the pixel circuit provided in FIG15A. The following illustrates an exemplary embodiment of the present disclosure through the operation process of the pixel circuit illustrated in FIG15A during the display phase. FIG15B is illustrated by taking the first control transistor M1 and the second control transistor M2 as N-type control transistors, and the third control transistor M3 to the seventh control transistor M7 as P-type control transistors as an example. The pixel circuit in FIG15B includes the first control transistor M1 to the seventh control transistor M7, a capacitor C, and eight signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, reset signal line Reset, first initial signal line INIT1, second initial signal line INIT2, light-emitting signal line EM, and high-level power line VDD).

[0224] 15A and 15B , the operation process of the pixel circuit may include:

[0225] The first stage P1 is called the initialization stage. The signal of the reset signal line Reset is a high-level signal, the first control transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written into the first node E1 through the turned-on first control transistor M1, initializing (resetting) the first node E1, clearing the pre-stored voltage inside it, and completing the initialization.

[0226] In the second phase P2, also known as the data writing phase or the threshold compensation phase, the first scanning signal line Gate1 is a low-level signal, the second scanning signal line Gate2 is a low-level signal, and the data signal line Data outputs a data voltage. During this phase, the first node E1 is a low-level signal, so the third control transistor M3 is turned on. The signal of the first scan signal line Gate1 is a low-level signal, the fourth control transistor M4 and the seventh control transistor M7 are turned on, the signal of the second scan signal line Gate2 is a high-level signal, the second control transistor M2 is turned on, and the data voltage output by the data signal line Data is provided to the first node E1 through the turned-on fourth control transistor M4, the second node E2, the turned-on third control transistor M3, the third node E3, and the turned-on second control transistor M2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third control transistor M3 is charged into the capacitor C until the voltage of the first node E1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third control transistor M3. The seventh control transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written to the fourth node E4 through the turned-on seventh control transistor M7, thereby initializing (resetting) the first electrode of the light-emitting device L, clearing the pre-stored voltage therein, and completing the initialization.

[0227] In the third stage P3, referred to as the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, the fifth control transistor M5 and the sixth control transistor M6 are turned on, and the power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth control transistor M5, the third control transistor M3, and the sixth control transistor M6, thereby driving the light-emitting device L to emit light.

[0228] During the pixel circuit driving process, the driving current flowing through the third control transistor M3 (driving control transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node E1 is Vd-|Vth|, the driving current of the third control transistor M3 is:

[0229] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0230] Wherein, I is the driving current flowing through the third control transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third control transistor M3, Vth is the threshold voltage of the third control transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0231] In an exemplary embodiment, the gate driving circuit provided by the embodiment of the present disclosure may be electrically connected to the second scan signal line Gate2 .

[0232] In an exemplary embodiment, FIG16A is a schematic diagram of an equivalent circuit of another pixel circuit. As shown in FIG16A , the pixel circuit may include eight control transistors (first to eighth control transistors M1 to M8), one capacitor C, and nine signal lines (a data signal line Data, a control signal line Scan, a scan signal line Gate, a reset signal line Reset, an emission signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a high-level power line VDD, and a low-level power line VSS).

[0233] In one exemplary embodiment, as shown in FIG16A , a first plate of capacitor C is connected to a high-level power supply line VDD, and a second plate of capacitor C is connected to a first node E1. A control electrode of first control transistor M1 is connected to reset signal line Reset, a first electrode of first control transistor M1 is connected to first initial signal line INIT1, and a second electrode of first control transistor M1 is connected to fourth node E4. A control electrode of second control transistor M2 is connected to scan signal line Gate, a first electrode of second control transistor M2 is connected to fourth node E4, and a second electrode of second control transistor M2 is connected to second node E2. A control electrode of third control transistor M3 is connected to first node E1, a first electrode of third control transistor M3 is connected to second node E2, and a second electrode of third control transistor M3 is connected to third node E3. A control electrode of fourth control transistor M4 is connected to scan signal line Gate, a first electrode of fourth control transistor M4 is connected to data signal line Data, and a second electrode of fourth control transistor M4 is connected to third node E3. A control electrode of the fifth control transistor M5 is connected to the light-emitting signal line EM, a first electrode of the fifth control transistor M5 is connected to the high-level power supply line VDD, and a second electrode of the fifth control transistor M5 is connected to the third node E3. A control electrode of the sixth control transistor M6 is connected to the light-emitting signal line EM, a first electrode of the sixth control transistor M6 is connected to the second node E2, and a second electrode of the sixth control transistor M6 is connected to the first electrode of the light-emitting device L. A control electrode of the seventh control transistor M7 is connected to the reset signal line Reset, a first electrode of the seventh control transistor M7 is connected to the second initial signal line INIT2, a second electrode of the seventh control transistor M7 is connected to the first electrode of the light-emitting device L, and a second electrode of the light-emitting device L is connected to the low-level power supply line VSS. A control electrode of the eighth control transistor M8 is connected to the control signal line Scan, a first electrode of the eighth control transistor M8 is connected to the first node E1, and a second electrode of the eighth control transistor M8 is connected to the fourth node E4.

[0234] In an exemplary embodiment, the control electrode of the seventh control transistor M7 can also be connected to the scan signal line Gate, the first electrode of the seventh control transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh control transistor M7 is connected to the first electrode of the light-emitting device L, and the second electrode of the light-emitting device L is connected to the low-level power line VSS.

[0235] In an exemplary embodiment, the signal of the high-level power line VDD is a continuously high-level signal, and the signal of the low-level power line VSS is a low-level signal.

[0236] In an exemplary embodiment, the eighth control transistor M8 is a metal oxide control transistor and is an N-type control transistor, and the first to seventh control transistors M1 to M7 are low temperature polysilicon control transistors and are P-type control transistors.

[0237] In an exemplary embodiment, the eighth control transistor M8 is an oxide control transistor, which can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0238] In an exemplary embodiment, the gate driving circuit provided by the embodiment of the present disclosure may be electrically connected to the control signal line Scan.

[0239] FIG16B is a timing diagram of the operation of the pixel circuit provided in FIG16A. The following describes an exemplary embodiment of the present disclosure through the operation process of the pixel circuit illustrated in FIG16B. The operation process of the pixel circuit may include:

[0240] The first phase A1 is called the reset phase. The signals on the control signal line Scan, the emission signal line EM, and the scan signal line Gate are all high-level signals, while the signal on the reset signal line Reset is low-level. The reset signal line Reset is low-level, the first control transistor M1 is turned on, the signal on the first initialization signal line INIT1 is supplied to the fourth node E4, the seventh control transistor M7 is turned on, and the initial voltage on the second initialization signal line INIT2 is supplied to the first electrode of the light-emitting device L, initializing (resetting) the first electrode of the light-emitting device L. For example, the pre-stored voltage within the first electrode is cleared, completing the initialization and ensuring that the light-emitting device L does not emit light. The signal on the control signal line Scan is high-level, the eighth control transistor M8 is turned on, and the signal on the fourth node E4 is supplied to the first node E1, initializing the capacitor C and clearing the previous data voltage in the capacitor C. The signals on the scan signal line Gate and the emission signal line EM are high-level signals, and the second control transistor M2, the fourth control transistor M4, the fifth control transistor M5, the sixth control transistor M6, and the seventh control transistor M7 are turned off. During this phase, the light-emitting device L does not emit light.

[0241] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signal on the scan signal line Gate is a low-level signal, the signals on the reset signal line Reset, the luminescence signal line EM, and the control signal line Scan are high-level signals, and the data signal line Data outputs a data voltage. During this phase, since the first node E1 is a low-level signal, the third control transistor M3 is turned on. The signal on the scan signal line Gate is a low-level signal, the second control transistor M2 and the fourth control transistor M4 are turned on, the signal on the control signal line Scan is a high-level signal, and the eighth control transistor M8 is turned on. The second control transistor M2, the fourth control transistor M4, and the eighth control transistor M8 are turned on, causing the data voltage output by the data signal line Data to be supplied to the first node E1 via the third node E3, the turned-on third control transistor M3, the second node E2, the turned-on second control transistor M2, the fourth node E4, and the turned-on eighth control transistor M8. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third control transistor M3 is charged into the capacitor C until the voltage at the first node E1 reaches Vd - |Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third control transistor M3. The signal on the reset signal line Reset is low, and the first control transistor M1 and the seventh control transistor M7 are turned off. The signal on the emission signal line EM is high, and the fifth control transistor M5 and the sixth control transistor M6 are turned off.

[0242] In the third phase A3, known as the light-emitting phase, the signals on the control signal line Scan and the light-emitting signal line EM are both low-level signals, while the signals on the scan signal line Gate and the reset signal line Reset are high-level signals. The reset signal line Reset is also low-level, and the first control transistor M1 and the seventh control transistor M7 are turned off. The control signal line Scan is low-level, while the signals on the scan signal line Gate and the reset signal line Reset are high-level signals. The second control transistor M2, the fourth control transistor M4, and the eighth control transistor M8 are turned off. The signal on the light-emitting signal line EM is low-level, and the fifth control transistor M5 and the sixth control transistor M6 are turned on. The power supply voltage output from the high-level power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth control transistor M5, the third control transistor M3, and the sixth control transistor M6, driving the light-emitting device L to emit light.

[0243] During the pixel circuit driving process, the driving current flowing through the third control transistor M3 (driving control transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node E1 is Vd-|Vth|, the driving current of the third control transistor M3 is:

[0244] I=K*(Vgs-Vth)2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0245] Wherein, I is the driving current flowing through the third control transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third control transistor M3, Vth is the threshold voltage of the third control transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0246] The gate drive circuit provided in the embodiments of the present disclosure can control the opening and closing of the gates of transistors in the pixel circuit to achieve pixel brightness refresh. The gate drive circuit controls the gates of the transistors in the pixel circuit to be in the closed state, which can prevent some pixels from being refreshed. In some special screens, such as AOD, static screens, or screens that are rarely updated, the voltage of the relevant pixels is not updated, avoiding repeated writing to the relevant pixels, which increases the power consumption of the display.

[0247] The present disclosure also provides a shift register driving method, which is configured to drive the shift register. The shift register driving method may include:

[0248] The cascade output subcircuit provides a signal from the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of the signals from the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node;

[0249] The output control subcircuit provides the signal of the first node to the fourth node and the signal of the second node to the fifth node under the control of the first node, the third node and the signals from the first control signal terminal to the third control signal terminal;

[0250] The scan output sub-circuit outputs the signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of the signals of the fourth node and the fifth node.

[0251] The shift register is the shift register provided by any of the aforementioned embodiments, and its implementation principle and effect are similar, which will not be described in detail here.

[0252] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0253] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0254] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A shift register, comprising: Cascade output subcircuit, output control subcircuit and scan output subcircuit; The cascade output subcircuit is electrically connected to the input terminal, the first clock signal terminal, the second clock signal line, the first power supply terminal, the second power supply terminal, the cascade output terminal, the first node, the second node and the third node respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of the signals of the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node and the third node; The output control subcircuit is electrically connected to the first control signal terminal to the third control signal terminal, the first node, the second node, the third node, the fourth node and the fifth node, respectively, and is configured to provide the signal of the first node to the fourth node and provide the signal of the second node to the fifth node under the control of the signals of the first node, the third node and the first control signal terminal to the third control signal terminal; The scan output sub-circuit is electrically connected to the fourth node, the fifth node, the scan signal output terminal, the first power supply terminal and the second power supply terminal, respectively, and is configured to output a signal from the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of the signals from the fourth node and the fifth node.

2. The shift register according to claim 1, wherein: The output control subcircuit comprises: a first control subcircuit, a second control subcircuit and a third control subcircuit; The first control subcircuit is electrically connected to the first node, the third node, the sixth node, and the first control signal terminal to the third control signal terminal, respectively, and is configured to provide a signal from the second control signal terminal or the third control signal terminal to the sixth node under the control of the signals from the first node, the third node, and the first control signal terminal; The second control subcircuit is electrically connected to the first node, the fourth node and the sixth node respectively, and is configured to provide the signal of the first node to the fourth node under the control of the signal of the sixth node; The third control subcircuit is electrically connected to the second node, the fifth node and the sixth node respectively, and is configured to provide the signal of the second node to the fifth node under the control of the signal of the sixth node.

3. The shift register according to claim 2, wherein: The first control subcircuit includes: a first transistor, a second transistor, a third transistor and a fourth transistor; The control electrode of the first transistor is electrically connected to the first control signal terminal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the third control signal terminal; The control electrode of the second transistor is electrically connected to the third node, and the first electrode of the second transistor is electrically connected to the sixth node; The control electrode of the third transistor is electrically connected to the first control signal terminal, the first electrode of the third transistor is electrically connected to the second control signal terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor; A control electrode of the fourth transistor is electrically connected to the first node, and a second electrode of the fourth transistor is electrically connected to the sixth node.

4. The shift register according to claim 2, wherein: The second control subcircuit includes: a fifth transistor; The control electrode of the fifth transistor is electrically connected to the sixth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

5. The shift register according to claim 2, wherein: The third control subcircuit comprises: a sixth transistor; The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the fifth node.

6. The shift register according to claim 2, wherein: The output control subcircuit further includes: a storage subcircuit; The storage sub-circuit is electrically connected to the fourth node and the sixth node, respectively, and is configured to store a voltage difference between the signal of the sixth node and the fourth node.

7. The shift register according to claim 6, wherein: The storage subcircuit includes: a first capacitor, the first capacitor including a first plate and a second plate; The first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the fourth node.

8. The shift register according to claim 1, wherein: The scan output subcircuit comprises: a seventh transistor and an eighth transistor; The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the scan signal output terminal; The control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the scan signal output terminal, and the second electrode of the eighth transistor is electrically connected to the second power supply terminal.

9. The shift register according to claim 8, wherein: The scan output subcircuit further includes: a second capacitor, the second capacitor including a first plate and a second plate; The first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

10. The shift register according to claim 1, wherein: The cascade output subcircuit comprises: a ninth transistor to a twenty-fifth transistor, and a third capacitor to a sixth capacitor; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output terminal; The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade output terminal; The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the seventh node, and the second electrode of the eleventh transistor is electrically connected to the ninth node; The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the second node, and the second electrode of the twelfth transistor is electrically connected to the third node; The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second node; A control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourteenth transistor is electrically connected to the input terminal, and a second electrode of the fourteenth transistor is electrically connected to the eighth node; The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the eighth node, and the second electrode of the fifteenth transistor is electrically connected to the twelfth node; A control electrode of the sixteenth transistor is electrically connected to the twelfth node, a first electrode of the sixteenth transistor is electrically connected to the third node, and a second electrode of the sixteenth transistor is electrically connected to the twelfth node; The control electrode of the seventeenth transistor is electrically connected to the first clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the input terminal, and the second electrode of the seventeenth transistor is electrically connected to the second node; The control electrode of the eighteenth transistor is electrically connected to the second node, the first electrode of the eighteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the seventh node; The control electrode of the nineteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the nineteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the seventh node; The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the second clock signal terminal, and the second electrode of the twentieth transistor is electrically connected to the eleventh node; The control electrode of the twenty-first transistor is electrically connected to the seventh node, and the first electrode of the twenty-first transistor is electrically connected to the first power supply terminal. electrically connected, the second electrode of the twenty-first transistor is electrically connected to the eleventh node; The control electrode of the twenty-second transistor is electrically connected to the ninth node, the first electrode of the twenty-second transistor is electrically connected to the second clock signal terminal, and the second electrode of the twenty-second transistor is electrically connected to the tenth node; A control electrode of the twenty-third transistor is electrically connected to the second clock signal terminal, a first electrode of the twenty-third transistor is electrically connected to the tenth node, and a second electrode of the twenty-third transistor is electrically connected to the first node; A control electrode of the twenty-fourth transistor is electrically connected to the second node, a first electrode of the twenty-fourth transistor is electrically connected to the first power supply terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the first node; A control electrode of the twenty-fifth transistor is electrically connected to the twelfth node, a first electrode of the twenty-fifth transistor is electrically connected to the twelfth node, and a second electrode of the twenty-fifth transistor is electrically connected to the fifth node; The third capacitor includes a first plate and a second plate, the first plate of the third capacitor is electrically connected to the third node, and the second plate of the third capacitor is electrically connected to the eleventh node; The fourth capacitor includes a first plate and a second plate, the first plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second plate of the fourth capacitor is electrically connected to the cascade output terminal; The fifth capacitor includes a first electrode plate and a second electrode plate, the first electrode plate of the fifth capacitor is electrically connected to the ninth node, and the second electrode plate of the fifth capacitor is electrically connected to the tenth node; The sixth capacitor includes a first plate and a second plate. The first plate of the sixth capacitor is electrically connected to the first node, and the second plate of the sixth capacitor is electrically connected to the first power supply terminal.

11. The shift register according to claim 1, wherein: The cascade output subcircuit includes: a ninth transistor to a twenty-fifth transistor, and a third capacitor to a sixth capacitor; the output control subcircuit includes: a first transistor to a sixth transistor and a first capacitor; and the scan output subcircuit includes: a seventh transistor, an eighth transistor, and a second capacitor; The control electrode of the first transistor is electrically connected to the first control signal terminal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the third control signal terminal; The control electrode of the second transistor is electrically connected to the third node, and the first electrode of the second transistor is electrically connected to the sixth node; The control electrode of the third transistor is electrically connected to the first control signal terminal, the first electrode of the third transistor is electrically connected to the second control signal terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor; The control electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the sixth node; The control electrode of the fifth transistor is electrically connected to the sixth node, the first electrode of the fifth transistor is electrically connected to the first node, and the The second electrode of the fifth transistor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the fifth node; The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the scan signal output terminal; The control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the scan signal output terminal, and the second electrode of the eighth transistor is electrically connected to the second power supply terminal; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output terminal; The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade output terminal; The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the seventh node, and the second electrode of the eleventh transistor is electrically connected to the ninth node; The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the second node, and the second electrode of the twelfth transistor is electrically connected to the third node; The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second node; A control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourteenth transistor is electrically connected to the input terminal, and a second electrode of the fourteenth transistor is electrically connected to the eighth node; The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the eighth node, and the second electrode of the fifteenth transistor is electrically connected to the twelfth node; A control electrode of the sixteenth transistor is electrically connected to the twelfth node, a first electrode of the sixteenth transistor is electrically connected to the third node, and a second electrode of the sixteenth transistor is electrically connected to the twelfth node; The control electrode of the seventeenth transistor is electrically connected to the first clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the input terminal, and the second electrode of the seventeenth transistor is electrically connected to the second node; The control electrode of the eighteenth transistor is electrically connected to the second node, the first electrode of the eighteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the seventh node; The control electrode of the nineteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the nineteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the seventh node; The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the second clock signal terminal, and the second electrode of the twentieth transistor is electrically connected to the eleventh node; a control electrode of the twenty-first transistor is electrically connected to the seventh node, a first electrode of the twenty-first transistor is electrically connected to the first power supply terminal, and a second electrode of the twenty-first transistor is electrically connected to the eleventh node; The control electrode of the twenty-second transistor is electrically connected to the ninth node, the first electrode of the twenty-second transistor is electrically connected to the second clock signal terminal, and the second electrode of the twenty-second transistor is electrically connected to the tenth node; A control electrode of the twenty-third transistor is electrically connected to the second clock signal terminal, a first electrode of the twenty-third transistor is electrically connected to the tenth node, and a second electrode of the twenty-third transistor is electrically connected to the first node; A control electrode of the twenty-fourth transistor is electrically connected to the second node, a first electrode of the twenty-fourth transistor is electrically connected to the first power supply terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the first node; A control electrode of the twenty-fifth transistor is electrically connected to the twelfth node, a first electrode of the twenty-fifth transistor is electrically connected to the twelfth node, and a second electrode of the twenty-fifth transistor is electrically connected to the fifth node; The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the fourth node; The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected to the fourth node, and the second plate of the second capacitor is electrically connected to the first power supply terminal; The third capacitor includes a first plate and a second plate, the first plate of the third capacitor is electrically connected to the third node, and the second plate of the third capacitor is electrically connected to the eleventh node; The fourth capacitor includes a first plate and a second plate, the first plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second plate of the fourth capacitor is electrically connected to the cascade output terminal; The fifth capacitor includes a first electrode plate and a second electrode plate, the first electrode plate of the fifth capacitor is electrically connected to the ninth node, and the second electrode plate of the fifth capacitor is electrically connected to the tenth node; The sixth capacitor includes a first plate and a second plate. The first plate of the sixth capacitor is electrically connected to the first node, and the second plate of the sixth capacitor is electrically connected to the first power supply terminal.

12. The shift register according to claim 1, wherein: The shift register is arranged on a display substrate, the display substrate comprises: a plurality of scanning signal lines, the working process of the display substrate comprises: a display phase and a blank phase between the display phases; the display substrate comprises: a plurality of display areas, the refresh frequencies of different display areas comprise a first refresh frequency and a second refresh frequency, the first refresh frequency being greater than the second refresh frequency; When the working process of the display substrate is in a blank stage, when the signal at the first control signal end is a low level signal, the signals at the second control signal end and the third control signal end are low level signals; When the working process of the display substrate is in the display stage and the shift register is connected to the scanning signal line located in the display area of ​​the first refresh frequency, when the signal at the first control signal end is a low level signal, the signals at the second control signal end and the third control signal end are low level signals; When the working process of the display substrate is the display stage, the shift register is connected to the scanning signal line located in the display area of ​​the second refresh frequency, and the cascade output terminal of the shift register outputs a low-level signal, when the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal; When the working process of the display substrate is the display stage, the shift register is connected to the scanning signal line located in the display area of ​​the second refresh frequency, and the cascade output terminal of the shift register outputs a high-level signal, when the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal; When the working process of the display substrate is the display stage, the shift register is connected to the scanning signal line located in the display area of ​​the second refresh frequency, and the cascade output terminal of the shift register outputs a low-level signal, when the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal; The duration of the signal at the first control signal terminal being a low level signal is shorter than the duration of the signal at any one of the second control signal terminal and the third control signal terminal being a low level signal.

13. A gate drive circuit comprising: A plurality of cascaded shift registers as claimed in any one of claims 1 to 12; The cascade output terminal of the i-th stage shift register is electrically connected to the input terminal of the i+1-th stage shift register, 1≤i≤M-1, and M is the total number of stages of the shift register.

14. A shift register driving method, configured to drive the shift register according to any one of claims 1 to 12, the method comprising: The cascade output subcircuit provides a signal from the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of the signals from the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node and the third node; The output control subcircuit provides the signal of the first node to the fourth node and provides the signal of the second node to the fifth node under the control of the first node, the third node and the signal from the first control signal terminal to the third control signal terminal; The scan output subcircuit outputs the signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of the signal of the fourth node and the fifth node.

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