Array substrate, electromagnetic touch display device and driving method therefor

Abstract

An array substrate, an electromagnetic touch display device and a driving method therefor. The array substrate comprises a base substrate, a source-drain metal layer, a common electrode layer located on the side of the source-drain metal layer away from the base substrate, and a plurality of first electromagnetic wires located on the side of the common electrode layer facing the base substrate. The source-drain metal layer comprises a plurality of data lines, and the common electrode layer comprises a plurality of first strip-shaped common electrode columns; each first electromagnetic wire is arranged corresponding to one of the plurality of data lines; the plurality of first electromagnetic wires and the plurality of first strip-shaped common electrode columns are arranged in a one-to-one correspondence mode; for each data line, each first strip-shaped common electrode column, and the first electromagnetic wire that correspond to each other, in an area defined by two straight lines passing through the two ends of each first strip-shaped common electrode and extending in a first direction, the orthographic projection of the first electromagnetic wire and the orthographic projection of the data line on the base substrate fall within the orthographic projection of the first strip-shaped common electrode on the base substrate. Therefore, the first strip-shaped common electrode can shield the first electromagnetic wire.

Description

Array substrate, electromagnetic touch display device and driving method thereof

[0001] This application claims priority to Chinese Patent Application No. 202310889814.4 filed on July 19, 2023. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to an array substrate, an electromagnetic touch display device, and a driving method thereof. Background Art

[0003] Electromagnetic touch usually uses an electromagnetic pen in combination with an electromagnetic touch panel to achieve touch function. The panel contains a multi-layer electromagnetic coil structure, a pressure sensor at the pen tip and an electromagnetic field transmitter. When the electromagnetic pen touches the display surface, the sensor inside the panel can determine the touch point position information of the electromagnetic pen in three-dimensional space by calculating the electromagnetic changes, and achieve a precise and delicate writing experience.

[0004] Summary of the Invention

[0005] In order to solve the problem of liquid crystal deflection caused by the potential difference between the electromagnetic traces and other layers of metal being greater than the threshold voltage of the liquid crystal, the embodiments of the present disclosure provide an array substrate, an electromagnetic touch display device and a driving method thereof, which can shield the electromagnetic traces or reduce the potential difference between the electromagnetic traces and other layers of metal, thereby improving the display effect.

[0006] At least one embodiment of the present disclosure provides an array substrate, comprising: a base substrate; a source-drain metal layer located on the base substrate, comprising a plurality of data lines arranged along a first direction and extending along a second direction, wherein the first direction and the second direction are arranged crosswise; a common electrode layer located on a side of the source-drain metal layer away from the base substrate, comprising a plurality of first strip-shaped common electrodes extending along the second direction, wherein the plurality of first strip-shaped common electrodes are arranged in an array on the base substrate to form a plurality of first strip-shaped common electrode columns; a plurality of first electromagnetic traces arranged along the first direction and extending along the second direction, and located on the common electrode layer; The electrode layer faces the side of the base substrate; each of the multiple first electromagnetic traces is arranged corresponding to one of the multiple data lines, and the multiple first electromagnetic traces are arranged in a one-to-one correspondence with the multiple first strip common electrode columns. For the corresponding data lines, the first strip common electrode columns and the first electromagnetic traces, within an area sandwiched by two straight lines passing through the two ends of each first strip common electrode and extending along the first direction, the orthographic projections of the first electromagnetic traces and the data lines on the base substrate fall within the orthographic projection of the first strip common electrode on the base substrate.

[0007] For example, in the array substrate provided by an embodiment of the present disclosure, the first strip-shaped common electrodes are continuously arranged in a direction parallel to the base substrate and perpendicular to the extending direction of the first strip-shaped common electrodes.

[0008] For example, in the array substrate provided by an embodiment of the present disclosure, for the data lines, the first strip common electrode columns and the first electromagnetic routing lines that correspond to each other, within the area sandwiched by two straight lines passing through the two ends of each of the first strip common electrodes and extending along the first direction, the orthographic projection of the interval between the first electromagnetic routing lines and the data lines on the base substrate falls within the orthographic projection of the first strip common electrode on the base substrate.

[0009] For example, in the array substrate provided in one embodiment of the present disclosure, the common electrode layer also includes a plurality of second strip common electrodes extending along the second direction, and the plurality of second strip common electrodes are arranged in an array on the base substrate to form a plurality of second strip common electrode columns, and each of the plurality of second strip common electrode columns is arranged to at least partially overlap with one of the plurality of data lines, and the data line that is at least partially overlapped with the second strip common electrode column and the data line that is arranged corresponding to the first electromagnetic trace are different data lines.

[0010] For example, in the array substrate provided by an embodiment of the present disclosure, at least one second strip-shaped common electrode column is disposed between every two adjacent first strip-shaped common electrode columns.

[0011] For example, in the array substrate provided by an embodiment of the present disclosure, two second strip-shaped common electrode columns are disposed between every two adjacent first strip-shaped common electrode columns.

[0012] For example, in the array substrate provided by an embodiment of the present disclosure, the width of the second strip-shaped common electrode in the first direction is smaller than the width of the first strip-shaped common electrode in the first direction.

[0013] For example, in the array substrate provided by an embodiment of the present disclosure, the plurality of first electromagnetic traces are located in the source / drain metal layer, and each of the plurality of first electromagnetic traces is disposed adjacent to one of the plurality of data lines.

[0014] For example, the array substrate provided by one embodiment of the present disclosure also includes: a gate layer, located between the base substrate and the source-drain metal layer, including a plurality of gate lines extending along the first direction and arranged along the second direction; a gate insulating layer, located on the side of the gate layer away from the base substrate; and a first interlayer insulating layer, located on the side of the source-drain metal layer away from the base substrate; a first conductive layer, located on the side of the first interlayer insulating layer away from the base substrate; a second interlayer insulating layer, located on the side of the first conductive layer away from the base substrate; and a plurality of second electromagnetic traces, located in the first conductive layer, extending along the first direction and arranged along the second direction, each of the plurality of second electromagnetic traces being arranged corresponding to one of the plurality of gate lines.

[0015] For example, in the array substrate provided in one embodiment of the present disclosure, the common electrode layer also includes a plurality of common electrode patterns, and the plurality of common electrode patterns are arranged in an array on the base substrate to form a plurality of common electrode pattern rows and a plurality of common electrode pattern columns, and each of the plurality of common electrode pattern columns is located between adjacent second strip common electrode columns or between adjacent first strip common electrode columns and second strip common electrode columns.

[0016] For example, in the array substrate provided in one embodiment of the present disclosure, the common electrode pattern includes a plurality of strip electrodes arranged along the first direction and extending along the second direction, a slit is provided between two adjacent strip electrodes, and the orthographic projection of at least one end of the slit of each common electrode pattern on the base substrate at least partially overlaps with the orthographic projection of the second electromagnetic trace on the base substrate.

[0017] For example, an array substrate provided by an embodiment of the present disclosure also includes: a plurality of pixel electrodes, which are arranged in an array along the first direction and the second direction, and are arranged one-to-one with the plurality of common electrode patterns; the source-drain metal layer also includes a plurality of drain electrodes, which are arranged in an array along the first direction and the second direction, and are arranged one-to-one with the plurality of pixel electrodes; the positive projection of the drain electrode on the base substrate overlaps with the positive projection of one of the plurality of gate lines on the base substrate; the drain electrode includes a connecting portion, the positive projection of the connecting portion on the base substrate overlaps with the positive projection of the corresponding pixel electrode on the base substrate to be connected to the pixel electrode; the connecting portion of the drain electrode overlapping with the same gate line and the second electromagnetic routing arranged corresponding to the gate line are respectively located on both sides of the center line of the gate line along the second direction.

[0018] For example, in an array substrate provided in an embodiment of the present disclosure, the gate layer further includes a plurality of common electrode lines extending along the first direction and arranged along the second direction, and each of the plurality of common electrode lines is arranged adjacent to one of the plurality of gate lines.

[0019] For example, in the array substrate provided by one embodiment of the present disclosure, each of the multiple second electromagnetic traces is arranged corresponding to one of the multiple common electrode lines, the second electromagnetic trace is consistent with the extension direction of the corresponding common electrode line, and the ratio of the overlapping area of ​​the orthographic projection of the second electromagnetic trace on the base substrate and the orthographic projection of the common electrode line on the base substrate to the orthographic projection area of ​​the common electrode line on the base substrate is greater than or equal to 80%.

[0020] For example, in the array substrate provided by one embodiment of the present disclosure, the orthographic projection of the common electrode line on the base substrate includes a first boundary segment that is farthest from the center line of the gate line adjacent to the common electrode line, and the orthographic projection of the second electromagnetic trace corresponding to the gate line on the base substrate includes a second boundary segment that is farthest from the center line of the gate line, and the distance between the first boundary segment and the center line of the gate line is greater than or equal to the distance between the second boundary segment and the center line of the gate line.

[0021] For example, in an array substrate provided by an embodiment of the present disclosure, the gate line includes a plurality of protrusions, which protrude toward corresponding common electrode lines, and the common electrode line includes a plurality of bending portions, which are arranged in a one-to-one correspondence with the protrusions and bend away from the protrusions. The common electrode line also includes a plurality of transverse connecting portions, and two adjacent bending portions are connected by the transverse connecting portions. The plurality of bending portions include a plurality of first bending portions and a plurality of second bending portions. In a plane parallel to the base substrate, the first strip-shaped common electrode column passes through the first bending portion, and the second strip-shaped common electrode column passes through the second bending portion. The size of the first bending portion in the first direction is larger than the size of the second bending portion in the first direction.

[0022] For example, the array substrate provided by one embodiment of the present disclosure also includes: a gate layer, located between the base substrate and the source-drain metal layer, including a plurality of gate lines extending along the first direction and arranged along the second direction; a gate insulating layer, located on the side of the gate layer away from the base substrate; a first interlayer insulating layer, located on the side of the source-drain metal layer away from the base substrate; a second conductive layer, located on the side of the first interlayer insulating layer away from the base substrate; and a third interlayer insulating layer, located on the side of the second conductive layer away from the base substrate; the plurality of first electromagnetic traces are located in the second conductive layer, and each of the plurality of first electromagnetic traces is at least partially overlapped with one of the plurality of data lines.

[0023] For example, the array substrate provided by one embodiment of the present disclosure also includes: a first conductive layer, located on the side of the gate insulation layer away from the base substrate; a second interlayer insulation layer, located on the side of the first conductive layer away from the base substrate; and a plurality of second electromagnetic traces, located in the first conductive layer, extending along the first direction and arranged along the second direction, each of the plurality of second electromagnetic traces being arranged corresponding to one of the plurality of gate lines.

[0024] At least one embodiment of the present disclosure further provides an electromagnetic touch display device, comprising: an array substrate according to any one of the above items; an opposing substrate arranged in a box with the array substrate; and a liquid crystal layer arranged between the array substrate and the opposing substrate.

[0025] At least one embodiment of the present disclosure also provides a driving method for an electromagnetic touch display device, wherein the electromagnetic touch display device includes an array substrate and an opposing substrate arranged in a box with each other, and a liquid crystal layer sandwiched between the array substrate and the opposing substrate, the array substrate includes a plurality of first electromagnetic traces and a common electrode layer, the first electromagnetic traces are arranged along a first direction and extend along a second direction intersecting the first direction, the driving method includes: providing a common voltage to the common electrode layer; and providing a touch voltage to the plurality of first electromagnetic traces; the difference between the touch voltage and the common voltage is less than a threshold voltage for rotation of liquid crystal molecules in the liquid crystal layer.

[0026] For example, in the driving method provided in one embodiment of the present disclosure, the array substrate also includes a plurality of second electromagnetic traces and a plurality of common electrode patterns located in the common electrode layer, the plurality of second electromagnetic traces are arranged along the second direction and extend along the first direction, the plurality of common electrode patterns are arranged in an array on the plane of the array substrate, the common electrode pattern includes a plurality of strip electrodes arranged along the first direction and extending along the second direction, a slit is provided between two adjacent strip electrodes, and the orthographic projection of at least one of the slits on the plane of the array substrate at least partially overlaps with the orthographic projection of the second electromagnetic trace on the plane of the array substrate, and the driving method also includes: providing the touch voltage to the plurality of second electromagnetic traces.

[0027] For example, in the driving method provided in one embodiment of the present disclosure, the difference between the touch voltage and the common voltage is less than or equal to 0.5V. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0029] FIG1 is a simulated diagram of liquid crystal deflection along a cross-section perpendicular to the longitudinal electromagnetic touch line of an electromagnetic touch display product in a normally black mode;

[0030] FIG2 is a schematic structural diagram of the array substrate shown in FIG1 ;

[0031] FIG3 is a simulated diagram of liquid crystal deflection along a cross-sectional plane perpendicular to the horizontal electromagnetic touch line of an electromagnetic touch display product in a normally black mode;

[0032] FIG4 is a schematic structural diagram of the array substrate shown in FIG3 ;

[0033] FIG5 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

[0034] FIG6 is a schematic diagram of the partial structure shown in FIG5;

[0035] FIG7 is a schematic cross-sectional view of FIG5 along the cutting line AB;

[0036] FIG8 is a schematic diagram of a partial structure of a first strip-shaped common electrode column provided in one embodiment of the present disclosure;

[0037] FIG9 is a schematic diagram of a partial structure of another first strip-shaped common electrode array provided by an embodiment of the present disclosure;

[0038] FIG10 is a schematic cross-sectional view of the structure along the cutting line CD in FIG5 ;

[0039] FIG11 is a schematic diagram of the partial structure shown in FIG5 ;

[0040] FIG12 is a simulated diagram of liquid crystal deflection along a cross-section perpendicular to the direction of the first electromagnetic wiring in FIG5;

[0041] FIG13 is a schematic structural diagram of an array substrate provided in one embodiment of the present disclosure;

[0042] FIG14 is a schematic diagram of the partial structure shown in FIG13;

[0043] FIG15 is a schematic cross-sectional view of the structure of FIG13 along the cutting line EF;

[0044] FIG16 is a schematic cross-sectional view of the structure along the cutting line GH in FIG13;

[0045] FIG17 is a schematic cross-sectional view of the structure of FIG13 along the cutting line IJ;

[0046] FIG18 is a schematic diagram of an electromagnetic touch display device provided by an embodiment of the present disclosure;

[0047] FIG19 is a schematic diagram of another electromagnetic touch display device provided by an embodiment of the present disclosure;

[0048] FIG20 is a flow chart of a driving method of an electromagnetic touch display device provided by an embodiment of the present disclosure;

[0049] FIG21 is a schematic structural diagram of another array substrate provided in one embodiment of the present disclosure;

[0050] FIG22 is a schematic cross-sectional view of FIG21 along the cutting line KL;

[0051] FIG23 is a schematic cross-sectional view of FIG21 along the cutting line MN; and

[0052] FIG. 24 is a liquid crystal deflection simulation diagram of FIG. 21 along a cross-sectional plane perpendicular to the second electromagnetic wiring direction. DETAILED DESCRIPTION

[0053] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0054] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0055] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present disclosure include the cases of "parallel", "perpendicular", "same" in a strict sense, as well as the cases of "approximately parallel", "approximately perpendicular", "approximately the same" and the like which contain certain errors. For example, the above-mentioned "approximately" may mean that the difference between the compared objects is 10% of the average value of the compared objects, or within 5%. When the number of a component or element is not specifically indicated below in the embodiments of the present disclosure, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The "same-layer arrangement" in the embodiments of the present disclosure refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0056] Compared to conventional display products, electromagnetic touch display products incorporate electromagnetic touch coils and common electrode lines within the display area. When the screen displays an image, the differing signals from the electromagnetic touch lines and the common electrode generate a potential difference. When this new electric field exceeds the threshold voltage of the liquid crystal, it drives the liquid crystal to deflect, resulting in undesirable light leakage. Addressing this light leakage by increasing the size of the black matrix will impact the pixel aperture ratio. Furthermore, electromagnetic touch display products contain a multi-layer electromagnetic coil structure, and the complex metal wiring also impacts pixel aperture.

[0057] Figure 1 is a simulated diagram of liquid crystal deflection in a cross-section perpendicular to the direction of the longitudinal electromagnetic touch lines in an electromagnetic touch display product in normally black mode; Figure 2 is a schematic diagram of the array substrate structure shown in Figure 1. As shown in Figures 1 and 2, the upper portion of the longitudinal electromagnetic touch line 11 is not covered by the common electrode 12. The electric field generated by the potential difference between the longitudinal electromagnetic touch line 11 and the common electrode 12 causes the liquid crystal 13 to deflect, resulting in undesirable light leakage when the screen is displaying. Figure 3 is a simulated diagram of liquid crystal deflection in a cross-section perpendicular to the direction of the transverse electromagnetic touch lines in an electromagnetic touch display product in normally black mode; Figure 4 is a schematic diagram of the array substrate structure shown in Figure 3. As shown in Figures 3 and 4, the upper portion of the transverse electromagnetic touch line 14 is covered by the common electrode 12. The electric field generated by the potential difference between the transverse electromagnetic touch line 13 and the common electrode 12 causes the liquid crystal to deflect, resulting in undesirable light leakage when the screen is displaying.

[0058] In this regard, embodiments of the present disclosure provide an array substrate, an electromagnetic touch display device, and a driving method thereof. The array substrate includes a base substrate, a source / drain metal layer, a common electrode layer, and a plurality of first electromagnetic traces. The source / drain metal layer is located on the base substrate and includes a plurality of data lines arranged along a first direction and extending along a second direction, wherein the first direction and the second direction are arranged to intersect each other; the common electrode layer is located on a side of the source / drain metal layer away from the base substrate and includes a plurality of first strip-shaped common electrodes extending along the second direction, wherein the plurality of first strip-shaped common electrodes are arranged in an array on the base substrate to form a plurality of first strip-shaped common electrode columns; a plurality of first electromagnetic traces are arranged along the first direction and extending along the second direction and are located on a side of the common electrode layer facing the base substrate; each of the plurality of first electromagnetic traces is arranged corresponding to one of the plurality of data lines, and the plurality of first electromagnetic traces are arranged in a one-to-one correspondence with the plurality of first strip-shaped common electrode columns; for the corresponding data lines, first strip-shaped common electrode columns, and first electromagnetic traces, within an area sandwiched by two straight lines passing through two ends of each first strip-shaped common electrode and extending along the first direction, the orthographic projections of the first electromagnetic traces and the data lines on the base substrate fall within the orthographic projections of the first strip-shaped common electrodes on the base substrate.

[0059] In the array substrate provided by the embodiments of the present disclosure, the first electromagnetic traces are covered by the first common electrode strips within the region bounded by two straight lines extending along a first direction and passing through the two ends of each first common electrode strip. The first common electrode strips shield the first electromagnetic traces, thereby reducing or preventing the electric field generated by the potential difference between the first electromagnetic traces and the common electrode layer from affecting liquid crystal deflection, further reducing or preventing undesirable light leakage. Furthermore, the first common electrode strips shield the data lines, reducing or preventing the electric field generated by the potential difference between the data lines and the common electrode layer from affecting liquid crystal deflection, further reducing or preventing undesirable light leakage.

[0060] Hereinafter, the array substrate, the electromagnetic touch display device and the driving method thereof provided by the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0061] One embodiment of the present disclosure provides an array substrate. Figure 5 is a schematic structural diagram of an array substrate provided in one embodiment of the present disclosure; Figure 6 is a schematic partial structural diagram of Figure 5; and Figure 7 is a schematic cross-sectional structural diagram along line AB of Figure 5. As shown in Figures 5 to 7, the array substrate 100 includes a base substrate 110, a source / drain metal layer 130, a common electrode layer 160, and a plurality of first electromagnetic traces 170. The source / drain metal layer 130 is located on the base substrate 110 and includes a plurality of data lines 131 arranged along a first direction X and extending along a second direction Y, with the first direction X and the second direction Y intersecting. The common electrode layer 160 is located on a side of the source / drain metal layer 130 away from the base substrate 110 and includes a plurality of first strip-shaped common electrodes 161 extending along the second direction Y. The plurality of first strip-shaped common electrodes 161 are arranged in an array on the base substrate 110 to form a plurality of first strip-shaped common electrode columns 161C, each of the plurality of first strip-shaped common electrode columns 161C extending along the second direction Y. A plurality of first electromagnetic traces 170 are arranged along the first direction X and extending along the second direction Y and are located on the side of the common electrode layer 160 facing the base substrate 110. In the cross-sectional view shown in FIG. 7 , the first electromagnetic traces 170 are located on the source / drain metal layer 130. However, this is not a limitation in the present disclosure; the first electromagnetic traces 170 may be located on the side of the common electrode layer 160 facing the base substrate 110. Each of the plurality of first electromagnetic traces 170 is disposed corresponding to one of the plurality of data lines 131, and the plurality of first electromagnetic traces 170 are disposed in a one-to-one correspondence with the plurality of first strip common electrode columns 161C. For the corresponding data lines 131, first strip common electrode columns 161C, and first electromagnetic traces 170, within a region sandwiched by a straight line L1 and a straight line L2 passing through both ends of each first strip common electrode 161 and extending along the first direction X, the orthographic projections of the first electromagnetic traces 170 and the data lines 131 on the base substrate 110 fall within the orthographic projections of the first strip common electrodes 161 on the base substrate 110.

[0062] In the array substrate 100 provided in the embodiment of the present disclosure, the first electromagnetic traces 170 are covered by the first common electrode strips 161 within the region bounded by the straight lines L1 and L2, which pass through the two ends of each first common electrode strip 161 and extend along the first direction X. The first common electrode strips 161 can shield the first electromagnetic traces 170, thereby reducing or preventing the electric field generated by the potential difference between the first electromagnetic traces 170 and the common electrode layer 160 from affecting liquid crystal deflection, further reducing or preventing the occurrence of undesirable light leakage. Furthermore, the first common electrode strips 161 can also shield the data lines 131, reducing or preventing the electric field generated by the potential difference between the data lines 131 and the common electrode layer 160 from affecting liquid crystal deflection, further reducing or preventing the occurrence of undesirable light leakage. It should be noted that the extension along the first direction X, the extension along the second direction Y or the extension along the specified direction mentioned in this application can be strictly extending along the direction or approximately extending along the direction. For example, extending approximately along the direction can include the extension direction of the local position having an angle less than or equal to 10 degrees with the direction, or the local position can have a bending feature or a protruding feature, etc.

[0063] In some examples, as shown in FIG5 , the array substrate 100 further includes a plurality of gate lines 121 extending along a first direction X and arranged along a second direction Y. The plurality of gate lines 121 and the plurality of data lines 131 define a plurality of sub-pixel openings 190, and the plurality of sub-pixel openings 190 are arranged in an array on the base substrate 110. Each of the plurality of first strip-shaped common electrodes 161 is disposed corresponding to one of the plurality of sub-pixel openings 190. For example, the sub-pixel openings 190 may be further defined by a black matrix layer described below to form a light-transmitting region of the sub-pixel corresponding to the sub-pixel opening 190. For example, the orthographic projection of the light-transmitting region on the base substrate falls within the orthographic projection of the sub-pixel opening 190 on the base substrate.

[0064] In some examples, as shown in FIG5 , the size of the first strip common electrode 161 in the second direction Y is greater than or equal to the size of the adjacent sub-pixel opening 190 in the second direction Y, thereby better reducing or avoiding unwanted light leakage caused by liquid crystal deflection.

[0065] FIG8 is a schematic diagram of a partial structure of a first strip-shaped common electrode array according to an embodiment of the present disclosure. As shown in FIG8 , the plurality of first strip-shaped common electrodes 161 of the first strip-shaped common electrode array 161C may be spaced apart from each other in the second direction Y. For example, as shown in FIG8 , a gap H1 is defined between two adjacent first strip-shaped common electrodes 161 in the second direction Y. The dimension of the gap H1 in the first direction X is greater than or equal to the dimension of the first strip-shaped common electrode 161 in the first direction X. For example, the plurality of first strip-shaped common electrodes 161 of the first strip-shaped common electrode array 161C may be connected via other connection structures of the common electrode layer 160 to achieve common signal transmission. For example, both ends 161a of a first strip-shaped common electrode 161 (only one end 161a of each first strip-shaped common electrode 161 is shown in the figure) are located outside the upper and lower boundaries of the corresponding sub-pixel opening 190 (only one boundary 190a of the upper and lower boundaries of each sub-pixel opening 190 is shown in the figure) in the extension direction of the first strip-shaped common electrode 161. It should be noted that, in this application, two adjacent first strip-shaped common electrodes 161 in the second direction Y refer to the absence of a first strip-shaped common electrode 161 between the two first strip-shaped common electrodes 161. However, other structures, such as a gap, may exist between the two first strip-shaped common electrodes 161. The sub-pixel opening 190 shown in FIG. 8 is merely used to exemplify the first strip-shaped common electrode column 161C and the first strip-shaped common electrode 161, and does not limit the embodiments of the present disclosure.

[0066] FIG9 is a schematic diagram of a partial structure of another first strip common electrode array provided in an embodiment of the present disclosure. As shown in FIG9(a), the plurality of first strip common electrodes 161 of the first strip common electrode array 161C can be continuous in the second direction Y, and there is no gap between two adjacent first strip common electrodes 161 in the second direction Y. For example, as shown in FIG9(b), there is a gap H2 between two adjacent first strip common electrodes 161 in the second direction Y, but the gap H2 and the first strip common electrode array 161C are offset in the second direction Y, and do not make the adjacent first strip common electrodes 161 completely discontinuous.

[0067] It should be noted that, in the example shown in FIG9 , the two end portions 161a of a first strip-shaped common electrode 161 (only one end portion 161a of each first strip-shaped common electrode 161 is shown in the figure) are located outside the upper and lower boundaries of the corresponding sub-pixel opening 190 (only one boundary 190a of the upper and lower boundaries of each sub-pixel opening 190 is shown in the figure) in the extension direction of the first strip-shaped common electrode 161. For example, as shown in FIG9 , each adjacent two first strip-shaped common electrodes 161 of the first strip-shaped common electrode column 161C are connected by a connecting portion 164. Of course, the embodiment of the present disclosure does not limit the structural design and arrangement of the first strip-shaped common electrode column 161C. The sub-pixel opening 190 shown in FIG9 is only used to exemplify the first strip-shaped common electrode column 161C and the first strip-shaped common electrode 161, and does not limit the embodiment of the present disclosure.

[0068] In some examples, as shown in Figures 5 to 7, the first strip common electrodes 161 are continuously arranged in a direction parallel to the base substrate 110 and perpendicular to the extension direction of the first strip common electrodes 161. This can reduce the difficulty of the manufacturing process of the first strip common electrodes 161 and improve the yield rate.

[0069] In some examples, as shown in Figures 5 to 7 , for the corresponding data lines 131, first strip-shaped common electrode columns 161C, and first electromagnetic traces 170, within the region enclosed by a straight line L1 and a straight line L2 passing through the two ends of each first strip-shaped common electrode 161 and extending along the first direction X, the orthographic projection of the gap Gap between the first electromagnetic trace 170 and the data line 131 on the base substrate 110 falls within the orthographic projection of the first strip-shaped common electrode 161 on the base substrate 110. This reduces or prevents the electric field generated by the potential difference between the first electromagnetic trace 170 or the data line 131 and the common electrode layer 160 through the gap Gap from affecting liquid crystal deflection, thereby reducing or preventing undesirable light leakage.

[0070] In some examples, each first electromagnetic trace 170 of the plurality of first electromagnetic traces 170 can correspond one-to-one with each data line 131 of the plurality of data lines 131, thereby increasing the number of first electromagnetic traces 170 and improving touch sensitivity. Of course, the disclosed embodiments do not limit the quantitative or positional correspondence between the first electromagnetic traces 170 and the data lines 131. For example, a first electromagnetic trace 170 can be provided for every equal number of data lines 131, or a first electromagnetic trace 170 can be provided for every different number of data lines 131.

[0071] For example, the array substrate further includes a plurality of sub-pixels, and the plurality of sub-pixels are arranged in a one-to-one correspondence with the plurality of sub-pixel openings. For example, the plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. For example, the first color, the second color, and the third color are different, for example, the first color is red, the second color is green, and the third color is blue. Of course, the present disclosure includes but is not limited to this, and the above-mentioned first color, second color, and third color may also be other colors. For example, the plurality of sub-pixels of the array substrate are arranged in an array on the base substrate to form a first color sub-pixel column, a second color sub-pixel column, and a third color sub-pixel column adjacent to each other in sequence.

[0072] For example, the first electromagnetic trace can be located between the first color sub-pixel column and the second color sub-pixel column. Of course, the present disclosure includes but is not limited to this. For example, the first electromagnetic trace can be set between each adjacent sub-pixel column.

[0073] FIG10 is a schematic cross-sectional view of the structure along the cutting line CD in FIG5 . As shown in FIG5 , FIG6 , and FIG10 , the common electrode layer 160 further includes a plurality of second strip-shaped common electrodes 162 extending along the second direction Y. The plurality of second strip-shaped common electrodes 162 are arranged in an array on the base substrate 110 to form a plurality of second strip-shaped common electrode columns 162C. Each second strip-shaped common electrode column 162C of the plurality of second strip-shaped common electrode columns 162C extends along the second direction Y. Each second strip-shaped common electrode column 162C of the plurality of second strip-shaped common electrode columns 162C at least partially overlaps with one of the plurality of data lines 131. The data line 131 at least partially overlapping with the second strip-shaped common electrode column 162C and the data line 131 corresponding to the first electromagnetic trace 170 are different data lines 131. The second strip common electrode 162 can shield the corresponding data line 131, thereby reducing or preventing the electric field generated by the potential difference between the data line 131 and the common electrode layer 160 from affecting the liquid crystal deflection, thereby reducing or preventing the occurrence of unwanted light leakage.

[0074] For example, as shown in Figures 5, 7, and 10, the data line 131 corresponding to the first electromagnetic trace 170 and the first strip common electrode column 161C is data line 1310, and the data line 131 corresponding to the second strip common electrode column 162C is data line 1311. Data line 1310 and data line 1311 are different data lines 131. The distinction between different data lines is only used to describe whether a data line is adjacent to the first strip common electrode column and does not limit the function or role of the data line itself.

[0075] In some examples, as shown in Figures 5, 6, and 10, for corresponding data lines 131 and second strip common electrode columns 162C, within a region sandwiched by straight lines L3 and L4, which pass through both ends of each second strip common electrode 162 and extend along the first direction X, the orthographic projection of the data line 131 on the base substrate 110 falls within the orthographic projection of the second strip common electrode 162 on the base substrate 110. This reduces or prevents the electric field generated by the potential difference between the data line 131 and the common electrode layer 160 from affecting liquid crystal deflection, thereby reducing or preventing the occurrence of undesirable light leakage.

[0076] 5 , the size of the second strip common electrode column 162C in the second direction Y is greater than or equal to the size of the adjacent sub-pixel opening 190 in the second direction Y. This can better reduce or avoid undesirable light leakage caused by liquid crystal deflection.

[0077] In some examples, the multiple second strip common electrodes 162 of the second strip common electrode column 162C can be spaced apart from each other or continuous in the second direction Y. For details, please refer to the description of the first strip common electrode column 161C in Figures 8 and 9 of this application, which will not be repeated here.

[0078] In some examples, as shown in FIG5 , at least one second strip common electrode column 162C is provided between each adjacent first strip common electrode column 161C. For example, as shown in FIG5 , two second strip common electrode columns 162C are provided between each adjacent first strip common electrode column 161C. Of course, the embodiment of the present disclosure does not limit the number of second strip common electrode columns 162C between each adjacent first common electrode column. It should be noted that adjacent first strip common electrode columns 161C means that there is no first strip common electrode column 161C between the two first strip common electrode columns 161C, but other structures may be provided.

[0079] In some examples, as shown in FIG5 , the width of the second strip-shaped common electrode 162 in the first direction X is smaller than the width of the first strip-shaped common electrode 161 in the first direction X. Therefore, under the premise of shielding the first electromagnetic trace 170 , the data line 1310 , and the data line 1311 , setting the width of the second strip-shaped common electrode 162 in the first direction X to be smaller than the width of the first strip-shaped common electrode 161 in the first direction X can also reduce the space occupied by the width of the second strip-shaped common electrode 162 in the first direction X, thereby facilitating the design and arrangement of other structures of the common electrode layer 160 .

[0080] In some examples, as shown in FIG7 , multiple first electromagnetic traces 170 are located in the source / drain metal layer 130, and each of the multiple first electromagnetic traces 170 is disposed adjacent to one of the multiple data lines 131. The first electromagnetic traces 170 and the data lines 131 are disposed in the same layer and formed using the same conductive material layer and the same patterning process, which can reduce the number of manufacturing steps, reduce the thickness of the array substrate 100, and ease processing difficulty.

[0081] In some examples, as shown in FIG5 , the adjacent first electromagnetic traces 170 and data lines 131 extend in substantially the same direction. The added first electromagnetic trace 170 affects the sub-pixel opening 190. By ensuring that the first electromagnetic trace 170 and the data line 131 extend in substantially the same direction, the effect of the first electromagnetic trace 170 on the sub-pixel opening 190 can be minimized, and the size occupied by the first electromagnetic trace 170 and the data line 131 in the first direction X can be minimized, thereby maximizing the size of the sub-pixel opening 190.

[0082] For example, as shown in FIG5 , the shapes of the first electromagnetic trace 170 and the data line 131 are substantially identical. For example, as shown in FIG5 , the first electromagnetic trace 170 and the data line 131 are substantially equidistant from each other. For example, as shown in FIG5 , where the data line 131 has a bend or protrusion, the first electromagnetic trace 170 also has a substantially identical bend or protrusion at the same location. Where the data line 131 extends in a straight line, the first electromagnetic trace 170 also has a substantially identical straight line at the same location.

[0083] In some examples, as shown in Figures 5 and 7, the gap Gap between adjacent first electromagnetic traces 170 and data lines 131 can be a minimum spacing that meets process requirements, thereby minimizing the impact of the first electromagnetic traces 170 on the pixel opening 190, minimizing the size occupied by the first electromagnetic traces 170 and the data lines 131 in the first direction X, and maximizing the size of the pixel opening 190. Of course, the embodiments of the present disclosure do not impose specific restrictions on the minimum spacing that meets process requirements and the gap Gap between the first electromagnetic traces 170 and the data lines 131.

[0084] FIG11 is a schematic diagram of the partial structure shown in FIG5 . As shown in FIG5 , FIG7 , and FIG11 , the array substrate 100 further includes a gate layer 120, a gate insulating layer 191, a first interlayer insulating layer 192, a first conductive layer 140, a second interlayer insulating layer 193, and a plurality of second electromagnetic traces 180. The gate layer 120 is located between the base substrate 110 and the source / drain metal layer 130 and includes a plurality of gate lines 121 extending along a first direction X and arranged along a second direction Y. The gate insulating layer 191 is located on a side of the gate layer 120 away from the base substrate 110. The first interlayer insulating layer 192 is located on a side of the source / drain metal layer 130 away from the base substrate 110. The first conductive layer 140 is located on a side of the first interlayer insulating layer 192 away from the base substrate 110. The second interlayer insulating layer 193 is located on a side of the first conductive layer 140 away from the base substrate 110. The plurality of second electromagnetic traces 180 are located in the first conductive layer 140 and extend along the first direction X and are arranged along the second direction Y. Each second electromagnetic wiring 180 in the plurality of second electromagnetic wirings 180 is disposed corresponding to one of the plurality of gate lines 121 .

[0085] In some examples, as shown in Figures 5, 7, and 11, each second electromagnetic trace 180 of the plurality of second electromagnetic traces 180 can correspond one-to-one with each grid line 121 of the plurality of grid lines 121, thereby increasing the number of second electromagnetic traces 180 and improving touch sensitivity. Of course, the embodiments of the present disclosure do not limit the quantitative correspondence and positional correspondence between the second electromagnetic traces 180 and the grid lines 121. For example, a second electromagnetic trace 180 can be provided for every equal number of grid lines 121, or a second electromagnetic trace 180 can be provided for every different number of grid lines 121.

[0086] In some examples, as shown in Figures 5 and 11 , the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 does not overlap with the orthographic projection of the corresponding gate line 121 on the base substrate 110. Of course, the embodiments of the present disclosure are not limited to this.

[0087] For example, the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 may at least partially overlap with the orthographic projection of the corresponding gate line 121 on the base substrate 110. The added second electromagnetic trace 180 affects the pixel opening 190. By making the second electromagnetic trace 180 at least partially overlap with the corresponding gate line 121, the impact of the second electromagnetic trace 180 on the pixel opening 190 can be minimized, and the size occupied by the second electromagnetic trace 180 and the corresponding gate line 121 in the second direction Y can be minimized, thereby maximizing the size of the pixel opening 190.

[0088] In some examples, as shown in FIG5 , the common electrode layer 160 further includes a plurality of common electrode patterns 163, and the plurality of common electrode patterns 163 are arranged in an array on the base substrate 110 to form a plurality of common electrode pattern rows 163R and a plurality of common electrode pattern columns 163C, and each common electrode pattern column 163C of the plurality of common electrode pattern columns 163C is located between adjacent second strip common electrode columns 162C or between adjacent first strip common electrode columns 161C and second strip common electrode columns 162C. It should be noted that in the present application, adjacent second strip common electrode columns 162C mean that there will be no second strip common electrode column 162C between the two second strip common electrode columns 162C, but other structures may be provided. Adjacent first strip common electrode columns 161C and second strip common electrode columns 162C mean that there will be no first strip common electrode column and second strip common electrode column 162C between the two, but other structures may be provided.

[0089] In some examples, as shown in FIG5 , the common electrode pattern 163 located between adjacent second strip common electrode columns 162C is connected to the adjacent second strip common electrode columns 162C. The common electrode pattern 163 located between adjacent first strip common electrode columns 161C and second strip common electrode columns 162C is connected to the adjacent first strip common electrode columns 161C and second strip common electrode columns 162C. Thus, the plurality of first strip common electrodes 161, the plurality of second strip common electrodes 162, and the plurality of common electrode patterns 163 on the common electrode layer 160 are connected.

[0090] In some examples, as shown in Figures 5 to 7, the common electrode pattern 163 includes a plurality of strip electrodes 1630 arranged along a first direction X and extending along a second direction Y, with a slit 1631 between two adjacent strip electrodes 1630, and an orthographic projection of an end of at least one slit 1631 of each common electrode pattern 163 on the base substrate 110 at least partially overlaps with an orthographic projection of the second electromagnetic trace 180 on the base substrate 110.

[0091] In some examples, as shown in FIG. 5 to FIG. 7 and FIG. 11 , the array substrate 100 further includes a plurality of pixel electrodes 135 , which are arranged in an array along the first direction X and the second direction Y and are disposed in one-to-one correspondence with the plurality of common electrode patterns 163 . The source-drain metal layer 130 also includes a plurality of drain electrodes 132, which are arranged in an array along the first direction X and the second direction Y, and are arranged in a one-to-one correspondence with the plurality of pixel electrodes 135. The orthographic projection of the drain electrode 132 on the base substrate 110 overlaps with the orthographic projection of one of the plurality of gate lines 121 on the base substrate 110. The drain electrode 132 includes a connecting portion 132a, and the orthographic projection of the connecting portion 132a on the base substrate 110 overlaps with the orthographic projection of the corresponding pixel electrode 135 on the base substrate 110 to be connected to the pixel electrode 135. The connecting portion 132a of the drain electrode 132 overlapping with the same gate line 121 and the second electromagnetic trace 180 corresponding to the gate line 121 are respectively located on both sides of the center line of the gate line 121 along the second direction Y.

[0092] In some examples, as shown in FIG. 5 and FIG. 11 , the array substrate 100 further includes an active layer 195 , and the active layer 195 is located between the gate insulating layer 191 and the source / drain metal layer 130 .

[0093] In this example, the drain electrode 132, the gate line 121 (or the gate 121a, the gate 121a and the gate line 121 are integrally formed) overlapping the drain electrode 132, the data line 131 (or the source electrode 131c, the source electrode 131c and the data line 131 are integrally formed) overlapping the gate line 121, and the active layer 195 overlapping both the data line 131 and the drain electrode 132 can form a driving transistor TFT. The driving transistor is connected to the corresponding pixel electrode 135 via the connecting portion 132a of the drain electrode 132, thereby achieving liquid crystal deflection drive. The second electromagnetic trace 180 and the connecting portion 132a of the drain electrode 132 are respectively arranged on both sides of the center line of the gate line 121, which can prevent the second electromagnetic trace 180 from affecting the driving transistor and can also better design and arrange the structures of the driving transistor and the second electromagnetic trace 180.

[0094] In some examples, as shown in Figures 5 to 7 and 11, the gate layer 120 further includes a plurality of common electrode lines 122 extending along a first direction X and arranged along a second direction Y. Each of the plurality of common electrode lines 122 is disposed adjacent to one of the plurality of gate lines 121. By adding the common electrode lines 122, the resistance of the common electrode layer 160 of the array substrate 100 can be reduced. For example, the common electrode lines 122 can be connected to the common electrode layer 160 through vias.

[0095] 5 , each common electrode line 122 of the plurality of common electrode lines 122 is disposed in one-to-one correspondence with each gate line 121 of the plurality of gate lines 121. Thus, the resistance of the common electrode layer 160 of the array substrate 100 can be better reduced.

[0096] In some examples, as shown in Figures 5 to 7 and 11, the common electrode lines 122 and gate lines 121 disposed adjacent to each other extend in substantially the same direction. The added common electrode lines 122 affect the sub-pixel openings 190. By ensuring that the common electrode lines 122 and gate lines 121 extend in substantially the same direction, the effect of the common electrode lines 122 on the sub-pixel openings 190 can be minimized, and the dimensions occupied by the common electrode lines 122 and gate lines 121 in the first direction X can be minimized, thereby maximizing the size of the sub-pixel openings 190.

[0097] For example, the shapes of the common electrode lines 122 and the gate lines 121 may be substantially identical. For example, as shown in FIG5 and FIG11 , the common electrode lines 122 and the gate lines 121 are substantially equidistant from each other. For example, where the gate lines 121 are at locations with bends or protrusions, the common electrode lines 122 at the same locations also have substantially identical bends or protrusions. Where the gate lines 121 are at locations with straight extensions, the common electrode lines 122 at the same locations also have substantially identical straight extensions.

[0098] In some examples, as shown in Figures 5 and 11, the spacing between adjacent common electrode lines 122 and gate lines 121 can be the minimum spacing that meets process requirements, thereby minimizing the impact of the common electrode lines 122 on the sub-pixel openings 190, minimizing the size occupied by the common electrode lines 122 and gate lines 121 in the first direction X, and maximizing the size of the sub-pixel openings 190. Of course, the embodiments of the present disclosure do not impose specific restrictions on the minimum spacing that meets process requirements and the spacing size between the common electrode lines 122 and gate lines 121.

[0099] In some examples, as shown in FIG5 and FIG11 , each second electromagnetic trace 180 in the plurality of second electromagnetic traces 180 is disposed corresponding to one of the plurality of common electrode lines 122, the second electromagnetic trace 180 and the corresponding common electrode line 122 extend in the same direction, and the ratio of the overlapping area of ​​the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 and the orthographic projection of the common electrode line 122 on the base substrate 110 to the orthographic projection area of ​​the common electrode line 122 on the base substrate 110 is greater than or equal to 80%. Thus, the second electromagnetic trace 180 can overlap with the common electrode line 122 as much as possible, minimizing the impact of the second electromagnetic trace 180 and the common electrode line 122 on the sub-pixel opening 190, thereby maximizing the size of the sub-pixel opening 190.

[0100] For example, as shown in Figures 5 and 11 , the second electromagnetic trace 180 and the corresponding common electrode line 122 can extend in substantially the same direction. For example, as shown in Figures 5 and 11 , the second electromagnetic trace 180 and the common electrode line 122 have substantially the same shape. For example, where the common electrode is bent, the second electromagnetic trace 180 also has substantially the same bending characteristics at the same location. Where the common electrode is straight, the second electromagnetic trace 180 also has substantially the same straight extension characteristics at the same location. For example, the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 can completely fall within the orthographic projection of the common electrode line 122 on the base substrate 110.

[0101] In some examples, as shown in Figures 5 and 11 , each second electromagnetic trace 180 of the plurality of second electromagnetic traces 180 can correspond one-to-one with each common electrode line 122 of the plurality of common electrode lines 122. Of course, the disclosed embodiments do not limit the number or position correspondence between the second electromagnetic traces 180 and the common electrode lines 122. For example, a second electromagnetic trace 180 can be provided for every equal number of common electrode lines 122, or a second electromagnetic trace 180 can be provided for every different number of common electrode lines 122.

[0102] In some examples, as shown in FIG. 5 and FIG. 11 , the line width of the second electromagnetic trace 180 is smaller than the line width of the common electrode line 122 , so that the second electromagnetic trace 180 and the common electrode line 122 can be overlapped as much as possible.

[0103] In some examples, as shown in FIG11 , the orthographic projection of the common electrode line 122 on the base substrate 110 includes a first boundary segment L5 that is farthest from the center line of the gate line 121 adjacent to the common electrode line 122. The orthographic projection of the second electromagnetic trace 180 corresponding to the gate line 121 on the base substrate 110 includes a second boundary segment L6 that is farthest from the center line of the gate line 121. The distance between the first boundary segment L5 and the center line of the gate line 121 is greater than or equal to the distance between the second boundary segment L6 and the center line of the gate line 121. Thus, the farthest boundary segment of the second electromagnetic trace 180 is closer to the gate line 121 than the farthest boundary segment of the common electrode line 122, thereby reducing the impact of the second electromagnetic trace 180 on the sub-pixel opening 190 and maximizing the size of the sub-pixel opening 190.

[0104] In some examples, the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 is closer to the orthographic projection of the gate line 121 on the base substrate 110 than the orthographic projection of the common electrode line 122 on the base substrate 110. The second electromagnetic trace 180 and the gate line 121 are located on different layers, so that the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 can be closer to the orthographic projection of the gate line 121 on the base substrate 110, thereby reducing the impact of the second electromagnetic trace 180 on the sub-pixel opening 190 and maximizing the size of the sub-pixel opening 190.

[0105] In some examples, as shown in FIG5 and FIG11 , the connection portion 132 a of the drain electrode 132 that overlaps the same gate line 121 and the common electrode line 122 corresponding to the gate line 121 are respectively located on either side of the center line of the gate line 121 along the second direction Y. Thus, the common electrode line 1220 can be prevented from affecting the driving transistor, and the structures of the driving transistor and the common electrode line 122 can be better designed and arranged.

[0106] In some examples, as shown in Figures 5 and 11, the gate line 121 includes a plurality of protrusions 1210, which protrude toward the corresponding common electrode line 122. The common electrode line 122 includes a plurality of bending portions 1221, which are arranged in a one-to-one correspondence with the protrusion 1210 and bend away from the protrusion 1210. The common electrode line 122 also includes a plurality of transverse connecting portions 1222, and two adjacent bending portions 1221 are connected by the transverse connecting portion 1222. The plurality of bending portions 1221 include a plurality of first bending portions 1221a and a plurality of second bending portions 1221b. In a plane parallel to the base substrate 110, the first strip common electrode column 161C passes through the first bending portion 1221a, and the second strip common electrode column 162C passes through the second bending portion 1221b. The size of the first bending portion 1221a in the first direction X is larger than the size of the second bending portion 1221b in the first direction X. The common electrode line 122 is bent only at the protruding portion 1210 of the gate line 121, thereby minimizing the impact on the sub-pixel opening 190. The dimension of the first bent portion 1221a in the first direction X is greater than the dimension of the second bent portion 1221b in the first direction X, which can ensure that the dimensions of each sub-pixel opening 190 are substantially consistent. It should be noted that in this application, two adjacent bent portions 1221 mean that there is no bent portion 1221 between the two bent portions 1221, but other structures may be present, such as a transverse connecting portion 1222.

[0107] In some examples, as shown in Figures 5 and 11 , the first strip-shaped common electrode array 161C has a notch at a position corresponding to the active layer 195, as shown in Figures 8 and 9 . Thus, the first strip-shaped common electrode array 161C is not completely continuous in the second direction. The second strip-shaped common electrode array 162C has a notch at a position corresponding to the active layer 195, as shown in Figures 8 and 9 . Thus, the first strip-shaped common electrode array 161C is not completely continuous in the second direction.

[0108] Figure 12 is a simulated diagram of liquid crystal deflection along a cross-section perpendicular to the first electromagnetic trace in Figure 5. As shown in Figures 5, 7, and 12, the top of first electromagnetic trace 170 is covered by first strip common electrode 161, shielding first electromagnetic trace 170. When a voltage signal is applied to first electromagnetic trace 170 that differs from the voltage signal applied to first strip common electrode 161, the liquid crystal exhibits essentially no deflection, thereby reducing or preventing undesirable light leakage.

[0109] In some examples, as shown in FIG5 to FIG7, FIG10, and FIG11, the method for manufacturing the array substrate 100 includes: forming a patterned gate layer 120 on a base substrate 110; depositing a gate insulating layer 191 on the gate layer 120; forming a patterned active layer 195 on the gate insulating layer 191; forming a patterned pixel electrode 135 on the active layer 195; forming a patterned source-drain metal layer 130 on the active layer 195, wherein the source-drain metal layer 130 overlaps with the pixel electrode 135 at a connection portion 132a of the drain electrode 132; A first interlayer insulating layer 192 is deposited on the source-drain metal layer 130 and the pixel electrode 135; a patterned first conductive layer 140 is formed on the first interlayer insulating layer 192, and the first conductive layer 140 includes a second electromagnetic trace 180; a patterned second interlayer insulating layer 193 is formed on the first conductive layer 140; and a patterned common electrode layer 160 is formed on the second interlayer insulating layer 193, and the common electrode layer 160 includes a first strip-shaped common electrode 161, a second strip-shaped common electrode 162 and a common electrode pattern 163.

[0110] In some examples, as shown in Figures 5 to 7, 10, and 11, the pixel electrode 135 may be a transparent conductive metal. For example, the common electrode layer 160 may be a transparent conductive metal layer. For example, the transparent conductive metal may be indium tin oxide, etc.

[0111] Figure 13 is a schematic diagram of the structure of an array substrate provided in one embodiment of the present disclosure; Figure 14 is a schematic diagram of a partial structure shown in Figure 13; and Figure 15 is a schematic diagram of the cross-sectional structure along section line EF in Figure 13. As shown in Figures 13 to 15, the array substrate 100 includes a base substrate 110, a gate layer 120, a gate insulation layer 191, a source / drain metal layer 130, a first interlayer insulation layer 192, a second conductive layer 150, a third interlayer insulation layer 194, a common electrode layer 160, and a plurality of first electromagnetic traces 170. The gate layer 120 is located between the base substrate 110 and the source / drain metal layer 130 and includes a plurality of gate lines 121 extending along a first direction X and arranged along a second direction Y. The gate insulating layer 191 is located on a side of the gate layer 120 away from the base substrate 110. The source / drain metal layer 130 is located on the base substrate 110 and includes a plurality of data lines 131 arranged along the first direction X and extending along the second direction Y. The first interlayer insulating layer 192 is located on a side of the source / drain metal layer 130 away from the base substrate 110. The second conductive layer 150 is located on a side of the first interlayer insulating layer 192 away from the base substrate 110. The third interlayer insulating layer 194 is located on a side of the second conductive layer 150 away from the base substrate 110. The common electrode layer 160 is located on a side of the third interlayer insulating layer 194 away from the base substrate 110 and includes a plurality of first strip-shaped common electrodes 161 extending along the second direction Y. The plurality of first strip-shaped common electrodes 161 are arranged in an array on the base substrate 110. The plurality of first strip common electrode columns 161C are arranged to form a plurality of first strip common electrode columns 161C, each of the plurality of first strip common electrode columns 161C extending along the second direction Y. The plurality of first electromagnetic traces 170 are arranged along the first direction X and extend along the second direction Y, and are located on the second conductive layer 150. Each of the plurality of first electromagnetic traces 170 is disposed corresponding to one of the plurality of data lines 131, and the plurality of first electromagnetic traces 170 are disposed in a one-to-one correspondence with the plurality of first strip common electrode columns 161C. For the corresponding data lines 131, first strip common electrode columns 161C, and first electromagnetic traces 170, within a region sandwiched by a straight line L1 and a straight line L2 passing through two ends of each first strip common electrode 161 and extending along the first direction X, the orthographic projections of the first electromagnetic traces 170 and the data lines 131 on the base substrate 110 fall within the orthographic projections of the first strip common electrodes 161 on the base substrate 110.

[0112] In the array substrate 100 provided in the embodiment of the present disclosure, the first electromagnetic traces 170 are covered by the first common electrode strips 161 within the region bounded by the straight lines L1 and L2, which pass through the two ends of each first common electrode strip 161 and extend along the first direction X. The first common electrode strips 161 can shield the first electromagnetic traces 170, thereby reducing or preventing the electric field generated by the potential difference between the first electromagnetic traces 170 and the common electrode layer 160 from affecting liquid crystal deflection, thereby reducing or preventing the occurrence of undesirable light leakage. Furthermore, the first common electrode strips 161 can also shield the data lines 131, thereby reducing or preventing the electric field generated by the potential difference between the data lines 131 and the common electrode layer 160 from affecting liquid crystal deflection, thereby reducing or preventing the occurrence of undesirable light leakage.

[0113] In some examples, as shown in FIG. 13 , a plurality of gate lines 121 and a plurality of data lines 131 define a plurality of sub-pixel openings 190 .

[0114] In some examples, as shown in FIG13 , the size of the first strip-shaped common electrode 161 in the second direction Y is greater than or equal to the size of the adjacent sub-pixel opening 190 in the second direction Y. Thus, undesirable light leakage can be better reduced or avoided.

[0115] In some examples, the multiple first strip common electrodes 161 of the first strip common electrode column 161C can be spaced apart from each other or continuous in the second direction Y. For details, please refer to the description of the first strip common electrode column 161C in Figures 8 and 9 of this application, which will not be repeated here.

[0116] In some examples, each first electromagnetic trace 170 of the plurality of first electromagnetic traces 170 can correspond one-to-one with each data line 131 of the plurality of data lines 131, thereby increasing the number of first electromagnetic traces 170 and improving touch sensitivity. Of course, the disclosed embodiments do not limit the quantitative or positional correspondence between the first electromagnetic traces 170 and the data lines 131. For example, a first electromagnetic trace 170 can be provided for every equal number of data lines 131, or a first electromagnetic trace 170 can be provided for every different number of data lines 131.

[0117] In some examples, as shown in FIG15 , the corresponding first electromagnetic trace 170 and the data line 131 are at least partially overlapped in a direction perpendicular to the base substrate 110. This minimizes the impact of the addition of the second electromagnetic trace 180 on the sub-pixel opening 190 and minimizes the size occupied by the first electromagnetic trace 170 and the data line 131 in the first direction X, thereby maximizing the size of the sub-pixel opening 190. For example, as shown in FIG15 , the orthographic projection of the data line 131 on the base substrate 110 can completely fall within the orthographic projection of the first electromagnetic trace 170 on the base substrate 110. For example, as shown in FIG13 , the corresponding first electromagnetic trace 170 and the data line 131 extend in substantially the same direction. For example, as shown in FIG13 , the corresponding first electromagnetic trace 170 and the data line 131 have substantially the same shape. For example, the orthographic projection of the first electromagnetic trace 170 on the base substrate 110 can also completely fall within the orthographic projection of the data line 131 on the base substrate 110.

[0118] FIG16 is a schematic cross-sectional view of the structure along section line GH in FIG13 . As shown in FIG13 , FIG14 , and FIG16 , the common electrode layer 160 further includes a plurality of second strip-shaped common electrodes 162 extending along a second direction Y. These plurality of second strip-shaped common electrodes 162 are arranged in an array on the base substrate 110 to form a plurality of second strip-shaped common electrode columns 162C. Each second strip-shaped common electrode 162 in the plurality of second strip-shaped common electrode columns 162C at least partially overlaps with one of the plurality of data lines 131. The data lines 131 at least partially overlapping with the second strip-shaped common electrode columns 162C and the data lines 131 corresponding to the first electromagnetic traces 170 are different data lines 131. The distinction between different data lines is intended solely to describe whether a data line corresponds to a first strip-shaped common electrode column and does not limit the function or purpose of the data lines themselves. The second strip common electrode 162 can shield the corresponding data line 131, thereby reducing or preventing the electric field generated by the potential difference between the data line 131 and the common electrode layer 160 from affecting the liquid crystal deflection, thereby reducing or preventing the occurrence of unwanted light leakage.

[0119] 13 and 15 , the data line 131 corresponding to the first electromagnetic trace 170 and the first strip common electrode column 161C is data line 1310 , and the data line 131 corresponding to the second strip common electrode column 162C is data line 1311 .

[0120] In some examples, as shown in Figures 13, 14, and 16, for corresponding data lines 131 and second strip common electrode columns 162C, within a region sandwiched by straight lines L3 and L4, which pass through both ends of each second strip common electrode 162 and extend along the first direction X, the orthographic projection of the data line 131 on the base substrate 110 falls within the orthographic projection of the second strip common electrode 162 on the base substrate 110. This reduces or prevents the electric field generated by the potential difference between the data line 131 and the common electrode layer 160 from affecting liquid crystal deflection, thereby reducing or preventing undesirable light leakage.

[0121] 13 , the size of the second strip common electrode column 162C in the second direction Y is greater than or equal to the size of the adjacent sub-pixel opening 190 in the second direction Y. This can better reduce or avoid unwanted light leakage.

[0122] In some examples, the multiple second strip common electrodes 162 of the second strip common electrode column 162C can be spaced apart from each other or continuous in the second direction Y. For details, please refer to the description of the first strip common electrode column 161C in Figures 8 and 9 of this application, which will not be repeated here.

[0123] In some examples, as shown in FIG13 , at least one second strip common electrode column 162C is disposed between each adjacent first strip common electrode column 161C. For example, as shown in FIG13 , two second strip common electrode columns 162C are disposed between each adjacent first strip common electrode column 161C. Of course, the present embodiment does not limit the number of second strip common electrode columns 162C between each adjacent first common electrode column.

[0124] In some examples, as shown in Figures 13 and 14 , the width of the second strip-shaped common electrode 162 in the first direction X is equal to the width of the first strip-shaped common electrode 161 in the first direction X. Of course, the embodiments of the present disclosure are not limited to this. For example, the width of the second strip-shaped common electrode 162 in the first direction X may also be smaller than the width of the first strip-shaped common electrode 161 in the first direction X. Specifically, the width of the second strip-shaped common electrode 162 in the first direction X may be designed based on the width of the first electromagnetic trace 170 and the overlapping relationship between the first electromagnetic trace 170 and the data line 131.

[0125] In some examples, as shown in Figures 13 to 16 , the base substrate 110 further includes a first conductive layer 140, a second interlayer insulating layer 193, and a plurality of second electromagnetic traces 180. The first conductive layer 140 is located on a side of the gate insulating layer 191 away from the base substrate 110, the second interlayer insulating layer 193 is located on a side of the first conductive layer 140 away from the base substrate 110, and the plurality of second electromagnetic traces 180 are located in the first conductive layer 140, extending along a first direction X and arranged along a second direction Y. Each second electromagnetic trace 180 is disposed corresponding to one of the plurality of gate lines 121.

[0126] In some examples, as shown in FIG13 , each second electromagnetic trace 180 of the plurality of second electromagnetic traces 180 can correspond one-to-one with each grid line 121 of the plurality of grid lines 121, thereby increasing the number of second electromagnetic traces 180 and improving touch sensitivity. Of course, the disclosed embodiments do not limit the quantitative and positional correspondence between the second electromagnetic traces 180 and the grid lines 121. For example, a second electromagnetic trace 180 can be provided for every equal number of grid lines 121, or a second electromagnetic trace 180 can be provided for every different number of grid lines 121.

[0127] In some examples, as shown in Figure 13 , the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 does not overlap with the orthographic projection of the corresponding gate line 121 on the base substrate 110. Of course, the embodiments of the present disclosure are not limited to this.

[0128] For example, the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 may at least partially overlap with the orthographic projection of the corresponding gate line 121 on the base substrate 110. The added second electromagnetic trace 180 affects the sub-pixel opening 190. By making the second electromagnetic trace 180 at least partially overlap with the corresponding gate line 121, the impact of the second electromagnetic trace 180 on the sub-pixel opening 190 can be minimized, and the size occupied by the second electromagnetic trace 180 and the corresponding gate line 121 in the second direction Y can be minimized, thereby maximizing the size of the sub-pixel opening 190.

[0129] In some examples, as shown in FIG13 , the common electrode layer 160 further includes a plurality of common electrode patterns 163, which are arranged in an array on the base substrate 110 to form a plurality of common electrode pattern rows 163R and a plurality of common electrode pattern columns 163C, each of the plurality of common electrode pattern columns 163C being located between adjacent second strip common electrode columns 162C or between adjacent first strip common electrode columns 161C and second strip common electrode columns 162C.

[0130] In some examples, as shown in FIG13 , the common electrode pattern 163 located between adjacent second strip common electrode columns 162C is connected to the adjacent second strip common electrode columns 162C. The common electrode pattern 163 located between adjacent first strip common electrode columns 161C and second strip common electrode columns 162C is connected to the adjacent first strip common electrode columns 161C and second strip common electrode columns 162C. Thus, the plurality of first strip common electrodes 161, the plurality of second strip common electrodes 162, and the plurality of common electrode patterns 163 on the common electrode layer 160 are connected.

[0131] In some examples, as shown in Figures 13 to 16, the common electrode pattern 163 includes a plurality of strip electrodes 1630 arranged along a first direction X and extending along a second direction Y, with a slit 1631 between two adjacent strip electrodes 1630, and an orthographic projection of an end of at least one slit 1631 of each common electrode pattern 163 on the base substrate 110 at least partially overlaps with an orthographic projection of the second electromagnetic trace 180 on the base substrate 110.

[0132] Figure 17 is a schematic cross-sectional view of the structure along the cutting line IJ of Figure 13. As shown in Figures 13 to 17, the array substrate 100 further includes a plurality of pixel electrodes 135, which are arranged in an array along the first direction X and the second direction Y and are disposed in a one-to-one correspondence with the plurality of common electrode patterns 163. The source-drain metal layer 130 also includes a plurality of drain electrodes 132, which are arranged in an array along the first direction X and the second direction Y, and are arranged in a one-to-one correspondence with the plurality of pixel electrodes 135. The orthographic projection of the drain electrode 132 on the base substrate 110 overlaps with the orthographic projection of one of the plurality of gate lines 121 on the base substrate 110. The drain electrode 132 includes a connecting portion 132a, and the orthographic projection of the connecting portion 132a on the base substrate 110 overlaps with the orthographic projection of the corresponding pixel electrode 135 on the base substrate 110 to be connected to the pixel electrode 135. The connecting portion 132a of the drain electrode 132 overlapping with the same gate line 121 and the second electromagnetic trace 180 corresponding to the gate line 121 are respectively located on both sides of the center line of the gate line 121 along the second direction Y.

[0133] In this example, the drain electrode 132, the gate line 121 overlapping with the drain electrode 132, the data line 131 overlapping with the gate line 121, and the active layer can form a driving transistor. The driving transistor is connected to the corresponding pixel electrode 135 via the connecting portion 132a of the drain electrode 132, thereby achieving liquid crystal deflection. Disposing the second electromagnetic trace 180 and the connecting portion 132a of the drain electrode 132 on either side of the center line of the gate line 121 can prevent the second electromagnetic trace 180 from affecting the driving transistor and can also better design and arrange the structures of the driving transistor and the second electromagnetic trace 180.

[0134] In some examples, as shown in Figure 17, the pixel electrode 135 is arranged on the second interlayer insulating layer 193, and an insulating layer is provided between the pixel electrode 135 and the source-drain metal layer 130. The pixel electrode 135 and the source-drain metal layer 130 can be connected at the position where connection is required by using an insulating layer via 196.

[0135] In some examples, as shown in Figures 13 and 14 , the pixel electrode 135 is a plate-shaped structure. Of course, the embodiment of the present disclosure does not limit the structure of the pixel electrode 135 .

[0136] In some examples, as shown in Figures 13 to 17, the gate layer 120 further includes a plurality of common electrode lines 122 extending along a first direction X and arranged along a second direction Y. Each of the plurality of common electrode lines 122 is disposed adjacent to one of the plurality of gate lines 121. By adding the common electrode lines 122, the resistance of the common electrode layer 160 of the array substrate 100 can be reduced. For example, the common electrode lines 122 can be connected to the common electrode layer 160 through vias.

[0137] 13 , each common electrode line 122 of the plurality of common electrode lines 122 is disposed in one-to-one correspondence with each gate line 121 of the plurality of gate lines 121. Thus, the resistance of the common electrode layer 160 of the array substrate 100 can be better reduced.

[0138] In some examples, as shown in Figures 13 and 14, the common electrode lines 122 and gate lines 121 disposed adjacent to each other are substantially equidistant. For example, the spacing between the common electrode lines 122 and gate lines 121 disposed adjacent to each other can be the minimum spacing that meets process requirements. For example, when the gate line 121 is at a location with a bent feature or a protruding feature, the common electrode line 122 also has substantially the same bent feature or protruding feature at the same location; and when the gate line 121 is at a location with a straight extension, the common electrode line 122 also has substantially the same straight extension feature at the same location. The added common electrode line 122 affects the sub-pixel opening 190. By making the common electrode lines 122 and gate lines 121 substantially equidistant, the spacing being the minimum spacing that meets process requirements, thereby minimizing the impact of the common electrode lines 122 on the sub-pixel opening 190, minimizing the size occupied by the common electrode lines 122 and gate lines 121 in the first direction X, and thereby maximizing the size of the sub-pixel opening 190. Of course, the embodiment of the present disclosure does not impose any specific restrictions on the minimum spacing that meets the process requirements and the spacing between the common electrode line 122 and the gate line 121 .

[0139] In some examples, as shown in Figures 13 and 14 , each second electromagnetic trace 180 in the plurality of second electromagnetic traces 180 is disposed corresponding to one of the plurality of common electrode lines 122, the second electromagnetic trace 180 and the corresponding common electrode line 122 extend in the same direction, and the ratio of the overlapping area of ​​the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 and the orthographic projection of the common electrode line 122 on the base substrate 110 to the orthographic projection area of ​​the common electrode line 122 on the base substrate 110 is greater than or equal to 80%. Thus, the second electromagnetic trace 180 can overlap with the common electrode line 122 as much as possible, minimizing the impact of the second electromagnetic trace 180 and the common electrode line 122 on the sub-pixel opening 190, thereby maximizing the size of the sub-pixel opening 190.

[0140] In some examples, as shown in Figures 13 and 14 , the second electromagnetic trace 180 and the corresponding common electrode line 122 can extend in substantially the same direction. For example, as shown in Figures 5 and 11 , the second electromagnetic trace 180 and the common electrode line 122 have substantially the same shape. For example, where the common electrode is bent, the second electromagnetic trace 180 also has substantially the same bending characteristics at the same location. Where the common electrode is straight, the second electromagnetic trace 180 also has substantially the same straight extension characteristics at the same location. For example, the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 can completely fall within the orthographic projection of the common electrode line 122 on the base substrate 110.

[0141] In some examples, each second electromagnetic trace 180 of the plurality of second electromagnetic traces 180 may correspond one-to-one with each common electrode line 122 of the plurality of common electrode lines 122. Of course, the embodiments of the present disclosure do not limit the number or position correspondence between the second electromagnetic traces 180 and the common electrode lines 122. For example, a second electromagnetic trace 180 may be provided for every equal number of common electrode lines 122, or a second electromagnetic trace 180 may be provided for every different number of common electrode lines 122.

[0142] In some examples, as shown in FIG13 to FIG17, the method for manufacturing the array substrate 100 includes: forming a patterned gate layer 120 on a base substrate 110; depositing a gate insulating layer 191 on the gate layer 120; forming a patterned active layer on the gate insulating layer 191; forming a patterned source-drain metal layer 130 on the active layer 195; forming a patterned first interlayer insulating layer 192 on the source-drain metal layer 130; forming a patterned first conductive layer 140 on the first interlayer insulating layer 192, the first conductive layer 140 including a second electromagnetic trace 180; forming a patterned second interlayer conductive layer 140 on the first conductive layer 140. an insulating layer 193; a patterned pixel electrode 135 is formed on the second interlayer insulating layer 193, and the pixel electrode 135 is connected to the source-drain metal layer 130 through a via 196; a patterned second conductive layer 150 is formed on the second interlayer insulating layer 193, and the second conductive layer 150 includes a first electromagnetic trace 170; a patterned third interlayer insulating layer 194 is formed on the second conductive layer 150 and the pixel electrode 135; a patterned common electrode layer 160 is formed on the third interlayer insulating layer 194, and the common electrode layer 160 includes a first strip-shaped common electrode 161, a second strip-shaped common electrode 162 and a common electrode pattern 163.

[0143] In some examples, the two ends of the first electromagnetic trace 170 can form a coil loop with the common electrode, and the two ends of the second electromagnetic trace 180 can form a coil loop with the common electrode. Multiple first electromagnetic traces 170 and multiple second electromagnetic traces 180 form a plurality of coil loop arrays. The coil loop array can receive signals, for example, and can calculate the position of the electromagnetic pen based on changes in magnetic flux, thereby realizing electromagnetic touch function. Of course, the embodiments of the present disclosure do not limit the structural design of electromagnetic touch.

[0144] One embodiment of the present disclosure also provides an electromagnetic touch display device. Figure 18 is a schematic diagram of an electromagnetic touch display device provided by one embodiment of the present disclosure. As shown in Figure 18, the electromagnetic touch display device 200 includes any of the aforementioned array substrates 100. Thus, the electromagnetic touch display device 200 exhibits the same beneficial technical effects as those of the aforementioned array substrate 100, which will not be further elaborated here.

[0145] FIG19 is a schematic diagram of another electromagnetic touch display device provided in one embodiment of the present disclosure. As shown in FIG19 , the electromagnetic touch display device 200 includes any of the aforementioned array substrates 100, an opposing substrate 210 positioned opposite the array substrate 100, and a liquid crystal layer 220 disposed between the array substrate 100 and the opposing substrate 210. The array substrate 100 in this example is the array substrate 100 shown in FIG5 , but is not limited thereto.

[0146] In some examples, as shown in FIG19 , the counter substrate 210 includes a black matrix layer 211, and the orthographic projections of the first electromagnetic trace 170 and the data line 131 on the base substrate 110 are located within the orthographic projection of the black matrix layer 201 on the base substrate 110. Through the structural design of the base substrate 110, when solving the problem of undesirable light leakage, it is not necessary to increase the size of the black matrix layer 211, thereby avoiding the impact on the sub-pixel opening. In addition, by matching the first electromagnetic trace 170 with the adjacent data line 131, and matching the second electromagnetic trace 180 with the adjacent gate line 121 and common electrode line 122, the impact of the addition of the first electromagnetic trace 170 and the second electromagnetic trace 180 on the sub-pixel opening can be minimized, and the increase in the size of the black matrix layer 211 can be minimized.

[0147] In some examples, a plurality of common electrode patterns arranged in an array may also be located on the counter substrate 200 .

[0148] For example, the electromagnetic touch display device may be a television, a computer, a navigation system, a car computer, an electronic picture frame, a tablet computer, a mobile phone, or other electronic product with an electromagnetic touch display function.

[0149] One embodiment of the present disclosure also provides a driving method for an electromagnetic touch display device. FIG20 is a flow chart of a driving method for an electromagnetic touch display device provided by one embodiment of the present disclosure. The electromagnetic touch display device includes an array substrate and an opposing substrate arranged in a box with each other, and a liquid crystal layer sandwiched between the array substrate and the opposing substrate. The array substrate includes a plurality of first electromagnetic traces and a common electrode layer. The first electromagnetic traces are arranged along a first direction and extend along a second direction intersecting the first direction. As shown in FIG20 , the driving method includes:

[0150] S100: providing a common voltage to the common electrode layer;

[0151] S200: Providing a touch voltage to the multiple first electromagnetic traces; the difference between the touch voltage and the common voltage is less than the threshold voltage for the rotation of the liquid crystal molecules in the liquid crystal layer. Therefore, the electric field generated by the potential difference between the first electromagnetic traces and the common electrode layer will not affect the deflection of the liquid crystal, thus avoiding the occurrence of unwanted light leakage. It should be noted that the two steps of the driving method can be performed simultaneously or in a time-sharing manner, and there is no order between the two steps. For example, the common voltage can be provided to the common electrode layer first, and then the touch voltage can be provided to the multiple first electromagnetic traces, or vice versa. For example, while providing the common voltage to the common electrode layer, the touch voltage can be provided to the multiple first electromagnetic traces.

[0152] For example, when the change in brightness of the display area of ​​the electromagnetic touch display device reaches a set value for the maximum change, the effective value of the applied driving voltage is defined as the threshold voltage. For example, this set value can be 10% or 15%. Of course, the embodiments of the present disclosure are not limited to this, and other acceptable values ​​can also be designed based on the size and performance requirements of the electromagnetic touch display device.

[0153] For example, the difference between the touch voltage and the common voltage is less than or equal to 0.5 V. Of course, the embodiment of the present disclosure does not impose any specific limitation on the value range of the threshold voltage, which can be set according to the size and performance requirements of the specific electromagnetic touch display device.

[0154] In some examples, the array substrate further includes a plurality of second electromagnetic traces arranged along a second direction and extending along the first direction. The driving method further includes providing a touch voltage to the plurality of second electromagnetic traces. Thus, the difference between the touch voltage and the common voltage is less than a threshold voltage for liquid crystal molecule rotation, and the electric field generated by the potential difference between the second electromagnetic traces and the common electrode layer does not affect liquid crystal deflection, thereby preventing undesirable light leakage.

[0155] In some examples, the touch voltage supplied to the first and second electromagnetic traces can be equal to the common voltage of the common electrode layer, and the first and second electromagnetic traces and the common electrode layer share a common signal. Consequently, there is no potential difference between the first and second electromagnetic traces and the common electrode layer, preventing undesirable light leakage.

[0156] Figure 21 is a schematic structural diagram of another array substrate provided in accordance with an embodiment of the present disclosure; Figure 22 is a schematic cross-sectional structural diagram of Figure 21 taken along section line KL. As shown in Figures 21 and 22, this array substrate 100 differs from the array substrate shown in Figure 5 in that the first strip-shaped common electrode 161 in the common electrode layer 160 has an opening 197, and at least a portion of the orthographic projection of the first electromagnetic trace 170 on the base substrate 110 lies within the orthographic projection of the opening 197 on the plane of the array substrate 100. Thus, without changing the structural design and opening design of the common electrode layer 160, the undesirable light leakage problem can be resolved by ensuring that the difference between the touch voltage and the common voltage is less than the threshold voltage for liquid crystal molecule rotation.

[0157] Figure 23 is a schematic cross-sectional view of the structure of Figure 21 along the cutting line MN; Figure 24 is a simulated diagram of liquid crystal deflection along a cross-sectional plane perpendicular to the direction of the second electromagnetic traces in Figure 21. As shown in Figures 21, 23, and 24, the array substrate 100 further includes a plurality of second electromagnetic traces 180 and a plurality of common electrode patterns 163. The plurality of common electrode patterns 163 are located on the common electrode layer 160. The plurality of second electromagnetic traces 180 are arranged along the second direction Y and extend along the first direction X. The plurality of common electrode patterns 163 are arranged in an array on the plane of the array substrate 100. The common electrode patterns 163 include a plurality of strip electrodes 1630 arranged along the first direction X and extending along the second direction Y. A slit 1631 is defined between two adjacent strip electrodes 1630. The orthographic projection of at least one slit 1631 on the plane of the array substrate 100 at least partially overlaps with the orthographic projection of the second electromagnetic trace 180 on the base substrate 110. A touch voltage is provided to the plurality of second electromagnetic traces 180 , so that the difference between the touch voltage and the common voltage is less than the threshold voltage for the rotation of the liquid crystal molecules. The electric field generated by the potential difference between the second electromagnetic traces 180 and the common electrode layer 160 does not affect the deflection of the liquid crystal, thereby avoiding the occurrence of unwanted light leakage.

[0158] For example, as shown in Figures 23 and 24 , the voltage signal applied to the second electromagnetic trace 180 is the same as the voltage signal applied to the common electrode layer 160. In this case, there is no potential difference between the second electromagnetic trace 180 and the common electrode layer 160, and the liquid crystal is substantially non-deflected. Consequently, undesirable light leakage does not occur during screen display.

[0159] For example, the thickness of the second electromagnetic trace 180 shown in Figures 23 and 24 can be designed as needed, and the present disclosure is not limited thereto. For example, the thickness of the second electromagnetic trace 180 can be increased to reduce resistance. For example, the thickness of the second electromagnetic trace 180 can be made substantially the same as the thickness of the source / drain metal layer 130.

[0160] In some examples, the voltage of the common electrode layer of the electromagnetic touch display device may be a negative voltage, zero, or a positive voltage, which is not limited in the embodiments of the present disclosure.

[0161] There are a few points to note:

[0162] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0163] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0164] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: substrate substrate; A source-drain metal layer, located on the base substrate, includes a plurality of data lines arranged along a first direction and extending along a second direction, wherein the first direction and the second direction are arranged to intersect each other; A common electrode layer, located on a side of the source-drain metal layer away from the base substrate, comprising a plurality of first strip-shaped common electrodes extending along the second direction, wherein the plurality of first strip-shaped common electrodes are arranged in an array on the base substrate to form a plurality of first strip-shaped common electrode columns; a plurality of first electromagnetic traces, arranged along the first direction and extending along the second direction, and located on a side of the common electrode layer facing the base substrate; Each of the plurality of first electromagnetic wirings is arranged corresponding to one of the plurality of data lines, and the plurality of first electromagnetic wirings are arranged one-to-one corresponding to the plurality of first strip-shaped common electrode columns. For the data lines, the first strip common electrode columns and the first electromagnetic routing lines that correspond to each other, in an area sandwiched by two straight lines passing through the two ends of each of the first strip common electrodes and extending along the first direction, the orthographic projections of the first electromagnetic routing lines and the data lines on the base substrate fall within the orthographic projections of the first strip common electrodes on the base substrate.

2. The array substrate according to claim 1, wherein: The first strip-shaped common electrodes are continuously arranged in a direction parallel to the base substrate and perpendicular to an extending direction of the first strip-shaped common electrodes.

3. The array substrate according to claim 1, wherein: For the data lines, the first strip common electrode columns and the first electromagnetic routing wires that correspond to each other, in an area sandwiched by two straight lines passing through the two ends of each of the first strip common electrodes and extending along the first direction, the orthographic projection of the interval between the first electromagnetic routing wires and the data lines on the base substrate falls within the orthographic projection of the first strip common electrode on the base substrate.

4. The array substrate according to any one of claims 1 to 3, wherein: The common electrode layer also includes a plurality of second strip common electrodes extending along the second direction, and the plurality of second strip common electrodes are arranged in an array on the base substrate to form a plurality of second strip common electrode columns, and each of the plurality of second strip common electrode columns is at least partially overlapped with one of the plurality of data lines, and the data line at least partially overlapped with the second strip common electrode column and the data line corresponding to the first electromagnetic routing are different data lines.

5. The array substrate according to claim 4, wherein: At least one second strip-shaped common electrode column is disposed between every two adjacent first strip-shaped common electrode columns.

6. The array substrate according to claim 5, wherein: Two second strip-shaped common electrode columns are disposed between every two adjacent first strip-shaped common electrode columns.

7. The array substrate according to claim 4, wherein: The width of the second strip-shaped common electrode in the first direction is smaller than the width of the first strip-shaped common electrode in the first direction.

8. The array substrate according to claim 4, wherein: The plurality of first electromagnetic routing lines are located in the source-drain metal layer, and each of the plurality of first electromagnetic routing lines is disposed adjacent to one of the plurality of data lines.

9. The array substrate according to claim 8, further comprising: A gate layer, located between the base substrate and the source-drain metal layer, comprising a plurality of gate lines extending along a first direction and arranged along the second direction; A gate insulating layer, located on a side of the gate layer away from the substrate; as well as A first interlayer insulating layer is located on a side of the source / drain metal layer away from the substrate; A first conductive layer, located on a side of the first interlayer insulating layer away from the substrate; A second interlayer insulating layer is located on a side of the first conductive layer away from the substrate; as well as A plurality of second electromagnetic traces are located in the first conductive layer, extending along a first direction and arranged along the second direction, Wherein, each of the plurality of second electromagnetic wires is arranged corresponding to one of the plurality of gate wires.

10. The array substrate according to claim 9, wherein: The common electrode layer also includes a plurality of common electrode patterns, which are arranged in an array on the base substrate to form a plurality of common electrode pattern rows and a plurality of common electrode pattern columns, and each of the plurality of common electrode pattern columns is located between adjacent second strip common electrode columns or between adjacent first strip common electrode columns and second strip common electrode columns.

11. The array substrate according to claim 10, wherein: The common electrode pattern includes a plurality of strip electrodes arranged along the first direction and extending along the second direction, a slit is provided between two adjacent strip electrodes, and an orthographic projection of an end portion of at least one slit of each common electrode pattern on the base substrate at least partially overlaps with an orthographic projection of the second electromagnetic trace on the base substrate.

12. The array substrate according to claim 10, further comprising: A plurality of pixel electrodes are arranged in an array along the first direction and the second direction and are arranged one-to-one corresponding to the plurality of common electrode patterns. The source-drain metal layer further includes a plurality of drain electrodes, which are arranged in an array along the first direction and the second direction and are arranged one-to-one with the plurality of pixel electrodes, and the orthographic projection of the drain electrode on the base substrate overlaps with the orthographic projection of one of the plurality of gate lines on the base substrate. The drain electrode comprises a connecting portion, the orthographic projection of the connecting portion on the base substrate overlaps with the orthographic projection of the corresponding pixel electrode on the base substrate to be connected to the pixel electrode, The connection portion of the drain electrode overlapping the same gate line and the second electromagnetic wiring arranged corresponding to the gate line are respectively located on both sides of the center line of the gate line along the second direction.

13. The array substrate according to claim 12, wherein: The gate layer further includes a plurality of common electrode lines extending along the first direction and arranged along the second direction, and each of the plurality of common electrode lines is disposed adjacent to one of the plurality of gate lines.

14. The array substrate according to claim 13, wherein: Each of the plurality of second electromagnetic wirings is arranged corresponding to one of the plurality of common electrode wires, The second electromagnetic trace is consistent with the corresponding common electrode line in extension direction, and the ratio of the overlapping area of ​​the orthographic projection of the second electromagnetic trace on the substrate and the orthographic projection of the common electrode line on the substrate to the orthographic projection area of ​​the common electrode line on the substrate is greater than or equal to 80%.

15. The array substrate according to claim 14, wherein: The orthographic projection of the common electrode line on the substrate includes a first boundary segment that is farthest from the center line of a gate line adjacent to the common electrode line, and the orthographic projection of the second electromagnetic trace corresponding to the gate line on the substrate includes a second boundary segment that is farthest from the center line of the gate line, and the distance between the first boundary segment and the center line of the gate line is greater than or equal to the distance between the second boundary segment and the center line of the gate line.

16. The array substrate according to claim 14, wherein: The gate line includes a plurality of protrusions, and the protrusions protrude toward the corresponding common electrode lines. The common electrode line includes a plurality of bending portions, the plurality of bending portions are arranged one by one corresponding to the protruding portion and are bent away from the protruding portion, the common electrode line also includes a plurality of transverse connecting portions, two adjacent bending portions are connected by the transverse connecting portions, the plurality of bending portions include a plurality of first bending portions and a plurality of second bending portions, in a plane parallel to the base substrate, the first strip common electrode The second strip common electrode column passes through the first bending portion, the second strip common electrode column passes through the second bending portion, and the size of the first bending portion in the first direction is greater than the size of the second bending portion in the first direction.

17. The array substrate according to claim 4, further comprising: A gate layer, located between the base substrate and the source-drain metal layer, comprising a plurality of gate lines extending along a first direction and arranged along the second direction; A gate insulating layer, located on a side of the gate layer away from the substrate; A first interlayer insulating layer is located on a side of the source / drain metal layer away from the substrate; A second conductive layer is located on a side of the first interlayer insulating layer away from the substrate; as well as A third interlayer insulating layer is located on a side of the second conductive layer away from the substrate; The plurality of first electromagnetic wirings are located in the second conductive layer, and each of the plurality of first electromagnetic wirings at least partially overlaps with one of the plurality of data lines.

18. The array substrate according to claim 17, further comprising: A first conductive layer, located on a side of the gate insulating layer away from the substrate; A second interlayer insulating layer is located on a side of the first conductive layer away from the substrate; as well as A plurality of second electromagnetic traces are located in the first conductive layer, extending along a first direction and arranged along the second direction, Wherein, each of the plurality of second electromagnetic wires is arranged corresponding to one of the plurality of gate wires.

19. An electromagnetic touch display device, comprising: The array substrate according to any one of claims 1 to 18; An opposing substrate, arranged in a box with the array substrate; as well as The liquid crystal layer is arranged between the array substrate and the counter substrate.

20. A driving method for an electromagnetic touch display device, the electromagnetic touch display device comprising an array substrate and an opposing substrate arranged opposite to each other and a liquid crystal layer sandwiched between the array substrate and the opposing substrate, the array substrate comprising a plurality of first electromagnetic traces and a common electrode layer, the first electromagnetic traces being arranged along a first direction and extending along a second direction intersecting the first direction, the driving method comprising: Providing a common voltage to the common electrode layer; as well as Providing a touch voltage to the plurality of first electromagnetic wirings; The difference between the touch voltage and the common voltage is smaller than the liquid crystal layer. The threshold voltage for crystal molecule rotation.

21. The driving method according to claim 20, wherein: The array substrate further includes a plurality of second electromagnetic traces and a plurality of common electrode patterns located in the common electrode layer, the plurality of second electromagnetic traces are arranged along a second direction and extend along the first direction, the plurality of common electrode patterns are arranged in an array on the plane of the array substrate, the common electrode pattern includes a plurality of strip electrodes arranged along the first direction and extending along the second direction, a slit is provided between two adjacent strip electrodes, and an orthographic projection of at least one of the slits on the plane of the array substrate at least partially overlaps with an orthographic projection of the second electromagnetic trace on the plane of the array substrate, and the driving method further includes: The touch voltage is provided to the plurality of second electromagnetic traces.

22. The driving method according to claim 20 or 21, wherein: A difference between the touch voltage and the common voltage is less than or equal to 0.5V.

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