Display device

Abstract

In an organic EL display device (1), on the lower layer side of a sealing film (80) in a frame region (FA), there is provided a lead-out line (40h) that extends from a display region (DA) so as to intersect a joining part (SZ) of the sealing film (80) and is lead out to a terminal part (TP). The lead-out line includes a first wiring layer (41) and a second wiring layer (42) laminated on the first wiring layer via a first interlayer insulating film (26). The first wiring layer and the second wiring layer are connected via a pair of first contact holes (Ha) formed in the first interlayer insulating film. A joining part is provided between the pair of first contact holes in plan view.

Description

display device

[0001] The present disclosure relates to a display device.

[0002] In recent years, organic electroluminescence (EL) display devices using organic electroluminescence (hereinafter referred to as EL) elements have been put to practical use. A plurality of organic EL elements are arranged in a predetermined array to form a display area where images are displayed. A frame area is provided outside the display area as a non-display area. The frame area is provided with a drive circuit for controlling image display, a power supply main line, lead lines, and the like.

[0003] Organic EL elements are susceptible to deterioration due to the influence of moisture. For this reason, organic EL display devices employ a technology for encapsulating the organic EL elements by covering them with an encapsulation film. One such technology is thin film encapsulation (TFE) technology. This technology aims to achieve high moisture barrier properties while maintaining flexibility through the use of an encapsulation film formed by alternately laminating inorganic and organic barrier layers.

[0004] The organic EL display device also includes a circuit board on which a drive circuit and other components are provided. The circuit board includes a surface insulating film made of an inorganic insulating material and a planarization film provided on the surface insulating film. The surface insulating film is provided so as to extend over the frame region. The sealing film forms a frame-shaped joint in the frame region where the inorganic barrier layer contacts the surface insulating film. The planarization film is made of an organic resin material and therefore has poor moisture barrier properties, but is surrounded by the joint together with the organic EL element. This provides the effect of preventing external moisture from penetrating the planarization film and being introduced into the display region.

[0005] A terminal portion for connecting to an external circuit is provided outside the joint portion in the frame region. A plurality of lead lines connected to source lines and the like are provided in the frame region between the display region and the terminal portion. Each of these lead lines extends from the display region through the lower layer of the sealing film so as to intersect with the joint portion and is led out to the terminal portion. It is conventionally known that the lead lines have a laminated structure.

[0006] For example, Patent Document 1 discloses that in an organic EL display device, lead lines are formed as a laminated body made of a gate metal layer and a source metal layer. An interlayer insulating layer is provided above the gate metal layer. A source metal layer is provided above the interlayer insulating layer. A contact opening is formed in the interlayer insulating layer. The source metal layer is connected to the gate metal layer through the opening.

[0007] International Publication No. 2018 / 229876

[0008] In the organic EL display device of Patent Document 1, a contact opening formed in an interlayer insulating layer extends along the length of the gate metal layer from the inside to the outside of the junction. The surface exposed through the contact opening in the gate metal layer is prone to becoming rough and uneven due to the etching process used to form the opening. This can create a path through which external moisture can penetrate the junction into the contact opening. If moisture penetrates through this path and down the lead wire into the display area, it can cause degradation of the organic EL element, reducing the display quality and reliability of the organic EL display device.

[0009] An object of the present disclosure is to prevent moisture from entering the display area through the lead wires.

[0010] The present disclosure relates to a display device. The display device according to the present disclosure includes a circuit board, a plurality of light-emitting elements provided on the circuit board, and a sealing film provided to cover the plurality of light-emitting elements. The plurality of light-emitting elements form a display area for displaying an image. A frame area is provided outside the display area as a non-display area where no image is displayed. The circuit board includes a base substrate and a stacked insulating film formed by stacking inorganic insulating materials on the base substrate so as to extend over the frame area. The sealing film has an inorganic barrier layer made of an inorganic insulating material. The frame area includes a frame-shaped joint portion where a portion along the periphery of the inorganic barrier layer contacts the stacked insulating film, and a terminal portion located outside the joint. A lead line is provided below the sealing film in the frame area, extending from the display area to intersect the joint portion and leading to the terminal portion. The lead line includes a first wiring layer and a second wiring layer stacked on the first wiring layer with a first inorganic insulating film interposed therebetween. The first wiring layer and the second wiring layer are connected to each other via a pair of first contact holes formed in the first inorganic insulating film, and the junction portion is provided between the pair of first contact holes in a plan view.

[0011] According to the display device according to the present disclosure, it is possible to prevent moisture from entering the display area through the lead wires.

[0012] FIG. 1 is a plan view illustrating a schematic configuration of an organic EL display device according to Embodiment 1. FIG. 2 is a cross-sectional view of the organic EL display device taken along line II-II in FIG. 1. FIG. 3 is a plan view illustrating pixels and various wirings in a display region of the organic EL display device. FIG. 4 is a cross-sectional view of the organic EL display device taken along line IV-IV in FIG. 3. FIG. 5 is a plan view illustrating a main portion of the organic EL display device surrounded by V in FIG. 1. FIG. 6 is a cross-sectional view of a main portion of the organic EL display device taken along line VI-VI in FIG. 5. FIG. 7 is a cross-sectional view of a main portion of the organic EL display device taken along line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view illustrating a manufacturing process of the organic EL display device according to Embodiment 1. FIG. 9A is a plan view illustrating a main portion of the organic EL display device according to Embodiment 1 during a light emission inspection. FIG. 9B is a plan view illustrating a main portion of an organic EL display device according to a comparative example during a light emission inspection. FIG. 10 is a plan view of a portion of the organic EL display device according to Embodiment 2 corresponding to FIG. 4. FIG. 11 is a cross-sectional view of a main portion of the organic EL display device taken along line XI-XI in FIG. 10. FIG. 12 is a cross-sectional view of a main portion of the organic EL display device taken along line XII-XII in FIG. 10 . FIG. 13 is a cross-sectional view of a main portion of the organic EL display device taken along line XIII-XIII in FIG. 10 . FIG. 14 is a cross-sectional view illustrating a manufacturing process of the organic EL display device of embodiment 2. FIG. 15 is a plan view of a portion of the organic EL display device of embodiment 3 corresponding to FIG. 5 . FIG. 16 is a cross-sectional view of a main portion of the organic EL display device taken along line XVI-XVI in FIG. 15 . FIG. 17 is a cross-sectional view of a main portion of the organic EL display device taken along line XVII-XVII in FIG. 15 . FIG. 18 is a cross-sectional view illustrating a manufacturing process of the organic EL display device of embodiment 3. FIG. 19A is a cross-sectional view illustrating the structure of a lead wire of a reference example. FIG. 19B is a cross-sectional view illustrating the structure of a lead wire of a reference example. FIG. 20 is a cross-sectional view illustrating a schematic configuration of an organic EL display device of another embodiment.

[0013] Exemplary embodiments will be described in detail below with reference to the drawings. In the following embodiments, an organic EL display device will be described as an example of a display device according to the present disclosure. Note that the drawings are intended to conceptually explain the technology of the present disclosure. Therefore, in the drawings, dimensions, ratios, or numbers may be exaggerated or simplified to facilitate understanding of the technology of the present disclosure.

[0014] In the following embodiments, the term "first direction" refers to the horizontal direction of the screen when the display device is oriented in a predetermined state of use. The term "second direction" refers to the direction perpendicular to the first direction and to the vertical direction of the screen when the display device is oriented in a predetermined state of use. A row of components such as subpixels refers to a horizontal arrangement of multiple components in a row in the first direction. A column of components such as subpixels refers to a vertical arrangement of multiple components in a row in the second direction.

[0015] In the following embodiments, when a component such as a film, layer, or element is provided or formed on another component such as another film, layer, or element, it does not only mean that the other component exists directly on top of the other component, but also includes cases where another component such as a film, layer, or element is interposed between the two components.

[0016] In the following embodiments, unless otherwise specified, a description that a certain component is connected to another component means that the components are electrically connected. This description not only means a direct connection, but also an indirect connection via other components, within the scope of the gist of the technology of the present disclosure. This description also includes a case where another component is integrated with a certain component, that is, a part of a certain component constitutes the other component.

[0017] In the following embodiments, a description that a certain component is in the same layer as another component means that the certain component is formed in the same process as the other component. A description that a certain component is a lower layer than the other component means that the certain component is deposited in an earlier process than the other component or is formed from a film deposited in an earlier process. A description that a certain component is an upper layer than the other component means that the certain component is deposited in a later process than the other component or is formed from a film deposited in a later process.

[0018] In the following embodiments, a description that a certain component is identical to or equivalent to another component does not mean only a state in which the certain component and the other component are completely identical or completely equivalent, but also a state in which the certain component and the other component are substantially identical or substantially equivalent, such as fluctuating within the range of manufacturing variations or tolerances.

[0019] In the following embodiments, the terms first, second, third, etc. are used to distinguish between terms to which these terms are attached, and do not limit the number of terms or even their order.

[0020] The organic EL display device 1 of this embodiment 1 is used as a display for a mobile device such as a multi-function phone called a smartphone or a tablet terminal. The organic EL display device 1 may also be used as a display for various other devices such as a personal computer (PC) or a television set.

[0021] -Configuration of Organic EL Display Device- The organic EL display device 1 is a display device that uses organic EL elements 65, also known as OLEDs (Organic Light Emitting Diodes). The organic EL display device 1 employs an active matrix drive system and is configured to provide a full-color display. As shown in Figures 1 and 2, the organic EL display device 1 has a display area DA and a frame area FA.

[0022] The display area DA is an area for displaying an image and constitutes a screen. The display area DA is provided, for example, in a rectangular shape. The display area DA may be a substantially rectangular shape, such as a shape with at least one arc-shaped side, a shape with at least one arc-shaped corner, or a shape with a notch on at least one side, or may be any other shape.

[0023] As shown in Fig. 3, the display area DA is composed of a plurality of pixels PX. The plurality of pixels PX are arranged in a matrix. Each pixel PX is composed of three sub-pixels SP. The three sub-pixels SP are a sub-pixel SPr that emits red light, a sub-pixel SPg that emits green light, and a sub-pixel SPb that emits blue light. These three sub-pixels SP are arranged, for example, in a striped pattern.

[0024] The display area DA is provided with a plurality of organic EL elements 65 and a plurality of pixel circuits PC. The plurality of organic EL elements 65 are provided corresponding to a plurality of sub-pixels SP. Each sub-pixel SP is formed by an organic EL element 65. The pixel circuit PC is a circuit for each sub-pixel, and controls the light emission of the organic EL element 65 that constitutes the corresponding sub-pixel SP.

[0025] 1 and 2 , the frame area FA is an area that constitutes the non-display portion outside the screen. The frame area FA is provided around the display area DA, for example, in the shape of a rectangular frame. The frame area FA may have a frame shape other than a rectangle. The frame area FA includes a joint portion SZ, a terminal portion TP, and a bending portion BP.

[0026] The joint portion SZ is a portion (hatched area in FIG. 1 ) where a portion along the periphery of the first inorganic barrier layer 81 constituting the sealing film 80 (described later) comes into contact with the laminated insulating film 36 included in the circuit board 5. The laminated insulating film 36 is a laminate of inorganic insulating films formed by laminating inorganic insulating materials. The joint portion SZ is provided in a frame shape so as to surround the display area DA, and blocks external moisture from entering the display area DA.

[0027] The terminal portion TP is a portion for connecting to an external circuit such as a display control circuit (source driver). The terminal portion TP is provided near the outer edge of a portion constituting one side of the frame area FA extending in the first direction Dx, and extends along that side. The terminal portion TP is located outside the joint portion SZ. A wiring board CB such as an FPC (Flexible Printed Circuit) is connected to the terminal portion TP.

[0028] The bent portion BP is provided between the terminal portion TP and the display area DA and extends horizontally across the entire frame area FA in the first direction Dx. The frame area FA is bent at the bent portion BP, for example, by about 180 degrees, to form a U-shape (shown by the two-dot chain line in FIG. 2 ). This positions the terminal portion TP on the rear side of the organic EL display device 1.

[0029] A driving circuit (not shown) is provided in the frame area FA. The driving circuit is arranged in a portion of the frame area FA that forms the side (each of the left and right sides in FIG. 1 ) adjacent to the side on which the terminal portion TP is provided. The driving circuit is monolithically formed as part of the TFT layer 20, which will be described later. The driving circuit includes a gate driver and an emission driver.

[0030] Although not shown, a first frame line and a second frame line are provided in the frame area FA. Both the first frame line and the second frame line are power supply trunk lines that are formed to surround the display area DA and extend to the terminal portion TP. A high-level power supply voltage (ELVDD) is supplied to the first frame line via the wiring board CB. A low-level power supply voltage (ELVSS) is supplied to the second frame line via the wiring board CB.

[0031] The frame area FA is further provided with a plurality of lead lines 40h. Each of the lead lines 40h is drawn out from the display area DA and extends to the terminal portion TP. The end of each lead line 40h located at the terminal portion TP and the ends of the first frame line and the second frame line each form a terminal. The terminal portion TP has these multiple terminals.

[0032] 2, the organic EL display device 1 includes a circuit board 5, a light-emitting element layer 60, and a sealing film 80. The circuit board 5 includes a substrate layer 10 and a TFT layer (thin film transistor layer) 20. The circuit board 5 includes a plurality of circuit elements provided in a display area DA.

[0033] <Substrate Layer> The substrate layer 10 is an example of a base substrate. The substrate layer 10 in this example is a substrate made of a flexible resin. The substrate layer 10 is formed of an organic resin material such as polyimide resin, polyamide resin, or epoxy resin. The substrate layer 10 is made up of an organic insulating layer made of the organic resin material described above and a silicon oxide (SiO ２ A protective film 11 is attached to the back surface of the substrate layer 10.

[0034] <TFT Layer> The TFT layer 20 is provided on the substrate layer 10. In addition to the drive circuit described above, the TFT layer 20 includes a base coat film 21, various wirings 40, and a plurality of pixel circuits PC shown in Figures 3 and 4. The drive circuit, the various wirings 40, and the pixel circuits PC are provided on the base coat film 21. The base coat film 21 is provided on the substrate layer 10 and extends over substantially the entire surface of the substrate layer 10.

[0035] The various wirings 40 include the first frame line, second frame line, and lead line 40h described above. In addition, the various wirings 40 include a plurality of gate lines 40g, a plurality of light-emitting control lines 40e, a plurality of initialization lines 40i, a plurality of power supply lines 40p, and a plurality of source lines 40s. Each of the gate lines 40g, light-emitting control lines 40e, initialization lines 40i, power supply lines 40p, and source lines 40s is provided in the display area DA.

[0036] The gate lines 40g are wirings that transmit gate signals to the pixel circuits PC. The gate lines 40g are arranged at intervals in the second direction Dy and extend parallel to each other in the first direction Dx. The gate lines 40g include first gate lines 40ga and second gate lines 40gb.

[0037] The first gate line 40ga is a gate line 40g used to control the P-channel TFT 50. The second gate line 40gb is a gate line 40g used to control the N-channel TFT 50. The first gate line 40ga and the second gate line 40gb are provided for each row of sub-pixels SP. Each first gate line 40ga and each second gate line 40gb is drawn out to the frame area FA and connected to a gate driver of the drive circuit.

[0038] Each of the plurality of light-emission control lines 40e is a wiring that transmits an emission signal to the pixel circuit PC. The plurality of light-emission control lines 40e are arranged at intervals from one another in the second direction Dy and extend parallel to one another in the first direction Dx. One light-emission control line 40e is provided for each row of sub-pixels SP. Each light-emission control line 40e is drawn out to the frame area FA and connected to an emission driver of the drive circuit.

[0039] The multiple initialization lines 40i are wirings that apply an initialization voltage to the pixel circuits PC. The multiple initialization lines 40i are arranged at intervals from one another in the second direction Dy and extend parallel to one another in the first direction Dx. One initialization line 40i is provided for each row of subpixels SP. Each initialization line 40i is drawn out to the frame area FA and connected to a drive circuit or a second frame line.

[0040] Each of the multiple power supply lines 40p is a wiring that applies a predetermined high-level power supply voltage (ELVDD) to the pixel circuits PC. The multiple power supply lines 40p are arranged at intervals from one another in the first direction Dx and extend parallel to one another in the second direction Dy. One power supply line 40p is provided for each column of sub-pixels SP. Each power supply line 40p is drawn out into the frame area FA and connected to the first frame line.

[0041] Each of the multiple source lines 40s is a wiring that transmits a source signal to the pixel circuit PC. The multiple source lines 40s are arranged at intervals from one another in the first direction Dx and extend parallel to one another in the second direction Dy. A source line 40s is provided for each column of subpixels SP. Each source line 40s is drawn out to a terminal portion TP as a lead line 40h and connected to a display control circuit (source driver) via a wiring substrate CB.

[0042] The first gate line 40ga, the light-emitting control line 40e, and the initialization line 40i are formed of the same material in the same layer as a first gate electrode 24 (described later). The second gate line 40gb is formed of the same material in the same layer as a second gate electrode 33 (described later) and a second capacitor electrode 30. The power supply line 40p and the source line 40s are formed of the same material in the same layer as a first terminal electrode 37 and a second terminal electrode 38 (described later).

[0043] Each pixel circuit PC is connected to a first gate line 40ga, a second gate line 40gb, a light-emitting control line 40e, an initialization line 40i, a power supply line 40p, and a source line 40s. Each pixel circuit PC operates based on signals and voltages supplied by these various wirings 40, and in each frame, resets the charge accumulated in the pixel electrode 61 and then supplies a drive current corresponding to the source signal to the organic EL element 65.

[0044] 4 to 7, the pixel circuit PC includes a plurality of TFTs 50 and a capacitor 55. The TFTs 50 and the capacitors 55 are each an example of a circuit element. The plurality of TFTs 50 constituting the pixel circuit PC include a first TFT 50A and a second TFT 50B. The first TFT 50A, the second TFT 50B, and the capacitor 55 are provided corresponding to a plurality of sub-pixels SP, and a pixel circuit PC is constituted for each sub-pixel SP.

[0045] The first TFT 50A is a P-channel TFT 50 and is configured as a top-gate type with a top-contact structure. The first TFT 50A has a first semiconductor layer 22, a first gate insulating film 23, a first gate electrode 24, an interlayer insulating film 35, a first terminal electrode 37, and a second terminal electrode 38.

[0046] The first semiconductor layer 22 is provided in an island shape on the base coat film 21, and is provided continuously for the multiple first TFTs 50A. The first semiconductor layer 22 may be separated into individual first TFTs 50A. The first semiconductor layer 22 includes a first channel region 22a and a pair of first conductor regions 22b. The first channel region 22a is provided between the pair of first conductor regions 22b. The pair of first conductor regions 22b are provided spaced apart from each other with the first channel region 22a sandwiched therebetween.

[0047] The first gate insulating film 23 is provided continuously over the multiple first TFTs 50A so as to cover the multiple first semiconductor layers 22. The first gate insulating film 23 may be provided in an island shape on each first semiconductor layer 22 and may be individually separated for each first TFT 50A. The first gate electrode 24 is provided on the first gate insulating film 23. The first gate electrode 24 overlaps with the first channel region 22a of the first semiconductor layer 22 via the first gate insulating film 23.

[0048] The interlayer insulating film 35 is provided so as to cover the plurality of first gate electrodes 24. The interlayer insulating film 35 is configured by stacking a first interlayer insulating film 26 and a second interlayer insulating film 34 in this order on the first gate insulating film 23. A plurality of third contact holes Hc are formed in the interlayer insulating film 35.

[0049] A pair of third contact holes Hc are provided for each predetermined first TFT 50A. The pair of third contact holes Hc penetrate to different first conductor regions 22b of the corresponding first semiconductor layer 22. The first terminal electrode 37 and the second terminal electrode 38 are provided at positions spaced apart from each other on the interlayer insulating film 35. The first terminal electrode 37 and the second terminal electrode 38 are connected to the first conductor region 22b of the first semiconductor layer 22 via different third contact holes Hc.

[0050] The second TFT 50B is an N-channel TFT 50 and is configured as a top-gate type with a bottom-contact structure. The second TFT 50B has a third terminal electrode 28, a fourth terminal electrode 29, a second semiconductor layer 31, a second gate insulating film 32, and a second gate electrode 33.

[0051] The third terminal electrode 28 and the fourth terminal electrode 29 are provided at positions spaced apart from each other on the first interlayer insulating film 26. A fourth contact hole Hd is formed in the second interlayer insulating film 34 corresponding to a predetermined second TFT 50B. The fourth contact hole Hd penetrates to the third terminal electrode 28 or the fourth terminal electrode 29 of the predetermined second TFT 50B. A relay line 40r and other wiring are provided on the second interlayer insulating film 34 for each pixel circuit PC. The relay line 40r is connected to the third terminal electrode 28 or the fourth terminal electrode 29 via the fourth contact hole Hd.

[0052] The second semiconductor layer 31 is provided in an island shape on the first interlayer insulating film 26, and is provided continuously for the plurality of second TFTs 50B. The second semiconductor layer 31 may be separated for each second TFT 50B. The second semiconductor layer 31 includes a second channel region 31a and a pair of second conductor regions 31b. The second channel region 31a is provided between the pair of second conductor regions 31b. The pair of second conductor regions 31b are provided spaced apart from each other with the second channel region 31a sandwiched therebetween.

[0053] One second conductor region 31b in the second semiconductor layer 31 partially overlaps the third terminal electrode 28, and the other second conductor region 31b partially overlaps the fourth terminal electrode 29. The second gate insulating film 32 is formed in an island shape on the first interlayer insulating film 26, and is provided continuously for the plurality of second TFTs 50B. The second gate insulating film 32 may be separated individually for each second TFT 50B.

[0054] The second gate insulating film 32 is provided so as to partially cover the multiple second semiconductor layers 31. The second gate insulating film 32 overlaps the second channel region 31a of each second semiconductor layer 31 and exposes the second conductor region 31b. The second gate electrode 33 is provided on the second gate insulating film 32. The second gate electrode 33 overlaps the second channel region 31a of the second semiconductor layer 31 with the second gate insulating film 32 interposed therebetween.

[0055] The capacitor 55 includes a first capacitance electrode 25, a second capacitance electrode 30, and a second gate insulating film 32. The first capacitance electrode 25 is formed of the same material in the same layer as the third terminal electrode 28 and the fourth terminal electrode 29, and is provided on the first interlayer insulating film 26. The second capacitance electrode 30 is provided on the second gate insulating film 32. The first capacitance electrode 25 and the second capacitance electrode 30 overlap each other with the second gate insulating film 32 interposed therebetween.

[0056] The base coat film 21, the first gate insulating film 23, the first interlayer insulating film 26, the second gate insulating film 32, and the second interlayer insulating film 34 are each made of, for example, silicon oxide (SiO ２ The insulating film may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxynitride, etc. These various inorganic insulating films may be made of a single layer film or a multilayer film.

[0057] The base coat film 21, the first gate insulating film 23, the first interlayer insulating film 26, the second gate insulating film 32, and the second interlayer insulating film 34 are stacked one on top of the other to form a stacked insulating film 36. That is, the stacked insulating film 36 is formed by stacking inorganic insulating materials. The stacked insulating film 36 is provided on the substrate layer 10 so as to extend over the entire display area DA and the frame area FA. The circuit board 5 includes such a stacked insulating film 36.

[0058] The various wirings 40 and electrodes described above are made of metal materials such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), etc. These various wirings 40 and electrodes may be made of a single layer film or a multilayer film.

[0059] The first semiconductor layer 22 is made of polysilicon. The polysilicon that constitutes the first semiconductor layer 22 is, for example, low temperature polycrystalline silicon (LTPS). The second semiconductor layer 31 is made of an oxide semiconductor. The oxide semiconductor that constitutes the second semiconductor layer 31 is, for example, an In—Ga—Zn—O-based semiconductor.

[0060] The TFT layer 20 further includes a planarization film 59. The planarization film 59 is provided on the second interlayer insulating film 34 so as to cover the various wirings 40, the plurality of TFTs 50, and the plurality of capacitors 55 in the display area DA. The planarization film 59 extends over the entire display area DA. The surface of the TFT layer 20 is planarized by the planarization film 59.

[0061] A fifth contact hole He is formed for each sub-pixel SP in the planarization film 59. The fifth contact hole He penetrates to the relay line 40r. The planarization film 59 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (Spin On Glass) material.

[0062] <Light-emitting element layer> The light-emitting element layer 60 is provided on the circuit board 5 (TFT layer 20). The light-emitting element layer 60 includes a plurality of organic EL elements 65 (organic electroluminescence elements) and an edge cover 66. The organic EL elements 65 are an example of a light-emitting element. The organic EL elements 65 are configured as a top-emission type. Light emitted by the organic EL elements 65 is extracted to the sealing film 80 side.

[0063] A plurality of organic EL elements 65 are provided corresponding to a plurality of sub-pixels SP. Each organic EL element 65 constitutes a sub-pixel SP. The light emission of each organic EL element 65 is controlled by the operation of the corresponding pixel circuit PC. Each organic EL element 65 has a pixel electrode 61, an organic EL layer 62, and a common electrode 63.

[0064] The pixel electrodes 61 are provided on the planarization film 59. The pixel electrodes 61 are arranged in a matrix corresponding to each of the plurality of sub-pixels SP. Each pixel electrode 61 is connected to a relay line 40r via a fifth contact hole He, and is connected to a third terminal electrode or a fourth terminal electrode (the fourth terminal electrode; pixel circuit PC in the example shown in FIG. 4 ) through the relay line 40r. The pixel electrode 61 functions as an anode and injects holes into the organic EL layer 62. It is preferable to use a conductive material with a large work function for the pixel electrode 61.

[0065] Examples of materials for the pixel electrodes 61 include metals such as silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), indium (In), and tin (Sn). The material for the pixel electrodes 61 may be a metal compound or an alloy. The material for the pixel electrodes 61 may be a conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrodes 61 may be formed of a single layer film or a laminated film.

[0066] The edge cover 66 is provided on the planarization film 59. The edge cover 66 is located above the pixel electrodes 61. The edge cover 66 is formed in a lattice shape so as to separate the multiple pixel electrodes 61. Specifically, the edge cover 66 extends between adjacent pixel electrodes 61 and around the periphery of the display area DA, and covers the outer edge (peripheral end portion) of each pixel electrode 61.

[0067] The edge cover 66 has a plurality of openings 67 corresponding to the sub-pixels SP. Each opening 67 partially exposes the pixel electrode 61 from the edge cover 66. The edge cover 66 is made of the same material as the planarizing film 59, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG material.

[0068] The organic EL layer 62 is provided on each pixel electrode 61 within the opening 67 of the edge cover 66. The organic EL layer 62 has a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer are stacked in this order on the pixel electrode 61 and are made of known compounds suitable for their respective functions. The organic EL layer 62 emits light when a current is applied between the pixel electrode 61 and the common electrode 63.

[0069] The common electrode 63 is provided as a continuous common film spanning multiple subpixels SP, extending across the entire display area DA. The common electrode 63 covers the edge cover 66 and each organic EL layer 62, and overlaps each pixel electrode 61 via the organic EL layer 62. The common electrode 63 also extends into the frame area FA and is connected to the second frame line. The common electrode 63 functions as a cathode and injects electrons into the organic EL layer 62. It is preferable to use a conductive material with a small work function for the common electrode 63.

[0070] Examples of materials for the common electrode 63 include conductive oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). The material for the common electrode 63 may be a metal such as silver (Ag), aluminum (Al), lithium (Li), magnesium (Mg), calcium (Ca), or ytterbium (Yb). The material for the common electrode 63 may be a metal compound or an alloy. The common electrode 63 may be formed of a single layer film or a laminated film.

[0071] <Sealing Film> The sealing film 80 is provided on the light-emitting element layer 60. The sealing film 80 covers and seals the plurality of organic EL elements 65, protecting each organic EL element 65 (particularly the organic EL layer 62) from moisture, oxygen, and the like. The sealing film 80 is provided over the entire display area DA and extends to the frame area FA. The sealing film 80 has a first inorganic barrier layer 81, an organic barrier layer 82, and a second inorganic barrier layer 83.

[0072] The first inorganic barrier layer 81 is provided to cover the common electrode 63. The organic barrier layer 82 is provided on the first inorganic barrier layer 81. The second inorganic barrier layer 83 is provided on the organic barrier layer 82. The first inorganic barrier layer 81 and the second inorganic barrier layer 83 extend further toward the outer periphery of the frame area FA than the organic barrier layer 82 and overlap each other in the outer portion of the frame area FA. The organic barrier layer 82 extends into the display area DA and its outer periphery, and is enclosed by the first inorganic barrier layer 81 and the second inorganic barrier layer 83.

[0073] The first inorganic barrier layer 81 and the second inorganic barrier layer 83 are each made of an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The organic barrier layer 82 is made of an organic resin material such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, polyamide resin, etc. The organic barrier layer 82 is formed by applying a liquid material.

[0074] <Lead Lines> The multiple lead lines 40h extend below the sealing film 80 so as to intersect with the joints SZ and are drawn out to the terminal portions TP (see FIG. 5). The lead lines 40h have a laminated structure. In this example, the lead lines 40h have a two-layer configuration. Specifically, the lead lines 40h include a first wiring layer 41 and a second wiring layer 42. The first wiring layer 41 is provided on the first gate insulating film 23. The second wiring layer 42 is laminated on the first wiring layer 41 via the first interlayer insulating film 26 and is covered by the second interlayer insulating film 34. The first interlayer insulating film 26 is an example of a first inorganic insulating film.

[0075] The first wiring layer 41 and the second wiring layer 42 are each formed in a forward tapered shape such that both side surfaces in the width direction of the lead line 40h approach each other toward the upper layer. The both side surfaces of the first wiring layer 41 and the second wiring layer 42 are offset from each other in the width direction of the lead line 40h. Specifically, the line width of the second wiring layer 42 is narrower than the line width of the first wiring layer 41. The both side surfaces of the second wiring layer 42 correspond to the upper surface of the first wiring layer 41 in the stacking direction of the first wiring layer 41 and the second wiring layer 42.

[0076] When the angle formed by the side surface of the first wiring layer 41 in the width direction toward the inside of the first wiring layer 41 with respect to a direction perpendicular to the thickness direction of the first wiring layer 41 is defined as a first inclination angle θ1, and the angle formed by the side surface of the second wiring layer 42 in the width direction toward the inside of the second wiring layer 42 with respect to a direction perpendicular to the thickness direction of the second wiring layer 42 is defined as a second inclination angle θ2, the first inclination angle θ1 and the second inclination angle θ2 satisfy the relationship θ2≦θ1. The first inclination angle θ1 is, for example, 20° to 90°. The second inclination angle θ2 is, for example, 10° to 85°.

[0077] A plurality of first contact holes Ha are formed in the first interlayer insulating film 26. A pair of the first contact holes Ha is provided for each lead line 40h. The first wiring layer 41 and the second wiring layer 42 are connected via the pair of first contact holes Ha. The pair of first contact holes Ha are positioned in a plan view along the length of the lead line 40h, with at least a portion of the joint SZ in the width direction (in this example, the entire joint SZ in the width direction) sandwiched between them.

[0078] The first wiring layer 41 is formed of the same material and in the same layer as the electrodes constituting the circuit elements or the wiring connected to the circuit elements. In this example, the first wiring layer 41 is formed of the same material and in the same layer as the first gate line 40ga, the light-emitting control line 40e, the initialization line 40i, and the first gate electrode 24. The second wiring layer 42 is also formed of the same material and in the same layer as the electrodes constituting the circuit elements or the wiring connected to the circuit elements. In this example, the second wiring layer 42 is formed of the same material and in the same layer as the third terminal electrode 28, the fourth terminal electrode 29, and the first capacitor electrode 25.

[0079] -Method of Manufacturing Organic EL Display Device- To manufacture the organic EL display device 1, first, an organic resin material is applied to the surface of a glass substrate and baked, thereby forming a substrate layer 10 on the glass substrate.

[0080] Next, the TFT layer 20, the light-emitting element layer 60, and the sealing film 80 are formed in this order on the substrate layer 10 using a known film formation method such as plasma CVD (Chemical Vapor Deposition), sputtering, or vacuum deposition, a known coating method such as spin coating or slit coating, or a known patterning technique such as photolithography.

[0081] Thereafter, the glass substrate is peeled off from the substrate layer 10 by, for example, irradiating the rear surface of the substrate layer 10 with laser light from the glass substrate side. Next, a protective film 11 is attached to the rear surface of the substrate layer 10. A polarizing plate and a cover panel are attached to the surface of the sealing film 80. Furthermore, a wiring substrate CB is connected to the terminal portion TP. As a result, a display control circuit (source driver) is mounted on the panel that constitutes the organic EL display device 1.

[0082] In this manner, the organic EL display device 1 can be manufactured.

[0083] 8( a) and 8(b), in the process of forming the TFT layer 20, a silicon oxide film and a silicon nitride film are sequentially formed on the substrate layer 10 by, for example, plasma CVD, thereby forming a base coat film 21.

[0084] Next, an amorphous silicon film is formed on the substrate on which the base coat film 21 has been formed, for example, by plasma CVD, and the amorphous silicon film is crystallized by laser annealing or the like to form a first semiconductor film. The first semiconductor film is then patterned by photolithography to form a first semiconductor layer 22. Furthermore, a silicon oxide film is formed on the substrate on which the first semiconductor layer 22 has been formed, for example, by plasma CVD, thereby forming a first gate insulating film 23.

[0085] Next, a molybdenum film is formed to a thickness of about 100 nm to 500 nm by, for example, sputtering on the substrate on which the first gate insulating film 23 has been formed. Subsequently, a photoresist is formed in a predetermined pattern on the substrate on which the molybdenum film has been formed by a known photo process. Subsequently, the molybdenum film is patterned by dry etching using the photoresist as a mask to form the first gate line 40ga, the light emission control line 40e, the initialization line 40i, and the first gate electrode 24. At this time, the etching gas may be, for example, carbon tetrachloride (CF ４ ) and oxygen (O ２ 8C, a first wiring layer 41 is formed from the same film as the first gate line 40ga etc. so as to have a tapered cross section.

[0086] Next, the surface of the substrate on which the first wiring layer 41 and the like have been formed is doped with impurity ions such as phosphorus using the first gate electrode 24 as a mask, thereby forming a first channel region 22 a and a pair of first conductor regions 22 b in the first semiconductor layer 22.

[0087] Furthermore, on the substrate doped with impurity ions, a silicon oxide film is formed to a thickness of approximately 50 nm to 500 nm, for example, by plasma CVD, so as to cover the first gate lines 40ga, the light-emission control lines 40e, the initialization lines 40i, the first gate electrodes 24, and the first wiring layer 41. Then, a silicon nitride film is formed to a thickness of approximately 20 nm to 200 nm. This forms the first interlayer insulating film 26. Next, the first interlayer insulating film 26 is patterned by photolithography involving dry etching to form a plurality of first contact holes Ha. As a result, the first wiring layer 41 is covered with the first interlayer insulating film 26, as shown in FIG. 8(d).

[0088] Next, a molybdenum film is formed to a thickness of about 100 nm to 500 nm by, for example, sputtering on the substrate on which the first interlayer insulating film 26 has been formed. Subsequently, a photoresist is formed in a predetermined pattern on the substrate on which the molybdenum film has been formed by a known photo process. Subsequently, the molybdenum film is patterned by dry etching using the photoresist as a mask to form the third terminal electrode 28, the fourth terminal electrode 29, and the first capacitor electrode 25. At this time, an etching gas such as carbon tetrachloride (CF ４ ) and oxygen (O ２ 8(e), a second wiring layer 42 is formed from the same film as the third terminal electrode 28, etc., so as to have a tapered cross section. This forms a plurality of lead wires 40h.

[0089] Next, on the substrate on which the second wiring layer 42 and the like have been formed, InGaZnO ４ Then, a second semiconductor film made of an oxide semiconductor such as SiO 2 is formed. Subsequently, the second semiconductor film is patterned by photolithography to form a second semiconductor layer 31.

[0090] Next, a silicon oxide film is formed by, for example, plasma CVD on the substrate on which the second semiconductor layer 31 is formed, followed by a molybdenum film. Subsequently, the silicon oxide film and the molybdenum film are patterned by photolithography to form the second gate insulating film 32 from the silicon oxide film, and the second gate line 40gb, the second gate electrode 33, and the second capacitor electrode 30 from the molybdenum film.

[0091] Next, a hydrogen plasma treatment is performed on the surface of the substrate on which the second gate electrode 33 and other components are formed, using the second gate electrode 33 as a mask. This hydrogen plasma treatment exposes the exposed portions of the second semiconductor layer 31 to plasma. When exposed to plasma, the oxide semiconductor constituting the second semiconductor layer 31 suffers oxygen deficiency, resulting in a low resistance. This results in the formation of a second channel region 31 a and a pair of second conductor regions 31 b in the second semiconductor layer 31.

[0092] Furthermore, on the substrate where the second semiconductor layer 31 has been subjected to such resistance reduction treatment, a silicon oxide film is formed to a thickness of approximately 100 nm to 1000 nm, for example, by plasma CVD, and then a silicon nitride film is formed to a thickness of approximately 100 nm to 500 nm. The stacked film made of the silicon oxide film and the silicon nitride film is then patterned by photolithography to form the second interlayer insulating film 34. Thus, as shown in FIG. 8( f ), the second wiring layer 42 is covered with the second interlayer insulating film 34. A stacked insulating film 36 is then formed on the substrate layer 10. This patterning also forms a third contact hole Hc and a fourth contact hole Hd in the stacked insulating film 36.

[0093] Next, a titanium film, an aluminum film, and a titanium film are formed in this order by, for example, sputtering on the substrate on which the second interlayer insulating film 34 has been formed. Subsequently, the stacked film made of the titanium film, the aluminum film, and the titanium film is patterned by photolithography to form the first terminal electrode 37, the second terminal electrode 38, the relay wire 40r, and the like.

[0094] Next, a photosensitive resin is applied by a known application method onto the substrate on which the first terminal electrodes 37 and the like have been formed. The photosensitive resin coating is then pre-baked, exposed to light, developed, and post-baked to form a planarization film 59 having third contact holes Hc. Then, by a known method, a pixel electrode 61, an edge cover 66, an organic EL layer 62, and a common electrode 63 are formed in this order on the substrate on which the planarization film 59 has been formed. In this manner, the light-emitting element layer 60 is formed.

[0095] Thereafter, as shown in FIG. 8( g), a first inorganic barrier layer 81 is formed by plasma CVD on the substrate on which the light-emitting element layer 60 has been formed. Subsequently, an organic resin material is applied to the substrate on which the first inorganic barrier layer 81 has been formed, and the applied film of the organic resin material is cured to form an organic barrier layer 82. Then, a second inorganic barrier layer 83 (not shown in FIG. 8( g)) is formed by plasma CVD on the substrate on which the organic barrier layer 82 has been formed. In this way, a sealing film 80 is formed, and joints SZ extending to intersect with each lead wire 40 h are configured.

[0096] Features of Embodiment 1 In the organic EL display device 1 of Embodiment 1, the lead line 40h has a layered structure including a first wiring layer 41 and a second wiring layer 42. This reduces the resistance of the lead line 40h. The first wiring layer 41 and the second wiring layer 42 are connected via a pair of first contact holes Ha formed in the first interlayer insulating film 26 interposed between them. A junction SZ is provided between the pair of first contact holes Ha in a planar view. This prevents the formation of a moisture intrusion path that penetrates the junction SZ, even if the surface of the first wiring layer 41 exposed through the first contact holes Ha is roughened by the etching process used to form the first contact holes Ha. This prevents moisture from penetrating the display area DA via the lead line 40h.

[0097] For example, in an organic EL display device 1 of a comparative example in which the configuration of the lead wires 40h as disclosed in Patent Document 1 is adopted, if moisture penetrates into the display area DA along the lead wires 40h, the brightness of the organic EL elements 65 will decrease due to degradation in the portion of the display area DA into which moisture penetrates (the portion surrounded by the dashed circle) as shown in Fig. 9B, resulting in display unevenness. In contrast, in the organic EL display device 1 of Embodiment 1, as described above, it is possible to prevent moisture from penetrating into the display area along the lead wires 40h, thereby preventing deterioration of the organic EL elements 65 and suppressing display unevenness as shown in Fig. 9A.

[0098] Furthermore, according to the organic EL display device 1 of this embodiment 1, a pair of first contact holes Ha are provided, one on the inside and one on the outside of the joint portion SZ, so that even if the connection portion between the first wiring layer 41 and the second wiring layer 42 in each first contact hole Ha becomes highly resistant for some reason and generates heat at that connection portion during operation of the organic EL display device 1, the effect of that heat on the joint portion SZ can be reduced, thereby also improving the reliability of the organic EL display device 1.

[0099] In the organic EL display device 1 of this embodiment 1, the first wiring layer 41 and the second wiring layer 42 are each formed to have a tapered cross section. Both side surfaces in the width direction of the first wiring layer 41 and the second wiring layer 42 having a tapered cross section approach each other toward the upper layer. This can improve the step coverage of the first inorganic barrier layer 81 with respect to the lead wire 40 h.

[0100] In the organic EL display device 1 of this embodiment 1, both side surfaces of the first wiring layer 41 and both side surfaces of the second wiring layer 42 are offset from each other in the width direction of the lead wire 40h. As shown in FIG. 19A , when the side surfaces of the first wiring layer 41 and the second wiring layer 42 correspond to the stacking direction of the two, the inclination angle of the side surfaces of the second wiring layer 42 tends to be steeper than the inclination angle of the side surfaces of the first wiring layer 41. In contrast, with this configuration, it is possible to prevent the inclination angle of the side surfaces of the second wiring layer 42 from becoming relatively steep. This is advantageous for improving the step coverage of the first inorganic barrier layer 81 with respect to the lead wire 40h.

[0101] In the organic EL display device 1 of this embodiment 1, the width of the second wiring layer 42 is smaller than the width of the first wiring layer 41. Both side surfaces of the second wiring layer 42 correspond to the upper surface of the first wiring layer 41 in the stacking direction of the first wiring layer 41 and the second wiring layer 42, and are therefore offset from both side surfaces of the first wiring layer 41 in the width direction of the lead-out wire 40h. This is advantageous for thinning the lead-out wire 40h while improving the step coverage of the first inorganic barrier layer 81 with respect to the lead-out wire 40h.

[0102] In the organic EL display device 1 of this embodiment 1, the second inclination angle θ2 formed by the side surface of the second wiring layer 42 is equal to or smaller than the first inclination angle θ1 formed by the side surface of the first wiring layer 41. This is advantageous for improving the step coverage of the first inorganic barrier layer 81 with respect to the lead wire 40 h.

[0103] In the organic EL display device 1 of this embodiment 1, the first wiring layer 41 is formed in the same layer and from the same material as the electrodes or wiring of the circuit elements provided in the display area DA. This eliminates the need to add a process for forming the first wiring layer 41 in addition to the process for forming the electrodes and wiring of the circuit elements in the manufacture of the organic EL display device 1. This prevents the number of processes required for manufacturing the organic EL display device 1 from increasing, and reduces the manufacturing cost of the organic EL display device 1.

[0104] In the organic EL display device 1 of this embodiment 1, the second wiring layer 42 is formed in the same layer and from the same material as the electrodes or wiring of the circuit elements provided in the display area DA. This eliminates the need to add a process for forming the second wiring layer 42 in addition to the process for forming the electrodes and wiring of the circuit elements in the manufacture of the organic EL display device 1. This prevents the number of processes required for manufacturing the organic EL display device 1 from increasing, thereby reducing the manufacturing cost of the organic EL display device 1.

[0105] Second Embodiment The organic EL display device 1 of the second embodiment differs from that of the first embodiment in the configuration of the lead wire 40h. In the following embodiments, the organic EL display device 1 is configured in the same manner as that of the first embodiment, except for the configuration of the lead wire 40h, which differs from that of the first embodiment.

[0106] 10 to 13, the lead line 40h in the organic EL display device 1 of this embodiment 2 has a three-layer configuration. Specifically, the lead line 40h includes a third wiring layer 43 in addition to a first wiring layer 41 and a second wiring layer 42. The second wiring layer 42 is covered with a second gate insulating film 32. The third wiring layer 43 is stacked on the second wiring layer 42 with the second gate insulating film 32 interposed therebetween. The second gate insulating film 32 is an example of a second inorganic insulating film. The third wiring layer 43 is stacked on the second wiring layer 42 with the second gate insulating film 32 interposed therebetween. The third wiring layer 43 is covered with a second interlayer insulating film 34.

[0107] The third wiring layer 43 is formed with a cross-sectional tapered shape in which both side surfaces in the width direction of the lead wire 40h approach each other toward the upper layer. The both side surfaces of the third wiring layer 43 are offset from the both side surfaces of the first wiring layer 41 and the second wiring layer 42 in the width direction of the lead wire 40h. Specifically, the line width of the third wiring layer 43 is wider than the line widths of the first wiring layer 41 and the second wiring layer 42. The both side surfaces of the first wiring layer 41 and the both side surfaces of the second wiring layer 42 each correspond to the upper surface of the third wiring layer 43 in the stacking direction of the first to third wiring layers 41 to 43.

[0108] When the angle formed by the side surface of the second wiring layer 42 in the width direction toward the inside of the second wiring layer 42 with respect to a direction perpendicular to the thickness direction of the second wiring layer 42 is defined as a second inclination angle θ2, and the angle formed by the side surface of the third wiring layer 43 in the width direction toward the inside of the third wiring layer 43 with respect to a direction perpendicular to the thickness direction of the third wiring layer 43 is defined as a third inclination angle θ3, the second inclination angle θ2 and the third inclination angle θ3 satisfy the relationship θ3≦θ2. The second inclination angle θ2 is, for example, 10° to 85°. The third inclination angle is, for example, 5° to 80°.

[0109] A plurality of second contact holes Hb are formed in the second gate insulating film 32. A pair of second contact holes Hb is provided for each lead-out line 40h. The second wiring layer 42 and the third wiring layer 43 are connected via the pair of second contact holes Hb. The pair of second contact holes Hb are positioned along the length of the lead-out line 40h in a plan view, with at least a portion of the joint SZ in the width direction (in this example, the entire width of the joint SZ) interposed between them. The second contact holes Hb are formed at positions offset from the first contact holes Ha in the length direction of the lead-out line 40h.

[0110] The third wiring layer 43 is formed in the same layer and made of the same material as the electrodes constituting the circuit elements or the wiring connected to the circuit elements. In this example, the third wiring layer 43 is formed in the same layer and made of the same material as the second gate line 40gb and the second gate electrode 33.

[0111] To manufacture the organic EL display device 1 of this embodiment 2, the second wiring layer 42 and the like are formed in the same manner as in embodiment 1 above, and then, as shown in Fig. 14(a), the second gate insulating film 32 is formed so as to cover the second wiring layer 42 as well as a part of the second semiconductor layer 31 (the part that will become the second channel region 31a) and the first capacitor electrode 25. Then, the second gate line 40gb and the second gate electrode 33 are formed on the substrate on which the second gate insulating film 32 has been formed in the same manner as in embodiment 1 above. At this time, as shown in Fig. 14(b), the third wiring layer 43 is also formed from the same film as the second gate line 40gb and the like.

[0112] Next, on the substrate on which the third wiring layer 43 and the like have been formed, a second interlayer insulating film 34 is formed by, for example, plasma CVD so as to cover the second gate line 40gb and the second gate electrode 33. At this time, as shown in Fig. 14(c) , the second interlayer insulating film 34 is formed so as to cover the third wiring layer 43. Then, in the same manner as in the first embodiment, the first terminal electrode 37, the second terminal electrode 38, the relay line 40r and the like are formed on the substrate on which the second interlayer insulating film 34 has been formed.

[0113] Next, in the same manner as in the first embodiment, a planarization film 59 and a light-emitting element layer 60 are formed on the substrate on which the first terminal electrodes 37 and the like have been formed. Thereafter, a first inorganic barrier layer 81, an organic barrier layer 82, and a second inorganic barrier layer 83 are formed in this order on the substrate on which the light-emitting element layer 60 has been formed. By doing so, as shown in FIG. 14( d ), a sealing film 80 is formed so as to cover the lead wires 40 h, and joints SZ extending to intersect with the lead wires 40 h are formed.

[0114] Features of Embodiment 2 In the organic EL display device 1 of Embodiment 2, the lead line 40h has a stacked structure including a third wiring layer 43 in addition to a first wiring layer 41 and a second wiring layer 42. This further reduces the resistance of the lead line 40h. The second wiring layer 42 and the third wiring layer 43 are connected via a pair of second contact holes Hb formed in the second interlayer insulating film 34. At least a portion of the junction SZ is interposed between the pair of second contact holes Hb in the longitudinal direction of the lead line 40h in a planar view. This prevents moisture from penetrating the junction SZ even if the surface of the second wiring layer 42 exposed through the second contact holes Hb is roughened by the etching process used to form the second contact holes Hb. This prevents moisture from penetrating the display area DA via the lead line 40h.

[0115] In the organic EL display device 1, the third wiring layer 43 is formed to have a tapered cross section. Both side surfaces in the width direction of the tapered cross section of the third wiring layer 43 approach each other toward the upper layer. This can improve the step coverage of the first inorganic barrier layer 81 with respect to the lead wire 40 h.

[0116] In the organic EL display device 1 of this second embodiment, both side surfaces of the third wiring layer 43 and both side surfaces of the first wiring layer 41 and the second wiring layer 42 are offset from each other in the width direction of the lead wire 40h. As shown in FIG. 19B , when the side surfaces of the third wiring layer 43 correspond to the stacking direction of the first wiring layer 41 and the second wiring layer 42, the inclination angle of the side surfaces of the third wiring layer 43 tends to be steeper than the inclination angles of the side surfaces of the first wiring layer 41 and the second wiring layer 42. In contrast, this configuration can prevent the inclination angles of the side surfaces of the second wiring layer 42 from becoming relatively steep. This is advantageous for improving the step coverage of the first inorganic barrier layer 81 with respect to the lead wire 40h.

[0117] In the organic EL display device 1 of this embodiment 2, the third inclination angle θ3 formed by the side surface of the third wiring layer 43 is equal to or smaller than the second inclination angle θ2 formed by the side surface of the second wiring layer 42. This is advantageous for improving the step coverage of the inorganic barrier layer with respect to the lead line 40 h.

[0118] Third Embodiment The lead wire 40h in the organic EL display device 1 of the third embodiment has a two-layer structure. Specifically, as shown in FIGS. 15 to 17, the lead wire 40h includes a first wiring layer 41 and a second wiring layer 42.

[0119] The first wiring layer 41 is provided only in the frame area FA. Specifically, the first wiring layer 41 extends from the frame area FA between the joint SZ and the display area DA, through the joint SZ, and into the frame area FA on the terminal portion TP side of the joint SZ. The first wiring layer 41 has a stacked structure in which multiple metal layers 44 are stacked. The multiple metal layers 44 include a first metal layer 44a, a second metal layer 44b, and a third metal layer 44c.

[0120] The first metal layer 44a is provided on the surface of the first gate insulating film 23. The second metal layer 44b is provided on the first metal layer 44a. The third metal layer 44c is provided on the second metal layer 44b. The first metal layer 44a and the third metal layer 44c are each made of titanium (Ti) or a titanium alloy. The second metal layer 44b is made of aluminum (Al) or an aluminum alloy. The first interlayer insulating film 26 is provided to cover the entire first wiring layer 41.

[0121] When the first wiring layer 41 has the above-described three-layer structure, the second metal layer 44b is exposed to an alkaline developer used in etching and photolithography (resist patterning) when patterning the first wiring layer 41, and is thereby side-etched so as to sink under the third metal layer 44c during the manufacturing process of the organic EL display device 1. As a result, the third metal layer 44c of the first wiring layer 41 protrudes laterally, forming a canopy-like portion on the first wiring layer 41.

[0122] In this case, the side end surfaces of the first wiring layer 41 cannot be tightly covered by the first interlayer insulating film 26, and gaps 45 are formed between the second metal layer 44b and the first interlayer insulating film 26 on the sides of the first wiring layer 41. However, the entire periphery of the gaps 45 in the first wiring layer 41 is covered and sealed by the first interlayer insulating film 26. Therefore, the gaps 45 in the first wiring layer 41 do not become a path for external moisture to penetrate into the display area DA.

[0123] Similar to the first embodiment, this first wiring layer 41 is formed in the same layer and from the same material as the first gate line 40ga, the light-emitting control line 40e, the initialization line 40i, and the first gate electrode 24. That is, similar to the first wiring layer 41, the first gate line 40ga, the light-emitting control line 40e, the initialization line 40i, and the first gate electrode 24 also have a three-layer structure consisting of a first metal layer 44a, a second metal layer 44b, and a third metal layer 44c.

[0124] The second wiring layer 42 extends from the display area DA to the terminal portion TP and constitutes the entire length of the lead line 40h. The second wiring layer 42 is provided so as to cover the entire first wiring layer 41 via the first interlayer insulating film 26. The side surfaces of the first wiring layer 41 and the second wiring layer 42 are offset from each other in the width direction of the lead line 40h.

[0125] Specifically, the line width of the second wiring layer 42 is wider than the line width of the first wiring layer 41. Both side surfaces of the first wiring layer 41 correspond to the upper surface of the second wiring layer 42 in the stacking direction of the first wiring layer 41 and the second wiring layer 42. The second wiring layer 42 is formed with a tapered cross section such that both side surfaces in the width direction of the lead wire 40h approach each other toward the upper layer. The second inclination angle θ2 is, for example, 10° to 85°.

[0126] Similar to the first embodiment, the second wiring layer 42 is formed in the same layer and from the same material as the third terminal electrode 28, etc. The second wiring layer 42 is stacked on the first wiring layer 41 with the first interlayer insulating film 26 interposed between them, and is covered with the second interlayer insulating film 34. The second wiring layer 42 is connected to the first wiring layer 41 via a pair of first contact holes Ha formed in the first interlayer insulating film 26.

[0127] To manufacture the organic EL display device 1 of this embodiment 3, the first gate insulating film 23 is formed in the same manner as in embodiment 1, and then a titanium film, an aluminum film, and a titanium film are deposited in that order by, for example, sputtering. Next, the stacked film consisting of these titanium, aluminum, and titanium films is patterned by photolithography to form the first gate line 40ga, the light-emitting control line 40e, the initialization line 40i, and the first gate electrode 24. At this time, as shown in FIG. 18( a), a first wiring layer 41 is also formed from the same film as the first gate line 40ga, etc.

[0128] Next, in the same manner as in the first embodiment, the first semiconductor layer 22 is doped with impurity ions to form the first channel region 22a and a pair of first conductor regions 22b, and then, as shown in Fig. 18(b), the first interlayer insulating film 26 is formed so as to cover the first wiring layer 41 and the like. Then, when the first contact holes Ha are formed in the first interlayer insulating film 26, the first interlayer insulating film 26 is patterned into a shape that covers the first wiring layer 41 individually, as shown in Fig. 18(c).

[0129] Next, in the same manner as in the first embodiment, the third terminal electrode 28, the fourth terminal electrode 29, and the first capacitor electrode 25 are formed on the substrate on which the first interlayer insulating film 26 has been formed. At this time, as shown in Fig. 18(d), the second wiring layer 42 is also formed from the same film as the third terminal electrode 28, etc., so as to have a tapered cross section. This forms a plurality of lead lines 40h.

[0130] Next, in the same manner as in the first embodiment, a second gate insulating film 32 and a second semiconductor layer 31 are formed on the substrate on which the second wiring layer 42 and the like are formed, and the second semiconductor layer 31 is subjected to a resistance reduction process to form a second channel region 31 a and a pair of second conductor regions 31 b. Then, a second interlayer insulating film 34 is formed on the substrate on which the resistance reduction process has been performed on the second semiconductor layer 31, and a third contact hole Hc and a fourth contact hole Hd are formed.

[0131] Next, on the substrate on which the second wiring layer 42 and the like have been formed, a second interlayer insulating film 34 is formed by, for example, plasma CVD so as to cover the second gate line 40gb and the second gate electrode 33. At this time, as shown in Fig. 18(e), the second interlayer insulating film 34 is formed so as to cover the second wiring layer 42. Then, on the substrate on which the second interlayer insulating film 34 has been formed, a first terminal electrode 37, a second terminal electrode 38, a relay line 40r and the like are formed in the same manner as in the first embodiment.

[0132] Next, in the same manner as in the first embodiment, a planarization film 59 and a light-emitting element layer 60 are formed on the substrate on which the first terminal electrodes 37 and the like have been formed. Thereafter, a first inorganic barrier layer 81, an organic barrier layer 82, and a second inorganic barrier layer 83 are formed in this order on the substrate on which the light-emitting element layer 60 has been formed. By doing so, as shown in FIG. 18( f), a sealing film 80 is formed so as to cover the lead wires 40 h, and joints SZ extending to intersect with each lead wire 40 h are formed.

[0133] Features of Embodiment 3 In the organic EL display device 1 of Embodiment 3, the first wiring layer 41 has a stacked structure. By using a low-resistance metal material (aluminum or an aluminum alloy in this example) for at least a portion of the multiple metal layers 44 forming the stacked structure, the resistance of the lead wire 40h can be further reduced. The entire first wiring layer 41 is covered by the first interlayer insulating film 26. As a result, the metal layer 44 (second metal layer 44b in this example) located in the middle or lower portion of the multiple metal layers 44 forming the first wiring layer 41 in the stacking direction is side-etched to extend beneath the upper metal layer 44 (third metal layer 44c in this example) during the etching process used to form the first wiring layer 41. Even if gaps 45 are formed on the sides of the first wiring layer 41, the gaps 45 can be enclosed and sealed by the first interlayer insulating film 26. This prevents the gaps 45 resulting from the side etching of the first wiring layer 41 from becoming a path for moisture penetration.

[0134] In the organic EL display device 1 of this third embodiment, the first wiring layer 41 includes a first metal layer 44a, a second metal layer 44b, and a third metal layer 44c. The second metal layer 44b is made of aluminum (Al) or an aluminum alloy. Aluminum (Al) or an aluminum alloy has relatively low electrical resistance and excellent conductivity. Therefore, the second metal layer 44b contributes to reducing the resistance of the first wiring layer 41. The first metal layer 44a and the third metal layer 44c are made of titanium (Ti) or a titanium alloy. Titanium and titanium alloys have relatively high corrosion resistance. Therefore, the first metal layer 44a and the third metal layer 44c function effectively as protective layers for the second metal layer 44b, which is made of aluminum (Al) or other metals that are susceptible to corrosion.

[0135] In the organic EL display device 1 of the third embodiment, the second wiring layer 42 is formed to have a tapered cross section. Both side surfaces in the width direction of the tapered cross section of the second wiring layer 42 approach each other toward the upper layer. This can improve the step coverage of the first inorganic barrier layer 81 with respect to the lead wire 40 h.

[0136] In the organic EL display device 1 of the third embodiment, the first wiring layer 41 is covered by the second wiring layer 42 via the second interlayer insulating film 34. Even if a gap 45 is formed on the side of the first wiring layer 41 due to side etching, the gap 45 can be surrounded and sealed by the stack of the first interlayer insulating film 26 and the second wiring layer 42. This is advantageous in preventing the gap 45 formed due to side etching of the first wiring layer 41 from becoming a path for moisture penetration.

[0137] Other Embodiments In the first embodiment described above, the line width of the second wiring layer 42 is narrower than the line width of the first wiring layer 41, and both side surfaces of the second wiring layer 42 correspond to the upper surface of the second wiring layer 42 in the stacking direction of the first wiring layer 41 and the second wiring layer 42. However, this is not limited to this. As shown in Fig. 20, the line width of the first wiring layer 41 may be narrower than the line width of the second wiring layer 42. Furthermore, both side surfaces of the first wiring layer 41 may correspond to the upper surface of the second wiring layer 42 in the stacking direction of the first wiring layer 41 and the second wiring layer 42.

[0138] In the first embodiment, the first wiring layer 41 is formed in the same layer and made of the same material as the gate lines 40g, and the second wiring layer 42 is formed in the same layer and made of the same material as the third terminal electrodes 28. However, this is not limiting, and the first wiring layer 41 and the second wiring layer 42 may each be formed in the same layer and made of the same material as electrodes constituting other circuit elements or wiring connected to the circuit elements. Furthermore, the first wiring layer 41 and the second wiring layer 42 may each be formed in a separate process from the electrodes constituting the circuit elements or wiring connected to the circuit elements. The same applies to the third wiring layer 43 in the second embodiment.

[0139] In the first embodiment, one first contact hole Ha is provided on the inside and one on the outside of the joint portion SZ for each lead line 40 h, but this is not limiting. A plurality of first contact holes Ha may be provided for each lead line 40 h on the inside of the joint portion SZ, or a plurality of first contact holes Ha may be provided for each lead line 40 h on the outside of the joint portion SZ. The same applies to the second contact holes Hb in the second embodiment.

[0140] In the above embodiment, the organic EL layer 62 is provided individually for each subpixel SP, but this is not limited to this. The organic EL layer 62 may be provided as a continuous layer common to multiple subpixels SP. In this case, the organic EL display device 1 may be provided with a color filter or the like to express color tones in each subpixel SP.

[0141] In the above embodiment, each pixel PX is configured with sub-pixels SP of three colors, but this is not limited to this. The sub-pixels SP that configure each pixel PX may be of four or more colors. Furthermore, the three sub-pixels SP that configure each pixel PX are arranged in a stripe pattern, but this is not limited to this. The arrangement of the multiple sub-pixels SP may be another arrangement, such as a pentile arrangement.

[0142] In the above embodiment, the pixel electrode 61 functions as an anode and the common electrode functions as a cathode, but this is not limiting. The organic EL display device 1 may be configured so that the pixel electrode 61 functions as a cathode and the common electrode 63 functions as an anode. In this case, the organic EL layer 62 has an inverted stacked structure.

[0143] In the above embodiment, the organic EL layer 62 has a five-layer structure including a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, but is not limited to this. The organic EL layer 62 may have a three-layer structure including a hole injection / transport layer, a light-emitting layer, and an electron injection / transport layer, or any other laminated structure may be adopted.

[0144] In the above embodiment, the base substrate of the organic EL display device 1 is the substrate layer 10, but this is not limiting. The base substrate may be made of any material, such as a plastic substrate made of polyethylene terephthalate (PET) or a glass substrate.

[0145] In the above embodiment, the organic EL display device 1 is illustrated as an example of a display device according to the present disclosure, but the present disclosure is not limited to this. The technology of the present disclosure can be applied to a display device including a plurality of light-emitting elements. An example of such a display device is a quantum dot display device including QLEDs (Quantum-dot Light Emitting Diodes), which are light-emitting elements using a quantum dot-containing layer.

[0146] As described above, preferred embodiments have been described as examples of the technology of the present disclosure. However, the technology of the present disclosure is not limited to these, and can be applied to embodiments in which appropriate modifications, substitutions, additions, omissions, etc. are made. It will be understood by those skilled in the art that various modifications are possible to the above-described embodiments without departing from the spirit of the technology of the present disclosure, and that such modifications also fall within the scope of the technology of the present disclosure.

[0147] As described above, the present disclosure is useful for display devices.

[0148] DA Display area FA Frame area Ha First contact hole Hb Second contact hole SZ Junction portion TP Terminal portion 1 Organic EL display device (display device) 5 Circuit substrate 10 Substrate layer (base substrate) 26 First interlayer insulating film (first inorganic insulating film) 32 Second gate insulating film (second inorganic insulating film) 36 Stacked insulating film 40h Lead wire 41 First wiring layer 42 Second wiring layer 43 Third wiring layer 44 Metal layer 44a First metal layer 44b Second metal layer 44c Third metal layer 50 TFT (circuit element) 55 Capacitor (circuit element) 65 Organic EL element (light-emitting element) 80 Sealing film 81 First inorganic barrier layer 82 Organic barrier layer 83 Second inorganic barrier layer

Claims

1. A display device comprising: a circuit board; a plurality of light-emitting elements provided on the circuit board; and a sealing film provided to cover the plurality of light-emitting elements, wherein the plurality of light-emitting elements form a display area for displaying an image, and a frame area is provided outside the display area as a non-display area in which no image is displayed, the circuit board includes a base substrate and a laminated insulating film provided on the base substrate so as to extend into the frame area and made of laminated inorganic insulating material, the sealing film having an inorganic barrier layer made of an inorganic insulating material, the frame area includes a frame-shaped joint portion at which a portion along a periphery of the inorganic barrier layer contacts the laminated insulating film, and a terminal portion located outside the joint, and a lead line is provided on a lower layer side of the sealing film in the frame area, the lead line extending from the display area to intersect with the joint portion and being led out to the terminal portion, the lead line including a first wiring layer and a second wiring layer laminated on the first wiring layer with a first inorganic insulating film interposed therebetween, and the first wiring layer and the second wiring layer are connected via a pair of first contact holes formed in the first inorganic insulating film, The display device, wherein the bonding portion is provided between the pair of first contact holes in a plan view.

2. A display device according to claim 1, wherein the first wiring layer and the second wiring layer are each formed with a cross-sectional tapered shape in which both side surfaces in the width direction of the lead line approach each other toward the upper layer.

3. A display device according to claim 2, wherein both side surfaces of the first wiring layer and the second wiring layer are offset from each other in the width direction of the lead lines.

4. A display device as described in claim 3, wherein the line width of the second wiring layer is narrower than the line width of the first wiring layer, and both side surfaces of the second wiring layer correspond to the upper surface of the first wiring layer in the stacking direction of the first wiring layer and the second wiring layer.

5. A display device as described in claim 3, wherein the line width of the first wiring layer is narrower than the line width of the second wiring layer, and both side surfaces of the first wiring layer correspond to the upper surface of the second wiring layer in the stacking direction of the first wiring layer and the second wiring layer.

6. A display device according to any one of claims 2 to 5, wherein when a first inclination angle θ1 is an angle that a side surface in the width direction of the first wiring layer makes inwardly of the first wiring layer with respect to a direction perpendicular to the thickness direction of the first wiring layer, and a second inclination angle θ2 is an angle that a side surface in the width direction of the second wiring layer makes inwardly of the second wiring layer with respect to a direction perpendicular to the thickness direction of the second wiring layer, the display device satisfies the relationship θ2≦θ1.

7. A display device according to any one of claims 1 to 6, wherein the pull-out line further includes a third wiring layer stacked on the second wiring layer with a second inorganic insulating film interposed between them, and one or both of the first wiring layer and the second wiring layer are connected to the third wiring layer via a pair of second contact holes formed in a stacked film consisting of the first inorganic insulating film and the second inorganic insulating film, and the pair of second contact holes are positioned in a positional relationship such that at least a portion of the junction is interposed between them along the length of the pull-out line in a planar view.

8. A display device according to claim 7, wherein the third wiring layer is formed with a cross-sectional tapered shape in which both side surfaces in the width direction of the lead line approach each other toward the upper layer.

9. A display device as described in claim 8, wherein the first wiring layer and the second wiring layer are each formed with a cross-sectional tapered shape in which both side surfaces in the width direction of the pull-out line approach each other toward the upper layer, and both side surfaces of the first wiring layer, the second wiring layer and the third wiring layer are in a mutually offset positional relationship in the width direction of the pull-out line.

10. A display device as claimed in claim 8 or 9, wherein when a second inclination angle θ2 is an angle that a side surface of the second wiring layer in the width direction makes inwardly of the second wiring layer with respect to a direction perpendicular to the thickness direction of the second wiring layer, and a second inclination angle θ3 is an angle that a side surface of the third wiring layer in the width direction makes inwardly of the third wiring layer with respect to a direction perpendicular to the thickness direction of the third wiring layer, the display device satisfies the relationship θ3≦θ2.

11. A display device according to claim 1, wherein the first wiring layer has a laminated structure in which a plurality of metal layers are stacked, and the first inorganic insulating film is provided so as to cover the entire first wiring layer.

12. A display device as described in claim 11, wherein the plurality of metal layers include a first metal layer, a second metal layer provided on the first metal layer, and a third metal layer provided on the second metal layer.

13. A display device according to claim 12, wherein the first metal layer and the third metal layer are each made of titanium or a titanium alloy, and the second metal layer is made of aluminum or an aluminum alloy.

14. A display device according to any one of claims 11 to 13, wherein the second wiring layer is formed with a cross-sectional tapered shape in which both side surfaces in the width direction of the lead line approach each other toward the upper layer.

15. A display device according to any one of claims 11 to 14, wherein the second wiring layer is provided so as to entirely cover the first wiring layer with the first inorganic insulating film interposed therebetween.

16. A display device according to any one of claims 1 to 15, wherein the circuit board includes a plurality of circuit elements provided in the display area, and the first wiring layer is formed in the same layer and from the same material as electrodes constituting the circuit elements or wiring connected to the circuit elements.

17. A display device according to any one of claims 1 to 16, wherein the circuit board includes a plurality of circuit elements provided in the display area, and the second wiring layer is formed in the same layer and from the same material as the electrodes constituting the circuit elements or the wiring connected to the circuit elements.

18. A display device according to any one of claims 1 to 17, wherein the sealing film includes a first inorganic barrier layer as the inorganic barrier layer, an organic barrier layer provided on the first inorganic barrier layer, and a second inorganic barrier layer provided on the organic barrier layer.

19. The display device according to any one of claims 1 to 18, wherein the light-emitting element is an organic electroluminescence element.

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