Method for assertion verification, assertion verification platform, electronic device, and readable storage medium

Abstract

Embodiments of the present invention relate to the technical field of computers, and provide a method for assertion verification, an assertion verification platform, an electronic device, and a readable storage medium. The method for assertion verification is applied to an assertion verification platform, and the assertion verification platform comprises a programmable logic chip, the programmable logic chip being configured with a design under test, a coverage monitor, and a hardware assertion test set. The method comprises: performing assertion verification on the design under test by using the hardware assertion test set, and determining, by means of the coverage monitor, the assertion coverage of the design under test; and when the assertion coverage of the design under test meets a preset condition, determining that the design under test passes verification.

Description

Assertion verification method, assertion verification platform, electronic device and readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 27, 2023, with application number 202310934159.X and titled “Assertion Verification Method, Assertion Verification Platform, Electronic Device and Readable Storage Medium,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present invention relates to the field of computer technology, and in particular to an assertion verification method, an assertion verification platform, an electronic device, and a readable storage medium. Background Art

[0004] With the increasing use of large-scale and ultra-large-scale integrated circuits (ICs) in industry, functional verification has become the most time-consuming process in chip development. Verification accounts for 70% of the development effort. One bottleneck is completing ASIC prototype verification on the FPGA platform. Although FPGA prototype verification can utilize FPGA boards to closely simulate the problems encountered by the chip in a physical environment and maintain a certain frequency (1MHz to 10MHz) during testing, the compilation and synthesis time of early EDA tools for FPGAs is too long. Furthermore, register-level data cannot be effectively obtained on FPGA boards, resulting in prototype verification failing to fully identify all errors. This significantly reduces verification efficiency and consumes a long time.

[0005] FPGAs, as a standard method and accelerator for prototyping, can significantly improve performance. However, using FPGAs to debug RTL designs is not simple. Current vendor-provided debugging tools, such as Signaltap and ILA, introduce significant area overhead and can only monitor a limited number of internal signals. Accelerators designed for prototyping by existing hardware vendors, such as Paladin and CoreShen Ding, have high design costs. A very large-scale integrated circuit design requires equipment costing over $1 million to support acceleration, and the speed is only around 5MHz. Moreover, existing hardware-based RTL testing solutions are executed at the instruction set architecture level, lacking low-level visibility into design details and unable to reveal internal errors and defects in the design. SystemVerilog assertions are suitable for automated detection of errors and defects within the design, but SystemVerilog assertions cannot be synthesized into hardware circuits and can only be used for software simulation, which is slower than hardware operation.

[0006] Summary of the Invention

[0007] The embodiments of the present invention provide an assertion verification method, an assertion verification platform, an electronic device, and a readable storage medium, which can solve the problem in related arts that assertions cannot be applied to hardware simulation.

[0008] To address the above-mentioned issues, in a first aspect, embodiments of the present invention disclose an assertion verification method, which is applied to an assertion verification platform. The assertion verification platform includes a programmable logic chip configured with a design under test, a coverage monitor, and a hardware-based assertion test set. The method includes:

[0009] Performing assertion verification on the design under test using the hardware assertion test set, and determining the assertion coverage of the design under test using the coverage monitor;

[0010] When the assertion coverage of the design under test meets a preset condition, it is determined that the design under test passes the verification.

[0011] In a second aspect, an embodiment of the present invention discloses an assertion verification platform, comprising a programmable logic chip and a first module; the programmable logic chip is configured with a design under test, a coverage monitor, and a hardware assertion test set;

[0012] The hardware assertion test set is used to perform assertion verification on the design under test;

[0013] The coverage monitor is used to determine the assertion coverage of the design under test;

[0014] The first module is configured to determine that the design under test passes verification when the assertion coverage of the design under test meets a preset condition.

[0015] In a third aspect, an embodiment of the present invention further discloses an electronic device, comprising a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned assertion verification method.

[0016] In a fourth aspect, an embodiment of the present invention further discloses a readable storage medium, which, when instructions in the readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the aforementioned assertion verification method.

[0017] In a fifth aspect, an embodiment of the present invention further discloses a computer program product (the computer program product is stored in a non-volatile storage medium), and the computer program product is executed by at least one processor to implement the assertion verification method as described above.

[0018] In a sixth aspect, an embodiment of the present invention further discloses a transmission apparatus / device, including the apparatus / device (configured to) be used in the assertion verification method as described above.

[0019] The embodiments of the present invention include the following advantages:

[0020] The assertion verification method provided by an embodiment of the present invention utilizes an assertion verification platform to perform assertion verification on the design under test. In the assertion verification platform provided by an embodiment of the present invention, non-synthesizable assertion statements are converted into an equivalent hardware assertion test set. The hardware assertion test set and the design under test are both burned into the programmable logic chip, thereby realizing hardware-based debugging acceleration of the design under test. Furthermore, during the assertion verification process, the embodiment of the present invention can collect the assertion coverage of the design under test through a coverage monitor, thereby quickly obtaining assertion verification results and improving verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0022] FIG1 is a flowchart of an embodiment of an assertion verification method of the present invention;

[0023] FIG2 is a schematic structural diagram of an assertion verification platform of the present invention;

[0024] FIG3 is a schematic diagram of the structure of another assertion verification platform of the present invention;

[0025] FIG4 is a schematic diagram of a target netlist generation process of the present invention;

[0026] FIG5 is a structural block diagram of an electronic device for assertion verification provided by an example of the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0028] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0029] In order to facilitate understanding of the embodiments provided by the present invention, the following points are explained:

[0030] 1. SV language (SystemVerilog) and SV assertion (SystemVerilog Assertion, SVA)

[0031] SystemVerilog is a hardware description language (HDL) used to design and verify digital circuits. It extends Verilog HDL, providing many new features and capabilities, making it more suitable for complex hardware design and verification tasks.

[0032] SVA is a key feature of SystemVerilog, used to describe and verify the behavior and properties of a system during the design and verification process. SVA allows designers to insert assertions into the hardware description to express properties about the design's behavior and state. SVA uses a syntax similar to sequential logic, which has rich expressive capabilities and can describe properties such as time correlation, sequence, and concurrency. SVA statements can be used for design verification, formal verification, and error debugging. SVA statements typically include the following:

[0033] i. Property: describes an expected or specified system behavior.

[0034] ii. Sequence: describes a sequence of events or states.

[0035] iii. Assertion: Combines properties and sequences and specifies when they are true.

[0036] iv. Clocking Block: defines the clock and sampling timing.

[0037] v. Coverage: Used to evaluate the property coverage of the design.

[0038] 2. Assertion-based Verification

[0039] Assertions are an effective hardware design verification method used to ensure that a design meets specific specifications and requirements. Assertions are statements that describe the behavior and properties of a design and are used to verify that the design meets these properties at runtime. Assertion-based verification uses assertions to verify that a design meets specific specifications and requirements. It can improve verification efficiency, reduce errors, and help design teams quickly identify and resolve design issues.

[0040] In assertion verification, the design is divided into two parts: the Design Under Test (DUT) and the test environment (Testbench). The test environment includes components such as test vector generators, clocks, monitors, and assertion checkers. The test vector generator generates input data, the clock provides timing information, the monitor is used to detect the output of the design, and the assertion checker is used to check whether the design meets the specified assertions. The basic principle of assertion verification is that when the test vector drives the design to run, the monitor monitors the output of the design and compares it with the expected results. At the same time, the assertion checker evaluates the assertion statement and issues a verification error if the assertion fails (that is, the assertion is false). This method can quickly discover errors in the design during the verification process and help developers confirm whether the design meets the specification requirements.

[0041] 3. Circuit synthesis

[0042] In hardware circuit design, "synthesize" is used to describe whether hardware description language code can be converted into properties of equivalent hardware circuits. This conversion process is usually completed by circuit synthesis tools (such as logic synthesizers).

[0043] Synthesizable code is code that can be converted into hardware circuits using a logic synthesizer. Logic synthesis is the process of converting high-level, abstract code written in a hardware description language (such as SystemVerilog) into low-level hardware elements such as basic logic gates and registers. Synthesizable code should be clearly structured and timed, using only hardware primitives and constructs supported by the synthesis tool.

[0044] Non-synthesizable code is code that cannot be directly converted into hardware using a logic synthesizer. It contains features that make sense at a high level of abstraction but cannot be mapped to hardware, such as delays, loops, and conditional branches. This code is often used for non-synthesizable purposes such as simulation, verification, and testing.

[0045] Some syntax and features in SVA are not synthesizable because they are mainly used to describe and verify the behavior and properties of the system rather than directly describe the hardware structure. For example:

[0046] i. Behaviors with delays. The delays cannot be directly mapped to the hardware’s sequential logic during synthesis.

[0047] ii. Sampling functions, such as "$rose()," "$stable()," and "$past()," are typically used in simulation environments to verify and debug designs. However, these sampling functions are generally unsynthesizable during synthesis because they cannot be directly mapped to equivalent elements in hardware circuits. Synthesis tools cannot directly convert these functions into hardware logic.

[0048] iii. Sequence operation keywords, such as intersect and firstmatch, are often used in the verification phase to check whether the design meets specific timing properties. Synthesis tools cannot directly convert these operators into hardware logic.

[0049] Because these features cannot be directly mapped to hardware circuits, synthesis tools cannot convert SVA code containing non-synthesizable features into equivalent hardware circuits. In actual designs, SVA is typically used in the verification phase rather than for direct hardware generation. Synthesizable hardware description language code and non-synthesizable verification code are usually written and used separately.

[0050] 4. Register-Transfer Level (RTL) circuit

[0051] RTL circuits are a common type of hardware description-level circuit. RTL circuits describe the behavior and structure of digital circuits and are represented using the register transfer level (RTL). RTL circuit descriptions are typically written in a hardware description language (HDL), such as VHSIC Hardware Description Language (VHDL), Verilog HDL, and SystemVerilog HDL. Designers can use RTL-level descriptions to define and implement the desired digital circuit functionality, and then use synthesis tools to convert the RTL-level descriptions into physical implementations in field-programmable gate arrays (FPGAs). In the field of FPGA and chip design and verification, RTL-level descriptions are crucial for design, verification, and debugging. They provide a level of abstraction that enables designers to describe circuit behavior at a higher level of abstraction and use appropriate tools for simulation, verification, and synthesis, ultimately generating a bitstream file that can be configured into the FPGA chip to implement the specific digital circuit functionality.

[0052] 5. FPGA

[0053] FPGAs are reconfigurable integrated circuits with a wide range of applications. Unlike traditional fixed-function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured according to user needs, adapting them to different applications and functions. FPGAs consist of a large number of programmable logic blocks and programmable interconnect resources. Programmable logic blocks typically consist of look-up tables (LUTs), registers, and other logic elements, and can perform various logic functions. Programmable interconnect resources are used to connect logic blocks to form the desired circuit structure. Using FPGAs, designers can describe the desired circuit functionality using a hardware description language (HDL) and, using programming tools, convert this into a bitstream compatible with the FPGA chip. The bitstream contains information for programming and configuring the FPGA's internal logic and interconnect resources. One of the main advantages of FPGAs is their programmability and flexibility. They allow designers to implement customized functions and algorithms at the hardware level without the traditional custom IC design and manufacturing process. This makes FPGAs crucial for prototyping and rapid design iteration.

[0054] 6. Dynamic Partial Reconfiguration (DPR)

[0055] Dynamic partial reconfiguration (DPR) of FPGAs refers to the ability to reconfigure portions of a circuit while the FPGA is running. In traditional FPGA designs, the entire circuit typically needs to be reprogrammed and reloaded into the FPGA to change its functionality. However, DPR technology allows only portions of the circuit to be reconfigured while the FPGA is running, without affecting other running circuits. The main advantages of dynamic partial reconfiguration lie in its flexibility and improved resource utilization. By using DPR, multiple functional modules can be implemented in the FPGA, each of which can be independently reconfigured as needed without reloading the entire design. This flexibility enables FPGAs to adapt to a variety of application requirements while reducing reprogramming and reloading time and accelerating design iterations.

[0056] 7. Electronic Design Automation (EDA) software

[0057] EDA software is industrial software used to assist in the design and production of very large-scale integrated circuits (VLSIs), encompassing the entire process of circuit chip design, manufacturing, packaging, and testing. As chip design becomes increasingly complex, integrated circuits based on advanced process nodes can reach billions of semiconductor devices, requiring the use of EDA software to achieve these results.

[0058] 8. Netlist

[0059] In electronic design automation, a netlist is a method of describing the connections of digital circuits using basic logic gates. Because a logic gate array has a similar arrangement to a wirelist, it is called a "netlist." A netlist typically conveys information about circuit connections, such as module instances, nets, and related properties. If more hardware information is required, hardware description languages ​​such as Verilog, VHDL, or other specialized languages ​​are typically used for description, verification, and simulation. High-level abstraction (such as the register transfer level) hardware descriptions can be converted into a low-level abstraction (logic gate level) circuit connection netlist through logic synthesis. This step can now be automated using tools, significantly reducing the complexity for designers working with very large-scale integrated circuits (VLSIs). Hardware manufacturers use this netlist to manufacture specific application-specific integrated circuits or other circuits. Some relatively small circuits can also be implemented on field-programmable gate arrays.

[0060] 9. Tool Command Language (TCL)

[0061] Tool Command Language (TCL) is an interpreted scripting language that provides general programming capabilities, including support for variables, procedures, and control structures. It also has a powerful, inherent core command set. TCL is often used for rapid prototyping, scripting, GUIs, and testing.

[0062] 10. Formal Verification

[0063] Formal verification is an IC design verification method that uses formal proofs to verify the functional correctness of a design. Formal verification can be divided into three categories: equivalence checking, formal model checking (also known as property checking), and theorem proving. Equivalence checking verifies consistency between the RTL design and the gate-level netlist, and between gate-level netlists.

[0064] An embodiment of the present invention provides an assertion verification method that can be applied to an assertion verification platform. By converting non-synthesizable assertion statements into an equivalent hardware assertion test set and collecting the assertion coverage of the tested design through a coverage monitor, assertion verification results can be quickly obtained, thereby improving verification efficiency.

[0065] 1 , there is shown a flowchart of an embodiment of an assertion verification method of the present invention. The method may specifically include the following steps:

[0066] Step 101: Perform assertion verification on the design under test using a hardware assertion test set, and determine the assertion coverage of the design under test using a coverage monitor;

[0067] Step 102: If the assertion coverage of the design under test meets a preset condition, determine that the design under test passes verification.

[0068] The assertion verification method provided in an embodiment of the present invention can be applied to an assertion verification platform. Referring to FIG2 , a schematic diagram of the structure of an assertion verification platform provided in an embodiment of the present invention is shown. As shown in FIG2 , the assertion verification platform includes a programmable logic (PL) chip, which is configured with a design under test (DUT), a coverage monitor, and a hardware-based assertion test set (Assertion Group).

[0069] Among them, the hardware assertion test set includes multiple assertion circuits, which are register conversion level circuits (RTL circuits) used to implement the same functions as assertion statements. By performing hardware simulation on the assertion statements, non-synthesizable assertion statements can be converted into equivalent synthesizable assertion circuits. For example, the assertion statements can be parsed to identify non-synthesizable keywords in the assertion statements, such as behaviors containing delays, sampling functions, sequence operation keywords, etc., and then, based on the verification logic, state transition and other information of these keywords, the equivalent circuits corresponding to these keywords are generated. Finally, according to the overall verification logic of the assertion statements, the equivalent circuits corresponding to these keywords are connected to obtain the assertion circuits corresponding to the assertion statements.

[0070] The coverage monitor is used to sample the assertion results and to collect statistics on the assertion coverage. Assertion coverage is a test metric that measures the extent to which assertion statements are executed during the test process. Assertion coverage is usually expressed as a percentage, specifically the ratio between the number of assertion statements that have been correctly executed and the total number of assertion statements. For example, if there are 100 assertion statements in the design file and 80 assertion statements are correctly executed in the test, then the assertion coverage is 80%. A higher assertion coverage indicates that the test covers more assertion statements, thereby providing a more comprehensive test guarantee. In an embodiment of the present invention, the preset condition can be set according to the specific verification requirements. For example, the preset condition can be that the assertion coverage of the design under test is greater than or equal to a preset threshold, and so on.

[0071] As an example, a coverage monitor can count the number of correct assertions. When the number of correct assertions for the design under test is greater than or equal to a preset threshold, the design under test is determined to have passed verification. Conversely, if the number of correct assertions for the design under test is less than the preset threshold, the design under test is determined to have failed verification. In this case, data simulation can be performed on the assertion failure to locate the cause and perform error debugging and repair.

[0072] During the assertion verification process of the design under test, the programmable logic chip (such as FPGA) in the assertion verification platform can be run, and the assertion circuit in the hardware assertion test set can be used to perform assertion verification on the design under test, and the assertion results of the design under test can be monitored through the coverage monitor. Once the signal to be monitored in the design under test runs in a manner that violates the description of the assertion statement, the assertion circuit will automatically mark the problem and output an assertion failure signal. When the coverage monitor detects the assertion failure signal, it can be determined that the assertion has failed. When the assertion coverage of the design under test meets the preset conditions, it can be determined that the design under test has passed the verification.

[0073] Current vendor-provided FPGA debugging tools have significant footprint overhead and can only monitor a limited number of internal signals. However, the present invention replaces FPGA debugging tools with a hardware-based assertion test suite. Compared to FPGA debugging tools, hardware-based assertion test suites have lower resource overhead and can monitor multiple groups of signals simultaneously.

[0074] In actual testing, the assertion verification method provided by this embodiment of the present invention verified the design under test on an FPGA using a hardware-based assertion test suite, achieving a performance improvement of up to 40,989 times compared to software simulation. Compared to debugging tools provided by existing vendors, this method minimizes area overhead and has no impact on the timing behavior of the device under test.

[0075] The assertion verification method provided by an embodiment of the present invention utilizes an assertion verification platform to perform assertion verification on the design under test. In the assertion verification platform provided by an embodiment of the present invention, non-synthesizable assertion statements are converted into an equivalent hardware assertion test set. The hardware assertion test set and the design under test are both burned into the programmable logic chip, thereby realizing hardware-based debugging acceleration of the design under test. Furthermore, during the assertion verification process, the embodiment of the present invention can collect the assertion coverage of the design under test through a coverage monitor, thereby quickly obtaining assertion verification results and improving verification efficiency.

[0076] In an optional embodiment of the present invention, the assertion verification platform further includes a simulation system and a processing system, the processing system includes an interrupt controller and a standard reference model; the programmable logic region is further configured with a hardware snapshot controller; the method further includes:

[0077] Step S11: When the coverage monitor detects an assertion failure, the coverage monitor sends a first indication to the interrupt controller;

[0078] Step S12: Upon receiving the first instruction, the interrupt controller interrupts the assertion verification of the design under test;

[0079] Step S13: When the assertion verification is interrupted, the hardware snapshot controller collects data information of each register in the design under test and sends the data information to the simulation system;

[0080] Step S14: The simulation system performs data simulation based on the data information and the standard reference model to locate the cause of assertion failure of the design under test and perform error debugging and repair.

[0081] With reference to Figure 3, a schematic diagram of the structure of another assertion verification platform provided by an embodiment of the present invention is shown. As shown in Figure 3, the assertion verification platform includes a programmable logic chip, a processing system (PS) and a simulation system. Among them, the programmable logic chip is configured with a design under test (DUT), a coverage monitor, a hardware assertion test set and a hardware snapshot controller (Snapshot Controller). The processing system includes an interrupt controller (Interrupt Controller) and a standard reference model (Reference Model) of the design under test, and the processing system can run on a hard-core ARM processor of a programmable logic chip (such as FPGA). The simulation system is used to perform data simulation after an assertion fails, reproduce the cause of the assertion failure and perform full waveform search, and locate error information. The simulation system may include simulation software (Model Sim), a simulation model (Sim Model), input stimulus and results (Mem Data), and the like.

[0082] In an embodiment of the present invention, when the coverage monitor detects an assertion failure, it can send a first indication to the interrupt controller, indicating the assertion failure. Upon receiving the first indication, the interrupt controller interrupts the operation of the design under test, and the coverage monitor stops sampling, thereby interrupting the assertion verification process of the design under test.

[0083] If assertion verification is interrupted, the hardware snapshot controller collects data from various registers at the time the false assertion is triggered, meaning the DUT stops running, and transmits this data via a bus to the simulation system. The simulation system uses simulation software, standard reference models, and simulation models to locate the cause of the assertion failure and perform error debugging and repair.

[0084] For example, the hardware snapshot controller can transmit the collected data information to the input stimulus and result section of the simulation software. By observing the variable values, signal transmission paths, and other information in the standard reference model during the simulation process, it can perform more fine-grained verification of the design under test and more accurately locate problems, thereby accelerating problem identification and repair. After fixing the assertion failure, the simulation can be rerun to verify the effectiveness of the fix and ensure that the assertion no longer fails.

[0085] In an optional embodiment of the present invention, the hardware assertion test set includes an assertion circuit, which is a hardware description level circuit; the hardware assertion test set is configured in a dynamic partial reconfiguration area of ​​the programmable logic chip; and the method further includes:

[0086] When the assertion coverage of the design under test meets a preset condition, the assertion circuit in the dynamic partial reconfiguration region is replaced to perform a next round of assertion verification on the design under test.

[0087] In an embodiment of the present invention, a programmable logic chip (hereinafter referred to as an "FPGA chip") can be divided into a static area and a dynamic partial reconfiguration area based on whether it supports reconfiguration. The design under test is burned into the static area of ​​the FPGA chip, and the assertion circuits in the hardware assertion test set are burned into the dynamic partial reconfiguration area of ​​the FPGA chip. This allows for flexible, rapid, batch updating of assertion circuits without affecting the design under test, allowing for testing of different signals of the design under test.

[0088] If the assertion coverage of the design under test meets the preset conditions, it can be determined that the design under test has passed this verification. In this case, the assertion circuit in the dynamic partial reconfiguration area can be replaced to perform the next round of assertion verification on the design under test, avoiding the time of recompiling and loading the design under test, so that the assertion circuits of different projects can be quickly and batch-changed for testing.

[0089] In an optional embodiment of the present invention, the hardware-based assertion test set includes an assertion circuit, which is a hardware description level circuit; before performing assertion verification on the design under test using the hardware-based assertion test set and determining the assertion coverage of the design under test using the coverage monitor, the method further includes:

[0090] Step S21: obtaining signal connection information between the design under test and the assertion circuit;

[0091] Step S22: generating a target netlist based on the signal connection information, the design under test, and the assertion circuit; the target netlist is used to describe the connection between the design under test and the assertion circuit using logic gates;

[0092] Step S23, generating a target bitstream file according to the target netlist;

[0093] Step S24: Utilize the target bitstream file to configure the design under test and the assertion circuit into the programmable logic chip.

[0094] In an embodiment of the present invention, the assertion circuit and the design under test can be converted into a target netlist, and the signals can be connected at the network level according to the signal connection information between the design under test and the assertion circuit to generate a target bitstream file that can be configured in the FPGA chip, thereby realizing a synthesizable circuit implementation with the same function as the assertion statement.

[0095] It should be noted that in electronic design automation, a netlist refers to a method of describing the connections of digital circuits using basic logic gates. Because a logic gate array has a similar arrangement to a wirelist, it is called a "netlist." A netlist typically conveys information about circuit connections, such as module instances, nets, and related properties. If more hardware information is required, hardware description languages ​​such as Verilog, VHDL, or other specialized languages ​​are typically used for description, verification, and simulation. High-level abstraction hardware descriptions (such as the register transfer level) can be converted into a low-level abstraction (logic gate level) circuit connection netlist through logic synthesis. This step can now be automated using tools, significantly reducing the complexity for designers working with very large-scale integrated circuits (VLSIs). Hardware manufacturers use this netlist to manufacture specific application-specific integrated circuits or other circuits. Some relatively small circuits can also be implemented on field-programmable gate arrays.

[0096] In an embodiment of the present invention, the target netlist is used to describe the connection between the design under test and the assertion circuit using logic gates. Specifically, in the target netlist, the input end of the assertion circuit is connected to the output end of the signal to be monitored in the design under test.

[0097] A target bitstream file can be generated based on the target netlist. A bitstream file is a binary file used to store and transmit configuration information for a programmable logic device (such as an FPGA). It contains bit information that configures the FPGA for specific hardware functions. In an embodiment of the present invention, the target bitstream file contains bit information that configures the FPGA for hardware verification of the design under test using an assertion circuit. Specifically, the target bitstream file contains the FPGA's logic gate configuration, register settings, and connection information. Using the target bitstream file, the assertion circuit and the design under test can be burned onto the FPGA board to implement the configuration of the FPGA.

[0098] Optionally, step S22 generates a target netlist based on the signal connection information, the design under test, and the assertion circuit, including:

[0099] Sub-step S221, converting the design under test into a first netlist, and converting the assertion circuit into a second netlist;

[0100] Sub-step S222: stitching the corresponding parts of the first netlist and the second netlist based on the signal connection information to obtain a target netlist; in the target netlist, the signal input end of the second netlist is connected to the output end of the signal to be monitored in the first netlist.

[0101] In an embodiment of the present invention, the design under test and the assertion circuit can be converted into corresponding netlists, and then the corresponding parts of the two netlists can be stitched together based on the same signal names to obtain a target netlist. In the target netlist, the signal input terminal of the second netlist is connected to the output terminal of the signal to be monitored in the first netlist.

[0102] Figure 4 shows a schematic diagram of the target netlist generation process. As shown in Figure 4, the synthesis tool provided by the FPGA manufacturer can be used to convert the RTL code of the design under test into a first netlist, and the RTL code of the assertion circuit into a second netlist. The netlist wiring tool then modifies the two netlists using Tool Command Language (TCL) instructions. Specifically, it stitches together corresponding portions of the two netlists based on identical signal names, inserts signal probes, and generates the target netlist.

[0103] In summary, an embodiment of the present invention provides an assertion verification method, which uses an assertion verification platform to perform assertion verification on the design under test. In the assertion verification platform provided by the embodiment of the present invention, non-synthesizable assertion statements are converted into equivalent hardware assertion test sets, and the hardware assertion test sets and the design under test are both burned into the programmable logic chip, thereby realizing the debugging acceleration of the design under test by hardware. Moreover, during the assertion verification process, the embodiment of the present invention can collect the assertion coverage of the design under test through a coverage monitor, thereby quickly obtaining the assertion verification results and improving the verification efficiency.

[0104] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0105] 2 , a schematic diagram of the structure of an assertion verification platform of the present invention is shown, wherein the assertion verification platform includes a programmable logic chip; the programmable logic chip is configured with a design under test, a coverage monitor, and a hardware assertion test set;

[0106] The hardware assertion test set is used to perform assertion verification on the design under test;

[0107] The coverage monitor is used to determine the assertion coverage of the design under test; if the assertion coverage of the design under test meets a preset condition, it is determined that the design under test has passed the verification.

[0108] Optionally, the assertion verification platform further includes a simulation system and a processing system, wherein the processing system includes an interrupt controller and a standard reference model;

[0109] The coverage monitor is configured to send a first indication to the interrupt controller when an assertion failure is detected;

[0110] The interrupt controller is configured to interrupt assertion verification of the design under test upon receiving the first indication;

[0111] The hardware snapshot controller is used to collect data information of each register in the design under test and send the data information to the simulation system when the assertion verification is interrupted;

[0112] The simulation system is used to perform data simulation based on the data information and the standard reference model to locate the assertion failure cause of the design under test and perform error debugging and repair.

[0113] Optionally, the hardware assertion test set includes an assertion circuit, which is a hardware description level circuit; the hardware test set is configured in a dynamic partial reconfiguration area of ​​the programmable logic chip; the assertion verification platform further includes a first module;

[0114] The first module is configured to replace the assertion circuit in the dynamic partial reconfiguration region when the assertion coverage of the design under test meets a preset condition, so as to perform a next round of assertion verification on the design under test.

[0115] Optionally, the hardware assertion test set includes an assertion circuit, which is a hardware description level circuit; and the assertion verification platform further includes:

[0116] An information acquisition module, configured to acquire signal connection information between the design under test and the assertion circuit;

[0117] A netlist generation module is configured to generate a target netlist based on the signal connection information, the design under test, and the assertion circuit; the target netlist is configured to describe the connection between the design under test and the assertion circuit using logic gates;

[0118] A bitstream file generating module, configured to generate a target bitstream file according to the target netlist;

[0119] A configuration module is used to configure the design under test and the assertion circuit into the programmable logic chip using the target bitstream file.

[0120] Optionally, the netlist generation module includes:

[0121] a netlist generation submodule, configured to convert the design under test into a first netlist and convert the assertion circuit into a second netlist;

[0122] The netlist stitching submodule is used to stitch the corresponding parts of the first netlist and the second netlist based on the signal connection information to obtain a target netlist; in the target netlist, the signal input end of the second netlist is connected to the output end of the signal to be monitored in the first netlist.

[0123] In summary, the assertion verification platform provided by the embodiment of the present invention can perform assertion verification on the design under test. In the assertion verification platform provided by the embodiment of the present invention, non-synthesizable assertion statements are converted into equivalent hardware assertion test sets. The hardware assertion test sets and the design under test are both burned into the programmable logic chip, realizing the debugging acceleration of the design under test by hardware. Moreover, during the assertion verification process, the embodiment of the present invention can collect the assertion coverage of the design under test through the coverage monitor, thereby quickly obtaining the assertion verification results and improving the verification efficiency.

[0124] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0125] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0126] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0127] Figure 5 is a block diagram of an electronic device for assertion verification according to an embodiment of the present invention. As shown in Figure 5 , the electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory stores executable instructions that cause the processor to execute the assertion verification method according to the aforementioned embodiment.

[0128] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0129] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, for example. The communication bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG5 shows only one line, but this does not imply that there is only one bus or only one type of bus.

[0130] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0131] An embodiment of the present invention further provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is enabled to execute the assertion verification method shown in FIG1 .

[0132] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0133] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0134] It is understood that the embodiments described in the embodiments of the present invention can be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the modules, units, and sub-units can be implemented in one or more ASICs, DSPs, digital signal processing devices (DSP devices, DSPDs), programmable logic devices (PLDs), FPGAs, general-purpose processors, controllers, microcontrollers, microprocessors, and other electronic units used to perform the functions described in the present invention, or a combination thereof.

[0135] For software implementation, the techniques described in the embodiments of the present invention can be implemented through modules (e.g., procedures, functions, etc.) that perform the functions described in the embodiments of the present invention. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0136] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0137] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0138] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0139] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0140] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0141] The above is a detailed introduction to the assertion verification method, assertion verification platform, electronic device and readable storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. An assertion verification method, applied to an assertion verification platform, wherein the assertion verification platform comprises a programmable logic chip, wherein the programmable logic chip is configured with a design under test, a coverage monitor, and a hardware assertion test set; The method comprises: Performing assertion verification on the design under test using the hardware assertion test set, and determining the assertion coverage of the design under test using the coverage monitor; When the assertion coverage of the design under test meets a preset condition, it is determined that the design under test passes the verification.

2. The method according to claim 1, wherein: The assertion verification platform further includes a simulation system and a processing system, wherein the processing system includes an interrupt controller and a standard reference model; a hardware snapshot controller is also configured in the programmable logic area; and the method further includes: The coverage monitor sends a first indication to the interrupt controller when detecting an assertion failure; The interrupt controller interrupts the assertion verification of the design under test when receiving the first indication; The hardware snapshot controller collects data information of each register in the design under test when the assertion verification is interrupted, and sends the data information to the simulation system; The simulation system performs data simulation according to the data information and the standard reference model to locate the assertion failure cause of the design under test and perform error debugging and repair.

3. The method according to claim 1, wherein: The hardware assertion test set includes an assertion circuit, and the assertion circuit is a hardware description level circuit; The hardware test set is configured in a dynamic partial reconfiguration area of ​​the programmable logic chip; the method further includes: When the assertion coverage of the design under test meets a preset condition, the assertion circuit in the dynamic partial reconfiguration region is replaced to perform a next round of assertion verification on the design under test.

4. The method according to claim 1, wherein: The hardware-based assertion test set includes an assertion circuit, which is a hardware description level circuit; before using the hardware-based assertion test set to perform assertion verification on the design under test and determining the assertion coverage of the design under test through the coverage monitor, the method further includes: Acquiring signal connection information between the design under test and the assertion circuit; Generate a target netlist based on the signal connection information, the design under test and the assertion circuit; the target netlist is used to describe the connection between the design under test and the assertion circuit using logic gates; Generate a target bitstream file according to the target netlist; The design under test and the assertion circuit are configured into the programmable logic chip using the target bitstream file.

5. The method according to claim 4, wherein: The generating a target netlist based on the signal connection information, the design under test and the assertion circuit comprises: converting the design under test into a first netlist and converting the assertion circuit into a second netlist; Based on the signal connection information, the first netlist and the corresponding parts of the second netlist are stitched together. processing to obtain a target netlist; in the target netlist, a signal input end of the second netlist is connected to an output end of the signal to be monitored in the first netlist.

6. An assertion verification platform, comprising a programmable logic chip; the programmable logic chip is configured with a design under test, a coverage monitor, and a hardware assertion test set; The hardware assertion test set is used to perform assertion verification on the design under test; The coverage monitor is used to determine the assertion coverage of the design under test; when the assertion coverage of the design under test meets a preset condition, it is determined that the design under test has passed the verification.

7. The assertion verification platform according to claim 6, wherein: The assertion verification platform also includes a simulation system and a processing system, wherein the processing system includes an interrupt controller and a standard reference model; The coverage monitor is used to send a first indication to the interrupt controller when an assertion failure is detected; The interrupt controller is configured to interrupt assertion verification of the design under test when receiving the first indication; The hardware snapshot controller is used to collect data information of each register in the design under test and send the data information to the simulation system in the case of assertion verification interruption; The simulation system is used to perform data simulation according to the data information and the standard reference model to locate the assertion failure cause of the design under test and perform error debugging and repair.

8. The assertion verification platform according to claim 6, wherein: The hardware assertion test set includes an assertion circuit, which is a hardware description level circuit; the hardware test set is configured in the dynamic partial reconfiguration area of ​​the programmable logic chip; the assertion verification platform also includes a first module; The first module is used to replace the assertion circuit in the dynamic partial reconfiguration area when the assertion coverage of the design under test meets a preset condition, so as to perform a next round of assertion verification on the design under test.

9. The assertion verification platform according to claim 6, wherein: The hardware assertion test set includes an assertion circuit, and the assertion circuit is a hardware description level circuit; The assertion verification platform also includes: An information acquisition module, used to acquire signal connection information between the design under test and the assertion circuit; A netlist generation module, configured to generate a target netlist based on the signal connection information, the design under test and the assertion circuit; the target netlist is configured to describe the connection between the design under test and the assertion circuit using logic gates; A bitstream file generating module, used for generating a target bitstream file according to the target netlist; A configuration module is used to configure the design under test and the assertion circuit into the programmable logic chip using the target bitstream file.

10. The assertion verification platform according to claim 9, wherein: The netlist generation module comprises: A netlist generation submodule, configured to convert the design under test into a first netlist and convert the assertion circuit into a second netlist; The netlist stitching submodule is used to stitch the first netlist and the corresponding parts in the second netlist based on the signal connection information to obtain a target netlist; in the target netlist, the signal input end of the second netlist is connected to the output end of the signal to be monitored in the first netlist.

11. An electronic device, comprising a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the assertion verification method as described in any one of claims 1 to 5. 12 . A readable storage medium, when instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the assertion verification method according to claim 1 .

13. A computer program product, (the computer program product is stored in a non-transitory storage medium,) the computer program product is executed by at least one processor to implement the assertion verification method according to any one of claims 1 to 5.

14. A transmission device / equipment, comprising the device / equipment (configured to be) used in the assertion verification method according to any one of claims 1 to 5.

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