Driving module, driving method, and display device

Abstract

The present disclosure provides a driving module, a driving method, and a display device. The driving module comprises N stages of driving circuits; N is an integer greater than 1; an n-th-stage driving circuit is separately electrically connected to an n-th input end, an n-th control clock signal end, an n-th output clock signal end, and an n-th-stage driving signal output end, and is used for, under the control of an n-th control clock signal and an n-th output clock signal, on the basis of an n-th input signal, controlling to output the n-th output clock signal to the n-th-stage driving circuit output end during an n-th output phase; effective voltage durations of driving signals output by the N stages of driving circuits do not overlap with each other; and n is a positive integer less than or equal to N. According to the driving module in embodiments of the present disclosure, by controlling control clock signals and output clock signals provided to different stages of driving circuits, the effective voltage durations of the driving signals output by the N stages of driving circuits do not overlap with each other, thereby realizing non-overlapping dual-pulse shifting timing output.

Description

Driving module, driving method and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310916527.8 filed in China on July 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a driving module, a driving method, and a display device. Background Art

[0004] In the relevant driving module, in the odd-numbered driving circuit, the control clock signal end is electrically connected to the first clock signal line, and the output clock signal end is electrically connected to the second clock signal line; in the even-numbered driving circuit, the control clock signal end is electrically connected to the second clock signal line, and the output clock signal line is electrically connected to the first clock signal line, resulting in that when each level of the driving circuit outputs a double-pulse driving signal, there is an overlapping time period between the effective voltage duration periods of the driving signal output by the odd-numbered driving circuit, and there is an overlapping time period between the effective voltage duration periods of the driving signal output by the even-numbered driving circuit, resulting in that during the overlapping time period, the data line cannot be given the normally required data voltage.

[0005] Summary of the Invention

[0006] In one aspect, an embodiment of the present disclosure provides a driving module, wherein the driving module includes N-stage driving circuits; N is an integer greater than 1;

[0007] The n-stage driving circuit is electrically connected to the n-th input terminal, the n-th control clock signal terminal, the n-th output clock signal terminal, and the n-stage driving signal output terminal, respectively, and is configured to, under the control of the n-th control clock signal provided by the n-th control clock signal terminal and the n-th output clock signal provided by the n-th output clock signal terminal, control the n-th output clock signal provided by the n-th output clock signal terminal to be output to the n-stage driving signal output terminal in an n-output stage according to the n-th input signal provided by the n-th input terminal;

[0008] The effective voltage duration periods of the driving signals output by the N-stage driving circuits do not overlap with each other;

[0009] n is a positive integer less than or equal to N.

[0010] Optionally, the driving module includes at least three clock signal lines;

[0011] One of the at least three clock signal lines is electrically connected to the nth control clock signal terminal, and another one of the at least three clock signal lines is electrically connected to the nth output clock signal terminal.

[0012] Optionally, the driving module includes three clock signal lines;

[0013] The 3a-2 control clock signal terminal is electrically connected to the first clock signal line, and the 3a-2 output clock signal terminal is electrically connected to the third clock signal line;

[0014] The 3a-1 control clock signal terminal is electrically connected to the third clock signal line, and the 3a-1 output clock signal terminal is electrically connected to the second clock signal line;

[0015] The 3a control clock signal terminal is electrically connected to the second clock signal line, and the 3a output clock signal line is electrically connected to the first clock signal line;

[0016] a is a positive integer.

[0017] Optionally, the first clock signal line is used to provide a first clock signal, the second clock signal line is used to provide a second clock signal, and the third clock signal line is used to provide a third clock signal;

[0018] The effective voltage duration period of the first clock signal, the effective voltage duration period of the second clock signal, and the effective voltage duration period of the third clock signal do not overlap with each other.

[0019] Optionally, the driving module includes eight clock signal lines;

[0020] The 8f-7 control clock signal terminal is electrically connected to the first clock signal line, and the 8f-7 output clock signal terminal is electrically connected to the fourth clock signal line;

[0021] The 8f-6 control clock signal terminal is electrically connected to the fourth clock signal line, and the 8f-6 output clock signal terminal is electrically connected to the seventh clock signal line;

[0022] The 8f-5 control clock signal terminal is electrically connected to the seventh clock signal line, and the 8f-5 output clock signal terminal is electrically connected to the second clock signal line;

[0023] The 8f-4th control clock signal terminal is electrically connected to the second clock signal line, and the 8f-4th output clock signal terminal is electrically connected to the fifth clock signal line;

[0024] The 8f-3 control clock signal terminal is electrically connected to the fifth clock signal line, and the 8f-3 output clock signal terminal is electrically connected to the eighth clock signal line;

[0025] The 8f-2 control clock signal terminal is electrically connected to the eighth clock signal line, and the 8f-2 output clock signal terminal is electrically connected to the third clock signal line;

[0026] The 8f-1 th control clock signal terminal is electrically connected to the third clock signal line, and the 8f-1 th output clock signal terminal is electrically connected to the sixth clock signal line;

[0027] The 8f-th control clock signal terminal is electrically connected to the sixth clock signal line, and the 8f-1-th output clock signal terminal is electrically connected to the first clock signal line;

[0028] f is a positive integer.

[0029] Optionally, the effective voltage duration period of the first clock signal provided by the first clock signal line, the effective voltage duration period of the second clock signal provided by the second clock signal line, the effective voltage duration period of the second clock signal provided by the third clock signal line, the effective voltage duration period of the fourth clock signal provided by the fourth clock signal line, the effective voltage duration period of the fifth clock signal provided by the fifth clock signal line, the effective voltage duration period of the sixth clock signal provided by the sixth clock signal line, the effective voltage duration period of the seventh clock signal provided by the seventh clock signal line, and the effective voltage duration period of the eighth clock signal provided by the eighth clock signal line do not overlap with each other.

[0030] Optionally, the driving module further includes N clock signal providing circuits;

[0031] The nth clock signal providing circuit includes an nth forward scanning clock providing circuit and an nth reverse scanning clock providing circuit;

[0032] The nth forward scan clock providing circuit is electrically connected to the forward scan control terminal, the first forward scan clock signal terminal, the second forward scan clock signal terminal, the nth control clock signal terminal, and the nth output clock signal terminal, respectively, and is used to control the connection or disconnection between the first forward scan clock signal terminal and the nth control clock signal terminal, and control the connection or disconnection between the second forward scan clock signal terminal and the nth output clock signal terminal, under the control of the forward scan control signal provided by the forward scan control terminal;

[0033] The nth reverse scan clock providing circuit is electrically connected to the reverse scan control terminal, the first reverse scan clock signal terminal, the second reverse scan clock signal terminal, the nth control clock signal terminal and the nth output clock signal terminal, respectively, and is used to control the connection or disconnection between the first reverse scan clock signal terminal and the nth control clock signal terminal, and control the connection or disconnection between the second reverse scan clock signal terminal and the nth output clock signal terminal under the control of the reverse scan control signal provided by the reverse scan control terminal.

[0034] Optionally, the nth forward scanning clock supply circuit includes a first supply transistor and a second supply transistor, and the nth reverse scanning clock supply circuit includes a third supply transistor and a fourth supply transistor;

[0035] The gate of the first providing transistor is electrically connected to the forward scanning control terminal, the first electrode of the first providing transistor is electrically connected to the first forward scanning clock signal terminal, and the second electrode of the first providing transistor is electrically connected to the nth control clock signal terminal;

[0036] The gate of the second providing transistor is electrically connected to the forward scan control terminal, the first electrode of the second providing transistor is electrically connected to the second forward scan clock signal terminal, and the second electrode of the second providing transistor is electrically connected to the nth output clock signal terminal;

[0037] The gate of the third providing transistor is electrically connected to the reverse scan control terminal, the first electrode of the third providing transistor is electrically connected to the first reverse scan clock signal terminal, and the second electrode of the third providing transistor is electrically connected to the nth control clock signal terminal;

[0038] The gate of the fourth providing transistor is electrically connected to the reverse scan control terminal, the first electrode of the fourth providing transistor is electrically connected to the second reverse scan clock signal terminal, and the second electrode of the fourth providing transistor is electrically connected to the nth output clock signal terminal;

[0039] The first providing transistor and the second providing transistor are both p-type transistors; or, the first providing transistor and the second providing transistor are both n-type transistors;

[0040] The third supply transistor and the fourth supply transistor are both p-type transistors; or, the third supply transistor and the fourth supply transistor are both n-type transistors.

[0041] Optionally, the nth stage driving circuit includes an nth input circuit, an nth first node control circuit, an nth second node control circuit, an nth first energy storage circuit, an nth second energy storage circuit and an nth output circuit;

[0042] The nth input circuit is electrically connected to the nth input terminal, the nth first node and the nth control clock signal terminal respectively, and is used to control the connection between the nth input terminal and the nth first node under the control of the nth control clock signal;

[0043] The nth first node control circuit is electrically connected to the nth first node, the nth output clock signal terminal, the nth second node, and the first voltage terminal, respectively, and is configured to control the connection between the nth first node and the first voltage terminal under the control of the nth output clock signal provided by the nth output clock signal terminal and the potential of the nth second node;

[0044] The nth second node control circuit is electrically connected to the nth control clock signal terminal, the nth first node, and the second voltage terminal, respectively, and is configured to control the connection between the nth second node and the second voltage terminal under the control of the nth control clock signal, and control the connection between the nth second node and the nth control clock signal terminal under the control of the potential of the nth first node;

[0045] The nth first energy storage circuit is electrically connected to the nth first node and the nth driving signal output terminal respectively, and is used for storing electric energy;

[0046] The nth second energy storage circuit is electrically connected to the nth second node, and is used to maintain the potential of the nth second node;

[0047] The nth output circuit is electrically connected to the nth first node, the nth second node, the first voltage terminal, the nth output clock signal terminal and the nth drive signal output terminal, respectively, and is used to control the connection between the nth drive signal output terminal and the nth output clock signal terminal under the control of the potential of the nth first node, and to control the connection between the nth drive signal output terminal and the first voltage terminal under the control of the potential of the nth second node.

[0048] Optionally, the input circuit includes an nth first transistor, the nth first node control circuit includes an nth second transistor and an nth third transistor, the nth second node control circuit includes an nth fourth transistor and an nth fifth transistor, the nth output circuit includes an nth seventh transistor and an nth eighth transistor, the nth first energy storage circuit includes an nth first capacitor, and the nth second energy storage circuit includes an nth second capacitor;

[0049] The gate of the nth first transistor is electrically connected to the nth control clock signal terminal, the first electrode of the nth first transistor is electrically connected to the input terminal, and the second electrode of the nth first transistor is electrically connected to the nth first node;

[0050] The gate of the nth second transistor is electrically connected to the nth output clock signal terminal, the first electrode of the nth second transistor is electrically connected to the nth first node, and the second electrode of the nth second transistor is electrically connected to the first electrode of the nth third transistor;

[0051] The gate of the nth third transistor is electrically connected to the nth second node, and the second electrode of the nth third transistor is electrically connected to the first voltage terminal;

[0052] a gate of the nth fourth transistor is electrically connected to the nth first node, a first electrode of the nth fourth transistor is electrically connected to the nth control clock signal terminal, and a second electrode of the nth fourth transistor is electrically connected to the nth second node;

[0053] The gate of the nth fifth transistor is electrically connected to the nth control clock signal terminal, the first electrode of the nth fifth transistor is electrically connected to the nth second node, and the second electrode of the nth fifth transistor is electrically connected to the second voltage terminal;

[0054] A first end of the nth first capacitor is electrically connected to the nth first node, and a second end of the nth first capacitor is electrically connected to the nth driving signal output terminal;

[0055] A first end of the nth second capacitor is electrically connected to the nth second node, and a second end of the nth second capacitor is electrically connected to the first voltage end;

[0056] a gate of the nth seventh transistor being electrically connected to the nth second node, a first electrode of the nth seventh transistor being electrically connected to the first voltage terminal, and a second electrode of the nth seventh transistor being electrically connected to the nth driving signal output terminal;

[0057] The gate of the nth eighth transistor is electrically connected to the nth first node, the first electrode of the nth eighth transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth eighth transistor is electrically connected to the nth output clock signal terminal.

[0058] Optionally, the n-th stage driving circuit further includes an n-th sixth transistor;

[0059] The nth first node is electrically connected to the gate of the nth eighth transistor through the nth sixth transistor;

[0060] The gate of the nth sixth transistor is electrically connected to the third voltage terminal, the first electrode of the nth sixth transistor is electrically connected to the nth first node, and the second electrode of the nth sixth transistor is electrically connected to the gate of the nth eighth transistor.

[0061] Optionally, the driving module according to at least one embodiment of the present disclosure further includes a forward scanning control circuit and a reverse scanning control circuit;

[0062] The forward scanning control circuit includes N-1 forward scanning control sub-circuits;

[0063] The hth forward scan control subcircuit is electrically connected to the forward scan control terminal, the drive signal output terminal of the hth stage drive circuit, and the input terminal of the h+1th stage drive circuit, respectively, and is configured to control the communication between the drive signal output terminal of the hth stage drive circuit and the input terminal of the h+1th stage drive circuit under the control of the forward scan control signal provided by the forward scan control terminal; h is a positive integer less than or equal to N-1;

[0064] The hth reverse scan control sub-circuit is electrically connected to the reverse scan control end, the drive signal output end of the N-h+1th level drive circuit and the input end of the Nhth level drive circuit, respectively, and is used to control the connection between the drive signal output end of the N-h+1th level drive circuit and the input end of the Nhth level drive circuit under the control of the reverse scan control signal provided by the reverse scan control end.

[0065] Optionally, the hth forward scan control subcircuit includes an hth forward scan control transistor, and the hth reverse scan control subcircuit includes an hth reverse scan control transistor;

[0066] The gate of the hth forward scan control transistor is electrically connected to the forward scan control terminal, the first electrode of the hth forward scan control transistor is electrically connected to the drive signal output terminal of the hth stage drive circuit, and the second electrode of the hth forward scan control transistor is electrically connected to the input terminal of the h+1th stage drive circuit;

[0067] The gate of the hth reverse scan control transistor is electrically connected to the reverse scan control end, the first electrode of the hth reverse scan control transistor is electrically connected to the drive signal output end of the N-h+1th level drive circuit, and the second electrode of the hth reverse scan control transistor is electrically connected to the input end of the Nh level drive circuit.

[0068] In a second aspect, an embodiment of the present disclosure further provides a driving method, which is applied to the above-mentioned driving module, and the driving method includes:

[0069] The n-stage driving circuit, under the control of the n-th control clock signal and the n-th output clock signal, controls, in the n-th output stage, the n-th output clock signal provided by the n-th output clock signal terminal to be output to the n-stage driving signal output terminal according to the n-th input signal provided by the n-th input terminal;

[0070] The effective voltage duration periods of the driving signals output by the N-level driving circuits do not overlap with each other;

[0071] n is a positive integer less than or equal to N; N is an integer greater than 1.

[0072] In a third aspect, an embodiment of the present disclosure further provides a display device comprising the above-mentioned driving module. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] FIG1 is a structural diagram of an n-th stage driving circuit Sn in a driving module according to at least one embodiment of the present disclosure;

[0074] FIG2 is a structural diagram of a driving module according to at least one embodiment of the present disclosure;

[0075] FIG3 is an operating timing diagram of at least one embodiment of the driving module shown in FIG2 of the present disclosure;

[0076] FIG4 is a structural diagram of a driving module according to at least one embodiment of the present disclosure;

[0077] FIG5A is an operation timing diagram of at least one embodiment of the driving module shown in FIG4 of the present disclosure;

[0078] FIG5B is a timing diagram of the operation of the driving module according to at least one embodiment of the present disclosure;

[0079] FIG5C is a timing diagram of the operation of the driving module according to at least one embodiment of the present disclosure;

[0080] FIG6 is a structural diagram of at least one embodiment of an n-th clock signal providing circuit;

[0081] FIG7 is a circuit diagram of at least one embodiment of an n-th clock signal providing circuit;

[0082] FIG8 is a structural diagram of at least one embodiment of an n-th stage driving circuit;

[0083] FIG9 is a circuit diagram of at least one embodiment of an n-th stage driving circuit;

[0084] FIG10 is a structural diagram of the hth forward scan control subcircuit;

[0085] FIG11 is a structural diagram of the hth reverse scan control subcircuit;

[0086] FIG12 is a structural diagram of a driving module according to at least one embodiment of the present disclosure;

[0087] FIG13 is a structural diagram of a two-stage driving circuit in a driving module according to at least one embodiment of the present disclosure;

[0088] FIG14 is a timing diagram of the operation of at least one embodiment of the driving module shown in FIG4 during forward scanning;

[0089] FIG. 15 is an operation timing diagram of at least one embodiment of the driving module shown in FIG. 4 during reverse scanning. DETAILED DESCRIPTION

[0090] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0091] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0092] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0093] The driving module described in the embodiment of the present disclosure includes N-level driving circuits; N is an integer greater than 1;

[0094] an n-stage driving circuit electrically connected to an n-th input terminal, an n-th control clock signal terminal, an n-th output clock signal terminal, and an n-stage driving signal output terminal, respectively, for controlling, under the control of an n-th control clock signal provided by the n-th control clock signal terminal and an n-th output clock signal provided by the n-th output clock signal terminal, and in accordance with the n-th input signal provided by the n-th input terminal, to output the n-th output clock signal to the n-stage driving signal output terminal in an n-output stage;

[0095] The effective voltage duration periods of the driving signals output by the N-stage driving circuits do not overlap with each other;

[0096] n is a positive integer less than or equal to N.

[0097] In a specific implementation, the driving circuit outputs the driving signal through its driving signal output terminal.

[0098] In the relevant driving module, in the odd-numbered driving circuit, the control clock signal end is electrically connected to the first clock signal line, and the output clock signal end is electrically connected to the second clock signal line; in the even-numbered driving circuit, the control clock signal end is electrically connected to the second clock signal line, and the output clock signal line is electrically connected to the first clock signal line, resulting in that when each level of the driving circuit outputs a double-pulse driving signal, there is an overlapping time period between the effective voltage duration periods of the driving signal output by the odd-numbered driving circuit, and there is an overlapping time period between the effective voltage duration periods of the driving signal output by the even-numbered driving circuit, resulting in that during the overlapping time period, the data line cannot be given the normally required data voltage.

[0099] Based on this, in the driving module described in the embodiment of the present disclosure, by controlling the control clock signal and the output clock signal provided to each level of driving circuit, the effective voltage duration periods of the driving signals output by the N-level driving circuits do not overlap with each other, thereby realizing non-overlapping double-pulse shift timing output.

[0100] In at least one embodiment of the present disclosure, when the transistor controlled by the drive signal is a p-type transistor, the effective voltage duration period of the drive signal is: a period of time during which the potential of the drive signal is continuously at a low voltage;

[0101] When the transistor controlled by the driving signal is an n-type transistor, the effective voltage duration period of the driving signal is: a time period in which the potential of the driving signal continues to be a high voltage.

[0102] As shown in FIG1 , the n-stage driving circuit Sn is electrically connected to the n-th input terminal In, the n-th control clock signal terminal CK1n, the n-th output clock signal terminal CK2n, and the n-stage driving signal output terminal OTn, respectively, and is configured to, under the control of the n-th control clock signal provided by the n-th control clock signal terminal CK1n and the n-th output clock signal provided by the n-th output clock signal terminal CK2n, control the n-th output clock signal provided by the n-th output clock signal terminal CK2n to be output to the n-stage driving signal output terminal OTn in the n-output stage according to the n-th input signal provided by the n-th input terminal In;

[0103] n is a positive integer less than or equal to N.

[0104] Optionally, the driving module includes at least three clock signal lines;

[0105] One of the at least three clock signal lines is electrically connected to the nth control clock signal terminal, and another one of the at least three clock signal lines is electrically connected to the nth output clock signal terminal.

[0106] In a specific implementation, the driving module may include at least three clock signal lines, the nth control clock signal terminal may be electrically connected to one of the at least three clock signal lines, and the nth output clock signal terminal may be electrically connected to another of the at least three clock signal lines.

[0107] In at least one embodiment of the present disclosure, the driving module includes three clock signal lines;

[0108] The 3a-2 control clock signal terminal is electrically connected to the first clock signal line, and the 3a-2 output clock signal terminal is electrically connected to the third clock signal line;

[0109] The 3a-1 control clock signal terminal is electrically connected to the third clock signal line, and the 3a-1 output clock signal terminal is electrically connected to the second clock signal line;

[0110] The 3a control clock signal terminal is electrically connected to the second clock signal line, and the 3a output clock signal line is electrically connected to the first clock signal line;

[0111] a is a positive integer.

[0112] For example, when the driving module includes three clock signal lines, the first control clock signal terminal can be electrically connected to the first clock signal line, the first output clock signal line can be electrically connected to the third clock signal line, the second control clock signal terminal can be electrically connected to the third clock signal line, the second output clock signal line can be electrically connected to the second clock signal line, the third control clock signal terminal can be electrically connected to the second clock signal line, the third output clock signal line can be electrically connected to the first clock signal line, and so on, but not limited to this.

[0113] Optionally, the first clock signal line is used to provide a first clock signal, the second clock signal line is used to provide a second clock signal, and the third clock signal line is used to provide a third clock signal;

[0114] The effective voltage duration period of the first clock signal, the effective voltage duration period of the second clock signal, and the effective voltage duration period of the third clock signal do not overlap with each other.

[0115] In at least one embodiment of the present disclosure, the second clock signal is delayed by a first predetermined time compared to the first clock signal, and the third clock signal is delayed by a second predetermined time compared to the second clock signal.

[0116] During specific implementation, the interval time between the double pulses of the two clock signals depends on circuit requirements and can be modified; the smaller the interval time, the fewer clock signals are required.

[0117] Optionally, at least one effective voltage duration segment of the first clock signal, at least one effective voltage duration segment of the second clock signal, and at least one effective voltage duration segment of the third clock signal are included in the effective voltage duration segment of the start signal connected to the input end of the first-stage driving circuit in the driving module.

[0118] In the driving module described in at least one embodiment of the present disclosure, the input end of the first-stage driving circuit is connected to the start signal, and the m-th input end included in the m-th-stage driving circuit can be electrically connected to the driving signal output end of the adjacent previous-stage driving circuit, but is not limited thereto.

[0119] In at least one embodiment of the present disclosure, the effective voltage duration period of the clock signal may refer to a time period in which the potential of the clock signal continues to be an effective voltage.

[0120] Optionally, when the transistor controlled by the driving signal is a p-type transistor, the effective voltage may be a low voltage; and when the transistor controlled by the driving signal is an n-type transistor, the effective voltage may be a high voltage.

[0121] As shown in FIG2 , in at least one embodiment of the present disclosure, the first-stage driving circuit included in the driving module is labeled S1 , the second-stage driving circuit included in the driving module is labeled S2 , and the third-stage driving circuit included in the driving module is labeled S3 ;

[0122] The input end of S1 is connected to the start signal SI;

[0123] The control clock signal terminal of S1 is electrically connected to the first clock signal line SCK1, and the output clock signal terminal of S1 is electrically connected to the third clock signal line SCK3;

[0124] The control clock signal terminal of S2 is electrically connected to the third clock signal line SCK3, and the output clock signal terminal of S2 is electrically connected to the second clock signal line SCK2;

[0125] The control clock signal terminal of S3 is electrically connected to the second clock signal line SCK2, and the output clock signal line of S3 is electrically connected to the first clock signal line SCK1;

[0126] The first clock signal line SCK1 is used to provide a first clock signal, the second clock signal line SCK2 is used to provide a second clock signal, and the third clock signal line SCK3 is used to provide a third clock signal;

[0127] The drive signal output terminal of S1 is marked as OT1, the drive signal output terminal of S2 is marked as OT2, and the drive signal output terminal of S3 is marked as OT3;

[0128] The input end of S2 is electrically connected to OT1, and the input end of S3 is electrically connected to OT2.

[0129] FIG. 3 is an operation timing diagram of at least one embodiment of the driving module shown in FIG. 2 .

[0130] As shown in FIG3 , the potential of the first clock signal provided by SCK1 is continuously at a low voltage for a time period T, the potential of the second clock signal provided by SCK2 is continuously at a low voltage for a time period T, and the potential of the third clock signal provided by SCK3 is continuously at a low voltage for a time period T;

[0131] The time interval between two pulses of the first clock signal is 7T, the time interval between two pulses of the second clock signal is 7T, and the time interval between two pulses of the third clock signal is 7T;

[0132] The second clock signal is delayed by 2T compared to the first clock signal, and the third clock signal is delayed by 2T compared to the second clock signal.

[0133] In at least one embodiment of the present disclosure, 2T can be the line period, and the time interval between the second clock signal and the first clock signal is not necessarily 2T, and the time interval between the third clock signal and the second clock signal is not necessarily 2T, as long as the line period of the required frequency is guaranteed.

[0134] Optionally, the driving module may include eight clock signal lines;

[0135] The 8f-7 control clock signal terminal is electrically connected to the first clock signal line, and the 8f-7 output clock signal terminal is electrically connected to the fourth clock signal line;

[0136] The 8f-6 control clock signal terminal is electrically connected to the fourth clock signal line, and the 8f-6 output clock signal terminal is electrically connected to the seventh clock signal line;

[0137] The 8f-5 control clock signal terminal is electrically connected to the seventh clock signal line, and the 8f-5 output clock signal terminal is electrically connected to the second clock signal line;

[0138] The 8f-4th control clock signal terminal is electrically connected to the second clock signal line, and the 8f-4th output clock signal terminal is electrically connected to the fifth clock signal line;

[0139] The 8f-3 control clock signal terminal is electrically connected to the fifth clock signal line, and the 8f-3 output clock signal terminal is electrically connected to the eighth clock signal line;

[0140] The 8f-2 control clock signal terminal is electrically connected to the eighth clock signal line, and the 8f-2 output clock signal terminal is electrically connected to the third clock signal line;

[0141] The 8f-1 th control clock signal terminal is electrically connected to the third clock signal line, and the 8f-1 th output clock signal terminal is electrically connected to the sixth clock signal line;

[0142] The 8f-th control clock signal terminal is electrically connected to the sixth clock signal line, and the 8f-1-th output clock signal terminal is electrically connected to the first clock signal line;

[0143] f is a positive integer.

[0144] In at least one embodiment of the present disclosure, the effective voltage duration period of the first clock signal provided by the first clock signal line, the effective voltage duration period of the second clock signal provided by the second clock signal line, the effective voltage duration period of the second clock signal provided by the third clock signal line, the effective voltage duration period of the fourth clock signal provided by the fourth clock signal line, the effective voltage duration period of the fifth clock signal provided by the fifth clock signal line, the effective voltage duration period of the sixth clock signal provided by the sixth clock signal line, the effective voltage duration period of the seventh clock signal provided by the seventh clock signal line, and the effective voltage duration period of the eighth clock signal provided by the eighth clock signal line do not overlap with each other.

[0145] As shown in FIG4 , the first-stage driving circuit included in the driving module is labeled S1, the second-stage driving circuit included in the driving module is labeled S2, the third-stage driving circuit included in the driving module is labeled S3, the fourth-stage driving circuit included in the driving module is labeled S4, the fifth-stage driving circuit included in the driving module is labeled S5, the sixth-stage driving circuit included in the driving module is labeled S6, the seventh-stage driving circuit included in the driving module is labeled S7, the eighth-stage driving circuit included in the driving module is labeled S8, and the ninth-stage driving circuit included in the driving module is labeled S9;

[0146] The input end of S1 is connected to the start signal SI;

[0147] The control clock signal terminal of S1 is electrically connected to the first clock signal line SCK1, and the output clock signal terminal of S1 is electrically connected to the fourth clock signal line SCK4;

[0148] The control clock signal terminal of S2 is electrically connected to the fourth clock signal line SCK4, and the output clock signal terminal of S2 is electrically connected to the seventh clock signal line SCK7;

[0149] The control clock signal terminal of S3 is electrically connected to the seventh clock signal line SCK7, and the output clock signal terminal of S3 is electrically connected to the second clock signal line SCK2;

[0150] The control clock signal terminal of S4 is electrically connected to the second clock signal line SCK2, and the output clock signal terminal of S4 is electrically connected to the fifth clock signal line SCK5;

[0151] The control clock signal terminal of S5 is electrically connected to the fifth clock signal line SCK5, and the output clock signal terminal of S5 is electrically connected to the eighth clock signal line SCK8;

[0152] The control clock signal terminal of S6 is electrically connected to the eighth clock signal line SCK8, and the output clock signal terminal of S6 is electrically connected to the third clock signal line SCK3;

[0153] The control clock signal terminal of S7 is electrically connected to the third clock signal line SCK3, and the output clock signal terminal of S7 is electrically connected to the sixth clock signal line SCK6;

[0154] The control clock signal terminal of S8 is electrically connected to the sixth clock signal line SCK6, and the output clock signal terminal of S7 is electrically connected to the first clock signal line SCK1;

[0155] The control clock signal terminal of S9 is electrically connected to the first clock signal line SCK1, and the output clock signal terminal of S9 is electrically connected to the fourth clock signal line SCK4;

[0156] The first clock signal line SCK1 is used to provide a first clock signal, the second clock signal line SCK2 is used to provide a second clock signal, the third clock signal line SCK3 is used to provide a third clock signal, the fourth clock signal line SCK4 is used to provide a fourth clock signal, the fifth clock signal line SCK5 is used to provide a fifth clock signal, the sixth clock signal line SCK6 is used to provide a sixth clock signal, the seventh clock signal line SCK7 is used to provide a seventh clock signal, and the eighth clock signal line SCK8 is used to provide an eighth clock signal;

[0157] The drive signal output terminal of S1 is marked as OT1, the drive signal output terminal of S2 is marked as OT2, the drive signal output terminal of S3 is marked as OT3, the drive signal output terminal of S4 is marked as OT4, the drive signal output terminal of S5 is marked as OT5, the drive signal output terminal of S6 is marked as OT6, the drive signal output terminal of S7 is marked as OT7, the drive signal output terminal of S8 is marked as OT8, and the drive signal output terminal of S9 is marked as OT9;

[0158] The input end of S2 is electrically connected to OT1, the input end of S3 is electrically connected to OT2, the input end of S4 is electrically connected to OT3, the input end of S5 is electrically connected to OT4, the input end of S6 is electrically connected to OT5, the input end of S7 is electrically connected to OT6, the input end of S8 is electrically connected to OT7, and the input end of S9 is electrically connected to OT8.

[0159] FIG. 5A is a timing diagram of the operation of the driving module shown in FIG. 4 .

[0160] As shown in FIG5A , the time during which the potential of each clock signal remains at a low voltage is a time period T, and the time interval between two pulses of each clock signal is 7T;

[0161] The second clock signal is delayed by 1T compared to the first clock signal, the third clock signal is delayed by 1T compared to the second clock signal, the fourth clock signal is delayed by 1T compared to the third clock signal, the fifth clock signal is delayed by 1T compared to the fourth clock signal, the sixth clock signal is delayed by 1T compared to the fifth clock signal, the seventh clock signal is delayed by 1T compared to the sixth clock signal, and the eighth clock signal is delayed by 1T compared to the seventh clock signal;

[0162] There is no overlap between the low voltage duration period of the first clock signal, the low voltage duration period of the second clock signal, the low voltage duration period of the third clock signal, the low voltage duration period of the fourth clock signal, the low voltage duration period of the fifth clock signal, the low voltage duration period of the sixth clock signal, the low voltage duration period of the seventh clock signal and the low voltage duration period of the eighth clock signal.

[0163] As shown in Figure 5A, two low voltage duration segments of the first clock signal, one low voltage duration segment of the second clock signal, one low voltage duration segment of the third clock signal, one low voltage duration segment of the fourth clock signal, one low voltage duration segment of the fifth clock signal, one low voltage duration segment of the sixth clock signal, one low voltage duration segment of the seventh clock signal and one low voltage duration segment of the eighth clock signal are included in the low voltage duration segment of the start signal SI.

[0164] In at least one embodiment of the present disclosure, the number of clock signals between the clock signal connected to the control clock signal terminal of the driving circuit and the clock signal connected to the output clock signal terminal of the driving circuit depends on the refresh frequency of the display area. In at least one embodiment shown in Figure 5A, 1T can be 1.37μs, so when SCK1 and SCK4 are selected as the control clock signal and output clock signal of the first driving circuit, the time interval between the driving signals output by the two adjacent driving circuits is 4.11μs. When the display area has a resolution of 4k, a refresh frequency of 60Hz can be achieved. Since the self-discharge time required by the driving circuit is 9μs to 12μs, the interval time between the two pulses of the clock signal is selected to be 7T.

[0165] In at least one embodiment of the present disclosure, when the driving module includes four clock signal lines,

[0166] The control clock signal terminal of the first-stage driving circuit may be electrically connected to the first clock signal line, and the output clock signal terminal of the first-stage driving circuit may be electrically connected to the fourth clock signal line;

[0167] The control clock signal terminal of the second-stage driving circuit may be electrically connected to the fourth clock signal line, and the output clock signal terminal of the second-stage driving circuit may be electrically connected to the third clock signal line;

[0168] The control clock signal terminal of the third-stage driving circuit may be electrically connected to the third clock signal line, and the output clock signal terminal of the second-stage driving circuit may be electrically connected to the second clock signal line;

[0169] The control clock signal terminal of the fourth-stage driving circuit may be electrically connected to the second clock signal line, and the output clock signal terminal of the second-stage driving circuit may be electrically connected to the first clock signal line;

[0170] And so on.

[0171] That is, when the driving module includes four clock signal lines,

[0172] The control clock signal terminal of the 4a-3 stage driving circuit is electrically connected to the first clock signal line, and the output clock signal terminal of the 4a-3 stage driving circuit is electrically connected to the fourth clock signal line;

[0173] The control clock signal terminal of the 4a-2 stage driving circuit is electrically connected to the fourth clock signal line, and the output clock signal terminal of the 4a-2 stage driving circuit is electrically connected to the third clock signal line;

[0174] The control clock signal terminal of the 4a-1 stage driving circuit is electrically connected to the third clock signal line, and the output clock signal terminal of the 4a-1 stage driving circuit is electrically connected to the second clock signal line;

[0175] The control clock signal terminal of the 4a-level driving circuit is electrically connected to the second clock signal line, and the output clock signal terminal of the 4a-level driving circuit is electrically connected to the first clock signal line;

[0176] a is a positive integer.

[0177] When the driving module includes four clock signal lines: a first clock signal line SCK1, a second clock signal line SCK2, a third clock signal line SCK3 and a fourth clock signal line SCK4, the waveforms of the driving signal output by the driving signal output terminal OT1 of the first-stage driving circuit, the driving signal output by the driving signal output terminal OT2 of the second-stage driving circuit, the driving signal output by the driving signal output terminal OT3 of the third-stage driving circuit and the driving signal output by the driving signal output terminal OT4 of the fourth-stage driving circuit are shown in FIG5B .

[0178] In at least one embodiment of the present disclosure, when the driving module includes six clock signal lines,

[0179] The control clock signal terminal of the first-stage driving circuit may be electrically connected to the first clock signal line, and the output clock signal terminal of the first-stage driving circuit may be electrically connected to the sixth clock signal line;

[0180] The control clock signal terminal of the second-stage driving circuit may be electrically connected to the sixth clock signal line, and the output clock signal terminal of the second-stage driving circuit may be electrically connected to the fifth clock signal line;

[0181] The control clock signal terminal of the third-stage driving circuit may be electrically connected to the fifth clock signal line, and the output clock signal terminal of the third-stage driving circuit may be electrically connected to the fourth clock signal line;

[0182] The control clock signal terminal of the fourth-stage driving circuit may be electrically connected to the fourth clock signal line, and the output clock signal terminal of the fourth-stage driving circuit may be electrically connected to the third clock signal line;

[0183] The control clock signal terminal of the fifth-stage driving circuit may be electrically connected to the third clock signal line, and the output clock signal terminal of the fifth-stage driving circuit may be electrically connected to the second clock signal line;

[0184] The control clock signal terminal of the sixth-stage driving circuit may be electrically connected to the second clock signal line, and the output clock signal terminal of the sixth-stage driving circuit may be electrically connected to the first clock signal line;

[0185] And so on.

[0186] That is, when the driving module includes six clock signal lines,

[0187] The control clock signal terminal of the 6a-5 stage driving circuit is electrically connected to the first clock signal line, and the output clock signal terminal of the 6a-5 stage driving circuit is electrically connected to the sixth clock signal line;

[0188] The control clock signal terminal of the 6a-4 stage driving circuit is electrically connected to the sixth clock signal line, and the output clock signal terminal of the 6a-4 stage driving circuit is electrically connected to the fifth clock signal line;

[0189] The control clock signal terminal of the 6a-3 stage driving circuit is electrically connected to the fifth clock signal line, and the output clock signal terminal of the 6a-3 stage driving circuit is electrically connected to the fourth clock signal line;

[0190] The control clock signal terminal of the 6a-2 stage driving circuit is electrically connected to the fourth clock signal line, and the output clock signal terminal of the 6a-2 stage driving circuit is electrically connected to the third clock signal line;

[0191] The control clock signal terminal of the 6a-1 stage driving circuit is electrically connected to the third clock signal line, and the output clock signal terminal of the 6a-1 stage driving circuit is electrically connected to the second clock signal line;

[0192] The control clock signal terminal of the 6a-level driving circuit is electrically connected to the second clock signal line, and the output clock signal terminal of the 6a-level driving circuit is electrically connected to the first clock signal line;

[0193] a is a positive integer.

[0194] When the driving module includes six clock signal lines: a first clock signal line SCK1, a second clock signal line SCK2, a third clock signal line SCK3, a fourth clock signal line SCK4, a fifth clock signal line SCK5 and a sixth clock signal line SCK6, the waveforms of the driving signal output by the driving signal output terminal OT1 of the first-stage driving circuit, the driving signal output by the driving signal output terminal OT2 of the second-stage driving circuit, the driving signal output by the driving signal output terminal OT3 of the third-stage driving circuit, the driving signal output by the driving signal output terminal OT4 of the fourth-stage driving circuit, the driving signal output by the driving signal output terminal OT5 of the fifth-stage driving circuit and the driving signal output by the driving signal output terminal OT6 of the sixth-stage driving circuit are shown in FIG5C .

[0195] In FIG. 5B and FIG. 5C , the signal labeled SI is a start signal.

[0196] In at least one embodiment of the present disclosure, when the input terminal of the n+1th stage driving circuit is electrically connected to the driving signal output terminal of the nth stage driving circuit,

[0197] The output clock signal terminal of the n-th stage driving circuit and the control clock signal terminal of the (n+1)-th stage driving circuit can be connected to the same clock signal.

[0198] In at least one embodiment of the driving module shown in Figure 4, eight clock signals are circulated as the control clock signals and output clock signals of the driving circuits of each stage. Therefore, the control clock signals and output clock signals connected to the driving circuits of each stage during forward scanning and the control clock signals and output clock signals connected to the driving circuits of each stage during reverse scanning are different.

[0199] For example, when the driving module includes eight clock signal lines and the driving module includes an 8b-level driving circuit (b is a positive integer),

[0200] When the driving module is in a forward scanning state, the control clock signal terminal of the 8b-level driving circuit of the driving module is electrically connected to the sixth clock signal line, and the output clock signal terminal of the 8b-level driving circuit is electrically connected to the first clock signal line;

[0201] When the driving module is in the reverse scanning state, the control clock signal terminal of the 8b-level driving circuit of the driving module is electrically connected to the first clock signal line, and the output clock signal terminal of the 8b-level driving circuit is electrically connected to the fourth clock signal line.

[0202] In order to solve the above problems, the driving module described in at least one embodiment of the present disclosure also includes N clock signal providing circuits, and the nth clock signal providing circuit provides corresponding control clock signals and corresponding output clock signals to the driving circuit during forward scanning and reverse scanning respectively.

[0203] In at least one embodiment of the present disclosure, the driving module further includes N clock signal providing circuits;

[0204] As shown in FIG6 , at least one embodiment of the nth clock signal providing circuit includes an nth forward scanning clock providing circuit 61 and an nth reverse scanning clock providing circuit 62 ;

[0205] The nth forward scan clock supply circuit 61 is electrically connected to the forward scan control terminal FS, the first forward scan clock signal terminal FSCK1, the second forward scan clock signal terminal FSCK2, the nth control clock signal terminal CK1n, and the nth output clock signal terminal CK2n, respectively, and is used to control the connection or disconnection between the first forward scan clock signal terminal FSCK1 and the nth control clock signal terminal CK1n, and the connection or disconnection between the second forward scan clock signal terminal FSCK2 and the nth output clock signal terminal CK2n, under the control of the forward scan control signal provided by the forward scan control terminal FS.

[0206] The nth reverse scan clock providing circuit 62 is electrically connected to the reverse scan control terminal BS, the first reverse scan clock signal terminal BSCK1, the second reverse scan clock signal terminal BSCK2, the nth control clock signal terminal CK1n and the nth output clock signal terminal CK2n, respectively, and is used to control the connection or disconnection between the first reverse scan clock signal terminal BSCK1 and the nth control clock signal terminal CK1n, and control the connection or disconnection between the second reverse scan clock signal terminal BSCK2 and the nth output clock signal terminal CK2n under the control of the reverse scan control signal provided by the reverse scan control terminal BS.

[0207] Optionally, the nth forward scanning clock supply circuit includes a first supply transistor and a second supply transistor, and the nth reverse scanning clock supply circuit includes a third supply transistor and a fourth supply transistor;

[0208] The gate of the first providing transistor is electrically connected to the forward scanning control terminal, the first electrode of the first providing transistor is electrically connected to the first forward scanning clock signal terminal, and the second electrode of the first providing transistor is electrically connected to the nth control clock signal terminal;

[0209] The gate of the second providing transistor is electrically connected to the forward scan control terminal, the first electrode of the second providing transistor is electrically connected to the second forward scan clock signal terminal, and the second electrode of the second providing transistor is electrically connected to the nth output clock signal terminal;

[0210] The gate of the third providing transistor is electrically connected to the reverse scan control terminal, the first electrode of the third providing transistor is electrically connected to the first reverse scan clock signal terminal, and the second electrode of the third providing transistor is electrically connected to the nth control clock signal terminal;

[0211] The gate of the fourth providing transistor is electrically connected to the reverse scan control terminal, the first electrode of the fourth providing transistor is electrically connected to the second reverse scan clock signal terminal, and the second electrode of the fourth providing transistor is electrically connected to the nth output clock signal terminal;

[0212] The first providing transistor and the second providing transistor are both p-type transistors; or, the first providing transistor and the second providing transistor are both n-type transistors;

[0213] The third supply transistor and the fourth supply transistor are both p-type transistors; or, the third supply transistor and the fourth supply transistor are both n-type transistors.

[0214] As shown in FIG7 , based on at least one embodiment of the n-th clock signal providing circuit shown in FIG6 ,

[0215] The nth forward scanning clock supply circuit includes a first supply transistor T1 and a second supply transistor T2, and the nth reverse scanning clock supply circuit includes a third supply transistor T3 and a fourth supply transistor T4;

[0216] The gate of the first supply transistor T1 is electrically connected to the forward scan control terminal FS, the source of the first supply transistor T1 is electrically connected to the first forward scan clock signal terminal FSCK1, and the drain of the first supply transistor T1 is electrically connected to the nth control clock signal terminal CK1n;

[0217] The gate of the second supply transistor T2 is electrically connected to the forward scan control terminal FS, the source of the second supply transistor T2 is electrically connected to the second forward scan clock signal terminal FSCK2, and the drain of the second supply transistor T2 is electrically connected to the nth output clock signal terminal CK2n;

[0218] The gate of the third supply transistor T3 is electrically connected to the reverse scan control terminal BS, the source of the third supply transistor T3 is electrically connected to the first reverse scan clock signal terminal BSCK1, and the drain of the third supply transistor T3 is electrically connected to the nth control clock signal terminal CK1n;

[0219] The gate of the fourth supply transistor T4 is electrically connected to the reverse scan control terminal BS, the source of the fourth supply transistor T4 is electrically connected to the second reverse scan clock signal terminal BSCK2, and the drain of the fourth supply transistor T4 is electrically connected to the nth output clock signal terminal CK2n;

[0220] The first providing transistor and the second providing transistor are both p-type transistors; the third providing transistor and the fourth providing transistor are both p-type transistors

[0221] At least one embodiment of the n-th clock signal providing circuit shown in FIG7 is in operation.

[0222] During forward scanning, FS provides a low voltage signal, BS provides a high voltage signal, T1 and T2 are turned on, FSCK1 is connected to CK1n, and FSCK2 is connected to CK2n.

[0223] During reverse scanning, FS provides a high voltage signal, BS provides a low voltage signal, T3 and T4 are turned on, BSCK1 is connected to CK1n, and BSCK2 is connected to CK2n.

[0224] By adopting the above clock signal supply circuit, each driving circuit can input the corresponding control clock signal and output the clock signal in both forward and reverse scanning states. In particular, the number of clock signals used as cyclic inputs is fixed regardless of forward scanning or reverse scanning.

[0225] The driving module described in at least one embodiment of the present disclosure can realize forward scanning and reverse scanning functions under the premise of achieving non-overlapping double pulse output.

[0226] In at least one embodiment of the present disclosure, the nth stage driving circuit includes an nth input circuit, an nth first node control circuit, an nth second node control circuit, an nth first energy storage circuit, an nth second energy storage circuit, and an nth output circuit;

[0227] The nth input circuit is electrically connected to the nth input terminal, the nth first node and the nth control clock signal terminal respectively, and is used to control the connection between the nth input terminal and the nth first node under the control of the nth control clock signal;

[0228] The nth first node control circuit is electrically connected to the nth first node, the nth output clock signal terminal, the nth second node, and the first voltage terminal, respectively, and is configured to control the connection between the nth first node and the first voltage terminal under the control of the nth output clock signal provided by the nth output clock signal terminal and the potential of the nth second node;

[0229] The nth second node control circuit is electrically connected to the nth control clock signal terminal, the nth first node, and the second voltage terminal, respectively, and is configured to control the connection between the nth second node and the second voltage terminal under the control of the nth control clock signal, and control the connection between the nth second node and the nth control clock signal terminal under the control of the potential of the nth first node;

[0230] The nth first energy storage circuit is electrically connected to the nth first node and the nth driving signal output terminal respectively, and is used for storing electric energy;

[0231] The nth second energy storage circuit is electrically connected to the nth second node, and is used to maintain the potential of the nth second node;

[0232] The nth output circuit is electrically connected to the nth first node, the nth second node, the first voltage terminal, the nth output clock signal terminal and the nth drive signal output terminal, respectively, and is used to control the connection between the nth drive signal output terminal and the nth output clock signal terminal under the control of the potential of the nth first node, and to control the connection between the nth drive signal output terminal and the first voltage terminal under the control of the potential of the nth second node.

[0233] In a specific implementation, the n-th stage driving circuit may include an n-th input circuit, an n-th first node control circuit, an n-th second node control circuit, an n-th first energy storage circuit, an n-th second energy storage circuit, and an n-th output circuit; the n-th input circuit controls the connection between the n-th input terminal and the n-th first node under the control of the n-th control clock signal; the n-th first node control circuit controls the connection between the n-th first node and the first voltage terminal under the control of the n-th output clock signal and the potential of the n-th second node; the n-th second node control circuit controls the connection between the n-th second node and the second voltage terminal under the control of the n-th control clock signal, and controls the connection between the n-th second node and the n-th control clock signal terminal under the control of the potential of the n-th first node; the n-th output circuit controls the connection between the n-th driving signal output terminal and the n-th output clock signal terminal under the control of the potential of the n-th first node, and controls the connection between the n-th driving signal output terminal and the first voltage terminal under the control of the potential of the n-th second node.

[0234] Optionally, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal.

[0235] As shown in FIG8 , at least one embodiment of the n-th stage driving circuit may include an n-th input circuit 81 , an n-th first node control circuit 82 , an n-th second node control circuit 83 , an n-th first energy storage circuit 84 , an n-th second energy storage circuit 85 , and an n-th output circuit 86 ;

[0236] The nth input circuit 81 is electrically connected to the nth input terminal In, the nth first node Vb and the nth control clock signal terminal CK1n, respectively, and is used to control the connection between the nth input terminal In and the nth first node Vb under the control of the nth control clock signal;

[0237] The nth first node control circuit 82 is electrically connected to the nth first node Vb, the nth output clock signal terminal CK2n, the nth second node Vc, and the first voltage terminal V1, respectively, and is configured to control the connection between the nth first node Vb and the first voltage terminal V1 under the control of the nth output clock signal provided by the nth output clock signal terminal CK2n and the potential of the nth second node Vc;

[0238] The nth second node control circuit 83 is electrically connected to the nth control clock signal terminal CK1n, the nth first node Vb, the nth second node Vc, and the second voltage terminal V2, respectively, and is configured to control the communication between the nth second node Vc and the second voltage terminal V2 under the control of the nth control clock signal, and control the communication between the nth second node Vc and the nth control clock signal terminal CK1n under the control of the potential of the nth first node Vb;

[0239] The nth first energy storage circuit 84 is electrically connected to the nth first node Vb and the nth driving signal output terminal OTn, respectively, for storing electric energy;

[0240] The nth second energy storage circuit 85 is electrically connected to the nth second node Vc, and is used to maintain the potential of the nth second node Vc;

[0241] The nth output circuit 86 is electrically connected to the nth first node Vb, the nth second node Vc, the first voltage terminal V1, the nth output clock signal terminal CK2n and the nth drive signal output terminal OTn, respectively, and is used to control the connection between the nth drive signal output terminal OTn and the nth output clock signal terminal CK2n under the control of the potential of the nth first node Vb, and to control the connection between the nth drive signal output terminal OTn and the first voltage terminal V1 under the control of the potential of the nth second node Vc.

[0242] Optionally, the input circuit includes an nth first transistor, the nth first node control circuit includes an nth second transistor and an nth third transistor, the nth second node control circuit includes an nth fourth transistor and an nth fifth transistor, the nth output circuit includes an nth seventh transistor and an nth eighth transistor, the nth first energy storage circuit includes an nth first capacitor, and the nth second energy storage circuit includes an nth second capacitor;

[0243] The gate of the nth first transistor is electrically connected to the nth control clock signal terminal, the first electrode of the nth first transistor is electrically connected to the nth input terminal, and the second electrode of the nth first transistor is electrically connected to the nth first node;

[0244] The gate of the nth second transistor is electrically connected to the nth output clock signal terminal, the first electrode of the nth second transistor is electrically connected to the nth first node, and the second electrode of the nth second transistor is electrically connected to the first electrode of the nth third transistor;

[0245] The gate of the nth third transistor is electrically connected to the nth second node, and the second electrode of the nth third transistor is electrically connected to the first voltage terminal;

[0246] A gate of the nth fourth transistor is electrically connected to the nth first node, a first electrode of the nth fourth transistor is electrically connected to the nth control clock signal terminal, and a second electrode of the nth fourth transistor is electrically connected to the nth second node;

[0247] The gate of the nth fifth transistor is electrically connected to the nth control clock signal terminal, the first electrode of the nth fifth transistor is electrically connected to the nth second node, and the second electrode of the nth fifth transistor is electrically connected to the second voltage terminal;

[0248] A first end of the nth first capacitor is electrically connected to the nth first node, and a second end of the nth first capacitor is electrically connected to the nth driving signal output terminal;

[0249] A first end of the nth second capacitor is electrically connected to the nth second node, and a second end of the nth second capacitor is electrically connected to the first voltage end;

[0250] a gate of the nth seventh transistor being electrically connected to the nth second node, a first electrode of the nth seventh transistor being electrically connected to the first voltage terminal, and a second electrode of the nth seventh transistor being electrically connected to the nth driving signal output terminal;

[0251] The gate of the nth eighth transistor is electrically connected to the nth first node, the first electrode of the nth eighth transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth eighth transistor is electrically connected to the nth output clock signal terminal.

[0252] Optionally, the n-th stage driving circuit further includes an n-th sixth transistor;

[0253] The nth first node is electrically connected to the gate of the nth eighth transistor through the nth sixth transistor;

[0254] The gate of the nth sixth transistor is electrically connected to the third voltage terminal, the first electrode of the nth sixth transistor is electrically connected to the nth first node, and the second electrode of the nth sixth transistor is electrically connected to the gate of the nth eighth transistor.

[0255] In a specific implementation, when the nth sixth transistor is a p-type transistor, the third voltage end may be a low voltage end, but is not limited thereto.

[0256] As shown in FIG9 , based on at least one embodiment of the n-th stage driving circuit shown in FIG8 , the input circuit includes an n-th first transistor M1, the n-th first node control circuit includes an n-th second transistor M2 and an n-th third transistor M3, the n-th second node control circuit includes an n-th fourth transistor M4 and an n-th fifth transistor M5, the n-th output circuit includes an n-th seventh transistor M7 and an n-th eighth transistor M8, the n-th first energy storage circuit includes an n-th first capacitor C1, and the n-th second energy storage circuit includes an n-th second capacitor C2;

[0257] The gate of the nth first transistor M1 is electrically connected to the nth control clock signal terminal CK1n, the source of the nth first transistor M1 is electrically connected to the nth input terminal In, and the drain of the nth first transistor M1 is electrically connected to the nth first node Vb;

[0258] The gate of the nth second transistor M2 is electrically connected to the nth output clock signal terminal CK2n, the source of the nth second transistor M2 is electrically connected to the nth first node Vb, and the drain of the nth second transistor M2 is electrically connected to the source of the nth third transistor M3;

[0259] The gate of the nth third transistor M3 is electrically connected to the nth second node Vc, and the drain of the nth third transistor M3 is electrically connected to the high voltage terminal VH;

[0260] The gate of the nth fourth transistor M4 is electrically connected to the nth first node Vb, the source of the nth fourth transistor M4 is electrically connected to the nth control clock signal terminal CK1n, and the drain of the nth fourth transistor M4 is electrically connected to the nth second node Vc;

[0261] The gate of the nth fifth transistor M5 is electrically connected to the nth control clock signal terminal CK1n, the source of the nth fifth transistor M5 is electrically connected to the nth second node Vc, and the drain of the nth fifth transistor M5 is electrically connected to the low voltage terminal VL;

[0262] A first end of the nth first capacitor C1 is electrically connected to the nth first node Vb, and a second end of the nth first capacitor C1 is electrically connected to the nth driving signal output terminal OTn;

[0263] A first end of the nth second capacitor C2 is electrically connected to the nth second node Vc, and a second end of the nth second capacitor C2 is electrically connected to the high voltage terminal VH;

[0264] The gate of the nth seventh transistor M7 is electrically connected to the nth second node Vc, the source of the nth seventh transistor M7 is electrically connected to the high voltage terminal VH, and the drain of the nth seventh transistor M7 is electrically connected to the nth driving signal output terminal OTn;

[0265] The gate of the nth eighth transistor M8 is electrically connected to the nth first node Vb, the source of the nth eighth transistor M8 is electrically connected to the nth drive signal output terminal OTn, and the drain of the nth eighth transistor M8 is electrically connected to the nth output clock signal terminal CK2n;

[0266] The n-th stage driving circuit further includes an n-th sixth transistor M6;

[0267] The nth first node Vb is electrically connected to the gate of the nth eighth transistor M8 through the nth sixth transistor M6;

[0268] The gate of the nth sixth transistor M6 is electrically connected to the low voltage terminal VL, the source of the nth sixth transistor M6 is electrically connected to the nth first node Vb, and the drain of the nth sixth transistor M6 is electrically connected to the gate of the nth eighth transistor M8.

[0269] In at least one embodiment of the n-th stage driving circuit shown in FIG. 9 , all transistors are p-type transistors.

[0270] When at least one embodiment of the n-th stage driving circuit shown in FIG9 is in operation, when the n-th stage driving circuit is a first-stage driving circuit, the n-th input terminal In is connected to the start signal,

[0271] In the input phase t1, when CK1n provides a low voltage signal and CK2n provides a high voltage signal, M1 is turned on, In provides a low voltage signal, the potential of Vb is low voltage, Vc is connected to CK1n, the potential of Vc is low voltage, M7 and M8 are turned on, and OTn outputs a high voltage signal;

[0272] In the output stage t2, when CK1n provides a high voltage signal and CK2n provides a low voltage signal, the potential of Vb is maintained at a low voltage, M4 is turned on, Vc is connected to CK1n, the potential of Vc is a high voltage, M7 is turned off, M8 is turned on, OTn is connected to CK2n, and OTn outputs a low voltage signal.

[0273] The driving module according to at least one embodiment of the present disclosure further includes a forward scanning control circuit and a reverse scanning control circuit;

[0274] The forward scanning control circuit includes N-1 forward scanning control sub-circuits;

[0275] As shown in FIG10 , the hth forward scan control sub-circuit 101 is electrically connected to the forward scan control terminal FS, the drive signal output terminal OTh of the hth stage drive circuit, and the input terminal Ih+1 of the h+1th stage drive circuit, respectively, and is configured to control the communication between the drive signal output terminal OTh of the hth stage drive circuit and the input terminal Ih+1 of the h+1th stage drive circuit under the control of the forward scan control signal provided by the forward scan control terminal FS; h is a positive integer less than or equal to N-1.

[0276] As shown in Figure 11, the hth reverse scan control sub-circuit 102 is electrically connected to the reverse scan control terminal BS, the drive signal output terminal OTN-h+1 of the N-h+1th stage drive circuit and the input terminal IN-h of the Nh-th stage drive circuit, respectively, and is used to control the connection between the drive signal output terminal OTN-h+1 of the N-h+1th stage drive circuit and the input terminal IN-h of the Nh-th stage drive circuit under the control of the reverse scan control signal provided by the reverse scan control terminal BS.

[0277] Optionally, the hth forward scan control subcircuit includes an hth forward scan control transistor, and the hth reverse scan control subcircuit includes an hth reverse scan control transistor;

[0278] The gate of the hth forward scan control transistor is electrically connected to the forward scan control terminal, the first electrode of the hth forward scan control transistor is electrically connected to the drive signal output terminal of the hth stage drive circuit, and the second electrode of the hth forward scan control transistor is electrically connected to the input terminal of the h+1th stage drive circuit;

[0279] The gate of the hth reverse scan control transistor is electrically connected to the reverse scan control end, the first electrode of the hth reverse scan control transistor is electrically connected to the drive signal output end of the N-h+1th level drive circuit, and the second electrode of the hth reverse scan control transistor is electrically connected to the input end of the Nh level drive circuit.

[0280] As shown in FIG12 , the first-stage driving circuit is labeled S1, the second-stage driving circuit is labeled S2, the N-2-stage driving circuit is labeled SN-2, the N-1-stage driving circuit is labeled SN-1, and the N-stage driving circuit is labeled SN.

[0281] The input terminal of S1 is electrically connected to the first start signal terminal STVF, and the drive signal output terminal of S1 is marked as OT1; the first start signal terminal STVF is used to provide a first start signal;

[0282] The drive signal output terminal of S2 is marked as OT2; the drive signal output terminal of SN-2 is marked as OTN-2, the drive signal output terminal of SN-1 is marked as OTN-1, and the drive signal output terminal of SN is marked as OTN;

[0283] The gate of the first forward scan control transistor M11 is electrically connected to the forward scan control terminal FS, the source of the first forward scan control transistor M11 is electrically connected to the drive signal output terminal OT1 of S1, and the drain of the first forward scan control transistor M11 is electrically connected to the input terminal of the second-stage drive circuit S2;

[0284] The gate of the second forward scan control transistor M12 is electrically connected to the forward scan control terminal FS, the source of the second forward scan control transistor M12 is electrically connected to the drive signal output terminal OT2 of S2, and the drain of the second forward scan control transistor M12 is electrically connected to the input terminal of the third-stage drive circuit;

[0285] The gate of the N-2th forward scan control transistor M1N-2 is electrically connected to the forward scan control terminal FS, the source of the N-2th forward scan control transistor M1N-2 is electrically connected to the drive signal output terminal OTN-2 of the SN-2, and the drain of the N-2th forward scan control transistor M1N-2 is electrically connected to the input terminal of the N-1th stage driving circuit SN-1;

[0286] The gate of the N-1th forward scan control transistor M1N-1 is electrically connected to the forward scan control terminal FS, the source of the N-1th forward scan control transistor M1N-1 is electrically connected to the drive signal output terminal OTN-1 of SN-1, and the drain of the N-1th forward scan control transistor M1N-1 is electrically connected to the input terminal of the N-stage drive circuit SN;

[0287] The input terminal of SN is electrically connected to the second start signal terminal STVB, and the second start signal terminal STVB is used to provide a second start signal;

[0288] The gate of the first reverse scan control transistor M21 is electrically connected to the reverse scan control terminal BS, the source of the first reverse scan control transistor M21 is electrically connected to the drive signal output terminal OTN of the N-th stage drive circuit SN, and the drain of the first reverse scan control transistor M21 is electrically connected to the input terminal of the N-1-th stage drive circuit SN-1;

[0289] The gate of the second reverse scan control transistor M22 is electrically connected to the reverse scan control terminal BS, the source of the second reverse scan control transistor M22 is electrically connected to the drive signal output terminal OTN-1 of the N-1th stage drive circuit SN-1, and the drain of the second reverse scan control transistor M22 is electrically connected to the input terminal of the N-2th stage drive circuit SN-2;

[0290] The gate of the N-2nd reverse scan control transistor M2N-2 is electrically connected to the reverse scan control terminal BS, the source of the N-2nd reverse scan control transistor M2N-2 is electrically connected to the drive signal output terminal of the third-stage drive circuit, and the drain of the N-2nd reverse scan control transistor M2N-2 is electrically connected to the input terminal of the second-stage drive circuit S2;

[0291] The gate of the N-1th reverse scan control transistor M2N-1 is electrically connected to the reverse scan control terminal BS, the source of the N-1th reverse scan control transistor M2N-1 is electrically connected to the drive signal output terminal OT2 of the second-stage drive circuit S2, and the drain of the N-1th reverse scan control transistor M2N-1 is electrically connected to the input terminal of the first-stage drive circuit S1.

[0292] In at least one embodiment shown in FIG. 12 , each forward scan control transistor and each reverse scan control transistor are p-type transistors, but the present invention is not limited thereto.

[0293] At least one embodiment of the driving module shown in FIG12 of the present disclosure is in operation.

[0294] During forward scanning, FS provides a low voltage signal and BS provides a high voltage signal, each forward scanning control transistor is turned on, and each reverse scanning control transistor is turned off;

[0295] During reverse scanning, FS provides a high voltage signal and BS provides a low voltage signal, each reverse scanning control transistor is turned on, and each forward scanning control transistor is turned off.

[0296] In FIG13 , the third-stage driving circuit is labeled S3, and the fourth-stage driving circuit is labeled S4;

[0297] The first forward scanning clock signal terminal FSCK1 of the third clock signal providing circuit P3 is electrically connected to the seventh clock signal line SCK7, and the second forward scanning clock signal terminal FSCK2 of the third clock signal providing circuit P3 is electrically connected to the second clock signal line SCK2;

[0298] The first reverse scan clock signal terminal BSCK1 of the third clock signal providing circuit P3 is electrically connected to the fourth clock signal line SCK4, and the second reverse scan clock signal terminal BSCK2 of the third clock signal providing circuit P3 is electrically connected to the seventh clock signal line SCK7;

[0299] The first forward scanning clock signal terminal FSCK1 of the fourth clock signal providing circuit P4 is electrically connected to the second clock signal line SCK2, and the second forward scanning clock signal terminal FSCK2 of the fourth clock signal providing circuit P4 is electrically connected to the fifth clock signal line SCK5;

[0300] The first reverse scanning clock signal terminal BSCK1 of the fourth clock signal providing circuit P4 is electrically connected to the first clock signal line SCK1, and the second reverse scanning clock signal terminal BSCK2 of the fourth clock signal providing circuit P4 is electrically connected to the fourth clock signal line SCK4;

[0301] The control clock signal terminal of S3 is electrically connected to the third control clock signal terminal CK13 of P3, and the output clock signal terminal of S3 is electrically connected to the third output clock signal terminal CK23 of P3;

[0302] The control clock signal terminal of S4 is electrically connected to the fourth control clock signal terminal CK14 of P4, and the output clock signal terminal of S4 is electrically connected to the fourth output clock signal terminal CK24 of P4;

[0303] The gate of the second forward scan control transistor M12 is electrically connected to the forward scan control terminal FS, the source of the second forward scan control transistor M12 is electrically connected to the drive signal output terminal of the second-stage drive circuit, and the drain of the second forward scan control transistor M12 is electrically connected to the input terminal of the third-stage drive circuit S3;

[0304] The gate of the third forward scan control transistor M13 is electrically connected to the forward scan control terminal FS, the source of the third forward scan control transistor M13 is electrically connected to the drive signal output terminal OT3 of the third-stage drive circuit, and the drain of the third forward scan control transistor M13 is electrically connected to the input terminal of the fourth-stage drive circuit S4;

[0305] The gate of the fourth forward scan control transistor M14 is electrically connected to the forward scan control terminal FS, the source of the fourth forward scan control transistor M14 is electrically connected to the drive signal output terminal OT4 of the fourth-stage drive circuit, and the drain of the fourth forward scan control transistor M14 is electrically connected to the input terminal of the fifth-stage drive circuit;

[0306] The gate of the N-4th reverse scan control transistor M2N-4 is electrically connected to the reverse scan control terminal BS, the source of the N-4th reverse scan control transistor M2N-4 is electrically connected to the drive signal output terminal of the fifth-stage drive circuit, and the drain of the N-4th reverse scan control transistor M2N-4 is electrically connected to the input terminal of the fourth-stage drive circuit S4;

[0307] The gate of the N-3rd reverse scan control transistor M2N-3 is electrically connected to the reverse scan control terminal BS, the source of the N-3rd reverse scan control transistor M2N-3 is electrically connected to the drive signal output terminal OT4 of the fourth-stage drive circuit S4, and the drain of the N-3rd reverse scan control transistor M2N-3 is electrically connected to the input terminal of the third-stage drive circuit S3.

[0308] In FIG13 , the input terminal of S3 is labeled I3 , and the input terminal of S4 is labeled I4 .

[0309] In at least one embodiment shown in FIG. 13 , each forward scan control transistor and each reverse scan control transistor are p-type transistors, but the present invention is not limited thereto.

[0310] FIG. 14 is an operating timing diagram of at least one embodiment of the driving module shown in FIG. 4 during forward scanning.

[0311] FIG. 15 is a timing diagram illustrating the operation of at least one embodiment of the driving module shown in FIG. 4 during reverse scanning.

[0312] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving module, and the driving method includes:

[0313] The n-stage driving circuit, under the control of the n-th control clock signal and the n-th output clock signal, controls, in the n-th output stage, the n-th output clock signal provided by the n-th output clock signal terminal to be output to the n-stage driving signal output terminal according to the n-th input signal provided by the n-th input terminal;

[0314] The effective voltage duration periods of the driving signals output by the N-level driving circuits do not overlap with each other;

[0315] n is a positive integer less than or equal to N; N is an integer greater than 1.

[0316] The display device described in the embodiment of the present disclosure includes the above-mentioned driving module.

[0317] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving module, comprising N-level driving circuits; N is an integer greater than 1; The n-stage driving circuit is electrically connected to the n-th input terminal, the n-th control clock signal terminal, the n-th output clock signal terminal and the n-stage driving signal output terminal respectively, and is used for controlling the n-th output clock signal to be output to the n-stage driving signal output terminal in the n-output stage according to the n-th input signal provided by the n-th input terminal under the control of the n-th control clock signal provided by the n-th control clock signal terminal and the n-th output clock signal provided by the n-th output clock signal terminal; The effective voltage duration periods of the driving signals output by the N-stage driving circuits do not overlap with each other; n is a positive integer less than or equal to N.

2. The driving module according to claim 1, wherein: The driving module includes at least three clock signal lines; One of the at least three clock signal lines is electrically connected to the nth control clock signal terminal, and another of the at least three clock signal lines is electrically connected to the nth output clock signal terminal.

3. The driving module according to claim 2, wherein: The driving module includes three clock signal lines; The 3a-2 control clock signal terminal is electrically connected to the first clock signal line, and the 3a-2 output clock signal terminal is electrically connected to the third clock signal line; The 3a-1 control clock signal terminal is electrically connected to the third clock signal line, and the 3a-1 output clock signal terminal is electrically connected to the second clock signal line; The 3a control clock signal terminal is electrically connected to the second clock signal line, and the 3a output clock signal line is electrically connected to the first clock signal line; a is a positive integer.

4. The driving module according to claim 3, wherein: The first clock signal line is used to provide a first clock signal, the second clock signal line is used to provide a second clock signal, and the third clock signal line is used to provide a third clock signal; The effective voltage duration period of the first clock signal, the effective voltage duration period of the second clock signal, and the effective voltage duration period of the third clock signal do not overlap with each other.

5. The driving module according to claim 2, wherein: The driving module includes four clock signal lines. The control clock signal terminal of the 4a-3 level driving circuit is electrically connected to the first clock signal line, and the output clock signal terminal of the 4a-3 level driving circuit is electrically connected to the fourth clock signal line; The control clock signal terminal of the 4a-2 stage driving circuit is electrically connected to the fourth clock signal line, and the output clock signal terminal of the 4a-2 stage driving circuit is electrically connected to the third clock signal line; The control clock signal terminal of the 4a-1 stage driving circuit is electrically connected to the third clock signal line, and the output clock signal terminal of the 4a-1 stage driving circuit is electrically connected to the second clock signal line; The control clock signal terminal of the 4a-level driving circuit is electrically connected to the second clock signal line, and the output clock signal terminal of the 4a-level driving circuit is electrically connected to the first clock signal line; a is a positive integer.

6. The driving module according to claim 5, wherein: The effective voltage duration period of the first clock signal provided by the first clock signal line, the effective voltage duration period of the second clock signal provided by the second clock signal line, the effective voltage duration period of the second clock signal provided by the third clock signal line, and the effective voltage duration period of the fourth clock signal provided by the fourth clock signal line do not overlap with each other.

7. The driving module according to claim 2, wherein: The control clock signal terminal of the 6a-5th level driving circuit is electrically connected to the first clock signal line, and the output clock signal terminal of the 6a-5th level driving circuit is electrically connected to the sixth clock signal line; The control clock signal terminal of the 6a-4 stage driving circuit is electrically connected to the sixth clock signal line, and the output clock signal terminal of the 6a-4 stage driving circuit is electrically connected to the fifth clock signal line; The control clock signal terminal of the 6a-3 stage driving circuit is electrically connected to the fifth clock signal line, and the output clock signal terminal of the 6a-3 stage driving circuit is electrically connected to the fourth clock signal line; The control clock signal terminal of the 6a-2 stage driving circuit is electrically connected to the fourth clock signal line, and the output clock signal terminal of the 6a-2 stage driving circuit is electrically connected to the third clock signal line; The control clock signal terminal of the 6a-1 stage driving circuit is electrically connected to the third clock signal line, and the output clock signal terminal of the 6a-1 stage driving circuit is electrically connected to the second clock signal line; The control clock signal terminal of the level 6a driving circuit is electrically connected to the second clock signal line, and the output clock signal terminal of the level 6a driving circuit is electrically connected to the first clock signal line; a is a positive integer.

8. The driving module according to claim 7, wherein: The effective voltage duration period of the first clock signal provided by the first clock signal line, the effective voltage duration period of the second clock signal provided by the second clock signal line, the effective voltage duration period of the second clock signal provided by the third clock signal line, the effective voltage duration period of the fourth clock signal provided by the fourth clock signal line, the effective voltage duration period of the fifth clock signal provided by the fifth clock signal line, and the effective voltage duration period of the sixth clock signal provided by the sixth clock signal line do not overlap with each other.

9. The driving module according to claim 2, wherein: The driving module includes eight clock signal lines; The 8f-7 control clock signal terminal is electrically connected to the first clock signal line, and the 8f-7 output clock signal terminal is electrically connected to the fourth clock signal line; The 8f-6 control clock signal terminal is electrically connected to the fourth clock signal line, and the 8f-6 output clock signal terminal is electrically connected to the seventh clock signal line; The 8f-5 control clock signal terminal is electrically connected to the seventh clock signal line, and the 8f-5 output clock signal terminal is electrically connected to the second clock signal line; The 8f-4 control clock signal terminal is electrically connected to the second clock signal line, and the 8f-4 output clock signal terminal is electrically connected to the fifth clock signal line; The 8f-3 control clock signal terminal is electrically connected to the fifth clock signal line, and the 8f-3 output clock signal terminal is electrically connected to the eighth clock signal line; The 8f-2 control clock signal terminal is electrically connected to the eighth clock signal line, and the 8f-2 output clock signal terminal is electrically connected to the third clock signal line. Clock signal line electrical connection; The 8f-1 control clock signal terminal is electrically connected to the third clock signal line, and the 8f-1 output clock signal terminal is electrically connected to the sixth clock signal line; The 8f-th control clock signal terminal is electrically connected to the sixth clock signal line, and the 8f-1-th output clock signal terminal is electrically connected to the first clock signal line; f is a positive integer.

10. The driving module according to claim 9, wherein: The effective voltage duration period of the first clock signal provided by the first clock signal line, the effective voltage duration period of the second clock signal provided by the second clock signal line, the effective voltage duration period of the second clock signal provided by the third clock signal line, the effective voltage duration period of the fourth clock signal provided by the fourth clock signal line, the effective voltage duration period of the fifth clock signal provided by the fifth clock signal line, the effective voltage duration period of the sixth clock signal provided by the sixth clock signal line, the effective voltage duration period of the seventh clock signal provided by the seventh clock signal line and the effective voltage duration period of the eighth clock signal provided by the eighth clock signal line do not overlap with each other.

11. The driving module according to any one of claims 1 to 10, wherein: The driving module also includes N clock signal providing circuits; The nth clock signal supply circuit includes an nth forward scanning clock supply circuit and an nth reverse scanning clock supply circuit; The nth forward scanning clock providing circuit is electrically connected to the forward scanning control terminal, the first forward scanning clock signal terminal, the second forward scanning clock signal terminal, the nth control clock signal terminal and the nth output clock signal terminal respectively, and is used to control the connection or disconnection between the first forward scanning clock signal terminal and the nth control clock signal terminal, and control the connection or disconnection between the second forward scanning clock signal terminal and the nth output clock signal terminal under the control of the forward scanning control signal provided by the forward scanning control terminal; The nth reverse scan clock providing circuit is electrically connected to the reverse scan control terminal, the first reverse scan clock signal terminal, the second reverse scan clock signal terminal, the nth control clock signal terminal and the nth output clock signal terminal, respectively, and is used to control the connection or disconnection between the first reverse scan clock signal terminal and the nth control clock signal terminal, and control the connection or disconnection between the second reverse scan clock signal terminal and the nth output clock signal terminal under the control of the reverse scan control signal provided by the reverse scan control terminal.

12. The driving module according to claim 11, wherein: The nth forward scanning clock supply circuit includes a first supply transistor and a second supply transistor, and the nth reverse scanning clock supply circuit includes a third supply transistor and a fourth supply transistor; The gate of the first providing transistor is electrically connected to the forward scanning control terminal, the first electrode of the first providing transistor is electrically connected to the first forward scanning clock signal terminal, and the second electrode of the first providing transistor is electrically connected to the nth control clock signal terminal; The gate of the second providing transistor is electrically connected to the forward scanning control terminal, the first electrode of the second providing transistor is electrically connected to the second forward scanning clock signal terminal, and the second electrode of the second providing transistor is electrically connected to the nth The output clock signal terminal is electrically connected; The gate of the third providing transistor is electrically connected to the reverse scanning control terminal, the first electrode of the third providing transistor is electrically connected to the first reverse scanning clock signal terminal, and the second electrode of the third providing transistor is electrically connected to the nth control clock signal terminal; The gate of the fourth providing transistor is electrically connected to the reverse scanning control terminal, the first electrode of the fourth providing transistor is electrically connected to the second reverse scanning clock signal terminal, and the second electrode of the fourth providing transistor is electrically connected to the nth output clock signal terminal; The first providing transistor and the second providing transistor are both p-type transistors; or, the first providing transistor and the second providing transistor are both n-type transistors; The third providing transistor and the fourth providing transistor are both p-type transistors; or, the third providing transistor and the fourth providing transistor are both n-type transistors.

13. The driving module according to any one of claims 1 to 10, wherein: The n-th stage driving circuit comprises an n-th input circuit, an n-th first node control circuit, an n-th second node control circuit, an n-th first energy storage circuit, an n-th second energy storage circuit and an n-th output circuit; The nth input circuit is electrically connected to the nth input terminal, the nth first node and the nth control clock signal terminal respectively, and is used to control the connection between the nth input terminal and the nth first node under the control of the nth control clock signal; The nth first node control circuit is electrically connected to the nth first node, the nth output clock signal terminal, the nth second node and the first voltage terminal respectively, and is used to control the connection between the nth first node and the first voltage terminal under the control of the nth output clock signal provided by the nth output clock signal terminal and the potential of the nth second node; The nth second node control circuit is electrically connected to the nth control clock signal terminal, the nth first node and the second voltage terminal respectively, and is used to control the connection between the nth second node and the second voltage terminal under the control of the nth control clock signal, and control the connection between the nth second node and the nth control clock signal terminal under the control of the potential of the nth first node; The nth first energy storage circuit is electrically connected to the nth first node and the nth driving signal output terminal respectively, and is used for storing electric energy; The nth second energy storage circuit is electrically connected to the nth second node, and is used to maintain the potential of the nth second node; The nth output circuit is electrically connected to the nth first node, the nth second node, the first voltage terminal, the nth output clock signal terminal and the nth drive signal output terminal, respectively, and is used to control the connection between the nth drive signal output terminal and the nth output clock signal terminal under the control of the potential of the nth first node, and to control the connection between the nth drive signal output terminal and the first voltage terminal under the control of the potential of the nth second node.

14. The driving module according to claim 13, wherein: The input circuit includes an nth first transistor, the nth first node control circuit includes an nth second transistor and an nth third transistor, the nth second node control circuit includes an nth fourth transistor and an nth fifth transistor, the nth output circuit includes an nth seventh transistor and an nth eighth transistor, the nth first energy storage circuit includes an nth first capacitor, and the nth second energy storage circuit includes an nth second capacitor; The gate of the nth first transistor is electrically connected to the nth control clock signal terminal, the first electrode of the nth first transistor is electrically connected to the input terminal, and the second electrode of the nth first transistor is electrically connected to the nth first node; The gate of the nth second transistor is electrically connected to the nth output clock signal terminal, the first electrode of the nth second transistor is electrically connected to the nth first node, and the second electrode of the nth second transistor is electrically connected to the first electrode of the nth third transistor; A gate of the nth third transistor is electrically connected to the nth second node, and a second electrode of the nth third transistor is electrically connected to the first voltage terminal; A gate of the nth fourth transistor is electrically connected to the nth first node, a first electrode of the nth fourth transistor is electrically connected to the nth control clock signal terminal, and a second electrode of the nth fourth transistor is electrically connected to the nth second node; The gate of the nth fifth transistor is electrically connected to the nth control clock signal terminal, the first electrode of the nth fifth transistor is electrically connected to the nth second node, and the second electrode of the nth fifth transistor is electrically connected to the second voltage terminal; A first end of the nth first capacitor is electrically connected to the nth first node, and a second end of the nth first capacitor is electrically connected to the nth driving signal output terminal; A first end of the nth second capacitor is electrically connected to the nth second node, and a second end of the nth second capacitor is electrically connected to the first voltage end; A gate of the nth seventh transistor is electrically connected to the nth second node, a first electrode of the nth seventh transistor is electrically connected to the first voltage terminal, and a second electrode of the nth seventh transistor is electrically connected to the nth driving signal output terminal; The gate of the nth eighth transistor is electrically connected to the nth first node, the first electrode of the nth eighth transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth eighth transistor is electrically connected to the nth output clock signal terminal.

15. The driving module according to claim 14, wherein: The nth stage driving circuit further includes an nth sixth transistor; The nth first node is electrically connected to the gate of the nth eighth transistor through the nth sixth transistor; The gate of the nth sixth transistor is electrically connected to the third voltage terminal, the first electrode of the nth sixth transistor is electrically connected to the nth first node, and the second electrode of the nth sixth transistor is electrically connected to the gate of the nth eighth transistor.

16. The driving module according to claim 11, wherein: Also includes a forward scanning control circuit and a reverse scanning control circuit; The forward scanning control circuit includes N-1 forward scanning control sub-circuits; The hth forward scanning control subcircuit is electrically connected to the forward scanning control terminal, the driving signal output terminal of the hth driving circuit and the input terminal of the h+1th driving circuit respectively, and is used to control the connection between the driving signal output terminal of the hth driving circuit and the input terminal of the h+1th driving circuit under the control of the forward scanning control signal provided by the forward scanning control terminal; h is a positive integer less than or equal to N-1; The hth reverse scan control subcircuit is electrically connected to the reverse scan control terminal, the drive signal output terminal of the N-h+1th level drive circuit and the input terminal of the Nhth level drive circuit, respectively, and is used to control the connection between the drive signal output terminal of the N-h+1th level drive circuit and the input terminal of the Nhth level drive circuit under the control of the reverse scan control signal provided by the reverse scan control terminal.

17. The driving module according to claim 16, wherein: The hth forward scanning control subcircuit includes an hth forward scanning control transistor, and the hth reverse scanning control subcircuit includes an hth reverse scanning control transistor; The gate of the hth forward scan control transistor is electrically connected to the forward scan control terminal, the first electrode of the hth forward scan control transistor is electrically connected to the drive signal output terminal of the hth stage drive circuit, and the second electrode of the hth forward scan control transistor is electrically connected to the input terminal of the h+1th stage drive circuit; The gate of the hth reverse scanning control transistor is electrically connected to the reverse scanning control end, the first electrode of the hth reverse scanning control transistor is electrically connected to the driving signal output end of the N-h+1th level driving circuit, and the second electrode of the hth reverse scanning control transistor is electrically connected to the input end of the Nhth level driving circuit.

18. A driving method, applied to the driving module according to any one of claims 1 to 17, the driving method comprising: The n-stage driving circuit, under the control of the n-th control clock signal and the n-th output clock signal, controls the n-th output clock signal provided by the n-th output clock signal terminal to be output to the n-stage driving signal output terminal in the n-th output stage according to the n-th input signal provided by the n-th input terminal; The effective voltage duration periods of the driving signals output by the N-level driving circuits do not overlap with each other; n is a positive integer less than or equal to N; N is an integer greater than 1.

19. A display device, comprising the driving module according to any one of claims 1 to 17.

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