Driving circuit, driving method, and display device

Abstract

A driving circuit, a driving method, and a display device. The driving circuit comprises a first node control circuit (11). The first node control circuit (11) is electrically connected to a first node (PU_CN), a first scan voltage end (CN), a second scan voltage end (CNB), a first control clock signal end (CKC1), a second control clock signal end (CKC2), an input end (I1), and a reset end (RST), respectively, and is used for controlling, under the control of a first control clock signal provided by the first control clock signal end (CKC1) and an input signal provided by the input end (I1), the first node (PU_CN) and the first scan voltage end (CN) to be connected or disconnected, and controlling, under the control of a second control clock signal provided by the second control clock signal end (CKC2) and a reset signal provided by the reset end (RST), the first node (PU_CN) and the second scan voltage end (CNB) to be connected or disconnected. Therefore, no long-term bias voltage is present between a source and a drain of a transistor, the aging speed of the transistor would not be increased, and the output of the driving circuit is normal.

Description

Driving circuit, driving method and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310932536.6 filed in China on July 27, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, and a display device. Background Art

[0004] In the related art, the first node control circuit includes a transistor whose gate is electrically connected to the input terminal, and a transistor whose gate is electrically connected to the reset terminal. Taking the case where the drive circuit is in a forward scanning state as an example, the drive circuit is only turned on within a frame and is in a closed state for the rest of the time. At this time, the potential of the first node is a low voltage (assuming it is -8V), and the first scanning voltage terminal provides a high voltage signal (assuming the first scanning voltage terminal provides an 8V voltage signal). For the transistor whose gate is electrically connected to the input terminal, the gate is connected to the low voltage signal, so there is a long-term bias between the source and drain of the transistor whose gate is electrically connected to the input terminal. The drain-source voltage Vds of the transistor whose gate is electrically connected to the input terminal is 16V, which accelerates the aging of the transistor and causes characteristic drift, resulting in abnormal output of the drive circuit. Similarly, there will also be a long-term bias between the source and drain of the transistor whose gate is electrically connected to the reset terminal, which is included in the first node control circuit, causing the aging of the transistor to accelerate.

[0005] Summary of the Invention

[0006] In one aspect, an embodiment of the present disclosure provides a driving circuit including a first node control circuit;

[0007] The first node control circuit is electrically connected to the first node, the first scanning voltage terminal, the second scanning voltage terminal, the first control clock signal terminal, the second control clock signal terminal, the input terminal and the reset terminal, respectively, and is used to control the connection or disconnection between the first node and the first scanning voltage terminal under the control of the first control clock signal provided by the first control clock signal terminal and the input signal provided by the input terminal, and to control the connection or disconnection between the first node and the second scanning voltage terminal under the control of the second control clock signal provided by the second control clock signal terminal and the reset signal provided by the reset terminal.

[0008] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes an output circuit;

[0009] The output circuit is electrically connected to the first output node, the output clock signal terminal and the driving output terminal respectively, and is used to control the output clock signal provided by the output clock signal terminal to be written into the driving output terminal under the control of the potential of the first output node.

[0010] Optionally, the first output node and the first node are electrically connected to each other.

[0011] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes an on-off control circuit;

[0012] The on-off control circuit is electrically connected to the first voltage terminal, the first node and the first output node respectively, and is used to control the connection between the first node and the first output node under the control of a first voltage signal provided by the first voltage terminal.

[0013] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a first control circuit and a second control circuit;

[0014] The first control circuit is electrically connected to the first node, the second output node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the second output node and the second voltage terminal under the control of the potential of the first node;

[0015] The second control circuit is electrically connected to the first control terminal, the third voltage terminal and the second output node, respectively, and is used to control the second output node to be disconnected from the third voltage terminal under the control of a first control signal provided by the first control terminal when the first control circuit controls the second output node to be connected to the second voltage terminal.

[0016] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a third control circuit;

[0017] The third control circuit is electrically connected to the first scanning voltage terminal, the second scanning voltage terminal, the first control clock signal terminal, the second control clock signal terminal and the first control terminal, respectively, and is used to write the second control clock signal provided by the second control clock signal terminal into the first control terminal under the control of the first scanning voltage provided by the first scanning voltage terminal, and to write the first control clock signal provided by the first control clock signal terminal into the first control terminal under the control of the second scanning voltage provided by the second scanning voltage terminal.

[0018] Optionally, the first node control circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0019] The gate of the first transistor is electrically connected to the input terminal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the first node;

[0020] The gate of the second transistor is electrically connected to the first control clock signal terminal, and the first electrode of the second transistor is electrically connected to the first scan voltage terminal;

[0021] The gate of the third transistor is electrically connected to the reset terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor;

[0022] A gate of the fourth transistor is electrically connected to the second control clock signal terminal, and a second electrode of the fourth transistor is electrically connected to the second scan voltage terminal.

[0023] Optionally, the first control circuit includes a fifth transistor, and the second control circuit includes a sixth transistor;

[0024] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second output node, and the second electrode of the fifth transistor is electrically connected to the second voltage terminal;

[0025] A gate of the sixth transistor is electrically connected to the first control terminal, a first electrode of the sixth transistor is electrically connected to the third voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second output node.

[0026] Optionally, the third control circuit includes a seventh transistor and an eighth transistor;

[0027] The gate of the seventh transistor is electrically connected to the first scan voltage terminal, the first electrode of the seventh transistor is electrically connected to the second control clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the first control terminal;

[0028] The gate of the eighth transistor is electrically connected to the second scan voltage terminal, the first electrode of the eighth transistor is electrically connected to the first control terminal, and the second electrode of the eighth transistor is electrically connected to the first control clock signal terminal.

[0029] Optionally, the on-off control circuit includes a ninth transistor;

[0030] A gate of the ninth transistor is electrically connected to the first voltage terminal, a first electrode of the ninth transistor is electrically connected to the first node, and a second electrode of the ninth transistor is electrically connected to the first output node.

[0031] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes an output reset circuit;

[0032] The output reset circuit is electrically connected to the second output node, the driving output terminal and the fourth voltage terminal respectively, and is used to control the connection or disconnection between the driving output terminal and the fourth voltage terminal under the control of the potential of the second output node.

[0033] Optionally, the output circuit includes an output transistor, and the output reset circuit includes an output reset transistor;

[0034] The gate of the output transistor is electrically connected to the first output node, the first electrode of the output transistor is electrically connected to the output clock signal terminal, and the second electrode of the output transistor is electrically connected to the driving output terminal;

[0035] A gate of the output reset transistor is electrically connected to the second output node, a first electrode of the output reset transistor is electrically connected to the driving output terminal, and a second electrode of the output reset transistor is electrically connected to the fourth voltage terminal.

[0036] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first output control circuit and a second output node reset circuit;

[0037] The first output control circuit is electrically connected to the first enable control terminal and the drive output terminal respectively, and is used to control the drive output terminal to output a valid voltage signal under the control of the first enable control signal provided by the first enable control terminal when the display panel is powered off; the display panel includes the drive circuit;

[0038] The second output node reset circuit is electrically connected to the second output node, the first enable control terminal and the fifth voltage terminal respectively, and is used to control the connection between the second output node and the fifth voltage terminal under the control of the first enable control signal provided by the first enable control terminal when the display panel is powered off.

[0039] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second output control circuit;

[0040] The second output control circuit is electrically connected to the second enable control terminal, the drive output terminal and the sixth voltage terminal, respectively, and is used to control the connection between the drive output terminal and the sixth voltage terminal in the touch stage, and to control the disconnection between the drive output terminal and the sixth voltage terminal in the display stage under the control of the second enable control signal provided by the second enable control terminal.

[0041] Optionally, the first output control circuit includes a tenth transistor, and the second output node reset circuit includes an eleventh transistor;

[0042] The gate of the tenth transistor is electrically connected to the first enable control terminal, the first electrode of the tenth transistor is electrically connected to the driving output terminal, and the second electrode of the tenth transistor is electrically connected to the first enable control terminal;

[0043] The gate of the eleventh transistor is electrically connected to the first enable control terminal, the first electrode of the eleventh transistor is electrically connected to the second output node, and the second electrode of the eleventh transistor is electrically connected to the fifth voltage terminal.

[0044] Optionally, the second output control circuit includes a twelfth transistor;

[0045] The gate of the twelfth transistor is electrically connected to the second enable control terminal, the first electrode of the twelfth transistor is electrically connected to the driving output terminal, and the second electrode of the twelfth transistor is electrically connected to the sixth voltage terminal.

[0046] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first node reset circuit, a first energy storage circuit, and a second energy storage circuit;

[0047] The first node reset circuit is electrically connected to the reset control terminal, the second output node, the first node, and the seventh voltage terminal, respectively, and is configured to control the connection or disconnection between the first node and the seventh voltage terminal under the control of the potential of the second output node, and to control the connection or disconnection between the first node and the seventh voltage terminal under the control of a reset control signal provided by the reset control terminal;

[0048] The first energy storage circuit is electrically connected to the first output node and the driving output terminal respectively, and is used to store electrical energy;

[0049] The second energy storage circuit is electrically connected to the second output node and is configured to store electrical energy.

[0050] Optionally, the first node reset circuit includes a thirteenth transistor and a fourteenth transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0051] The gate of the thirteenth transistor is electrically connected to the second output node, the first electrode of the thirteenth transistor is electrically connected to the first node, and the second electrode of the thirteenth transistor is electrically connected to the seventh voltage terminal;

[0052] The gate of the fourteenth transistor is electrically connected to the reset control terminal, the first electrode of the fourteenth transistor is electrically connected to the first node, and the second electrode of the fourteenth transistor is electrically connected to the seventh voltage terminal;

[0053] A first end of the first capacitor is electrically connected to the first output node, and a second end of the first capacitor is electrically connected to the driving output end;

[0054] A first end of the second capacitor is electrically connected to the second output node, and a second end of the second capacitor is electrically connected to the seventh voltage terminal.

[0055] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit. The driving method includes:

[0056] The first node control circuit controls the connection or disconnection between the first node and the first scanning voltage terminal under the control of the first control clock signal and the input signal. The first node control circuit controls the connection or disconnection between the first node and the second scanning voltage terminal under the control of the second control clock signal and the reset signal.

[0057] Optionally, the driving circuit further includes a first control circuit, a second control circuit, a third control circuit, an on-off control circuit, an output circuit, an output reset circuit, a first node reset circuit, a first energy storage circuit, and a second energy storage circuit; and the display cycle includes a first stage, a second stage, a third stage, and a fourth stage which are sequentially arranged;

[0058] The driving method includes:

[0059] In the first stage, the first node control circuit controls the connection between the first node and the first scanning voltage terminal under the control of the first control clock signal and the input signal; the on-off control circuit controls the connection between the first node and the first output node under the control of the first voltage signal; the output circuit controls the writing of the output clock signal to the driving output terminal under the control of the potential of the first output node; and the first control circuit controls the connection between the second output node and the second voltage terminal under the control of the potential of the first node.

[0060] In the second stage, the output circuit, under the control of the potential of the first output node, controls the writing of the output clock signal to the driving output terminal, and the first energy storage circuit bootstraps the potential of the first node; the first control circuit, under the control of the potential of the first node, controls the connection between the second output node and the second voltage terminal;

[0061] In the third stage, the first node control circuit controls the connection between the first node and the second scanning voltage terminal under the control of the second control clock signal and the reset signal; the third control circuit writes the second control clock signal to the first control terminal under the control of the first scanning voltage; the second control circuit controls the connection between the second output node and the third voltage terminal under the control of the first control signal; and the output reset circuit controls the connection between the driving output terminal and the fourth voltage terminal under the control of the potential of the second output node.

[0062] In the fourth stage, the output reset circuit controls the connection between the driving output terminal and the fourth voltage terminal under the control of the potential of the second output node.

[0063] Optionally, the driving circuit further includes a second output control circuit; and the driving method further includes:

[0064] In the touch control stage, the second output control circuit controls the connection between the driving output terminal and the sixth voltage terminal under the control of the second enable control signal.

[0065] In the display phase, the second output control circuit controls the drive output terminal and the sixth voltage terminal to be disconnected under the control of the second enable control signal.

[0066] Optionally, the driving circuit further includes a first output control circuit and a second output node reset circuit;

[0067] The driving method further includes:

[0068] When the display panel is powered off, the first output control circuit controls the driving output terminal to output a valid voltage signal under the control of the first enable control signal; the second output node reset circuit controls the connection between the second output node and the fifth voltage terminal under the control of the first enable control signal.

[0069] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0071] FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0072] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0073] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0074] FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0075] FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0076] FIG7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0077] FIG8 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0078] FIG9 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0079] FIG10 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0080] FIG11 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0081] FIG12 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0082] FIG13 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0083] FIG14 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0084] FIG15 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0085] FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0086] FIG17 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG16 ;

[0087] FIG18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0088] FIG19 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0089] FIG20 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0090] FIG21 is a schematic diagram showing the connection relationship of a four-stage drive circuit cascade;

[0091] FIG22 is an operation timing diagram of at least one embodiment shown in FIG21 during forward scanning;

[0092] FIG. 23 is a timing diagram illustrating the operation of at least one embodiment shown in FIG. 21 during reverse scanning. DETAILED DESCRIPTION

[0093] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0094] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0095] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0096] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes a first node control circuit 11 ;

[0097] The first node control circuit 11 is electrically connected to the first node PU_CN, the first scanning voltage terminal CN, the second scanning voltage terminal CNB, the first control clock signal terminal CKC1, the second control clock signal terminal CKC2, the input terminal I1 and the reset terminal RST, respectively, and is used to control the connection or disconnection between the first node PU_CN and the first scanning voltage terminal CN under the control of the first control clock signal provided by the first control clock signal terminal CKC1 and the input signal provided by the input terminal I1, and to control the connection or disconnection between the first node PU_CN and the second scanning voltage terminal CNB under the control of the second control clock signal provided by the second control clock signal terminal CKC2 and the reset signal provided by the reset terminal RST.

[0098] Optionally, the first control clock signal terminal CKC1 may be a fourth clock signal terminal, and the second control clock signal terminal CKC2 may be a second clock signal terminal, but the sequence is not limited thereto.

[0099] In the related art, the first node control circuit includes a transistor whose gate is electrically connected to the input terminal I1, and a transistor whose gate is electrically connected to the reset terminal RST. Taking the driving circuit in the forward scanning state as an example, the driving circuit is only turned on within one frame and is in the off state for the rest of the time. At this time, the potential of PU_CN is a low voltage (assuming it is -8V), and CN provides a high voltage signal (assuming CN provides an 8V voltage signal). For the transistor whose gate is electrically connected to the input terminal I1, the gate is connected to the low voltage signal. Therefore, there is a long-term bias between the source and drain of the transistor whose gate is electrically connected to the input terminal I1. The drain-source voltage Vds of the transistor whose gate is electrically connected to the input terminal I1 is 16V. The aging speed of the transistor is accelerated, the characteristics drift, and the output of the driving circuit is abnormal. Similarly, there will also be a long-term bias between the source and drain of the transistor whose gate is electrically connected to the reset terminal RST, which is included in the first node control circuit, causing the aging speed of the transistor to be accelerated.

[0100] Based on this, in the driving circuit described in the embodiment of the present disclosure, the first node control circuit 11 controls the connection or disconnection between the first node PU_CN and the first scanning voltage terminal CN under the control of the first control clock signal and the input signal, so that there will be no long-term bias between the source and drain of the transistor whose gate is electrically connected to the input terminal I1 included in the first node control circuit 11, and there will be no long-term bias between the source and drain of the transistor whose gate is electrically connected to the reset terminal RST included in the first node control circuit 11, which will not cause the aging speed of the transistor to be accelerated, so that the output of the driving circuit is normal.

[0101] The driving circuit described in at least one embodiment of the present disclosure can perform bidirectional scanning;

[0102] When the driving circuit is in a forward scanning state, CN outputs a high voltage signal and CNB outputs a low voltage signal;

[0103] When the driving circuit is in a reverse scanning state, CN outputs a low voltage signal and CNB outputs a high voltage signal.

[0104] Optionally, the driving circuit described in at least one embodiment of the present disclosure may further include an output circuit;

[0105] The output circuit is electrically connected to the first output node, the output clock signal terminal and the driving output terminal respectively, and is used to control the output clock signal provided by the output clock signal terminal to be written into the driving output terminal under the control of the potential of the first output node.

[0106] In a specific implementation, the driving circuit may further include an output circuit, and the output circuit writes the output clock signal into the driving output terminal under the control of the potential of the first output node.

[0107] Optionally, the first output node is electrically connected to the first node.

[0108] According to a specific embodiment, the first output node and the first node may be electrically connected to each other.

[0109] As shown in FIG2 , based on at least one embodiment of the driving circuit described in FIG1 , the driving circuit described in at least one embodiment of the present disclosure may further include an output circuit 21 ;

[0110] The output circuit 21 is electrically connected to the first output node PU, the output clock signal terminal CKO and the driving output terminal OT respectively, and is used to control the output clock signal provided by the output clock signal terminal CKO to be written into the driving output terminal OT under the control of the potential of the first output node PU;

[0111] The first output node PU is electrically connected to the first node PU_CN.

[0112] Optionally, the output clock signal terminal CKO may be a first clock signal terminal, but is not limited thereto.

[0113] The driving circuit according to at least one embodiment of the present disclosure further includes an on-off control circuit;

[0114] The on-off control circuit is electrically connected to the first voltage terminal, the first node and the first output node respectively, and is used to control the connection between the first node and the first output node under the control of a first voltage signal provided by the first voltage terminal.

[0115] In a specific implementation, the driving circuit described in at least one embodiment of the present disclosure may further include an on-off control circuit, which controls the connection between the first node and the first output node under the control of the first voltage signal.

[0116] Optionally, when the transistor included in the on-off control circuit is an n-type transistor, the first voltage end may be a high voltage end; when the transistor included in the on-off control circuit is a p-type transistor, the first voltage end may be a low voltage end.

[0117] As shown in FIG3 , based on at least one embodiment of the driving circuit described in FIG1 , the driving circuit described in at least one embodiment of the present disclosure may further include an output circuit 21 and an on / off control circuit 31 ;

[0118] The output circuit 21 is electrically connected to the first output node PU, the output clock signal terminal CKO and the driving output terminal OT respectively, and is used to control the output clock signal provided by the output clock signal terminal CKO to be written into the driving output terminal OT under the control of the potential of the first output node PU;

[0119] The on-off control circuit 31 is electrically connected to the first voltage terminal V1, the first node PU_CN and the first output node PU respectively, and is used to control the connection between the first node PU_CN and the first output node PU under the control of the first voltage signal provided by the first voltage terminal V1.

[0120] The driving circuit according to at least one embodiment of the present disclosure may further include a first control circuit and a second control circuit;

[0121] The first control circuit is electrically connected to the first node, the second output node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the second output node and the second voltage terminal under the control of the potential of the first node;

[0122] The second control circuit is electrically connected to the first control terminal, the third voltage terminal and the second output node, respectively, and is used to control the second output node to be disconnected from the third voltage terminal under the control of a first control signal provided by the first control terminal when the first control circuit controls the second output node to be connected to the second voltage terminal.

[0123] In a specific implementation, the driving circuit may further include a first control circuit and a second control circuit;

[0124] The first control circuit controls the connection or disconnection between the second output node and the second voltage terminal under the control of the potential of the first node;

[0125] When the first control circuit controls the second output node to be connected to the second voltage terminal, the second control circuit controls the second output node to be disconnected from the third voltage terminal under the control of a first control signal provided by the first control terminal.

[0126] Optionally, the second voltage terminal may be a low voltage terminal, and the third voltage terminal may be a high voltage terminal.

[0127] In at least one embodiment of the present disclosure, by setting the first control circuit and the second control circuit, the transistors included in the first control circuit and the transistors included in the second control circuit will not turn on at the same time, thereby avoiding the DC path formed by the simultaneous opening of the two transistors in the related design, which can effectively reduce the power consumption of the driving circuit and improve the service life of the TFT (thin film transistor).

[0128] Moreover, when the driving circuit described in at least one embodiment of the present disclosure is in operation, when the potential of the first output node is pulled high, there is no signal to pull up the potential of the second output node, thereby avoiding the situation in which the potential of the first output node and the potential of the second output node are pulled high at the same time in the original design. This allows the potential of the first output node to maintain a higher potential, improves the competitive relationship between the first output node and the second output node, and makes the output state of the driving circuit more stable.

[0129] The driving circuit according to at least one embodiment of the present disclosure may further include a third control circuit;

[0130] The third control circuit is electrically connected to the first scanning voltage terminal, the second scanning voltage terminal, the first control clock signal terminal, the second control clock signal terminal and the first control terminal, respectively, and is used to write the second control clock signal provided by the second control clock signal terminal into the first control terminal under the control of the first scanning voltage provided by the first scanning voltage terminal, and to write the first control clock signal provided by the first control clock signal terminal into the first control terminal under the control of the second scanning voltage provided by the second scanning voltage terminal.

[0131] As shown in FIG4 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit according to at least one embodiment of the present disclosure may further include a first control circuit 41 , a second control circuit 42 , and a third control circuit 43 ;

[0132] The first control circuit 41 is electrically connected to the first node PU_CN, the second output node PD, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the second output node PD and the second voltage terminal V2 under the control of the potential of the first node PU_CN;

[0133] The second control circuit 42 is electrically connected to the first control terminal Ct1, the third voltage terminal V3, and the second output node PD, respectively, and is configured to control the second output node PD to be disconnected from the third voltage terminal V3 under the control of a first control signal provided by the first control terminal Ct1 when the first control circuit 41 controls the second output node PD to be connected to the second voltage terminal V2;

[0134] The third control circuit 43 is electrically connected to the first scanning voltage terminal CN, the second scanning voltage terminal CNB, the first control clock signal terminal CKC1, the second control clock signal terminal CKC2 and the first control terminal Ct1, respectively, and is used to write the second control clock signal provided by the second control clock signal terminal CKC2 into the first control terminal Ct1 under the control of the first scanning voltage provided by the first scanning voltage terminal CN, and to write the first control clock signal provided by the first control clock signal terminal CK1 into the first control terminal Ct1 under the control of the second scanning voltage provided by the second scanning voltage terminal CNB.

[0135] In at least one embodiment of the present disclosure, the first control terminal Ct1 may be electrically connected to the second control circuit to control the operation of the second control circuit.

[0136] As shown in FIG5 , based on at least one embodiment of the driving circuit shown in FIG3 , the driving circuit according to at least one embodiment of the present disclosure may further include a first control circuit 41 , a second control circuit 42 , and a third control circuit 43 ;

[0137] The first control circuit 41 is electrically connected to the first node PU_CN, the second output node PD, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the second output node PD and the second voltage terminal V2 under the control of the potential of the first node PU_CN;

[0138] The second control circuit 42 is electrically connected to the first control terminal Ct1, the third voltage terminal V3, and the second output node PD, respectively, and is configured to control the second output node PD to be disconnected from the third voltage terminal V3 under the control of a first control signal provided by the first control terminal Ct1 when the first control circuit 41 controls the second output node PD to be connected to the second voltage terminal V2;

[0139] The third control circuit 43 is electrically connected to the first scanning voltage terminal CN, the second scanning voltage terminal CNB, the first control clock signal terminal CKC1, the second control clock signal terminal CKC2 and the first control terminal Ct1, respectively, and is used to write the second control clock signal provided by the second control clock signal terminal CKC2 into the first control terminal Ct1 under the control of the first scanning voltage provided by the first scanning voltage terminal CN, and to write the first control clock signal provided by the first control clock signal terminal CK into the first control terminal Ct1 under the control of the second scanning voltage provided by the second scanning voltage terminal CNB.

[0140] Optionally, the first node control circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0141] The gate of the first transistor is electrically connected to the input terminal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the first node;

[0142] The gate of the second transistor is electrically connected to the first control clock signal terminal, and the first electrode of the second transistor is electrically connected to the first scan voltage terminal;

[0143] The gate of the third transistor is electrically connected to the reset terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor;

[0144] A gate of the fourth transistor is electrically connected to the second control clock signal terminal, and a second electrode of the fourth transistor is electrically connected to the second scan voltage terminal.

[0145] Optionally, the first control circuit includes a fifth transistor, and the second control circuit includes a sixth transistor;

[0146] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second output node, and the second electrode of the fifth transistor is electrically connected to the second voltage terminal;

[0147] A gate of the sixth transistor is electrically connected to the first control terminal, a first electrode of the sixth transistor is electrically connected to the third voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second output node.

[0148] Optionally, the third control circuit includes a seventh transistor and an eighth transistor;

[0149] The gate of the seventh transistor is electrically connected to the first scan voltage terminal, the first electrode of the seventh transistor is electrically connected to the second control clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the first control terminal;

[0150] The gate of the eighth transistor is electrically connected to the second scan voltage terminal, the first electrode of the eighth transistor is electrically connected to the first control terminal, and the second electrode of the eighth transistor is electrically connected to the first control clock signal terminal.

[0151] Optionally, the on-off control circuit includes a ninth transistor;

[0152] A gate of the ninth transistor is electrically connected to the first voltage terminal, a first electrode of the ninth transistor is electrically connected to the first node, and a second electrode of the ninth transistor is electrically connected to the first output node.

[0153] The driving circuit according to at least one embodiment of the present disclosure may further include an output reset circuit;

[0154] The output reset circuit is electrically connected to the second output node, the driving output terminal and the fourth voltage terminal respectively, and is used to control the connection or disconnection between the driving output terminal and the fourth voltage terminal under the control of the potential of the second output node.

[0155] In a specific implementation, the driving circuit may further include an output reset circuit. The output reset circuit controls the connection or disconnection between the driving output terminal and the fourth voltage terminal under the control of the potential of the second output node.

[0156] Optionally, the fourth voltage end may be a low voltage end, but is not limited thereto.

[0157] As shown in FIG6 , based on at least one embodiment of the driving circuit shown in FIG4 , the driving circuit according to at least one embodiment of the present disclosure may further include an output reset circuit 61 ;

[0158] The output reset circuit 61 is electrically connected to the second output node PD, the driving output terminal OT and the fourth voltage terminal V4 respectively, and is used to control the connection or disconnection between the driving output terminal OT and the fourth voltage terminal V4 under the control of the potential of the second output node PD.

[0159] As shown in FIG7 , based on at least one embodiment of the driving circuit shown in FIG5 , the driving circuit according to at least one embodiment of the present disclosure may further include an output reset circuit 61 ;

[0160] The output reset circuit is electrically connected to the second output node PD, the driving output terminal OT and the fourth voltage terminal V4 respectively, and is used to control the connection or disconnection between the driving output terminal OT and the fourth voltage terminal V4 under the control of the potential of the second output node PD.

[0161] Optionally, the output circuit includes an output transistor, and the output reset circuit includes an output reset transistor;

[0162] The gate of the output transistor is electrically connected to the first output node, the first electrode of the output transistor is electrically connected to the output clock signal terminal, and the second electrode of the output transistor is electrically connected to the driving output terminal;

[0163] A gate of the output reset transistor is electrically connected to the second output node, a first electrode of the output reset transistor is electrically connected to the driving output terminal, and a second electrode of the output reset transistor is electrically connected to the fourth voltage terminal.

[0164] Optionally, the output clock signal terminal may be a first clock signal terminal.

[0165] The driving circuit according to at least one embodiment of the present disclosure may further include a first output control circuit and a second output node reset circuit;

[0166] The first output control circuit is electrically connected to the first enable control terminal and the driving output terminal respectively, and is used to control the driving output terminal to output a valid voltage signal under the control of the first enable control signal provided by the first enable control terminal when the display panel is powered off;

[0167] The second output node reset circuit is electrically connected to the second output node, the first enable control terminal and the fifth voltage terminal respectively, and is used to control the connection between the second output node and the fifth voltage terminal under the control of the first enable control signal provided by the first enable control terminal when the display panel is powered off.

[0168] Optionally, the fifth voltage end may be a low voltage end, but is not limited thereto.

[0169] In at least one embodiment of the present disclosure, the driving circuit may further include a first output control circuit and a second output node reset circuit;

[0170] When the display panel is powered off, the first output control circuit controls the driving output terminal to output a valid voltage signal under the control of the first enable control signal, so as to discharge the pixel circuit included in the display panel and discharge the internal charge of the display panel to prevent residual charge;

[0171] When the display panel is powered off, the second output node reset circuit controls the second output node to be electrically connected to the fifth voltage terminal under the control of the first enable control signal to pull down the potential of the second output node PD.

[0172] Optionally, when the transistor whose gate is electrically connected to the driving output end in the pixel circuit is an n-type transistor, the effective voltage signal can be a high voltage signal; when the transistor whose gate is electrically connected to the driving output end in the pixel circuit is an n-type transistor, the effective voltage signal can be a low voltage signal.

[0173] As shown in FIG8 , based on at least one embodiment of the driving circuit shown in FIG6 , the driving circuit may further include a first output control circuit 81 and a second output node reset circuit 82 ;

[0174] The first output control circuit 81 is electrically connected to the first enable control terminal EN and the driving output terminal OT, respectively, and is used to control the driving output terminal OT to output a valid voltage signal under the control of the first enable control signal provided by the first enable control terminal EN when the display panel is powered off;

[0175] The second output node reset circuit 82 is electrically connected to the second output node PD, the first enable control terminal EN and the fifth voltage terminal V5, respectively, and is used to control the connection between the second output node PD and the fifth voltage terminal V5 under the control of the first enable control signal provided by the first enable control terminal EN when the display panel is powered off.

[0176] As shown in FIG9 , based on at least one embodiment of the driving circuit shown in FIG7 , the driving circuit may further include a first output control circuit 81 and a second output node reset circuit 82 ;

[0177] The first output control circuit 81 is electrically connected to the first enable control terminal EN and the driving output terminal OT, respectively, and is used to control the driving output terminal OT to output a valid voltage signal under the control of the first enable control signal provided by the first enable control terminal EN when the display panel is powered off;

[0178] The second output node reset circuit 82 is electrically connected to the second output node PD, the first enable control terminal EN and the fifth voltage terminal V5, respectively, and is used to control the connection between the second output node PD and the fifth voltage terminal V5 under the control of the first enable control signal provided by the first enable control terminal EN when the display panel is powered off.

[0179] The driving circuit according to at least one embodiment of the present disclosure may further include a second output control circuit;

[0180] The second output control circuit is electrically connected to the second enable control terminal, the drive output terminal and the sixth voltage terminal, respectively, and is used to control the connection between the drive output terminal and the sixth voltage terminal in the touch stage, and to control the disconnection between the drive output terminal and the sixth voltage terminal in the display stage under the control of the second enable control signal provided by the second enable control terminal.

[0181] Optionally, the sixth voltage terminal may be a low voltage terminal, but is not limited thereto.

[0182] In a specific implementation, when the display panel is a TDDI (touch and display driver integration) display product, the driving circuit may further include a second output control circuit. Under the control of a second enable signal, the output circuit controls the connection between the driving output terminal and the sixth voltage terminal in the touch stage, so that the driving output terminal outputs an invalid voltage signal. In the display stage, the driving output terminal is controlled to be disconnected from the sixth voltage terminal so as not to affect the display.

[0183] Optionally, when the transistor whose gate is electrically connected to the driving output end in the pixel circuit is an n-type transistor, the invalid voltage signal may be a low voltage signal; when the transistor whose gate is electrically connected to the driving output end in the pixel circuit is an n-type transistor, the invalid voltage signal may be a high voltage signal.

[0184] As shown in FIG10 , based on at least one embodiment of the driving circuit shown in FIG6 , the driving circuit according to at least one embodiment of the present disclosure may further include a second output control circuit 101 ;

[0185] The second output control circuit 101 is electrically connected to the second enable control terminal EN2, the drive output terminal OT and the sixth voltage terminal V6, respectively, and is used to control the connection between the drive output terminal OT and the sixth voltage terminal V6 in the touch stage under the control of the second enable control signal provided by the second enable control terminal EN2, and to control the disconnection between the drive output terminal OT and the sixth voltage terminal V6 in the display stage.

[0186] As shown in FIG11 , based on at least one embodiment of the driving circuit shown in FIG7 , the driving circuit according to at least one embodiment of the present disclosure may further include a second output control circuit 101 ;

[0187] The second output control circuit 101 is electrically connected to the second enable control terminal EN2, the drive output terminal OT and the sixth voltage terminal V6, respectively, and is used to control the connection between the drive output terminal OT and the sixth voltage terminal V6 in the touch stage under the control of the second enable control signal provided by the second enable control terminal EN2, and to control the disconnection between the drive output terminal OT and the sixth voltage terminal V6 in the display stage.

[0188] Optionally, the first output control circuit includes a tenth transistor, and the second output node reset circuit includes an eleventh transistor;

[0189] The gate of the tenth transistor is electrically connected to the first enable control terminal, the first electrode of the tenth transistor is electrically connected to the driving output terminal, and the second electrode of the tenth transistor is electrically connected to the first enable control terminal;

[0190] The gate of the eleventh transistor is electrically connected to the first enable control terminal, the first electrode of the eleventh transistor is electrically connected to the second output node, and the second electrode of the eleventh transistor is electrically connected to the fifth voltage terminal.

[0191] Optionally, the second output control circuit includes a twelfth transistor;

[0192] The gate of the twelfth transistor is electrically connected to the second enable control terminal, the first electrode of the twelfth transistor is electrically connected to the driving output terminal, and the second electrode of the twelfth transistor is electrically connected to the sixth voltage terminal.

[0193] The driving circuit according to at least one embodiment of the present disclosure may further include a first node reset circuit, a first energy storage circuit, and a second energy storage circuit;

[0194] The first node reset circuit is electrically connected to the reset control terminal, the second output node, the first node, and the seventh voltage terminal, respectively, and is configured to control the connection or disconnection between the first node and the seventh voltage terminal under the control of the potential of the second output node, and to control the connection or disconnection between the first node and the seventh voltage terminal under the control of a reset control signal provided by the reset control terminal;

[0195] The first energy storage circuit is electrically connected to the first output node and the driving output terminal respectively, and is used to store electrical energy;

[0196] The second energy storage circuit is electrically connected to the second output node and is configured to store electrical energy.

[0197] Optionally, the seventh voltage end may be a low voltage end, but is not limited thereto.

[0198] In a specific implementation, the driving circuit may include a first node control circuit, a first energy storage circuit and a second energy storage circuit. The first node reset circuit controls the connection or disconnection between the first node and the seventh voltage terminal under the control of the potential of the second output node, and controls the connection or disconnection between the first node and the seventh voltage terminal under the control of the reset control signal.

[0199] As shown in FIG12 , based on at least one embodiment of the driving circuit shown in FIG10 , the driving circuit according to at least one embodiment of the present disclosure may further include a first node reset circuit 121 , a first energy storage circuit 122 , and a second energy storage circuit 123 ;

[0200] The first node reset circuit 121 is electrically connected to the reset control terminal R1, the second output node PD, the first node PU_CN, and the seventh voltage terminal V7, respectively, and is configured to control the connection or disconnection between the first node PU_CN and the seventh voltage terminal V7 under the control of the potential of the second output node PD, and to control the connection or disconnection between the first node PU_CN and the seventh voltage terminal V7 under the control of the reset control signal provided by the reset control terminal R1;

[0201] The first energy storage circuit 122 is electrically connected to the first output node PU and the driving output terminal OT respectively, and is used to store electrical energy;

[0202] The second energy storage circuit 123 is electrically connected to the second output node PD and is configured to store electrical energy.

[0203] As shown in FIG13 , based on at least one embodiment of the driving circuit shown in FIG11 , the driving circuit according to at least one embodiment of the present disclosure may further include a first node reset circuit 121 , a first energy storage circuit 122 , and a second energy storage circuit 123 ;

[0204] The first node reset circuit 121 is electrically connected to the reset control terminal R1, the second output node PD, the first node PU_CN, and the seventh voltage terminal, respectively, and is configured to control the connection or disconnection between the first node PU_CN and the seventh voltage terminal V7 under the control of the potential of the second output node PD, and to control the connection or disconnection between the first node PU_CN and the seventh voltage terminal V7 under the control of the reset control signal provided by the reset control terminal R1;

[0205] The first energy storage circuit 122 is electrically connected to the first output node PU and the driving output terminal OT respectively, and is used to store electrical energy;

[0206] The second energy storage circuit 123 is electrically connected to the second output node PD and is configured to store electrical energy.

[0207] Optionally, the first node reset circuit includes a thirteenth transistor and a fourteenth transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0208] The gate of the thirteenth transistor is electrically connected to the second output node, the first electrode of the thirteenth transistor is electrically connected to the first node, and the second electrode of the thirteenth transistor is electrically connected to the seventh voltage terminal;

[0209] The gate of the fourteenth transistor is electrically connected to the reset control terminal, the first electrode of the fourteenth transistor is electrically connected to the first node, and the second electrode of the fourteenth transistor is electrically connected to the seventh voltage terminal;

[0210] A first end of the first capacitor is electrically connected to the first output node, and a second end of the first capacitor is electrically connected to the driving output end;

[0211] A first end of the second capacitor is electrically connected to the second output node, and a second end of the second capacitor is electrically connected to the seventh voltage terminal.

[0212] As shown in FIG14 , based on at least one embodiment of the driving circuit shown in FIG12 , the driving circuit may further include a first output control circuit 81 and a second output node reset circuit 82 ;

[0213] The first output control circuit 81 is electrically connected to the first enable control terminal EN and the driving output terminal OT, respectively, and is used to control the driving output terminal OT to output a valid voltage signal under the control of the first enable control signal provided by the first enable control terminal EN when the display panel is powered off;

[0214] The second output node reset circuit 82 is electrically connected to the second output node PD, the first enable control terminal EN and the fifth voltage terminal V5, respectively, and is used to control the connection between the second output node PD and the fifth voltage terminal V5 under the control of the first enable control signal provided by the first enable control terminal EN when the display panel is powered off.

[0215] As shown in FIG15 , based on at least one embodiment of the driving circuit shown in FIG13 , the driving circuit may further include a first output control circuit 81 and a second output node reset circuit 82 ;

[0216] The first output control circuit 81 is electrically connected to the first enable control terminal EN and the driving output terminal OT, respectively, and is used to control the driving output terminal OT to output a valid voltage signal under the control of the first enable control signal provided by the first enable control terminal EN when the display panel is powered off;

[0217] The second output node reset circuit 82 is electrically connected to the second output node PD, the first enable control terminal EN and the fifth voltage terminal V5, respectively, and is used to control the connection between the second output node PD and the fifth voltage terminal V5 under the control of the first enable control signal provided by the first enable control terminal EN when the display panel is powered off.

[0218] As shown in FIG16 , based on at least one embodiment of the driving circuit shown in FIG13 , the first node control circuit includes a first transistor T1 , a second transistor T2 , a third transistor T3 and a fourth transistor T4 ;

[0219] The gate of the first transistor T1 is electrically connected to the input terminal I1, the source of the first transistor T1 is electrically connected to the drain of the second transistor T2, and the drain of the first transistor T1 is electrically connected to the first node PU_CN;

[0220] The gate of the second transistor T2 is electrically connected to the fourth clock signal terminal CK4, and the source of the second transistor T2 is electrically connected to the first scan voltage terminal CN;

[0221] The gate of the third transistor T3 is electrically connected to the reset terminal RST, the source of the third transistor T3 is electrically connected to the first node PU_CN, and the drain of the third transistor T3 is electrically connected to the source of the fourth transistor T4;

[0222] The gate of the fourth transistor T4 is electrically connected to the second clock signal terminal CK2, and the drain of the fourth transistor T4 is electrically connected to the second scan voltage terminal CNB;

[0223] The first control circuit includes a fifth transistor T5, and the second control circuit includes a sixth transistor T6;

[0224] The gate of the fifth transistor T5 is electrically connected to the first node PU_CN, the source of the fifth transistor T5 is electrically connected to the second output node PD, and the drain of the fifth transistor T5 is electrically connected to the low voltage terminal VGL_G;

[0225] The gate of the sixth transistor T6 is electrically connected to the first control terminal Ct1, the source of the sixth transistor T6 is electrically connected to the low voltage terminal VGL_G, and the drain of the sixth transistor T6 is electrically connected to the second output node PD;

[0226] The third control circuit includes a seventh transistor T7 and an eighth transistor T8;

[0227] The gate of the seventh transistor T7 is electrically connected to the first scan voltage terminal CN, the source of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the drain of the seventh transistor T7 is electrically connected to the first control terminal Ct1;

[0228] The gate of the eighth transistor T8 is electrically connected to the second scanning voltage terminal CNB, the source of the eighth transistor T8 is electrically connected to the first control terminal Ct1, and the drain of the eighth transistor T8 is electrically connected to the fourth clock signal terminal CK4;

[0229] The on-off control circuit includes a ninth transistor T9;

[0230] The gate of the ninth transistor T9 is electrically connected to the high voltage terminal VGH_G, the source of the ninth transistor T9 is electrically connected to the first node PU_CN, and the drain of the ninth transistor T9 is electrically connected to the first output node PU;

[0231] The output circuit includes an output transistor TO, and the output reset circuit includes an output reset transistor TF;

[0232] The gate of the output transistor TO is electrically connected to the first output node PU, the source of the output transistor TO is electrically connected to the first clock signal terminal CK1, and the drain of the output transistor TO is electrically connected to the driving output terminal OT;

[0233] The gate of the output reset transistor TF is electrically connected to the second output node PD, the source of the output reset transistor TF is electrically connected to the driving output terminal OT, and the drain of the output reset transistor TF is electrically connected to the low voltage terminal VGL_G;

[0234] The second output control circuit includes a twelfth transistor T12;

[0235] The gate of the twelfth transistor T12 is electrically connected to the second enable control terminal EN2, the source of the twelfth transistor T12 is electrically connected to the driving output terminal OT, and the drain of the twelfth transistor T1 is electrically connected to the low voltage terminal VGL_G;

[0236] The first node reset circuit includes a thirteenth transistor T13 and a fourteenth transistor T14, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0237] The gate of the thirteenth transistor T13 is electrically connected to the second output node PD, the source of the thirteenth transistor T13 is electrically connected to the first node PU_CN, and the drain of the thirteenth transistor T13 is electrically connected to the low voltage terminal VGL_G;

[0238] The gate of the fourteenth transistor T14 is electrically connected to the reset control terminal R1, the source of the fourteenth transistor T14 is electrically connected to the first node PU_CN, and the drain of the fourteenth transistor T14 is electrically connected to the low voltage terminal VGL_G;

[0239] A first end of the first capacitor C1 is electrically connected to the first output node PU, and a second end of the first capacitor C1 is electrically connected to the driving output terminal OT;

[0240] A first end of the second capacitor C2 is electrically connected to the second output node PD, and a second end of the second capacitor C2 is electrically connected to the low voltage terminal VGL_G;

[0241] In at least one embodiment shown in FIG. 16 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0242] In at least one embodiment shown in FIG. 16 of the present disclosure, T2 is added between T1 and CN, and T4 is added between T3 and CNB. T2 acts as a voltage divider for T1, and T4 acts as a voltage divider for T3. The bias voltage between CN and PU_CN is shared by T1 and T2, improving the bias environment of T1. The bias voltage between CNB and PU_CN is shared by T3 and T4, improving the bias environment of T3 and enhancing the reliability of the drive circuit. Simultaneously, when the potential of PU_CN increases, the gate potential of T6 remains low, and T6 is turned off. This avoids the DC path between the clock signal terminal and the low voltage terminal caused by the simultaneous opening of two transistors in the original design, effectively reducing the power consumption of the drive circuit and increasing the service life of the transistors.

[0243] In at least one embodiment of the present disclosure shown in FIG16 , while the PU potential is being pulled high, no signal is pulling up the PD potential. This prevents the PU and PD potentials in the associated drive circuit from being pulled high simultaneously, allowing the PU potential to maintain a relatively high level, improving the competitive relationship between the PU and PD, and making the output state of the drive circuit more stable. Furthermore, the redundant transistor in the original model (the gate of the redundant transistor is electrically connected to the drive output terminal, the first electrode of the redundant transistor is electrically connected to the second output node, and the second electrode of the redundant transistor is electrically connected to the low voltage terminal) is removed, saving space occupied by the drive circuit and achieving a narrow-frame design.

[0244] In a specific implementation, the input terminal I1 may be electrically connected to the driving output terminal of the adjacent previous stage driving circuit, and the reset terminal may be electrically connected to the driving output terminal of the adjacent next stage driving circuit, but the present invention is not limited thereto.

[0245] As shown in FIG17 , during operation of at least one embodiment of the driving circuit shown in FIG16 of the present disclosure, taking forward scanning as an example, CN provides a high voltage signal and CNB provides a low voltage signal. A display cycle may include a first stage S1, a second stage S2, a third stage S3, and a fourth stage S4, which are sequentially arranged.

[0246] In the first stage S1, I1 provides a high voltage signal, CK4 provides a high voltage signal, T1 and T2 are open, PU_CN is connected to CN, the potential of PU_CN is high voltage, T9 is open, the potential of PU is high voltage, TO is open, CK1 outputs a low voltage signal, OT outputs a low voltage signal; T5 is open, the potential of PD is low voltage;

[0247] In the second stage S2, I1 provides a low voltage signal, RST provides a low voltage signal, CK2 and CK4 both provide low voltage signals, T1, T2, T3 and T4 are all turned off, TO is turned on, CK1 outputs a high voltage signal, the potential of PU is bootstrapped by C1, OT outputs a high voltage signal; T5 is turned on, and the potential of PD is low voltage;

[0248] In the third stage S3, RST outputs a high voltage signal, I1 outputs a low voltage signal, CK2 provides a high voltage signal, T3 and T4 are turned on, PU_CN is connected to CNB, the potential of PU_CN is low voltage, T9 is turned on, the potential of PU is low voltage, and TO is turned off;

[0249] In the third stage S3, T7 is turned on, T8 is turned off, CK2 provides a high voltage signal, the potential of Ct1 is high voltage, T6 is turned on, PD is connected to VGH_G, the potential of PD is high voltage, TF is turned on, and OT outputs a low voltage signal;

[0250] In the fourth stage S4, I1 and RST both output low voltage signals, T1 and T3 are both turned off, the potential of PU remains at a low voltage, CK2 provides a low voltage signal, T6 is turned off, the potential of PD remains at a high voltage, TF is turned on, and OT outputs a low voltage signal.

[0251] As shown in Figure 17, when the display panel is scanning in the forward direction, the duty cycle of the first clock signal provided by the first clock signal terminal CK1, the duty cycle of the second clock signal provided by the second clock signal terminal CK2, the duty cycle of the third clock signal provided by the third clock signal terminal CK3, and the duty cycle of the fourth clock signal provided by the fourth clock signal terminal CK4 are all 1 / 4, the period of the first clock signal provided by the first clock signal terminal CK1, the period of the second clock signal provided by the second clock signal terminal CK2, the period of the third clock signal provided by the third clock signal terminal CK3, and the period of the fourth clock signal provided by the fourth clock signal terminal CK4 are all T, the second clock signal is delayed by T / 4 compared with the first clock signal, the third clock signal is delayed by T / 4 compared with the second clock signal, and the fourth clock signal is delayed by T / 4 compared with the third clock signal, but is not limited to this.

[0252] When at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure is in operation, during the blank period between two frames of display time, R1 provides a high voltage signal, T14 is turned on, the potential of PU_CN is a low voltage, T9 is turned on, and the potential of PU is a low voltage.

[0253] When at least one embodiment of the driving circuit shown in FIG16 of the present disclosure is in operation, during the touch stage, EN2 provides a high voltage signal, T12 is turned on, and OT outputs a low voltage signal to turn off the pixel circuit in the effective display area to prevent problems such as leakage and mischarging of the pixel circuit; during the display period, EN2 provides a low voltage signal and T12 is turned off, which does not affect the display.

[0254] When at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure is in operation, during reverse scanning, CN provides a low voltage signal and CNB provides a high voltage signal.

[0255] In at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure, T9 may not be provided.

[0256] The difference between at least one embodiment of the driving circuit shown in FIG. 18 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure is that T12,

[0257] The difference between at least one embodiment of the driving circuit shown in FIG19 of the present disclosure and at least one embodiment of the driving circuit shown in FIG16 of the present disclosure is that at least one embodiment of the driving circuit shown in FIG19 of the present disclosure further includes a first output control circuit;

[0258] The first output control circuit includes a tenth transistor T10, and the second output node reset circuit includes an eleventh transistor T11;

[0259] The gate of the tenth transistor T10 is electrically connected to the first enable control terminal EN, the source of the tenth transistor T10 is electrically connected to the driving output terminal OT, and the drain of the tenth transistor T10 is electrically connected to the first enable control terminal EN;

[0260] A gate of the eleventh transistor T11 is electrically connected to the first enable control terminal EN, a source of the eleventh transistor T11 is electrically connected to the second output node PD, and a drain of the eleventh transistor T11 is electrically connected to the low voltage terminal VGL_G.

[0261] In at least one embodiment of the driving circuit shown in FIG. 19 of the present disclosure, all transistors are n-type transistors, but the present invention is not limited thereto.

[0262] At least one embodiment of the driving circuit shown in FIG. 19 of the present disclosure is in operation.

[0263] When the display panel is powered off, EN is controlled to provide a high voltage signal, T10 is turned on, so that OT outputs a high voltage signal, the potential of the gate of T11 is a high voltage, PD is connected to VGL_G, the potential of PD is pulled low, and then the data line is controlled to output a ground voltage signal, and the potential of the common electrode voltage is controlled to be the ground voltage, thereby discharging the internal charge of the display panel.

[0264] The difference between at least one embodiment of the driving circuit shown in FIG. 20 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 19 of the present disclosure is that the twelfth transistor T12 is not included.

[0265] In at least one embodiment of the driving circuit disclosed herein, T9 may not be provided.

[0266] FIG21 is a schematic diagram showing the connection relationship of a four-stage cascade driving circuit. In at least one embodiment shown in FIG21 , the structure of the driving circuit is as shown in FIG16 ;

[0267] As shown in FIG21 , the first-stage driving circuit P1 includes a first transistor T011, a first second transistor T012, a first third transistor T013, a first fourth transistor T014, a first fifth transistor T015, a first sixth transistor T016, a first seventh transistor T017, a first eighth transistor T018, a first ninth transistor T019, a first twelfth transistor T0112, a first thirteenth transistor T0113, a first fourteenth transistor T0114, a first output transistor TO1, a first output reset transistor TF1, a first capacitor C11, and a first second capacitor C12.

[0268] The second-stage driving circuit P2 includes a second first transistor T021, a second second transistor T022, a second third transistor T023, a second fourth transistor T024, a second fifth transistor T025, a second sixth transistor T026, a second seventh transistor T027, a second eighth transistor T028, a second ninth transistor T029, a second twelfth transistor T0212, a second thirteenth transistor T0213, a second fourteenth transistor T0214, a second output transistor TO2, a second output reset transistor TF2, a second first capacitor C21, and a second second capacitor C22;

[0269] The third-stage driving circuit P3 includes a third first transistor T031, a third second transistor T032, a third third transistor T033, a third fourth transistor T034, a third fifth transistor T035, a third sixth transistor T036, a third seventh transistor T037, a third eighth transistor T038, a third ninth transistor T039, a third twelfth transistor T0312, a third thirteenth transistor T0313, a third fourteenth transistor T0314, a third output transistor TO3, a third output reset transistor TF3, a third first capacitor C31, and a third second capacitor C32;

[0270] The fourth-stage driving circuit P4 includes a fourth first transistor T041, a fourth second transistor T042, a fourth third transistor T043, a fourth fourth transistor T044, a fourth fifth transistor T045, a fourth sixth transistor T046, a fourth seventh transistor T047, a fourth eighth transistor T048, a fourth ninth transistor T049, a fourth twelfth transistor T0412, a fourth thirteenth transistor T0413, a fourth fourteenth transistor T0414, a fourth output transistor TO4, a third output reset transistor TF4, a fourth first capacitor C41, and a fourth second capacitor C42.

[0271] In FIG21 , the terminal labeled STV is a starting voltage terminal, and the input terminal of the first-stage driving circuit is electrically connected to the starting voltage terminal STV;

[0272] The drive output terminal labeled OT1 is P1, the drive output terminal labeled OT2 is P2, the drive output terminal labeled OT3 is P3, and the drive output terminal labeled OT4 is P4;

[0273] OT1 is electrically connected to the input terminal of P2, and the reset terminal of P2 is electrically connected to OT3;

[0274] OT2 is electrically connected to the input terminal of P3, and the reset terminal of P3 is electrically connected to OT4;

[0275] OT3 is electrically connected to the input terminal of P4, and the terminal labeled RST4 is the reset terminal in P4.

[0276] In at least one embodiment shown in FIG. 21 ,

[0277] In the first-stage driving circuit P1, the gate of T2 is electrically connected to the fourth clock signal terminal CK4, the gate of T4 is electrically connected to the second clock signal terminal CK2, the source of T7 is electrically connected to the second clock signal terminal CK2, the drain of T8 is electrically connected to the fourth clock signal terminal CK4, and the source of T0 is electrically connected to the first clock signal terminal CK1;

[0278] In the second-stage driving circuit P2, the gate of T2 is electrically connected to the first clock signal terminal CK1, the gate of T4 is electrically connected to the third clock signal terminal CK3, the source of T7 is electrically connected to the third clock signal terminal CK3, the drain of T8 is electrically connected to the first clock signal terminal CK1, and the source of T0 is electrically connected to the second clock signal terminal CK2;

[0279] In the third-stage driving circuit P3, the gate of T2 is electrically connected to the second clock signal terminal CK2, the gate of T4 is electrically connected to the fourth clock signal terminal CK4, the source of T7 is electrically connected to the fourth clock signal terminal CK4, the drain of T8 is electrically connected to the second clock signal terminal CK2, and the source of T0 is electrically connected to the third clock signal terminal CK3;

[0280] In the fourth-stage driving circuit P4, the gate of T2 is electrically connected to the third clock signal terminal CK3, the gate of T4 is electrically connected to the first clock signal terminal CK1, the source of T7 is electrically connected to the first clock signal terminal CK1, the drain of T8 is electrically connected to the third clock signal terminal CK3, and the source of TO is electrically connected to the fourth clock signal terminal CK4.

[0281] In FIG21 , the node labeled PU_CN1 is the first node in P1, the node labeled PU1 is the first output node in P1, and the node labeled PD1 is the second output node in P1;

[0282] The node labeled PU_CN2 is the first node in P2, the node labeled PU2 is the first output node in P2, and the node labeled PD2 is the second output node in P2;

[0283] The node labeled PU_CN3 is the first node in P3, the node labeled PU3 is the first output node in P3, and the node labeled PD3 is the second output node in P3;

[0284] The node labeled PU_CN4 is the first node in P4, the node labeled PU4 is the first output node in P4, and the node labeled PD4 is the second output node in P4.

[0285] FIG. 22 is a timing diagram illustrating the operation of at least one embodiment shown in FIG. 21 during forward scanning.

[0286] As shown in FIG22 , in at least one embodiment shown in FIG21 , during forward scanning, CN may output a high voltage signal, CNB may output a low voltage signal, and a display cycle may include a first stage S1 , a second stage S2 , a third stage S3 , a fourth stage S4 , and a fifth stage S5 , which are sequentially arranged.

[0287] In the first stage S1, STV provides a high voltage signal, CK4 provides a high voltage signal, and CK1, CK2 and CK3 all provide low voltage signals.

[0288] In the first-stage driver circuit P1, T011 and T012 are turned on, the potentials of PU_CN1 and PU1 are both high voltage, C11 is charged through T011, T012, and T09, TO1 is turned on, CK1 provides a low voltage signal, OT1 outputs a low voltage signal, T017 is turned on, CK2 provides a low voltage signal, and T016 is turned off. Since the potential of PU_CN1 is high voltage, T015 is turned on, and the potential of PD1 is low voltage, there is no problem of two transistors in the related driver circuit being turned on at the same time, forming a DC path between CK2 and VGL_G.

[0289] In the second-stage driving circuit P2, CK1 provides a low voltage signal, T022 is turned off, OT1 outputs a low voltage signal, T021 is turned off, the potential of PD2 remains at a high voltage, T0213 is turned on, the potentials of PU_CN2 and PU2 remain at a low voltage, TF2 is turned on, and OT2 outputs a low voltage signal;

[0290] In the third-stage driving circuit P3, CK2 provides a low voltage signal, T032 is turned off, OT2 outputs a low voltage signal, T031 is turned off, OT2 outputs a low voltage signal, and T031 is turned off; T037 is turned on, CK4 provides a high voltage signal, T036 is turned on, the potential of PD3 remains at a high voltage, T0313 is turned on, the potentials of PU_CN3 and PU3 are low voltages, TF3 is turned on, and OT3 outputs a low voltage signal;

[0291] In the fourth-stage driving circuit P4, CK3 provides a low voltage signal, T042 is turned off, OT3 outputs a low voltage signal, T041 is turned off, the potential of PD4 is a high voltage, T0413 is turned on, the potentials of PU_CN4 and PU4 are low voltages, TF4 is turned on, and OT3 outputs a low voltage signal;

[0292] In the second phase S2, CK1 outputs a high voltage signal, and CK2, CK3, and CK4 all output low voltage signals;

[0293] In the first-stage driving circuit P1, the potential of PU1 is high, TO1 is turned on, CK1 outputs a high voltage signal, OT1 outputs a high voltage signal, and due to the bootstrap effect of C11, the potential of PU1 is further increased; CN outputs a high voltage signal, T017 is turned on, CK2 outputs a low voltage signal, and T016 is turned off; because the potential of PU_CN1 is high, T015 is turned on, and the potential of PD1 is low;

[0294] In the second-stage driving circuit P2, CK1 provides a high voltage signal, T022 is turned on, OT1 outputs a high voltage signal, T021 is turned on, the potentials of PU_CN2 and PU2 are high voltage, TO2 is turned on, CK2 outputs a low voltage signal, OT2 outputs a low voltage signal; CN outputs a high voltage signal, T027 is turned on, CK3 outputs a low voltage signal, and T026 is turned off; the potential of PU_CN2 is high voltage, T025 is turned on, and the potential of PD2 is low voltage. At this time, no two transistors in the relevant driving circuit are turned on at the same time, and no DC path is formed between CK3 and VGL_G;

[0295] In the third-stage driving circuit P3, CK2 outputs a low voltage signal, T032 is turned off, OT2 outputs a low voltage signal, T03 is turned off, CN outputs a high voltage signal, and T037 is turned on; CK4 outputs a high voltage signal, T036 is turned on, charging PD3, the potential of PD3 is high voltage, T0313 is turned on, the potential of PU_CN3 and the potential of PU3 are low voltage, TF4 is turned on, and OT3 outputs a low voltage signal;

[0296] In the fourth-stage driving circuit P4, CK3 outputs a low voltage signal, T042 is turned off, OT3 outputs a low voltage signal, and T041 is turned off; CN outputs a high voltage signal, and T047 is turned on; CK1 outputs a high voltage signal, and T046 is turned on to charge PD4. The potential of PD4 is high, T0413 is turned on, and OT4 outputs a low voltage signal;

[0297] In the third stage S3, CK2 outputs a high voltage signal, and CK1, CK3, and CK4 output low voltage signals;

[0298] In the first-stage driving circuit P1, CK2 outputs a high voltage signal, T014 is turned on, OT2 outputs a high voltage signal, T013 is turned on, CNB outputs a low voltage signal, the potentials of PU_CN1 and PU1 are low voltage, TO1 is turned off; T016 is turned on, the potential of PD1 is high voltage, TF1 is turned on, and OT1 outputs a low voltage signal;

[0299] In the second-stage driving circuit P2, CK2 outputs a high voltage signal. Due to the bootstrap effect of C21, the potential of PU2 is further increased; TO2 is turned on, OT2 outputs a high voltage signal; CK2 outputs a low voltage signal, T026 is turned off, and since the potential of PU_CN2 is high, T025 is turned on, and the potential of PD2 is low.

[0300] In the third-stage driving circuit P3, CK2 outputs a high voltage signal, T032 is turned on, OT2 outputs a high voltage signal, T031 is turned on, the potentials of PU_CN3 and PU3 are high voltage, TO3 is turned on, CK3 outputs a low voltage signal, OT3 outputs a low voltage signal; CK4 outputs a low voltage signal, T036 is turned off; the potential of PU_CN3 is high voltage, T035 is turned on, and the potential of PD3 is low voltage. At this time, no two transistors in the relevant driving circuit are turned on at the same time, and no DC path is formed between CK4 and VGL_G.

[0301] In the fourth-stage driving circuit P4, CK3 outputs a low-voltage signal, T042 is turned off, OT3 outputs a low-voltage signal, T041 is turned off, and the potential of PD4 remains at a high level; T0413 is turned on, the potentials of PU_CN4 and PU4 remain at a low voltage, TF4 is turned on, and OT4 outputs a low-voltage signal;

[0302] In the fourth stage S4, CK3 outputs a high voltage signal, and CK1, CK2, and CK4 output low voltage signals;

[0303] In the first-stage driving circuit P1, CK4 outputs a low voltage signal, T012 is turned off, STV provides a low voltage signal, T011 is turned off, the potential of PD1 is a high voltage, T0113 is turned off, the potential of PD1 is a high voltage, TF1 is turned on, and OT1 outputs a low voltage signal;

[0304] In the second-stage driving circuit P2, CK3 outputs a high voltage signal, T024 is turned on, CNB outputs a low voltage signal, the potentials of PU_CN2 and PU2 are low voltage, TO2 is turned off, CK3 outputs a high voltage signal, T026 is turned on, the potential of PD2 is high voltage, TF2 is turned on, and OT2 outputs a low voltage signal;

[0305] In the third-stage driving circuit P3, CK3 outputs a high voltage signal. Due to the bootstrap effect of C31, the potential of PU3 is further increased, TO3 is turned on, OT3 outputs a high voltage signal, CK4 outputs a low voltage signal, T036 is turned off, and since the potential of PU_CN3 is a high voltage, T035 is turned on, and the potential of PD3 remains at a low level.

[0306] In the fourth-stage driving circuit P4, CK3 outputs a high voltage signal, T042 is turned on, OT3 outputs a high voltage signal, T041 is turned on, the potentials of PU_CN4 and PU4 are high voltage, TO4 is turned on, CK4 outputs a low voltage signal, and OT4 outputs a low voltage signal; CK1 outputs a low voltage signal, T046 is turned off, the potential of PU_CN4 is high voltage, T045 is turned on, and the potential of PD4 is low voltage. At this time, no two transistors in the relevant driving circuit are turned on at the same time, and no DC path is formed between CK2 and VGL_G.

[0307] In the fifth stage S5, CK4 outputs a high voltage signal, and CK1, CK2, and CK3 output low voltage signals;

[0308] In the first-stage driving circuit P1, CK4 outputs a high-voltage signal, T012 turns on, OT4 outputs a high-voltage signal, T011 turns on, the potentials of PU_CN1 and PU1 are high, TO1 turns on, CK1 outputs a low-voltage signal, OT1 outputs a low-voltage signal; CK2 outputs a low-voltage signal, T016 turns on, and the potential of PD1 is low. At this time, no two transistors in the related driving circuit are turned on at the same time, and no DC path is formed between CK2 and VGL_G.

[0309] In the second-stage driving circuit P2, CK1 outputs a low voltage signal, T022 is turned off, OT1 outputs a low voltage signal, T021 is turned off, the potential of PD2 is a high voltage, T0213 is turned on, the potentials of PU_CN2 and PU2 are low voltages, TF2 is turned on, and OT2 outputs a low voltage signal;

[0310] In the third-stage driving circuit P3, CK4 outputs a high voltage signal, T034 is turned on, OT4 outputs a high voltage signal, T033 is turned on, CNB outputs a low voltage signal, the potentials of PU_CN3 and PU3 are low voltage, and TO3 is turned off; CK4 outputs a high voltage signal, T036 is turned on, the potential of PD3 is high voltage, TF3 is turned on, and OT3 outputs a low voltage signal;

[0311] In the fourth-level driving circuit P4, CK4 outputs a high voltage signal. Due to the bootstrap effect of C41, the potential of PU4 is further increased, TO4 is turned on, OT4 outputs a high voltage signal, CK1 outputs a low voltage signal, T042 is turned off, and since the potential of PU_CN4 is a high voltage, T045 is turned on, and the potential of PD4 remains at a low voltage.

[0312] In at least one embodiment of the present disclosure, the display panel includes a driving module, which includes a multi-stage driving circuit; the four-stage driving circuit is used as a cycle to repeat the above-mentioned opening timing to realize the scanning opening and closing of all row gate lines, wherein the function of each first capacitor is to bootstrap the voltage of the first output node, and the function of each second capacitor is to maintain the potential of the second output node and reduce the noise of the second output node.

[0313] FIG. 23 is a timing diagram illustrating the operation of at least one embodiment shown in FIG. 21 during reverse scanning.

[0314] As shown in Figure 23, during reverse scanning, the duty cycle of the first clock signal provided by the first clock signal terminal CK1, the duty cycle of the second clock signal provided by the second clock signal terminal CK2, the duty cycle of the third clock signal provided by the third clock signal terminal CK3, and the duty cycle of the fourth clock signal provided by the fourth clock signal terminal CK4 are all 1 / 4, the period of the first clock signal provided by the first clock signal terminal CK1, the period of the second clock signal provided by the second clock signal terminal CK2, the period of the third clock signal provided by the third clock signal terminal CK3, and the period of the fourth clock signal provided by the fourth clock signal terminal CK4 are all T, the third clock signal is delayed by T / 4 than the fourth clock signal, the second clock signal is delayed by T / 4 than the third clock signal, and the first clock signal is delayed by T / 4 than the second clock signal, but is not limited to this.

[0315] When at least one embodiment shown in Figure 21 is performing reverse scanning, CN outputs a low voltage signal, CNB outputs a high voltage signal, and the bias between CNB and each first node is jointly borne by each third transistor and each fourth transistor, thereby improving the bias environment of the third transistor and enhancing the reliability of the driving circuit.

[0316] As shown in FIG. 23 , in at least one embodiment shown in FIG. 21 , when performing reverse scanning, CN may output a low voltage signal and CNB may output a high voltage signal.

[0317] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes:

[0318] The first node control circuit controls the connection or disconnection between the first node and the first scanning voltage terminal under the control of the first control clock signal and the input signal. The first node control circuit controls the connection or disconnection between the first node and the second scanning voltage terminal under the control of the second control clock signal and the reset signal.

[0319] In at least one embodiment of the present disclosure, the driving circuit further includes a first control circuit, a second control circuit, a third control circuit, an on-off control circuit, an output circuit, an output reset circuit, a first node reset circuit, a first energy storage circuit, and a second energy storage circuit; the display cycle includes a first stage, a second stage, a third stage, and a fourth stage which are sequentially arranged;

[0320] The driving method includes:

[0321] In the first stage, the first node control circuit controls the connection between the first node and the first scanning voltage terminal under the control of the first control clock signal and the input signal; the on-off control circuit controls the connection between the first node and the first output node under the control of the first voltage signal; the output circuit controls the writing of the output clock signal to the driving output terminal under the control of the potential of the first output node; and the first control circuit controls the connection between the second output node and the second voltage terminal under the control of the potential of the first node.

[0322] In the second stage, the output circuit, under the control of the potential of the first output node, controls the writing of the output clock signal to the driving output terminal, and the first energy storage circuit bootstraps the potential of the first node; the first control circuit, under the control of the potential of the first node, controls the connection between the second output node and the second voltage terminal;

[0323] In the third stage, the first node control circuit controls the connection between the first node and the second scanning voltage terminal under the control of the second control clock signal and the reset signal; the third control circuit writes the second control clock signal to the first control terminal under the control of the first scanning voltage; the second control circuit controls the connection between the second output node and the third voltage terminal under the control of the first control signal; and the output reset circuit controls the connection between the driving output terminal and the fourth voltage terminal under the control of the potential of the second output node.

[0324] In the fourth stage, the output reset circuit controls the connection between the driving output terminal and the fourth voltage terminal under the control of the potential of the second output node.

[0325] Optionally, the driving circuit further includes a second output control circuit; and the driving method further includes:

[0326] In the touch control stage, the second output control circuit controls the connection between the driving output terminal and the sixth voltage terminal under the control of the second enable control signal.

[0327] In the display phase, the second output control circuit controls the drive output terminal and the sixth voltage terminal to be disconnected under the control of the second enable control signal.

[0328] Optionally, the driving circuit further includes a first output control circuit and a second output node reset circuit;

[0329] The driving method further includes:

[0330] When the display panel is powered off, the first output control circuit controls the driving output terminal to output a valid voltage signal under the control of the first enable control signal; the second output node reset circuit controls the connection between the second output node and the fifth voltage terminal under the control of the first enable control signal.

[0331] The display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.

[0332] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit, comprising a first node control circuit; The first node control circuit is electrically connected to the first node, the first scanning voltage terminal, the second scanning voltage terminal, the first control clock signal terminal, the second control clock signal terminal, the input terminal and the reset terminal, respectively, and is used to control the connection or disconnection between the first node and the first scanning voltage terminal under the control of the first control clock signal provided by the first control clock signal terminal and the input signal provided by the input terminal, and to control the connection or disconnection between the first node and the second scanning voltage terminal under the control of the second control clock signal provided by the second control clock signal terminal and the reset signal provided by the reset terminal.

2. The driving circuit according to claim 1, wherein: Also includes an output circuit; The output circuit is electrically connected to the first output node, the output clock signal terminal and the driving output terminal respectively, and is used to control the output clock signal provided by the output clock signal terminal to be written into the driving output terminal under the control of the potential of the first output node.

3. The driving circuit according to claim 2, wherein: The first output node and the first node are electrically connected to each other.

4. The driving circuit according to claim 2, wherein: Also includes an on-off control circuit; The on-off control circuit is electrically connected to the first voltage terminal, the first node and the first output node respectively, and is used to control the connection between the first node and the first output node under the control of a first voltage signal provided by the first voltage terminal.

5. The driving circuit according to claim 1, wherein: Also includes a first control circuit and a second control circuit; The first control circuit is electrically connected to the first node, the second output node and the second voltage terminal respectively, and is used to control the connection or disconnection between the second output node and the second voltage terminal under the control of the potential of the first node; The second control circuit is electrically connected to the first control terminal, the third voltage terminal and the second output node, respectively, and is used to control the second output node to be disconnected from the third voltage terminal under the control of a first control signal provided by the first control terminal when the first control circuit controls the second output node to be connected to the second voltage terminal.

6. The driving circuit according to claim 5, wherein: Also comprising a third control circuit; The third control circuit is electrically connected to the first scanning voltage terminal, the second scanning voltage terminal, the first control clock signal terminal, the second control clock signal terminal and the first control terminal, respectively, and is used to write the second control clock signal provided by the second control clock signal terminal into the first control terminal under the control of the first scanning voltage provided by the first scanning voltage terminal, and to write the first control clock signal provided by the first control clock signal terminal into the first control terminal under the control of the second scanning voltage provided by the second scanning voltage terminal.

7. The driving circuit according to claim 1, wherein: The first node control circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor is electrically connected to the input terminal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the first node; The gate of the second transistor is electrically connected to the first control clock signal terminal, and the first electrode of the second transistor is electrically connected to the first scan voltage terminal; The gate of the third transistor is electrically connected to the reset terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor; A gate of the fourth transistor is electrically connected to the second control clock signal terminal, and a second electrode of the fourth transistor is electrically connected to the second scan voltage terminal.

8. The driving circuit according to claim 5, wherein: The first control circuit includes a fifth transistor, and the second control circuit includes a sixth transistor; The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second output node, and the second electrode of the fifth transistor is electrically connected to the second voltage terminal; A gate of the sixth transistor is electrically connected to the first control terminal, a first electrode of the sixth transistor is electrically connected to the third voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second output node.

9. The driving circuit according to claim 6, wherein: The third control circuit includes a seventh transistor and an eighth transistor; The gate of the seventh transistor is electrically connected to the first scan voltage terminal, the first electrode of the seventh transistor is electrically connected to the second control clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the first control terminal; A gate of the eighth transistor is electrically connected to the second scan voltage terminal, a first electrode of the eighth transistor is electrically connected to the first control terminal, and a second electrode of the eighth transistor is electrically connected to the first control clock signal terminal.

10. The driving circuit according to claim 4, wherein: The on-off control circuit includes a ninth transistor; A gate of the ninth transistor is electrically connected to the first voltage terminal, a first electrode of the ninth transistor is electrically connected to the first node, and a second electrode of the ninth transistor is electrically connected to the first output node.

11. The driving circuit according to claim 2, wherein: Also included is an output reset circuit; The output reset circuit is electrically connected to the second output node, the driving output terminal and the fourth voltage terminal respectively, and is used to control the connection or disconnection between the driving output terminal and the fourth voltage terminal under the control of the potential of the second output node.

12. The driving circuit according to claim 11, wherein: The output circuit includes an output transistor, and the output reset circuit includes an output reset transistor; The gate of the output transistor is electrically connected to the first output node, the first electrode of the output transistor is electrically connected to the output clock signal terminal, and the second electrode of the output transistor is electrically connected to the driving output terminal; A gate of the output reset transistor is electrically connected to the second output node, a first electrode of the output reset transistor is electrically connected to the driving output terminal, and a second electrode of the output reset transistor is electrically connected to the fourth voltage terminal.

13. The driving circuit according to any one of claims 1 to 12, wherein: Also includes a first output control circuit and a second output node reset circuit; The first output control circuit is electrically connected to the first enable control terminal and the drive output terminal respectively, and is used to control the drive output terminal under the control of the first enable control signal provided by the first enable control terminal when the display panel is powered off. The terminal outputs a valid voltage signal; the display panel includes the driving circuit; The second output node reset circuit is electrically connected to the second output node, the first enable control terminal and the fifth voltage terminal, respectively, and is used to control the connection between the second output node and the fifth voltage terminal under the control of a first enable control signal provided by the first enable control terminal when the display panel is powered off.

14. The driving circuit according to any one of claims 1 to 12, wherein: Also comprising a second output control circuit; The second output control circuit is electrically connected to the second enable control terminal, the drive output terminal and the sixth voltage terminal, respectively, and is used to control the connection between the drive output terminal and the sixth voltage terminal in the touch stage, and to control the disconnection between the drive output terminal and the sixth voltage terminal in the display stage, under the control of the second enable control signal provided by the second enable control terminal.

15. The driving circuit according to claim 13, wherein: The first output control circuit includes a tenth transistor, and the second output node reset circuit includes an eleventh transistor; The gate of the tenth transistor is electrically connected to the first enable control terminal, the first electrode of the tenth transistor is electrically connected to the drive output terminal, and the second electrode of the tenth transistor is electrically connected to the first enable control terminal; A gate of the eleventh transistor is electrically connected to the first enable control terminal, a first electrode of the eleventh transistor is electrically connected to the second output node, and a second electrode of the eleventh transistor is electrically connected to the fifth voltage terminal.

16. The driving circuit according to claim 14, wherein: The second output control circuit includes a twelfth transistor; The gate of the twelfth transistor is electrically connected to the second enable control terminal, the first electrode of the twelfth transistor is electrically connected to the driving output terminal, and the second electrode of the twelfth transistor is electrically connected to the sixth voltage terminal.

17. The driving circuit according to any one of claims 1 to 12, wherein: Also includes a first node reset circuit, a first energy storage circuit and a second energy storage circuit; The first node reset circuit is electrically connected to the reset control terminal, the second output node, the first node and the seventh voltage terminal respectively, and is used to control the connection or disconnection between the first node and the seventh voltage terminal under the control of the potential of the second output node, and control the connection or disconnection between the first node and the seventh voltage terminal under the control of the reset control signal provided by the reset control terminal; The first energy storage circuit is electrically connected to the first output node and the driving output terminal respectively, and is used to store electric energy; The second energy storage circuit is electrically connected to the second output node and is used for storing electric energy.

18. The driving circuit according to claim 17, wherein: The first node reset circuit includes a thirteenth transistor and a fourteenth transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; The gate of the thirteenth transistor is electrically connected to the second output node, the first electrode of the thirteenth transistor is electrically connected to the first node, and the second electrode of the thirteenth transistor is electrically connected to the seventh voltage terminal; The gate of the fourteenth transistor is electrically connected to the reset control terminal, the first electrode of the fourteenth transistor is electrically connected to the first node, and the second electrode of the fourteenth transistor is electrically connected to the seventh voltage terminal; The first end of the first capacitor is electrically connected to the first output node, and the second end of the first capacitor is electrically connected to the driver node. The output terminal is electrically connected; A first end of the second capacitor is electrically connected to the second output node, and a second end of the second capacitor is electrically connected to the seventh voltage terminal.

19. A driving method, applied to the driving circuit according to any one of claims 1 to 18, the driving method comprising: The first node control circuit controls the connection or disconnection between the first node and the first scanning voltage terminal under the control of the first control clock signal and the input signal. The first node control circuit controls the connection or disconnection between the first node and the second scanning voltage terminal under the control of the second control clock signal and the reset signal.

20. The driving method according to claim 19, wherein: The driving circuit further includes a first control circuit, a second control circuit, a third control circuit, an on-off control circuit, an output circuit, an output reset circuit, a first node reset circuit, a first energy storage circuit and a second energy storage circuit; the display cycle includes a first stage, a second stage, a third stage and a fourth stage which are arranged in sequence; The driving method comprises: In the first stage, the first node control circuit controls the connection between the first node and the first scanning voltage terminal under the control of the first control clock signal and the input signal; the on-off control circuit controls the connection between the first node and the first output node under the control of the first voltage signal; the output circuit controls the writing of the output clock signal into the driving output terminal under the control of the potential of the first output node; the first control circuit controls the connection between the second output node and the second voltage terminal under the control of the potential of the first node; In the second stage, the output circuit controls the output clock signal to be written into the driving output terminal under the control of the potential of the first output node, and the first energy storage circuit bootstraps and pulls up the potential of the first node; the first control circuit controls the second output node to be connected to the second voltage terminal under the control of the potential of the first node; In the third stage, the first node control circuit controls the first node to be connected to the second scanning voltage terminal under the control of the second control clock signal and the reset signal; the third control circuit writes the second control clock signal to the first control terminal under the control of the first scanning voltage; the second control circuit controls the second output node to be connected to the third voltage terminal under the control of the first control signal; the output reset circuit controls the drive output terminal to be connected to the fourth voltage terminal under the control of the potential of the second output node; In the fourth stage, the output reset circuit controls the connection between the driving output terminal and the fourth voltage terminal under the control of the potential of the second output node.

21. The driving method according to claim 19, wherein: The driving circuit further includes a second output control circuit; and the driving method further includes: In the touch control stage, the second output control circuit controls the connection between the driving output terminal and the sixth voltage terminal under the control of the second enable control signal. In the display stage, the second output control circuit controls the drive output terminal and the sixth voltage terminal to be disconnected under the control of the second enable control signal.

22. The driving method according to claim 19, wherein: The driving circuit also includes a first output control circuit and a second output node reset circuit; The driving method further comprises: When the display panel is powered off, the first output control circuit controls the driving output terminal to output a valid voltage signal under the control of the first enable control signal; the second output node reset circuit controls the connection between the second output node and the fifth voltage terminal under the control of the first enable control signal.

23. A display device comprising the driving circuit according to any one of claims 1 to 18.

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