Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises data lines (210), gate lines (220), and fan-out wires (300). The data lines (210) comprise data line groups (2100) arranged in a first direction, each data line group (2100) comprises N data lines (210), and in each data line group (2100), the m-th data line (210) is electrically connected to the (m+N / 2)-th data line (210). The fan-out wires (300) comprise fan-out wire groups (3100) arranged in the first direction, each fan-out wire group (3100) comprises N / 2 fan-out wires (300), the fan-out wires (300) in the same fan-out wire group (3100) are electrically connected to the data lines (210) in the same data line group (2100), and the N / 2 fan-out wires (300) are electrically connected to the m-th data line (210) to the (m-1+N / 2)-th data line (210) in a one-to-one correspondence, respectively. Each data line (210) in at least one data line group (2100) is electrically connected to the corresponding fan-out wire (300) by means of first adapter parts (410), and the number of first adapter parts (410) by means of which the m-th data line (210) is electrically connected to the fan-out wire (300) is the same as the number of first adapter parts (410) by means of which the (m+N / 2)-th data line (210) is electrically connected to the fan-out wire (300). Thus, the risk of vertical lines caused by resistance differences can be avoided.

Description

Array substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202310930941.4 filed on July 27, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to an array substrate and a display device. Background Art

[0003] Display devices using dual gate technology reduce the number of data lines by half and double the number of gate lines to reduce the number of source driver integrated circuits (ICs) connected to the data lines by half and double the number of gate driver ICs connected to the gate lines, thereby reducing costs.

[0004] Summary of the Invention

[0005] Embodiments of the present disclosure provide an array substrate and a display device.

[0006] The present disclosure provides an array substrate comprising a display area and a non-display area located at least to one side of the display area. The array substrate includes: a plurality of sub-pixels located in the display area, a plurality of data lines, a plurality of gate lines, and a plurality of fan-out routing lines located in the non-display area. The plurality of data lines are arranged along a first direction; the plurality of gate lines are arranged along a second direction, with a gate line pair formed by two gate lines disposed between two adjacent sub-pixels arranged along the second direction, the first direction intersecting the second direction; and the plurality of fan-out routing lines are configured to be electrically connected to the plurality of data lines. The plurality of data lines include a plurality of data line groups arranged along the first direction, each data line group including N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; the plurality of fan-out routing lines include a plurality of fan-out routing lines groups arranged along the first direction, each fan-out routing line group including N / 2 fan-out routing lines, and the fan-out routing lines in the same fan-out routing line group are electrically connected to the data lines in the same data line group, and the N / 2 fan-out routing lines are electrically connected to the mth data line to the (m-1+N / 2)th data lines, respectively, in a one-to-one correspondence; each data line in at least one data line group is electrically connected to the corresponding fan-out routing line via at least one first transition portion, and in the at least one data line group, the number of the first transition portions through which the mth data line is electrically connected to the fan-out routing line is the same as the number of the first transition portions through which the (m+N / 2)th data line is electrically connected to the fan-out routing line.

[0007] For example, according to an embodiment of the present disclosure, the first transfer portion includes at least two first transfer holes, and in the at least one data line group, the number of the first transfer holes through which the mth data line is electrically connected to the fan-out routing is the same as the number of the first transfer holes through which the (m+N / 2)th data line is electrically connected to the fan-out routing.

[0008] For example, according to an embodiment of the present disclosure, the non-display area includes a first non-display area and a second non-display area respectively located on both sides of the display area in the second direction, and the multiple fan-out lines and the first transfer portion are all located in the first non-display area; the array substrate also includes an electrostatic release structure, and the electrostatic release structure includes a first electrostatic release structure and a second electrostatic release structure, wherein the first electrostatic release structure is located in the first non-display area, and the second electrostatic release structure is located in the second non-display area, and the first electrostatic release structure is located between the multiple data lines and the first transfer portion, and the multiple data lines are electrically connected to the multiple fan-out lines through the first electrostatic release structure and the first transfer portion; the multiple data lines are electrically connected to the second electrostatic release structure through multiple second transfer portions, and the second electrostatic release structure is located on a side of the second transfer portion away from the multiple data lines, and the number of the second transfer portions through which the mth data line is electrically connected to the second electrostatic release structure is the same as the number of the second transfer portions through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure.

[0009] For example, according to an embodiment of the present disclosure, each second transfer portion includes at least two second transfer holes, and the number of the second transfer holes through which the mth data line is electrically connected to the second electrostatic release structure is the same as the number of the second transfer holes through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure.

[0010] For example, according to an embodiment of the present disclosure, in the at least one fan-out routing group, two adjacent fan-out routings are respectively a first fan-out routing and a second fan-out routing, and the first fan-out routing and the second fan-out routing are arranged in different layers; a straight line extending along the first direction passes through the first transfer portion electrically connected to each fan-out routing in the at least one fan-out routing group.

[0011] For example, according to an embodiment of the present disclosure, the mth data line is electrically connected to the (m+N / 2)th data line through a first connecting line located in the first non-display area, the first connecting line is connected to the first transfer portion, and the first connecting line and the fan-out line electrically connected to it are arranged on the same layer.

[0012] For example, according to an embodiment of the present disclosure, the mth data line is electrically connected to the (m+N / 2)th data line through a second connecting line located in the second non-display area, and the second electrostatic release structure is connected to the second transfer portion through a third connecting line, and the third connecting line is arranged on the same layer as the second connecting line.

[0013] For example, according to an embodiment of the present disclosure, the first transfer part includes at least two layers of conductive parts and a first transfer hole; the at least two layers of conductive parts include three layers of conductive parts, including a first conductive part, a third conductive part, and a second conductive part stacked with the first conductive part and the third conductive part, and one of the first conductive part and the third conductive part is connected to the fan-out routing and is arranged on the same layer, or, the at least two layers of conductive parts include two layers of conductive parts, including a first conductive part and a second conductive part stacked with the first conductive part, and the first conductive part is connected to the fan-out routing and is arranged on the same layer.

[0014] For example, according to an embodiment of the present disclosure, each first transfer portion electrically connected to each fan-out routing in the at least one fan-out routing group includes two transfer sub-portions arranged along the second direction, the number of the first connecting routing is multiple, and at least one first connecting routing passes through the gap between the two transfer sub-portions included in the first transfer portion that is not connected to it.

[0015] For example, according to an embodiment of the present disclosure, each adapter sub-section includes two adapter blocks arranged along the second direction; in each first adapter section, the adapter block closest to the multiple data lines is arranged on the same layer as the data lines, the adapter block closest to the fan-out routing is arranged on the same layer as the fan-out routing connected to the adapter block, and the two adapter blocks in the middle are connected and arranged on the same layer.

[0016] For example, according to an embodiment of the present disclosure, in the at least one fan-out routing group, each fan-out routing is arranged on the same layer, and each first transfer portion electrically connected to each fan-out routing in the at least one fan-out routing group includes a three-layer conductive portion and a first transfer hole, the three-layer conductive portion includes a first sub-conductive portion, a second sub-conductive portion, and a third sub-conductive portion that is stacked with the first sub-conductive portion and the second sub-conductive portion, the first sub-conductive portion is located between the second sub-conductive portion and the multiple data lines, the data lines are arranged on the same layer as the first sub-conductive portion, and the fan-out routing is connected to the second sub-conductive portion and is arranged on the same layer.

[0017] For example, according to an embodiment of the present disclosure, the mth data line is electrically connected to the (m+N / 2)th data line through a first connecting route, the first connecting route is connected to the first transfer portion, and the first connecting route and the fan-out route electrically connected to it are arranged on the same layer; the number of the first connecting routes is multiple, and the multiple first connecting routes include at least two types of first connecting routes, one first connecting route includes a portion located on a side of the first transfer portion not connected to it away from the multiple data lines, and the other first connecting route includes a portion located on a side of the first transfer portion not connected to it close to the multiple data lines.

[0018] For example, according to an embodiment of the present disclosure, the second transfer part includes a three-layer conductive part and a second transfer hole, the three-layer conductive part includes a fourth sub-conductive part, a fifth sub-conductive part and a sixth sub-conductive part stacked with the fourth sub-conductive part and the fifth sub-conductive part, the fourth sub-conductive part is located between the fifth sub-conductive part and the multiple data lines, the data line is arranged on the same layer as the fourth sub-conductive part, the fifth sub-conductive part is arranged on the same layer as the second connecting trace, and the second connecting trace and the third connecting trace are both connected to the fifth sub-conductive part.

[0019] For example, according to an embodiment of the present disclosure, one of the first fan-out routing and the second fan-out routing is arranged on the same layer as the multiple data lines, and the other of the first fan-out routing and the second fan-out routing is arranged on the same layer as the multiple gate lines.

[0020] For example, according to an embodiment of the present disclosure, the second connecting wire and the third connecting wire are both provided on the same layer as the plurality of gate lines.

[0021] For example, according to an embodiment of the present disclosure, the mth data line is electrically connected to the (m+N / 2)th data line through a second connecting line located in the second non-display area, and the second electrostatic release structure is connected to the second transfer portion through a third connecting line, and the third connecting line and the second connecting line are located on different layers.

[0022] For example, according to an embodiment of the present disclosure, the array substrate further includes a detection signal line and a switch component located in the second non-display area. The detection signal line and the switch component are both located on a side of the second electrostatic discharge structure away from the display area, and the detection signal line is connected to the second electrostatic discharge structure via the switch component.

[0023] For example, according to an embodiment of the present disclosure, N is 12, and the multiple gate lines include a first gate line and a second gate line alternately arranged along the second direction, the six columns of sub-pixels electrically connected to the first data line to the sixth data line in the same data line group are electrically connected to the first gate line, and the six columns of sub-pixels electrically connected to the seventh data line to the twelfth data line in the same data line group are electrically connected to the second gate line.

[0024] For example, according to an embodiment of the present disclosure, at least one gate line is provided with a plurality of bends, and the plurality of bends include a plurality of first bends and a plurality of second bends alternately arranged along the first direction, and the orientation of the first bends is opposite to the orientation of the second bends; each sub-pixel includes a transistor, and each bend surrounds the transistor in N sub-pixels electrically connected to a data line group.

[0025] An embodiment of the present disclosure provides an array substrate, comprising a display area and a first non-display area and a second non-display area respectively located on both sides of the display area, the array substrate comprising: a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area, the plurality of data lines being arranged along a first direction; a plurality of gate lines located in the display area, the plurality of gate lines being arranged along a second direction, and a gate line pair formed by two gate lines being arranged between two adjacent sub-pixels arranged along the second direction, the first direction intersecting with the second direction; and a plurality of fan-out routing lines located in the first non-display area, the plurality of fan-out routing lines being configured to be electrically connected to the plurality of data lines. The multiple data lines include multiple data line groups arranged along the first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; the array substrate also includes an electrostatic release structure located in the second non-display area, the multiple data lines are electrically connected to the electrostatic release structure through multiple transition parts, and the electrostatic release structure is located on a side of the transition part away from the multiple data lines. In at least one data line group, the number of transition parts through which the mth data line is electrically connected to the electrostatic release structure is the same as the number of transition parts through which the (m+N / 2)th data line is electrically connected to the electrostatic release structure.

[0026] For example, according to an embodiment of the present disclosure, each adapter portion includes at least two adapter holes, and in the at least one data line group, the number of the adapter holes through which the mth data line is electrically connected to the electrostatic release structure is the same as the number of the adapter holes through which the (m+N / 2)th data line is electrically connected to the electrostatic release structure.

[0027] For example, according to an embodiment of the present disclosure, the mth data line is electrically connected to the (m+N / 2)th data line through a first sub-connection line located in the second non-display area, the electrostatic release structure is connected to the transfer part through a second sub-connection line, and the first sub-connection line and the second sub-connection line are arranged on the same layer.

[0028] For example, according to an embodiment of the present disclosure, the first sub-connection wiring and the second sub-connection wiring are both provided on the same layer as the gate line.

[0029] The present disclosure provides a display device comprising any of the above array substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0031] FIG1 is a schematic diagram of a partial planar structure of an array substrate provided according to an embodiment of the present disclosure.

[0032] FIG2 is a schematic planar structural diagram of some sub-pixels, data lines, and gate lines in the display area of ​​the array substrate shown in FIG1 .

[0033] FIG3 is a schematic diagram of a partial planar structure of a non-display area of ​​an array substrate where fan-out wiring is located.

[0034] FIG4 is a schematic diagram of a partial planar structure of the array substrate shown in FIG3 .

[0035] FIG. 5 is a circuit schematic diagram showing electrical connections between data lines and fan-out traces in the array substrate shown in FIG. 3 and FIG. 4 .

[0036] FIG. 6 is a schematic diagram of a partial structure of a first non-display area in the array substrate shown in FIG. 1 .

[0037] FIG. 7 is a circuit schematic diagram showing electrical connections between data lines and fan-out traces in the array substrate shown in FIG. 6 .

[0038] 8 and 9 are partial cross-sectional views taken along line AA′ and line BB′ shown in FIG. 6 , respectively.

[0039] FIG10 is a schematic diagram showing the positional relationship between the first adapter portion and the first connecting line according to another example of an embodiment of the present disclosure.

[0040] FIG11 is a schematic diagram showing the positional relationship among a first transfer portion, a first connecting trace, and a fan-out trace according to another example of an embodiment of the present disclosure.

[0041] FIG. 12 is a schematic diagram of a partial structure of the second non-display area shown in FIG. 1 in one example.

[0042] FIG13 is a partial enlarged view of the array substrate shown in FIG12 .

[0043] FIG. 14 is a circuit schematic diagram showing electrical connection between the data line and the second electrostatic discharge structure in the array substrate shown in FIG. 13 .

[0044] FIG. 15 is a schematic diagram of a partial structure of the second non-display area in the array substrate shown in FIG. 1 in another example.

[0045] FIG. 16 is a circuit schematic diagram showing electrical connection between the data line and the second electrostatic discharge structure in the array substrate shown in FIG. 15 .

[0046] FIG17 is a schematic block diagram of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are simply used to distinguish different components. The terms "include" or "comprises" and similar terms mean that the element or object preceding the term includes the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The characteristics of "parallel," "perpendicular," and "same" used in the embodiments of this disclosure include the characteristics of "parallel," "perpendicular," and "same" in the strict sense, as well as "approximately parallel," "approximately perpendicular," and "approximately the same" that include certain errors, taking into account the errors associated with the measurement of specific quantities (for example, the limitations of the measurement system), and represent the acceptable deviation range for a specific value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the stated value. When the number of a component is not specifically specified below in the embodiments of this disclosure, it means that the component can be one or more, or can be understood as at least one. "At least one" means one or more, and "a plurality" means at least two. As used herein, "same-layer arrangement" refers to a structure in which two (or more) structures are formed through the same deposition process and patterned through the same patterning process, and the materials used for the structures may be the same or different. As used herein, "integrated arrangement" refers to a structure in which two (or more) structures are formed through the same deposition process and patterned through the same patterning process, and the materials used for the structures may be the same or different.

[0049] The present disclosure provides an array substrate and a display device. The array substrate includes a display area and a non-display area located on at least one side of the display area. The array substrate includes a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines located in the display area, as well as a plurality of fan-out lines located in the non-display area. The plurality of data lines are arranged along a first direction; the plurality of gate lines are arranged along a second direction, and a gate line pair formed by two gate lines is provided between two adjacent sub-pixels arranged along the second direction, with the first direction intersecting the second direction; and the plurality of fan-out lines are configured to be electrically connected to the plurality of data lines. The multiple data lines include multiple data line groups arranged along a first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; the multiple fan-out routing lines include multiple fan-out routing lines groups arranged along the first direction, each fan-out routing line group includes N / 2 fan-out routing lines, and the fan-out routing lines in the same fan-out routing line group are electrically connected to the data lines in the same data line group, and the N / 2 fan-out routing lines are electrically connected to the mth data line to the (m-1+N / 2)th data line in a one-to-one correspondence; each data line in at least one data line group is electrically connected to the corresponding fan-out routing line through at least one first adapter, and in at least one data line group, the number of first adapters through which the mth data line is electrically connected to the fan-out routing line is the same as the number of first adapters through which the (m+N / 2)th data line is electrically connected to the fan-out routing line.

[0050] By setting the number of first adapters through which different data lines are electrically connected to the fan-out lines to be the same, it is beneficial to reduce the difference in transmission resistance of different data lines, thereby avoiding the risk of vertical stripes caused by the resistance difference.

[0051] The present disclosure provides another array substrate, comprising a display area and a first non-display area and a second non-display area, respectively, located on either side of the display area. The array substrate includes: a plurality of sub-pixels located in the display area, a plurality of gate lines, and a plurality of fan-out routing lines located in the first non-display area. The plurality of data lines are arranged along a first direction; the plurality of gate lines are arranged along a second direction, with a gate line pair formed by two gate lines disposed between two adjacent sub-pixels arranged along the second direction, with the first direction intersecting the second direction; and the plurality of fan-out routing lines are configured to be electrically connected to the plurality of data lines. The multiple data lines include multiple data line groups arranged along a first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; the array substrate also includes an electrostatic release structure, the electrostatic release structure includes a first electrostatic release structure and a second electrostatic release structure, the first electrostatic release structure is located in a first non-display area and between the multiple data lines and the multiple fan-out lines, the second electrostatic release structure is located in a second non-display area, the multiple data lines are electrically connected to the second electrostatic release structure through multiple transition parts, the second electrostatic release structure is located on a side of the transition part away from the multiple data lines, and in at least one data line group, the number of transition parts through which the mth data line is electrically connected to the second electrostatic release structure is the same as the number of transition parts through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure.

[0052] By setting the number of second transition portions through which each data line is electrically connected to the second electrostatic release structure to be the same, the difference in on-resistance between the far end of each data line and the second electrostatic release structure can be minimized, thereby reducing the risk of specific defects.

[0053] The array substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0054] FIG1 is a schematic diagram of a partial planar structure of an array substrate provided according to an embodiment of the present disclosure.

[0055] As shown in FIG1 , the array substrate includes a display area 10 and a non-display area 20 located on at least one side of the display area 10. For example, the non-display area 20 may be located on one side of the display area 10, or on both sides of the display area 10, or surround the display area 10.

[0056] As shown in FIG1 , the array substrate includes a plurality of sub-pixels 100 located in a display area 10, a plurality of data lines 210, a plurality of gate lines 220, and a plurality of fan-out traces 300 located in a non-display area 20. For example, the array substrate includes a base substrate 01, and the sub-pixels 100, the data lines 210, the gate lines 220, and the fan-out traces 300 are all base substrate 01. For example, the area where the sub-pixels 100 are located may be the area defined by the intersection of the data lines 210 and the gate lines 220.

[0057] FIG2 is a schematic planar structural diagram of some sub-pixels, data lines, and gate lines in the display area of ​​the array substrate shown in FIG1 .

[0058] For example, as shown in Figure 2, each sub-pixel 100 may include a pixel electrode 110 and a common electrode (not shown), and the common electrode may be an electrode shared by multiple sub-pixels 100. For example, each sub-pixel 100 includes a transistor 120, for example, the transistor 120 may be a thin film transistor 120. According to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. The transistor provided in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor according to actual needs. For example, the gate of the transistor 120 is electrically connected to the gate line 220, one of the source and drain of the transistor 120 is electrically connected to the data line 210, and the other of the source and drain of the transistor 120 is electrically connected to the pixel electrode 110. For example, the gate line 220 controls the opening or closing of the transistor 120, and the data line 210 inputs the voltage signal required for displaying the picture to the pixel electrode 110 of the sub-pixel 100 through the transistor 120 to realize the display of the display device including the display substrate.

[0059] For example, the plurality of sub-pixels 100 may include sub-pixels of different colors, such as a blue sub-pixel that displays blue light, a green sub-pixel that displays green light, and a red sub-pixel that displays red light. Of course, the plurality of sub-pixels may also include white sub-pixels. FIG1 schematically illustrates the plurality of sub-pixels 100 including red sub-pixels, green sub-pixels, and blue sub-pixels that are repeatedly arranged in sequence along a first direction, such as the X direction, where three adjacent sub-pixels of different colors form a pixel.

[0060] As shown in FIG1 , a plurality of data lines 210 are arranged along a first direction, and a plurality of gate lines 220 are arranged along a second direction, with the first direction and the second direction intersecting. FIG1 schematically illustrates that the first direction is the X direction and the second direction is the Y direction. However, this is not limiting, and the first and second directions can be interchangeable. For example, the angle between the first and second directions is 80 to 110 degrees. For example, the first direction is perpendicular to the second direction.

[0061] As shown in FIG1 , a gate line pair formed by two gate lines 220 is disposed between two adjacent sub-pixels 100 arranged along the second direction. For example, the plurality of gate lines 220 includes a first gate line 221 and a second gate line 222 alternately disposed along the second direction. For example, the gate line pair includes the first gate line 221 and the second gate line 222.

[0062] As shown in FIG1 , the plurality of data lines 210 include a plurality of data line groups 2100 arranged along a first direction. Each data line group 2100 includes N data lines. In each data line group 2100, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2. In the array substrate provided by the present disclosure, the mth data line in each data line group is electrically connected to the (m+N / 2)th data line, equivalent to each data line group including only N / 2 data lines, thereby halving the number of data lines. N is an even number.

[0063] For example, as shown in FIG1 , a plurality of sub-pixels 100 can be arranged in an array along a first direction and a second direction. For example, the sub-pixels 100 arranged along the Y direction can be a column of sub-pixels, and the plurality of sub-pixels 100 include multiple columns of sub-pixels. For example, each column of sub-pixels is electrically connected to a data line 210. For example, the multiple columns of sub-pixels include multiple sub-pixel column groups, and the multiple sub-pixel column groups are electrically connected to the multiple data line groups 2100 in a one-to-one correspondence. For example, each sub-pixel column group includes N columns of sub-pixels, and in each sub-pixel column group, the data line 210 electrically connected to the mth column of sub-pixels and the data line 210 electrically connected to the (m+N / 2)th column of sub-pixels are electrically connected to each other, such as end-to-end, and the mth column of sub-pixels and the (m+N / 2)th column of sub-pixels are electrically connected to the first gate line 221 and the second gate line 222, respectively. This is equivalent to each sub-pixel column group being electrically connected to only N / 2 data lines, which helps to reduce the number of data lines, thereby reducing the number of source driver chips, thereby reducing costs. However, the present invention is not limited thereto, and multiple sub-pixels may also be arranged in other ways, such as a triangle arrangement, a diamond arrangement, etc., which can be set according to needs.

[0064] As shown in Figure 1, multiple fan-out traces 300 are configured to be electrically connected to multiple data lines 210. The multiple fan-out traces 300 include multiple fan-out trace groups 3100 arranged along a first direction. Each fan-out trace group 3100 includes N / 2 fan-out traces, and the fan-out traces 300 in the same fan-out trace group 3100 are electrically connected to the data lines 210 in the same data line group 2100. The N / 2 fan-out traces 300 are respectively electrically connected to the mth data line to the (m-1+N / 2)th data line in a one-to-one correspondence. In the array substrate provided by the present disclosure, the mth data line in each data line group is electrically connected to the (m+N / 2)th data line, and the routing lines in the fan-out routing group are electrically connected to the mth data line to the (m-1+N / 2)th data line in a one-to-one correspondence, so that the number of routing lines in the fan-out routing group corresponding to each data line group is N / 2, which is equivalent to each data line group including only N / 2 data lines, so as to achieve halving the number of data lines while halving the number of fan-outs in the fan-out routing group, which is beneficial to reducing the resistance difference caused by the length difference of different fan-out routing lines.

[0065] In some examples, as shown in FIG1 and FIG2 , N is 12, and m is a positive integer not greater than 6, for example, m can be 1, 2, 3, 4, 5, or 6. The six columns of sub-pixels 100 electrically connected to the first to sixth data lines in the same data line group 2100 are electrically connected to the first gate line 221, and the six columns of sub-pixels 100 electrically connected to the seventh to twelfth data lines in the same data line group 2100 are electrically connected to the second gate line 222.

[0066] For example, as shown in Figures 1 and 2, 12 adjacent columns of sub-pixels constitute a sub-pixel column group. For example, three adjacent sub-pixels of different colors arranged along the X direction form a pixel, and a sub-pixel column group includes four columns of pixels. For example, the array substrate shown in Figure 1 can be used in FHD (Full High Definition) HADS (High Advanced-Super Dimensional Switching) display devices, where FHD stands for Full High Definition and HADS stands for Advanced Super Dimensional Switching.

[0067] For example, as shown in Figures 1 and 2, a display device including the array substrate shown in Figure 1 can be driven using a column inversion method. The column inversion method refers to inverting the polarity of the displayed data every predetermined number of sub-pixel columns. With the column inversion method, the polarity of the data signal on each data line is always the same polarity (positive or negative) in a frame. As shown in Figure 1, the voltage polarity stored in the two sub-pixel columns connected to the same data line 210 is the same, and the voltage polarity stored in the two sub-pixel columns connected to two adjacent data lines 210 is opposite. Therefore, although the m-th column sub-pixel and the (m+3)-th column sub-pixel are configured to display the same color light, the two data lines connected to the m-th column sub-pixel and the (m+3)-th column sub-pixel transmit data signals of opposite polarities, while the m-th column sub-pixel and the (m+6)-th column sub-pixel are configured to display the same color light, and the data lines electrically connected to these two columns of sub-pixels transmit data signals of the same polarity, then the data lines electrically connected to the m-th column sub-pixel and the (m+6)-th column sub-pixel are connected end to end respectively, thereby halving the number of data signal lines and avoiding problems such as head shake wrinkles, fine lines (Fine-pitch), and high power consumption of color mixing.

[0068] 1 , the number N of data lines 210 in the data line group 2100 is not less than 4. For example, N may be an even number such as 6 or 8, and may be set according to product requirements.

[0069] By arranging the data lines into data line groups, the thin-film transistors of each sub-pixel can be electrically connected to the data line closest to it. This prevents the problem of the thin-film transistors of a sub-pixel being unable to connect to its nearest data line when the thin-film transistors of adjacent sub-pixels are electrically connected to their corresponding data lines, resulting in large differences in the length of the connection structures between the thin-film transistors of adjacent sub-pixels and their corresponding data lines. The array substrate shown in Figure 1 has the characteristics of low cost, low power consumption, and high aperture ratio.

[0070] Figure 3 is a schematic diagram of a partial planar structure of a non-display area of ​​an array substrate where fan-out wiring is located. Figure 4 is a schematic diagram of a partial planar structure of the array substrate shown in Figure 3 .

[0071] The array substrate shown in FIG. 3 and FIG. 4 has the sub-pixels 100 , the data lines 210 , and the gate lines 220 in the display area shown in FIG. 1 and FIG. 2 .

[0072] As shown in Figures 3 and 4, the array substrate further includes an electrostatic discharge unit 50. The data lines 210 are electrically connected to the fan-out traces 300 via the electrostatic discharge unit (ESD) 50, or the data lines 210 are electrically connected to the fan-out traces 300 via the electrostatic discharge unit 50 and the adapter 51. Taking the connection of 12 adjacent data lines 210 to 6 adjacent fan-out traces 300 as an example, the adjacent two data lines 210 transmit data signals of different polarities, and the mth data line 210 is electrically connected to the (m+6)th data line 210 via the connecting trace 51.

[0073] As shown in FIG3 and FIG4 , among the plurality of fan-out traces 300 , two adjacent fan-out traces 31 and 32 are located in different layers. For example, the fan-out trace 31 is arranged on the same layer as the data line 210 , and the fan-out trace 32 is arranged on the same layer as the gate line 220 .

[0074] Figure 5 is a circuit diagram showing the electrical connection between the data lines and the fan-out wiring in the array substrate shown in Figures 3 and 4. Figure 4 schematically shows the positions of 12 adjacent data lines S1 to S12.

[0075] During the study, the inventors of the present application found that: as shown in Figures 3 and 4, the first data line S1 is directly connected to the fan-out trace 31, and the seventh data line S7 is electrically connected to the same fan-out trace 31 through two adapters 41; the second data line S2 is electrically connected to the fan-out trace 32 through a adapter 41, and the eighth data line S8 is electrically connected to the same fan-out trace 32 through a adapter 41; the third data line S3 is directly connected to the fan-out trace 31, and the ninth data line S9 is electrically connected to the same fan-out trace 31 through two adapters 41. 1; the fourth data line S4 is electrically connected to the fan-out trace 32 through a transfer portion 41, and the tenth data line S10 is electrically connected to the same fan-out trace 32 through a transfer portion 41; the fifth data line S5 is electrically connected to the fan-out trace 31 through two transfer portions 41, and the eleventh data line S11 is directly connected to the same fan-out trace 31; the sixth data line S6 is electrically connected to the fan-out trace 32 through a transfer portion 41, and the twelfth data line S12 is electrically connected to the same fan-out trace 32 through a transfer portion 41.

[0076] As shown in Figures 3 to 5, only an electrostatic discharge unit 50 is provided between the 1st data line S1, the 3rd data line S3 and the 11th data line S11 and the corresponding fan-out wiring 300, and the two adapter portions 41 provided between the 7th data line S7, the 9th data line S9 and the 5th data line S5 and the corresponding fan-out wiring 300 are equivalent to two resistors R0 and R1; a adapter portion 41 provided between the 2nd data line S2, the 4th data line S4 and the 6th data line S6 and the corresponding fan-out wiring 300 is equivalent to a resistor R2, and a adapter portion 41 provided between the 8th data line S8, the 10th data line S10 and the 12th data line S12 and the corresponding fan-out wiring 300 is equivalent to a resistor R3.

[0077] The overall resistance of different data lines and corresponding fan-out traces is different. For example, the data signal required by data line S1 is directly transmitted into the display area without passing through the adapter; while the data signal required by data line S7 connected to data line S1 needs to pass through two additional adapters before entering the display area. The adapter includes at least two stacked conductive layers, and the two conductive layers are electrically connected through vias. Compared with the resistance of the metal connection trace, the resistance of the adapter is larger. For example, the resistance of a adapter is usually above 50Ω, while the resistance of a metal connection trace is only 5Ω. Therefore, even if the data signal transmitted from the fan-out trace to the data line S1 and the data line S7 is the same, during the data signal transmission process, the signal resistance difference can reach at least 100Ω for the sub-pixel electrically connected to the data line S1 and the sub-pixel electrically connected to the data line S7, resulting in a significant increase in the risk of vertical stripes.

[0078] Therefore, among the data signals transmitted from the fan-out traces to the data lines, some data signals are directly transmitted into the display area, while some data signals need to pass through one or two additional adapters before entering the display area. Therefore, the resistance differences corresponding to different data lines cause the risk of vertical stripes to increase significantly.

[0079] Figure 6 is a schematic diagram of a partial structure of the first non-display area of ​​the array substrate shown in Figure 1. Figure 6 schematically illustrates the positions of data lines S1 through S12. The structure of the first adapter portion of the array substrate shown in Figure 6 on the side away from the fan-out traces can have the same features as the structure of the first adapter portion of the array substrate shown in Figure 3 on the side away from the fan-out traces.

[0080] As shown in Figures 1 and 6, each data line 210 in at least one data line group 2100 is electrically connected to the corresponding fan-out routing 300 through at least one first transfer portion 410. In at least one data line group 2100, the number of first transfer portions 410 through which the m-th data line 210 is electrically connected to the fan-out routing 300 is the same as the number of first transfer portions 410 through which the (m+N / 2)-th data line 210 is electrically connected to the fan-out routing 300.

[0081] The array substrate provided by the present disclosure helps reduce the load difference of the signal lines electrically connected to at least two columns of sub-pixels by arranging the data lines connected to each other to be electrically connected to the corresponding fan-out lines through the same number of first adapters, thereby reducing the risk of vertical stripes caused by resistance differences.

[0082] For example, as shown in FIG1 and FIG6, different data lines 210 are electrically connected to the corresponding fan-out lines 300 through the same number of first adapters 410, which helps to reduce the transmission resistance difference between different data lines and thus avoid the risk of vertical stripes caused by resistance differences.

[0083] In some examples, as shown in FIG6 , the first transfer portion 410 includes at least two first transfer holes 4100. In at least one data line group 2100, the number of first transfer holes 4100 through which the mth data line 210 is electrically connected to the fan-out trace 300 is the same as the number of first transfer holes 4100 through which the (m+N / 2)th data line 210 is electrically connected to the fan-out trace 300. By arranging the data lines connected to each other to be electrically connected to the same fan-out trace through the same number of first transfer holes, it is advantageous to achieve consistent loads for the signal lines electrically connected to at least two columns of sub-pixels, thereby avoiding the risk of vertical streaks caused by resistance differences.

[0084] For example, as shown in FIG. 6 , each first transition portion 410 includes the same number of first transition holes 4100 .

[0085] In some examples, as shown in FIG1 and FIG6 , the non-display area 20 includes a first non-display area 21 and a second non-display area 22, respectively located on either side of the display area 10 in the second direction. The plurality of fan-out traces 300 and the first transition portion 410 are both located in the first non-display area 21. The array substrate further includes an electrostatic discharge structure 500, the electrostatic discharge structure 500 including a first electrostatic discharge structure 510 located in the first non-display area 21. The first electrostatic discharge structure 510 is located in the plurality of data lines 210, such as between the data lines 210 disposed in the display area and the first transition portion 410. The plurality of data lines 210 are electrically connected to the plurality of fan-out traces 300 via the first electrostatic discharge structure 510 and the first transition portion 410.

[0086] FIG. 7 is a circuit schematic diagram showing electrical connections between data lines and fan-out traces in the array substrate shown in FIG. 6 .

[0087] For example, as shown in Figures 6 and 7, the electrostatic discharge structure 500 also includes an electrostatic ring (Shorting Ring, SR) 501, such as the first electrostatic discharge structure 510 includes multiple sub-electrostatic discharge structures, each sub-electrostatic discharge structure may include multiple transistors M, such as including two transistors M9 and M11 or two transistors M13 and M15; Each sub-electrostatic discharge structure is connected to a data line 210, and multiple sub-electrostatic discharge structures are all connected to the electrostatic ring 501. When there is a larger impact current on the data line, the transistor in the sub-electrostatic discharge structure can be opened to further discharge the larger impact current to the electrostatic ring. When there is a larger impact current on the electrostatic ring, the sub-electrostatic discharge structure may also be opened, and current can be transmitted to the data line.

[0088] For example, as shown in Figures 1 and 6, a dummy gate area (not shown) can be further provided between the display area 10 and the electrostatic discharge structure 500 to make the load of the GOA (Gate Driven on Array) Reset unit close to the load of the display area gate line. For example, a common electrode trace (not shown) can be further provided between the dummy gate area and the electrostatic discharge structure 500 to be electrically connected to the common signal line in the display area to provide a planar distributed VCOM signal. For example, a pad is provided on the side of the fan-out trace 300 away from the display area 10 to achieve binding with the circuit board.

[0089] In some examples, as shown in FIG6 , in at least one fan-out routing group 3100 , two adjacent fan-out routings 300 are respectively a first fan-out routing 310 and a second fan-out routing 320 , and the first fan-out routing 310 and the second fan-out routing 320 are arranged in different layers. For example, the first fan-out routing 310 and the second fan-out routing 320 are arranged alternately.

[0090] In some examples, as shown in FIG6 , one of the first fan-out trace 310 and the second fan-out trace 320 is disposed on the same layer as the plurality of data lines 210, and the other of the first fan-out trace 310 and the second fan-out trace 320 is disposed on the same layer as the plurality of gate lines 220. FIG6 schematically illustrates that the first fan-out trace 310 is disposed on the same layer as the data lines, and the second fan-out trace 320 is disposed on the same layer as the gate lines, but the present invention is not limited thereto, and the first fan-out trace and the second fan-out trace may be interchangeable.

[0091] For example, as shown in FIG6 , the first data line S1 is electrically connected to the first fan-out trace 310 through two first transfer portions 410, and the seventh data line S7 is electrically connected to the same first fan-out trace 310 through two first transfer portions 410; the second data line S2 is electrically connected to the second fan-out trace 320 through two first transfer portions 410, and the eighth data line S8 is electrically connected to the same second fan-out trace 320 through two first transfer portions 410; the third data line S3 is electrically connected to the first fan-out trace 310 through two first transfer portions 410, and the ninth data line S9 is electrically connected to the same first fan-out trace 310 through two first transfer portions 410. The fourth data line S4 is electrically connected to the second fan-out trace 320 through two first transfer portions 410, and the tenth data line S10 is electrically connected to the same second fan-out trace 320 through two first transfer portions 410; the fifth data line S5 is electrically connected to the first fan-out trace 310 through two first transfer portions 410, and the eleventh data line S11 is electrically connected to the same first fan-out trace 310 through two first transfer portions 410; the sixth data line S6 is electrically connected to the second fan-out trace 320 through two first transfer portions 410, and the twelfth data line S12 is electrically connected to the same second fan-out trace 320 through two first transfer portions 410.

[0092] For example, as shown in Figures 1, 6, and 7, the same number of first transfer portions 410 are provided between the mth data line Sm and the S(m+6)th data line and the corresponding fan-out trace 300. For example, if two first transfer portions 410 are provided, the two first transfer portions 410 provided between the mth data line Sm and the corresponding fan-out trace 300 are equivalent to two resistors R4 and R5, and the two first transfer portions 410 provided between the S(m+6)th data line and the corresponding fan-out trace 300 are equivalent to two resistors R6 and R7. As a result, the overall resistance of different data lines and the corresponding fan-out traces is substantially consistent, which helps reduce the risk of vertical streaks.

[0093] In some examples, as shown in FIG6 , a straight line extending along the first direction passes through a first transition portion 410 electrically connected to each fan-out trace 300 in at least one fan-out trace group 3100. For example, the straight line may pass through the geometric center of the first transition portion 410 electrically connected to each fan-out trace 300 in at least one fan-out trace group 3100. For example, the straight line may pass through an edge of the first transition portion 410 electrically connected to each fan-out trace 300 in at least one fan-out trace group 3100. For example, the straight line may pass through a first transition hole 4100 in the first transition portion 410 electrically connected to each fan-out trace 300 in at least one fan-out trace group 3100.

[0094] For example, as shown in Figure 6, the plurality of first transition portions 410 connected to the fan-out traces 300 of each fan-out trace group 3100 are arranged along a first direction. For example, the edges of the plurality of first transition portions 410 connected to the fan-out traces 300 of each fan-out trace group 3100 that are closest to the display area and that are parallel to the first direction are substantially located on the same straight line, and the edges of the plurality of first transition portions 410 connected to the fan-out traces 300 of each fan-out trace group 3100 that are farthest from the display area and that are parallel to the first direction are substantially located on the same straight line.

[0095] For example, the first adapter portion 410 shown in Figure 6 can have the same shape and size as the adapter portion 41 shown in Figure 4. Compared with the arrangement of the adapter portion 41 connected to the data line S1 to the data line S12 shown in Figure 4, the arrangement of the first adapter portion 410 provided in the present disclosure as shown in Figure 6 only increases by less than 40 microns in the second direction, such as less than 35 microns, such as 34 microns, which has little impact on the product frame and can be basically ignored.

[0096] In some examples, as shown in FIG6 , the mth data line 210 is electrically connected to the (m+N / 2)th data line 210 via a first connecting trace 610 located in the first non-display area. The first connecting trace 610 is connected to the first transfer portion 410. The first connecting trace 610 and the fan-out trace 300 electrically connected thereto are disposed on the same layer. For example, there may be multiple first connecting traces 610, some of which may be disposed on the same layer as the data line 210, and other portions of which may be disposed on the same layer as the gate line 220.

[0097] In some examples, as shown in FIG6 , each first transfer portion 410 electrically connected to each fan-out trace 300 in at least one fan-out trace group 3100 includes two transfer sub-portions 4101 arranged along the second direction. For example, the two transfer sub-portions 4101 are electrically connected. For example, a gap is provided between the two transfer sub-portions 4101.

[0098] 6 , the first connection trace 610 and the fan-out trace 300 are both electrically connected to the transfer sub-section 4101, whichever is closer to the fan-out trace 300, of the two transfer sub-sections 4101. For example, a portion of the transfer sub-section 4101 and the first connection trace 610 and the fan-out trace 300 connected thereto may be an integrated structure.

[0099] In some examples, as shown in FIG6 , there are multiple first connecting traces 610, and at least one first connecting trace 610 passes through the gap between two transfer sub-sections 4101 included in a first transfer portion 410 that is not connected to the first connecting trace 610. For example, a portion of the multiple first connecting traces 610 is located between the first transfer portion 410 and the fan-out trace 300, while another portion of the multiple first connecting traces 610 passes through the gap between two transfer sub-sections 4101 included in at least one first transfer portion 410. This helps to reduce the space occupied by the first transfer portion and the first connecting traces, thereby reducing the impact on the product frame.

[0100] For example, as shown in Figure 6, the more of the N first transition portions 410 connected to the N data lines in the same data line group that overlap with the first connection trace 610, the smaller the distance between the first electrostatic discharge structure 510 and the fan-out trace 300 can be set, and the smaller the impact on the frame. For example, the first transition portion 410 connected to the second data line S2 to the first transition portion 410 connected to the eleventh data line S11 all overlap with the first connection trace 610, which helps to minimize the distance between the first electrostatic discharge structure 510 and the fan-out trace 300.

[0101] For example, as shown in Figure 6, the distance between two adjacent first transfer portions 410 is greater than the line width of the two first connecting traces 610, so that the first connecting trace can pass through the gap between the two adjacent first transfer portions 410 and connect to the transfer block 4102 in the first transfer portion 410 close to the fan-out trace 300.

[0102] In some examples, as shown in FIG6 , each adapter sub-section 4101 includes two adapter blocks 4102 arranged along the second direction. For example, the two adapter blocks 4102 included in the same adapter sub-section 4101 are spaced apart. For example, the two adapter blocks 4102 included in the same adapter sub-section 4101 can be arranged on the same layer or on different layers. For example, the size of each adapter block 4102 in the X direction is larger than the size in the Y direction, so as to maintain a good electrical connection while reducing the size in the Y direction and reducing the impact on the frame.

[0103] In some examples, as shown in FIG6 , in each first adapter portion 410, the adapter block 4102 closest to the plurality of data lines is arranged on the same layer as the data lines, the adapter block 4102 closest to the fan-out trace 300 is arranged on the same layer as the fan-out trace 300 connected to the adapter block 4102, and the two adapter blocks 4102 located in the middle are connected and arranged on the same layer. For example, a connection structure is provided between the two adapter sub-sections 4101 included in the same first adapter portion 410, and the connection structure can be an integrated structure with the two adapter blocks 4102 located in the middle. For example, the two adapter blocks 4102 located in the middle can be arranged on the same layer as the data lines 210 or the gate lines 220.

[0104] For example, as shown in FIG6 , a connection structure is provided between two transfer sub-sections 4101 included in the same first transfer section 410. The first connection trace 610 can overlap with the connection structure. For example, the connection structure can be provided on the same layer as the data line 210 or the gate line 220. For example, the dimension of the connection structure in the Y direction is greater than the line width of the first connection trace 610. For example, the dimension of the connection structure in the X direction is smaller than the dimension of the transfer block 4102 in the X direction, so as to reduce the overlapping area between the connection structure and the first connection trace.

[0105] 8 and 9 are partial cross-sectional views taken along line AA′ and line BB′ shown in FIG. 6 , respectively.

[0106] In some examples, as shown in FIG. 6 , FIG. 8 , and FIG. 9 , each first transfer portion 410 includes at least two layers of conductive portions and a first transfer hole 4100 located between two stacked layers of the at least two layers of conductive portions.

[0107] In some examples, as shown in Figures 6 and 8 , the at least two layers of conductive portions include three layers of conductive portions, including a first conductive portion 411, a third conductive portion 413, and a second conductive portion 412 stacked with both the first conductive portion 411 and the third conductive portion 413. One of the first conductive portion 411 and the third conductive portion 413 is connected to the fan-out trace 300 and disposed on the same layer. Figures 6 and 8 schematically illustrate that the third conductive portion 413 is connected to the fan-out trace 300 and disposed on the same layer, but are not limited thereto. In other first transition portions, the first conductive portion is connected to the fan-out trace and disposed on the same layer.

[0108] For example, as shown in Figure 8, the array substrate includes an insulating layer 02 located between the first conductive part 411 and the third conductive part 413, and an insulating layer 03 located between the first conductive part 411 and the second conductive part 412. The second conductive part 412 is located on the side of the first conductive part 411 away from the base substrate 01, and the third conductive part 413 is located between the first conductive part 411 and the base substrate 01.

[0109] For example, as shown in FIG8 , the first conductive portion 411 is disposed on the same layer as the data line, the third conductive portion 413 is disposed on the same layer as the gate line, and the second conductive portion 412 is disposed on the same layer as the common electrode of the sub-pixel. Of course, the disclosed embodiments are not limited thereto, and the first conductive portion and the third conductive portion can be interchangeable. For example, the connection structure between the two third conductive portions 413 overlaps with the first connecting trace 610, and the first connecting trace 610 is located on the side of the third conductive portion 413 away from the base substrate 01.

[0110] In some examples, as shown in Figures 6 and 9, the at least two layers of conductive portions include two layers of conductive portions, including a first conductive portion 411 and a second conductive portion 412 stacked with the first conductive portion 411. The first conductive portion 411 is connected to the fan-out trace 300 and is disposed on the same layer. For example, the first conductive portion 411 is disposed on the same layer as the data line, and the second conductive portion 412 is disposed on the same layer as the common electrode of the sub-pixel. For example, the connection structure between the two first conductive portions 411 overlaps with the first connecting trace 610, and the first connecting trace 610 is located between the first conductive portion 411 and the base substrate 01.

[0111] For example, as shown in Figures 6 to 9, the adapter block 4102 can be a first conductive portion 411 or a third conductive portion 413. For example, the adapter block 4102 closest to the data line can be a first conductive portion 411. For example, the adapter block 4102 connected to the first fan-out trace 310 and arranged on the same layer can be a first conductive portion 411, and the adapter block 4102 connected to the second fan-out trace 320 and arranged on the same layer can be a third conductive portion 413. For example, the two adapter blocks 4102 located in the middle can be equipped with either the first conductive portion 411 or the third conductive portion 413 as required.

[0112] For example, as shown in FIG6 , among the plurality of first transition portions 410 connected to data lines S1 to S12, a first portion of the first transition portions 410 do not overlap with the first connection traces 610, a second portion of the first transition portions 410 overlaps with one first connection trace 610, and a third portion of the first transition portions 410 overlaps with two first connection traces 610. For example, the first transition portions 410 connected to data lines S1 and S12 do not overlap with the first connection traces 610, the first transition portions 410 connected to data lines S2, S3, S6, S7, S10, and S11 overlap with one first connection trace 610, and the first transition portions 410 connected to data lines S4, S5, S8, and S9 overlap with two first connection traces 610. For example, two adjacent first transfer portions 410 overlap with two first connection traces 610 , and the first transfer traces 610 overlapping with the two adjacent first transfer portions 410 are all disposed in the same layer.

[0113] For example, as shown in FIG6 , a first connecting trace 610 connecting data line S1 and data line S7 is disposed on a different layer than a first connecting trace 610 connecting data line S12 and data line S6 and is substantially symmetrically distributed about an axis of symmetry between data line S6 and data line S7. For example, both first connecting traces 610 overlap with the first transition portion 410.

[0114] In some examples, as shown in Figures 2 and 3, at least one gate line 220 is provided with multiple curved portions 2200. The multiple curved portions 2200 include multiple first curved portions 2201 and multiple second curved portions 2202 arranged alternately along a first direction. The orientation of the first curved portions 2201 is opposite to that of the second curved portions 2202. For example, the first curved portions 2201 are oriented in the direction indicated by the arrow in the Y direction, and the second curved portions 2202 are oriented in the direction opposite to the direction indicated by the arrow in the Y direction. Of course, the first curved portions and the second curved portions can be interchangeable.

[0115] 2 and 3 , each bent portion 2200 surrounds transistors 120 in N sub-pixels 100 electrically connected to one data line group 2100. For example, each bent portion 2200 surrounds transistors 120 in 12 sub-pixels 100 electrically connected to one data line group 2100.

[0116] FIG10 is a schematic diagram showing the positional relationship between the first adapter portion and the first connecting line according to another example of an embodiment of the present disclosure.

[0117] The difference between the array substrate shown in Figure 10 and the array substrate shown in Figure 6 is that the relative position relationship between the first connecting line 610 and the first adapter 410 is different. The array substrate shown in Figure 10 provides another wiring method for connecting the first connecting line 610 to the first adapter 410.

[0118] For example, as shown in Figure 10, the first connecting line 610 passes through the gap between the two transfer sub-parts included in the first transfer part 410 connected to the 2nd data line to the 6th data line, and the gap between the two transfer sub-parts included in other first transfer parts 410 is not passed through by the first connecting line 610.

[0119] For example, as shown in FIG10 , the following description is based on the direction opposite to the arrow indicated by the X direction as downward. For example, the three transfer sub-portions on the side away from the data lines of the three first transfer portions 410 connected to the data line S4, the data line S5, and the data line S6 are all surrounded by the first connecting trace 610. For example, the first connecting trace 610 connecting the data line S1 and the data line S7 is a curved trace that passes between the middle of the two first transfer portions 410 connected to the data line S2 and the data line S3 (i.e., between the two transfer sub-portions included in each first transfer portion 410), below the first transfer portion 410 connected to the data line S4, between the middle of the first transfer portion 410 connected to the data line S5, and below the first transfer portion 410 connected to the data line S6. For example, the first connecting trace 610 connecting the data line S2 and the data line S8 is a bent trace, which bypasses the middle of the first adapter portion 410 connected to the data line S4 (that is, between the two adapter sub-parts included in each first adapter portion 410), the bottom of the first adapter portion 410 connected to the data line S5, the middle of the first adapter portion 410 connected to the data line S6, and the bottom of the first adapter portion 410 connected to the data line S7.

[0120] For example, as shown in Figure 10, the first adapter portion 410 connected to the data lines S1 and S7-S12 does not overlap with the first connection trace 610, the first adapter portion 410 connected to the data lines S2-S4 overlaps with one first connection trace 610, and the first adapter portion 410 connected to the data lines S5 and S6 overlaps with two first connection traces 610.

[0121] FIG11 is a schematic diagram illustrating the positional relationship between a first adapter, a first connecting trace, and a fan-out trace according to another example of an embodiment of the present disclosure. The data lines, gate lines, and electrostatic discharge structure in the array substrate shown in FIG11 may have the same features as those shown in FIG1 to FIG4 and FIG6 , and are not further described here.

[0122] In some examples, as shown in Figure 11, in at least one fan-out routing group, each fan-out routing 300 is disposed on the same layer. For example, the fan-out routing 300 in each fan-out routing group is disposed on the same layer.

[0123] In some examples, as shown in FIG11 , each first transfer portion 410 electrically connected to each fan-out trace 300 in at least one fan-out trace group includes three layers of conductive portions and a first transfer hole 4100 located between two stacked layers of conductive portions within the three layers of conductive portions. The three layers of conductive portions include a first sub-conductive portion 4111, a second sub-conductive portion 4112, and a third sub-conductive portion 4113 stacked with both the first sub-conductive portion 4111 and the second sub-conductive portion 4112. The first sub-conductive portion 4111 is located between the second sub-conductive portion 4112 and a plurality of data lines, the data lines being arranged in the same layer as the first sub-conductive portion 4111. The fan-out trace 300 is arranged in the same layer as the second sub-conductive portion 4112, and the fan-out trace 300 is connected to the second sub-conductive portion 4112. For example, the fan-out trace 300 and the second sub-conductive portion 4112 connected thereto may be an integrated structure.

[0124] In the array substrate provided in Figure 11, by setting the fan-out routing to a single-layer structure, and each data line is electrically connected to the corresponding fan-out routing through the same number of first adapters, such as one first adapter, it is beneficial to reduce the difference in transmission resistance of different data lines, thereby avoiding the risk of vertical stripes caused by resistance differences.

[0125] For example, as shown in FIG11 , the fan-out trace 300 and the second sub-conductive portion 4112 are both disposed on the same layer as the gate line. For example, the third sub-conductive portion 4113 is disposed on the same layer as the common electrode of the sub-pixel. For example, a straight line extending along the X direction can only pass through a portion of the first transition portion 410.

[0126] In some examples, as shown in Figure 11, the first connection trace 610 is connected to the first transition portion 410, and the first connection trace 610 and the fan-out trace 300 electrically connected thereto are arranged on the same layer. For example, the first connection trace 610, the first transition portion 410, and the fan-out trace 300 connected to each other can be an integrated structure.

[0127] In some examples, as shown in Figure 11, there are multiple first connecting traces 610, and the multiple first connecting traces 610 include at least two types of first connecting traces 6101 and 6102, one first connecting trace 6101 includes a portion located on a side of the first transfer portion 410 that is not connected to it and is away from the multiple data lines, and the other first connecting trace 6102 includes a portion located on a side of the first transfer portion 410 that is not connected to it and is close to the multiple data lines.

[0128] For example, as shown in Figure 11, six adjacent first transfer portions 410 electrically connected to the same data line group are arranged along a first direction, and part of the first connection traces 610 are located between these six first transfer portions 410 and the fan-out trace 300; another six adjacent first transfer portions 410 electrically connected to the same data line group are arranged along a direction having a certain angle with the first direction, and another part of the first connection traces 610 are located on the side of the other six first transfer portions 410 away from the fan-out trace 300.

[0129] Figure 12 is a schematic diagram of a partial structure of the second non-display area shown in Figure 1 in an example. Figure 13 is an enlarged partial view of the array substrate shown in Figure 12. Figure 14 is a schematic circuit diagram of the electrical connection between the data line and the second electrostatic discharge structure in the array substrate shown in Figure 13.

[0130] In some examples, as shown in Figures 1, 12 and 13, the electrostatic release structure 500 includes a second electrostatic release structure 520 located in the second non-display area 22, and multiple data lines 210 are electrically connected to the second electrostatic release structure 520 through multiple second transition portions 420, and the second electrostatic release structure 520 is located on a side of the second transition portion 420 away from the multiple data lines 210.

[0131] For example, as shown in Figures 12 and 14, the electrostatic discharge structure 500 also includes an electrostatic ring (Shorting Ring, SR) 502, such as the second electrostatic discharge structure 520 includes multiple sub-electrostatic discharge structures, each sub-electrostatic discharge structure may include multiple transistors M, such as including two transistors M17 and M19 or two transistors M21 and M23; Each sub-electrostatic discharge structure is connected to a data line 210, and multiple sub-electrostatic discharge structures are all connected to the electrostatic ring 502. When there is a larger impact current on the data line, the transistor in the sub-electrostatic discharge structure can be opened to further discharge the larger impact current to the electrostatic ring. When there is a larger impact current on the electrostatic ring, the sub-electrostatic discharge structure may also be opened, and the current can be transmitted to the data line.

[0132] For example, as shown in FIG12 , a common electrode line (not shown) may be further provided between the second transfer portion 420 and the display area, and electrically connected to the common signal line in the display area to provide a planarly distributed VCOM signal.

[0133] In some examples, as shown in Figures 12 and 13, the array substrate further includes a detection signal line 710 and a switch component 720 located in the second non-display area. The detection signal line 710 and the switch component 720 are both located on a side of the second electrostatic discharge structure 520 away from the display area, and the detection signal line 710 is connected to the second electrostatic discharge structure 520 via the switch component 720. For example, the array substrate further includes a detection signal switch line 730 located in the second display area. For example, the plurality of data lines 210 are grouped according to the signals transmitted by sub-pixels of different colors, such as data lines S1, S4, S7, and S10, which are data lines that transmit data signals for red sub-pixels; data lines S2, S5, S8, and S11, which are data lines that transmit data signals for green sub-pixels; and data lines S3, S6, S9, and S12, which are data lines that transmit data signals for blue sub-pixels.

[0134] For example, as shown in FIG12 and FIG13, when producing a display device including an array substrate, it is necessary to detect whether there is a problem with the display. In the detection stage, a high-level signal can be loaded on the detection signal switch line 730 (for example, when the switch component is an N-type transistor, a high-level signal is loaded; when the switch component is a P-type transistor, a low-level signal is loaded), the control switch component 720 is in an open state, and the signal corresponding to the red sub-pixel transmitted by the detection signal line 710 (the first detection signal line 7101) is transmitted to the data line S1, the data line S4, the data line S7 and the data line S8 through the control switch component. S10 and other data lines; when the control switch component 720 is in the open state, the signal corresponding to the green sub-pixel transmitted by the detection signal line 710 (the second detection signal line 7102) is transmitted to the data lines S2, data line S5, data line S8 and data line S11 through the control switch component; when the control switch component 720 is in the open state, the signal corresponding to the blue sub-pixel transmitted by the detection signal line 710 (the third detection signal line 7103) is transmitted to the data lines S3, data line S6, data line S9 and data line S12 through the control switch component.

[0135] For example, as shown in Figures 12 and 13, when the display device including the array substrate is operating normally, a low-level signal is loaded on the detection signal switch line 730 to control the switch component 720 to be in a closed state. At this time, only the data line Sm is connected to the data line S(m+6).

[0136] For example, as shown in Figure 12, at least one switching component 720 can be a thin film transistor, and the gate of the thin film transistor and the detection signal switch line 730 are an integrated structure. The thin film transistor includes a first pole and a second pole, the first pole is connected to the second electrostatic release structure 520, the second pole is connected to the detection signal line 710 through a block connection portion 740, and the second pole overlaps with other detection signal lines 710 that are not connected to it, and a pad 750 is provided at the overlapping position. For example, the pad 750 can be provided in the same layer as the active layer of the thin film transistor. By providing a pad at the overlapping position of the second pole of the thin film transistor and the detection signal line, the probability of electrostatic breakdown at the overlapping position of the second pole and the detection signal line can be reduced, and the step difference between this position and the position where the active layer of the thin film transistor is located can also be improved.

[0137] In some examples, as shown in Figure 13, the mth data line 210 is electrically connected to the (m+N / 2)th data line 210 through a second connecting line 620 located in the second non-display area, and the second electrostatic release structure 520 is connected to the second transfer portion 420 through a third connecting line 630, and the third connecting line 630 and the second connecting line 620 are located in different layers.

[0138] For example, as shown in Figure 13, the mth data line 210 is electrically connected to the (m+6)th data line 210 via a second connection line 620 located in the second non-display area. For example, one of the second connection line 620 and the third connection line 630 is disposed on the same layer as the data line, and the other is disposed on the same layer as the gate line.

[0139] For example, as shown in Figures 12 and 13, the second adapter 420 includes two adapter blocks 4202, one adapter block 4202 is a first adapter block close to the data line 210, and the other adapter block 4202 is a second adapter block away from the data line 210. The first adapter block is arranged in the same layer as the data line 210, and the second adapter block is arranged in the same layer as the gate line 220. For example, the third connecting line 630 is arranged in the same layer as the data line 210, and the third connecting line 630 is connected to the first adapter block. For example, the third connecting line 630 and the first adapter block are an integrated structure. For example, the second connecting line 620 and the gate line 220 are arranged in the same layer, and the second connecting line 620 is connected to the second adapter block. For example, the second connecting line 620 and the second adapter block are an integrated structure.

[0140] During research, the inventors of this application discovered that, as shown in Figures 12 to 14 , the first data line S1, the second data line S2, the third data line S3, the tenth data line S10, the eleventh data line S11, and the twelfth data line S12 are all directly connected to the third connection line 630; the remaining data lines 210 are all connected to the corresponding third connection lines 630 via two second adapters 420. For example, the two second adapters 420 provided between the seventh data line S7, the eighth data line S8, and the ninth data line S9 and the corresponding third connection lines 630 are equivalent to the two resistors R1 and R10, and the two second adapters 420 provided between the fourth data line S4, the fifth data line S5, and the sixth data line S6 and the corresponding third connection lines 630 are equivalent to the two resistors R14 and R15.

[0141] The overall resistance between different data lines and the corresponding third connection lines is different. Therefore, the remote anti-static ability of each data line is different for different data lines. For example, the impact current transmission resistance between different data lines and the second electrostatic release structure is different. As shown in FIG13 , compared with the first data line S1, the second data line S2, the third data line S3, the tenth data line S10, the eleventh data line S11 and the twelfth data line S12, which are all directly connected to the third connection line 630, the remaining other data lines 210 are mostly connected to the corresponding third connection line 630 through two second adapters 420. When large external static electricity is introduced into the display device, the probability of inducing static electricity to pass through different electrostatic release structures is different. For example, large static electricity is easily concentrated on the electrostatic release structure that is not connected to the second adapter, resulting in electrostatic selectivity, that is, causing poor specificity.

[0142] Figure 15 is a schematic diagram of a partial structure of the second non-display area of ​​the array substrate shown in Figure 1. Figure 15 schematically illustrates the positions of data lines S1 to S12. The structure of the second adapter portion of the array substrate shown in Figure 15 on the side away from the second electrostatic discharge structure can have the same features as the structure of the second adapter portion of the array substrate shown in Figure 12 on the side away from the second electrostatic discharge structure. The structure of the second adapter portion of the array substrate shown in Figure 15 can have the same structure as the second adapter portion of the array substrate shown in Figure 12.

[0143] In some examples, as shown in Figure 15, the number of second transfer portions 420 through which the mth data line is electrically connected to the second electrostatic release structure 520 is the same as the number of second transfer portions 420 through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure 520.

[0144] By setting the number of second transition portions through which each data line is electrically connected to the second electrostatic release structure to be the same, the difference in on-resistance between the far end of each data line and the second electrostatic release structure can be minimized, thereby reducing the risk of specific defects.

[0145] In some examples, as shown in Figure 15, each second transfer portion 420 includes at least two second transfer holes 4200, and the number of second transfer holes 4200 through which the mth data line is electrically connected to the second electrostatic release structure 520 is the same as the number of second transfer holes 4200 through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure 520. This can make the on-resistance between the far end of each data line and the second electrostatic release structure basically equal, further reducing the risk of specific adverse reactions.

[0146] In some examples, as shown in FIG15 , the mth data line is electrically connected to the (m+N / 2)th data line via a second connection trace 620 located in the second non-display area, and the second electrostatic discharge structure 520 is connected to the second adapter 420 via a third connection trace 630. The third connection trace 630 is provided on the same layer as the second connection trace 620. Providing the second and third connection traces on the same layer facilitates ensuring that the number of second adapters through which each data line is electrically connected to the corresponding third connection trace is the same.

[0147] In some examples, as shown in Figures 12 and 15, the second connecting traces 620 and the third connecting traces 630 are both arranged in the same layer as the plurality of gate lines 220. For example, the second connecting traces 620 and the third connecting traces 630 are both connected to the second adapter block of the second adapter portion 420. For example, the second adapter block and the second connecting traces 620 and the third connecting traces 630 connected thereto are an integrated structure.

[0148] FIG. 16 is a circuit schematic diagram showing electrical connection between the data line and the second electrostatic discharge structure in the array substrate shown in FIG. 15 .

[0149] For example, as shown in Figures 15 and 16, the same number of second transition portions 420 are provided between the mth data line Sm and the S(m+6)th data line and their corresponding second electrostatic release structures 520. For example, if each has one second transition portion 420, then one second transition portion 420 provided between the mth data line Sm and its corresponding second electrostatic release structure 520 is equivalent to one resistor R11, and one second transition portion 420 provided between the S(m+6)th data line and its corresponding second electrostatic release structure 520 is equivalent to one resistor R8. As a result, the on-resistance between the far end of each data line and the second electrostatic release structure is substantially equal, further reducing the risk of specific defects.

[0150] In some examples, as shown in FIG12 and FIG15 , each second transfer portion 420 includes three layers of conductive portions and a second transfer hole 4200 located between two stacked layers of conductive portions in the three layers of conductive portions. The three layers of conductive portions include a fourth sub-conductive portion 4201, a fifth sub-conductive portion 4202, and a sixth sub-conductive portion 4203 stacked with the fourth and fifth sub-conductive portions 4202. The fourth sub-conductive portion 4201 is located between the fifth sub-conductive portion 4202 and a plurality of data lines 210. The data lines 210 are provided in the same layer as the fourth sub-conductive portion 4201. The fifth sub-conductive portion 4202 is provided in the same layer as the second connection trace 620, and both the second connection trace 620 and the third connection trace 630 are connected to the fifth sub-conductive portion 4202. For example, the sixth sub-conductive portion 4203 can be provided in the same layer as the common electrode of the sub-pixel.

[0151] For example, as shown in Figure 15, the connection relationship between the fourth sub-conductive part 4201 and the sixth sub-conductive part 4203 can refer to the connection relationship between the second conductive part 412 and the first conductive part 411 shown in Figure 9, and the connection relationship between the fifth sub-conductive part 4202 and the sixth sub-conductive part 4203 can refer to the connection relationship between the third conductive part 413 and the first conductive part 411 shown in Figure 8.

[0152] Another embodiment of the present disclosure provides an array substrate, which may be referred to as the array substrate shown in FIG. 1 to FIG. 16 . The array substrate includes a display area 10 and a first non-display area 21 and a second non-display area 22 located on both sides of the display area 10 .

[0153] As shown in FIG1 , the array substrate includes a plurality of sub-pixels 100 located in a display area 10, a plurality of data lines 210, a plurality of gate lines 220, and a plurality of fan-out routing lines 300 located in a first non-display area 21. The plurality of data lines 210 are arranged along a first direction, the plurality of gate lines 220 are arranged along a second direction, and a gate line pair formed by two gate lines is provided between two adjacent sub-pixels 100 arranged along the second direction, with the first direction intersecting the second direction. The plurality of fan-out routing lines 300 are configured to be electrically connected to the plurality of data lines 210. The plurality of data lines 210 include a plurality of data line groups 2100 arranged along the first direction, each data line group 2100 including N data lines. In each data line group 2100, the mth data line 210 is electrically connected to the (m+N / 2)th data line 210, where m is a positive integer not greater than N / 2. The sub-pixels, data lines, gate lines and fan-out wiring in the array substrate provided in this embodiment may have the same features as those in the above embodiments, and are not described again here.

[0154] As shown in Figures 1 to 16, the array substrate also includes an electrostatic release structure 520 (equivalent to the second electrostatic release structure 520 in the above embodiment), which is located in the second non-display area 22. The multiple data lines 210 are electrically connected to the electrostatic release structure 520 through multiple transition portions 420 (equivalent to the second transition portions 420 in the above embodiment). The electrostatic release structure 520 is located on the side of the transition portion 420 away from the multiple data lines 210.

[0155] For example, the array substrate further includes a first electrostatic discharge structure 510 located in the first non-display area 21 and between the plurality of data lines 210 and the plurality of fan-out traces 300 .

[0156] The first electrostatic discharge structure, fan-out trace, and first transition portion in the array substrate provided in this embodiment may have the same features as those in the above-described embodiment, and are not described in detail here. The second electrostatic discharge structure and transition portion in the array substrate provided in this embodiment may have the same features as those in the above-described embodiment, and are not described in detail here.

[0157] As shown in Figures 15 and 16, in at least one data line group, the number of transition portions 420 through which the m-th data line is electrically connected to the second electrostatic release structure 520 is the same as the number of transition portions 420 through which the (m+N / 2)-th data line is electrically connected to the second electrostatic release structure 520. For example, N can be the same as N in the above embodiment. The connection method between the data lines and the second electrostatic release structure in the array substrate provided in this embodiment is only the example shown in Figure 15, and does not include the example shown in Figure 13. The connection method between the data lines and the fan-out traces in the array substrate provided in this embodiment includes the connection method provided in any of the examples in Figures 4 to 11.

[0158] By setting the number of transition portions through which each data line is electrically connected to the second electrostatic release structure to be the same, the difference in on-resistance between the distal end of each data line and the second electrostatic release structure can be minimized, thereby reducing the risk of specific defects.

[0159] In some examples, as shown in Figure 15, each adapter portion 420 includes at least two adapter holes 4200 (equivalent to the second adapter hole 4200 in the above embodiment). In at least one data line group, the number of adapter holes 4200 through which the mth data line 210 is electrically connected to the second electrostatic release structure 520 is the same as the number of adapter holes 4200 through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure 520. This can make the on-resistance between the far end of each data line and the second electrostatic release structure basically equal, further reducing the risk of specific adverse reactions.

[0160] In some examples, as shown in FIG15 , the mth data line is electrically connected to the (m+N / 2)th data line via a first sub-connection trace 620 (equivalent to the second connection trace 620 in the above embodiment) located in the second non-display area, and the second electrostatic release structure 520 is connected to the adapter 420 via a second sub-connection trace 630 (equivalent to the third connection trace 630 in the above embodiment). The first sub-connection trace 620 and the second sub-connection trace 630 are arranged on the same layer. Arranging the first sub-connection trace and the second sub-connection trace on the same layer facilitates achieving an equal number of adapters through which each data line is electrically connected to the second electrostatic release structure.

[0161] 12 and 15 , the first sub-connection trace 620 and the second sub-connection trace 630 are both provided on the same layer as the gate line 220. The first sub-connection trace and the second sub-connection trace in this embodiment may have the same features as the second connection trace and the third connection trace in the above embodiment, and are not described in detail herein.

[0162] For example, as shown in Figures 6 and 13, in one example of an embodiment of the present disclosure, the number of first transfer portions 410 through which the data line Sm is electrically connected to the fan-out routing 300 is the same as the number of first transfer portions 410 through which the data line S(m+N / 2) is electrically connected to the same fan-out routing 300, and the number of second transfer portions 420 through which the data line Sm is electrically connected to the second electrostatic release structure 520 is different from the number of second transfer portions 420 through which the data line S(m+N / 2) is electrically connected to the same second electrostatic release structure 520.

[0163] For example, as shown in Figures 6 and 15, in one example of an embodiment of the present disclosure, the number of first transfer portions 410 through which the data line Sm is electrically connected to the fan-out routing 300 is the same as the number of first transfer portions 410 through which the data line S(m+N / 2) is electrically connected to the same fan-out routing 300, and the number of second transfer portions 420 through which the data line Sm is electrically connected to the second electrostatic release structure 520 is the same as the number of second transfer portions 420 through which the data line S(m+N / 2) is electrically connected to the same second electrostatic release structure 520.

[0164] For example, as shown in Figures 4 and 15, in one example of an embodiment of the present disclosure, the number of transition portions 41 through which the data line Sm is electrically connected to the fan-out routing 300 is different from the number of transition portions 41 through which the data line S(m+N / 2) is electrically connected to the same fan-out routing 300, and the number of second transition portions 420 through which the data line Sm is electrically connected to the second electrostatic release structure 520 is the same as the number of second transition portions 420 through which the data line S(m+N / 2) is electrically connected to the same second electrostatic release structure 520.

[0165] 17 is a schematic block diagram of a display device according to another embodiment of the present disclosure. Another embodiment of the present disclosure provides a display device, wherein the display device 800 includes any of the above-mentioned array substrates 900 .

[0166] For example, the display device further includes an opposing substrate disposed opposite the array substrate. For example, the opposing substrate may be a color filter substrate. For example, the display device further includes a liquid crystal layer located between the array substrate and the opposing substrate.

[0167] For example, the display device may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc., but the present embodiment is not limited thereto.

[0168] There are a few points to note:

[0169] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0170] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0171] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. An array substrate, comprising a display area and a non-display area located at least on one side of the display area, the array substrate comprising: A plurality of sub-pixels are located in the display area; A plurality of data lines are located in the display area, and the plurality of data lines are arranged along a first direction; A plurality of gate lines are located in the display area, the plurality of gate lines are arranged along a second direction, a gate line pair formed by two gate lines is arranged between two adjacent sub-pixels arranged along the second direction, and the first direction intersects the second direction; A plurality of fan-out wirings are located in the non-display area, and the plurality of fan-out wirings are configured to be electrically connected to the plurality of data lines. The plurality of data lines include a plurality of data line groups arranged along the first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; The plurality of fan-out routing lines include a plurality of fan-out routing line groups arranged along the first direction, each fan-out routing line group includes N / 2 fan-out routing lines, and the fan-out routing lines in the same fan-out routing line group are electrically connected to the data lines in the same data line group, and the N / 2 fan-out routing lines are electrically connected to the mth data line to the (m-1+N / 2)th data line in a one-to-one correspondence; Each data line in at least one data line group is electrically connected to the corresponding fan-out routing through at least one first transfer portion, and in the at least one data line group, the number of the first transfer portions through which the mth data line is electrically connected to the fan-out routing is the same as the number of the first transfer portions through which the (m+N / 2)th data line is electrically connected to the fan-out routing.

2. The array substrate according to claim 1, wherein, The first transfer portion includes at least two first transfer holes, and in the at least one data line group, the number of the first transfer holes through which the mth data line is electrically connected to the fan-out routing is the same as the number of the first transfer holes through which the (m+N / 2)th data line is electrically connected to the fan-out routing.

3. The array substrate according to claim 1 or 2, wherein, The non-display area includes a first non-display area and a second non-display area respectively located on both sides of the display area in the second direction, and the plurality of fan-out wirings and the first transfer portion are both located in the first non-display area; The array substrate further includes an electrostatic release structure, wherein the electrostatic release structure includes a first electrostatic release structure and a second electrostatic release structure, wherein the first electrostatic release structure is located at the first non-display area, the second electrostatic release structure is located in the second non-display area, the first electrostatic release structure is located between the plurality of data lines and the first transfer portion, and the plurality of data lines are electrically connected to the plurality of fan-out wirings through the first electrostatic release structure and the first transfer portion; The multiple data lines are electrically connected to the second electrostatic release structure through multiple second transfer parts, the second electrostatic release structure is located on a side of the second transfer part away from the multiple data lines, and the number of the second transfer parts through which the mth data line is electrically connected to the second electrostatic release structure is the same as the number of the second transfer parts through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure.

4. The array substrate according to claim 3, wherein, Each second connection part includes at least two second connection holes, and the number of the second connection holes through which the m-th data line is electrically connected to the second electrostatic discharge structure is the same as the number of the second connection holes through which the (m + N / 2)-th data line is electrically connected to the second electrostatic discharge structure.

5. The array substrate according to any one of claims 1-4, wherein, In the at least one fan-out routing group, two adjacent fan-out routings are a first fan-out routing and a second fan-out routing respectively, and the first fan-out routing and the second fan-out routing are arranged on different layers. A straight line extending along the first direction passes through the first connection part electrically connected to each fan-out routing in the at least one fan-out routing group.

6. The array substrate according to claim 5, wherein, The m-th data line and the (m + N / 2)-th data line are electrically connected through a first connection trace located in the first non-display area, the first connection trace is connected to the first connection part, and the first connection trace and the fan-out routing electrically connected thereto are arranged on the same layer.

7. The array substrate according to claim 3 or 4, wherein, The m-th data line and the (m + N / 2)-th data line are electrically connected through a second connection trace located in the second non-display area, the second electrostatic discharge structure is connected to the second connection part through a third connection trace, and the third connection trace and the second connection trace are arranged on the same layer.

8. The array substrate according to claim 6, wherein, The first connection part includes at least two conductive parts and a first connection hole. The at least two conductive parts include three conductive parts, including a first conductive part, a third conductive part, and a second conductive part laminated with both the first conductive part and the third conductive part. One of the first conductive part and the third conductive part is connected to the fan-out routing and arranged on the same layer. Or, the at least two conductive parts include two conductive parts, including a first conductive part and a second conductive part laminated with the first conductive part. The first conductive part is connected to the fan-out routing and arranged on the same layer.

9. The array substrate according to claim 8, wherein, Each first connection part electrically connected to each fan-out routing in the at least one fan-out routing group includes two connection sub-parts arranged along the second direction. The number of the first connection traces is multiple, and at least one first connection trace passes through the interval between the two connection sub-parts included in the first connection part that is not connected to it.

10. The array substrate according to claim 9, wherein, Each connection sub-part includes two connection blocks arranged along the second direction. In each first connection part, the connection block closest to the multiple data lines is arranged on the same layer as the data lines, the connection block closest to the fan-out routing and the fan-out routing connected to the connection block are arranged on the same layer, and the two connection blocks in the middle are connected and arranged on the same layer.

11. The array substrate according to any one of claims 1-4, wherein, In the at least one fan-out routing group, each fan-out routing is arranged on the same layer. Each first connection part electrically connected to each fan-out routing in the at least one fan-out routing group includes three conductive parts and a first connection hole. The three conductive parts include a first sub-conductive part, a second sub-conductive part, and a third sub-conductive part laminated with both the first sub-conductive part and the second sub-conductive part. The first sub-conductive part is located between the second sub-conductive part and the multiple data lines, the data lines are arranged on the same layer as the first sub-conductive part, and the fan-out routing is connected to the second sub-conductive part and arranged on the same layer.

12. The array substrate according to claim 11, wherein, The mth data line is electrically connected to the (m+N / 2)th data line via a first connecting line, the first connecting line is connected to the first transfer portion, and the first connecting line and the fan-out line electrically connected thereto are arranged on the same layer; There are multiple first connection routings, and the multiple first connection routings include at least two types of first connection routings, one first connection routing includes a portion located on a side of a first adapter portion that is not connected to it and is away from the multiple data lines, and the other first connection routing includes a portion located on a side of the first adapter portion that is not connected to it and is close to the multiple data lines.

13. The array substrate according to claim 7, wherein, The second transfer portion includes a three-layer conductive portion and a second transfer hole, the three-layer conductive portion includes a fourth sub-conductive portion, a fifth sub-conductive portion and a sixth sub-conductive portion which is stacked with the fourth sub-conductive portion and the fifth sub-conductive portion, the fourth sub-conductive portion is located between the fifth sub-conductive portion and the plurality of data lines, the data lines are arranged in the same layer as the fourth sub-conductive portion, the fifth sub-conductive portion is arranged in the same layer as the second connecting trace, and the second connecting trace and the third connecting trace are both connected to the fifth sub-conductive portion.

14. The array substrate according to claim 5 or 6, wherein One of the first fan-out routing and the second fan-out routing is disposed at the same layer as the plurality of data lines, and the other of the first fan-out routing and the second fan-out routing is disposed at the same layer as the plurality of gate lines.

15. The array substrate according to claim 7, wherein, The second connecting wiring and the third connecting wiring are both arranged on the same layer as the plurality of gate lines.

16. The array substrate according to claim 3, wherein The mth data line is electrically connected to the (m+N / 2)th data line via a second connecting line located in the second non-display area, the second electrostatic release structure is connected to the second adapter via a third connecting line, and the third connecting line and the second connecting line are located in different layers.

17. The array substrate according to claim 3, 4, 7 or 16, further comprising: The detection signal line and the switch component are located in the second non-display area, The detection signal line and the switch component are both located on a side of the second electrostatic release structure away from the display area, and the detection signal line is connected to the second electrostatic release structure through the switch component.

18. The array substrate according to any one of claims 1-17, wherein, N is 12, and the multiple gate lines include first gate lines and second gate lines alternately arranged along the second direction, six columns of sub-pixels electrically connected to the first data line to the sixth data line in the same data line group are electrically connected to the first gate line, and six columns of sub-pixels electrically connected to the seventh data line to the twelfth data line in the same data line group are electrically connected to the second gate line.

19. The array substrate according to any one of claims 1-18, wherein, At least one gate line is provided with a plurality of curved portions, wherein the plurality of curved portions include a plurality of first curved portions and a plurality of second curved portions alternately arranged along the first direction, and the orientation of the first curved portions is opposite to the orientation of the second curved portions; Each sub-pixel includes a transistor, and each bent portion surrounds the transistor in N sub-pixels electrically connected to one data line group.

20. An array substrate, comprising a display area and a first non-display area and a second non-display area respectively located on both sides of the display area, the array substrate comprising: A plurality of sub-pixels are located in the display area; A plurality of data lines are located in the display area, and the plurality of data lines are arranged along a first direction; A plurality of gate lines are located in the display area, the plurality of gate lines are arranged along a second direction, a gate line pair formed by two gate lines is arranged between two adjacent sub-pixels arranged along the second direction, and the first direction intersects the second direction; A plurality of fan-out lines are located in the first non-display area, and the plurality of fan-out lines are configured to be connected to the The plurality of data lines are electrically connected, The plurality of data lines include a plurality of data line groups arranged along the first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; The array substrate also includes an electrostatic release structure located in the second non-display area, the multiple data lines are electrically connected to the electrostatic release structure through multiple transition parts, the electrostatic release structure is located on a side of the transition part away from the multiple data lines, and in at least one data line group, the number of transition parts through which the mth data line is electrically connected to the electrostatic release structure is the same as the number of transition parts through which the (m+N / 2)th data line is electrically connected to the electrostatic release structure.

21. The array substrate according to claim 20, wherein, Each adapter portion includes at least two adapter holes. In the at least one data line group, the number of the adapter holes through which the mth data line is electrically connected to the electrostatic release structure is the same as the number of the adapter holes through which the (m+N / 2)th data line is electrically connected to the electrostatic release structure.

22. The array substrate according to claim 20 or 21, wherein The mth data line is electrically connected to the (m+N / 2)th data line via a first sub-connection line located in the second non-display area, the electrostatic release structure is connected to the transfer portion via a second sub-connection line, and the first sub-connection line and the second sub-connection line are arranged on the same layer.

23. The array substrate according to claim 22, wherein, The first sub-connection wiring and the second sub-connection wiring are both arranged in the same layer as the gate line.

24. A display device comprising the array substrate according to any one of claims 1 to 23.

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