Display substrate and electrophoretic display device

Abstract

The present disclosure relates to the technical field of display, and provides a display substrate and an electrophoretic display device. The display substrate comprises a base substrate, and M rows and N columns of pixel units arranged in an array on the base substrate, wherein M and N are both positive integers, and M is not equal to N. The pixel units in the same row are electrically connected to the same first signal line, and the pixel units in the same column are electrically connected to the same second signal line; at least one third signal line is provided on each of two opposite sides of any column of pixel units in a row direction; any first signal line is electrically connected to at least one third signal line, and multiple third signal lines electrically connected to the same first signal line are electrically connected; and for any two first signal lines, the ratio of the product of total resistance and total capacitance formed by one end of one of the first signal lines and the third signal lines electrically connected to the first signal line to the product of total resistance and total capacitance formed by one end of the other first signal line and the third signal lines electrically connected to the first signal line ranges from 0.5 to 1.5.

Description

Display substrate and electrophoretic display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and an electrophoretic display device. Background Art

[0002] With the development of display technology, people have higher and higher requirements for electrophoretic display devices. For example, the demand for the extreme bezel of the product is getting higher and higher. Therefore, in-plane routing is adopted to achieve an extremely narrow bezel.

[0003] However, most electrophoretic display products use an M×N pixel resolution where M and N are inconsistent. Existing in-plane wiring designs are limited by the inconsistency between M and N, resulting in dummy lines in the set leads. The introduction of dummy lines increases the load (e.g., capacitance) of each pixel unit in the column (or each pixel unit in the row), thereby causing an unbalanced in-plane load on the electrophoretic display product and affecting the display effect.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a display substrate and an electrophoretic display device.

[0006] In a first aspect, a technical solution adopted to solve the technical problem of the present disclosure is a display substrate, comprising a base substrate, and pixel units arranged in an array in M ​​rows and N columns on the base substrate, where M and N are both positive integers, and M is not equal to N; wherein the pixel units in the same row are electrically connected to the same first signal line, and the pixel units in the same column are electrically connected to the same second signal line;

[0007] For any column of the pixel units, at least one third signal line is respectively provided on two opposite sides in the row direction; wherein, any first signal line is electrically connected to at least one third signal line, and multiple third signal lines electrically connected to the same first signal line are electrically connected;

[0008] For any two of the first signal lines, a ratio of a product of a total resistance and a total capacitance formed by one end of the first signal line and the third signal line electrically connected thereto is in a range of 0.5 to 1.5.

[0009] In some embodiments, the display substrate further includes an integrated chip disposed on the base substrate, and the integrated chip is located on one side opposite to the display area where the M rows and N columns of pixel units arranged in an array are located along the column direction.

[0010] In some embodiments, the first signal line electrically connected to one of the third signal lines is farther away from the integrated chip than the first signal line electrically connected to a plurality of the third signal lines.

[0011] In some embodiments, among the at least one third signal line electrically connected to the first signal line in some rows, at least one third signal line is disconnected at a connection node with the first signal line.

[0012] In some embodiments, among the plurality of third signal lines connected to the same first signal line, except for the third signal line directly connected to the integrated chip, at least one of the other third signal lines is disconnected at a connection node with the first signal line.

[0013] In some embodiments, among the plurality of third signal lines connected to the same first signal line, two adjacent third signal lines have their ends connected in parallel via connecting lines.

[0014] In some embodiments, for the first signal line electrically connected to one of the third signal lines, one end of the third signal line electrically connected thereto is connected to the integrated chip, and the other end is connected to an anti-static unit or a reference voltage terminal.

[0015] In some embodiments, among the multiple third signal lines connected to the same first signal line, one end of one third signal line is electrically connected to the integrated chip, and one end of one third signal line is electrically connected to the anti-static unit or the reference voltage end.

[0016] In some embodiments, the first signal line electrically connected to the plurality of third signal lines includes a plurality of;

[0017] For each of the first signal lines electrically connected to a plurality of the third signal lines, a line connecting the i-th connection nodes of each of the first signal lines is located on the same first straight line; i is a positive integer.

[0018] In some embodiments, a line connecting the i-th connection node of each first signal line and a line connecting the (i+1)-th connection node of each first signal line are parallel to each other.

[0019] In some embodiments, the first signal line electrically connected to the plurality of third signal lines includes a plurality of;

[0020] For each of the first signal lines electrically connected to the plurality of third signal lines, the lines connecting the i-th connection nodes of each of the first signal lines are not located on the same first straight line; i is a positive integer.

[0021] In some embodiments, for some of the first signal lines electrically connected to multiple third signal lines, the connection lines of the i-th connection nodes of each of the first signal lines are located on the same first straight line, and the connection lines of the i-th connection nodes of each of the first signal lines are parallel to the connection lines of the i+1-th connection nodes of each of the first signal lines.

[0022] In some embodiments, for any two of the first signal lines, the product of the total capacitance and the total resistance formed by one end of the first signal line and the signal input end of the third signal line electrically connected thereto is equal.

[0023] In some embodiments, for the plurality of third signal lines electrically connected to the same first signal line, their orthographic projections on the substrate fall within orthographic projections of the pixel units in the same column on the substrate.

[0024] In some embodiments, the display substrate further includes a first conductive layer, an insulating layer, and a second conductive layer sequentially disposed on the base substrate;

[0025] The first signal line is located in the first conductive layer;

[0026] The second signal line and the third signal line are located in the second conductive layer;

[0027] The third signal line is electrically connected to the first signal line through a connection via hole penetrating the insulating layer.

[0028] In some embodiments, the display substrate is applied to an electrophoretic display device.

[0029] In a second aspect, an embodiment of the present disclosure provides an electrophoretic display device, which includes the display substrate described in any one of the first aspects above. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1a is a schematic diagram of an in-plane wiring solution in the prior art;

[0031] FIG1b is a schematic diagram of another in-plane wiring solution in the prior art;

[0032] FIG2 is a schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0033] FIG3a is a schematic diagram showing a first signal line electrically connected to a third signal line according to an embodiment of the present disclosure;

[0034] FIG3 b is a schematic diagram of an exemplary embodiment of the present disclosure, in which a first signal line is electrically connected to a plurality of third signal lines;

[0035] FIG3c is another exemplary schematic diagram of a first signal line electrically connected to a plurality of third signal lines provided by an embodiment of the present disclosure;

[0036] FIG4 is a schematic diagram of routing of first signal lines in different rows and third signal lines electrically connected thereto, provided by an embodiment of the present disclosure;

[0037] FIG5 is a schematic diagram of an in-plane wiring layout according to Example 1 provided in an embodiment of the present disclosure;

[0038] FIG6 is a schematic diagram of an in-plane wiring layout according to Example 2 provided in an embodiment of the present disclosure;

[0039] FIG7 is a schematic diagram of an in-plane wiring layout according to Example 3 provided in an embodiment of the present disclosure;

[0040] FIG8 is a schematic diagram of an in-plane wiring layout according to Example 4 provided in an embodiment of the present disclosure;

[0041] FIG9 a is a schematic diagram of an unbroken T-shaped wiring provided by an embodiment of the present disclosure;

[0042] FIG9 b is a schematic diagram of a T-shaped wiring after being broken according to an embodiment of the present disclosure;

[0043] FIG10 is a schematic diagram of an in-plane wiring layout according to Example 5 provided in an embodiment of the present disclosure;

[0044] FIG11 is a schematic diagram of an in-plane wiring layout according to Example 6 provided in an embodiment of the present disclosure;

[0045] FIG12 is a schematic diagram of an in-plane wiring layout of Example 7 provided in an embodiment of the present disclosure;

[0046] FIG13 is a schematic diagram of an in-plane wiring layout of Example 8 provided in an embodiment of the present disclosure;

[0047] FIG14a is a schematic diagram of a single third signal line being disconnected at a connection node according to an embodiment of the present disclosure;

[0048] FIG14b is a schematic diagram of a plurality of third signal lines disconnected at a connection node and connected in parallel according to an embodiment of the present disclosure;

[0049] FIG14c is a schematic diagram of a plurality of third signal lines connected end to end in parallel according to an embodiment of the present disclosure.

[0050] The figures are marked as follows: 00, lead; 01, dummy line; Gate, gate line; Data, data line; 1, pixel unit; 21, first signal line; 22, second signal line; 23, third signal line; X, row direction; Y, column direction; 3, connection node; 21_a, one end of the first signal line 21; 24, connection line; 4, signal input end; 5, left half area; 6, right half area; IC, integrated chip. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0052] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0053] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0054] In related technologies, ESL (Electronic Shelf Label) is an electronic price tag. The main ways to implement ESL technology include cholesterol liquid crystal display technology, electrophoretic display technology (EPD) and electrowetting display technology. Among them, electrophoretic display technology is the most widely used. At present, EPD has played its low power consumption and eye protection advantages and is widely used in electronic price tags, readers, outdoor bus stops, etc. Among them, readers are business-to-consumer (TOC) products, and users have increasingly high demands for extreme borders, so it is necessary to adopt in-plane routing to achieve extremely narrow borders. In addition, due to their large size, bus stops often use split-screen display, and split-screen display also requires in-plane routing to achieve narrow borders. Sub-millimeter light-emitting diode (Mini LED) products that use spliced ​​display require zero gaps between the split screens, so the signal lines also need to use in-plane routing to achieve narrow borders.

[0055] FIG. 1 a is a schematic diagram of an in-plane wiring solution in the prior art, and FIG. 1 b is a schematic diagram of another in-plane wiring solution in the prior art.

[0056] As shown in Figure 1a or Figure 1b, the signal transmission line that is led out from the integrated chip (IC) and transmitted to the pixel unit in the AA area is called a fan-out line or fanout routing. In-plane routing specifically refers to: the gate line Gate or data line Data fanout wiring is directly led out from the display area AA of the display panel to reach the pixel unit 1. Among them, the data line Data is in the horizontal direction (that is, the row direction), the gate line Gate is in the vertical direction (that is, the column direction), and the lead 00 of the data line Data is in the vertical direction, that is, the transmission path of the data signal is to go up in the vertical direction first, and then in the horizontal direction. This setting reduces the left and right borders of the electrophoretic display product, thereby increasing the proportion of the AA area in the panel and improving the user experience.

[0057] In a specific design, the pixel resolution of an electrophoretic display product is M(Data) × N(Gate). The gate lines (Gate) are arranged vertically, and the data lines (Data) are arranged horizontally. Therefore, the data lines (Data) must be transmitted vertically and then horizontally within the display area (AA). Assuming M / N = n, when n is an integer, each column of pixel cells 1 corresponds to n Data lines 00. However, in most cases, n is not an integer, so each column of pixel cells 1 corresponds to at least (n+1) Data lines. Therefore, a dummy line 01 must exist between Data lines 00.

[0058] As shown in FIG. 1a or FIG. 1b , the pixel resolution of the electrophoretic display product is 6 (Data) × 5 (Gate). The number of gate lines Gate and data lines Data is not equal. Therefore, at least two Data leads 00 are provided for each column of pixel units 1 , for a total of 10 Data leads 00 , of which 6 are electrically connected to the data lines Data and 4 are dummy lines 01 .

[0059] As shown in Figure 1a, the in-plane routing scheme employed is characterized by a concentrated distribution of the six data lines 00 connected to the data lines and the four dummy lines 01. Because the introduction of dummy lines 01 increases the load (e.g., capacitance and resistance) in the columns they are located in, this concentrated routing arrangement results in a significant difference in the load on pixel units 2 located in area C and those located in area D, leading to uneven display between areas C and D.

[0060] As shown in Figure 1b, in the in-plane wiring scheme adopted, the dummy line 01 and the Data lead 00 actually connected to the data line Data are evenly distributed, so that the load of each column of pixel units 1 arranged side by side in the row direction of the display area AA changes continuously, which improves the display effect to a certain extent compared to the technical solution shown in Figure 1a. However, although the load of each column changes continuously, the difference between the maximum and minimum values ​​of the load is large. Therefore, under the same screen, the brightness of different positions in the AA area is tested using an optical device (eye1 or CMD700D). It is found that there is a large difference between the brightness at the position of the maximum load and the brightness at the position of the minimum load. It can be seen from this that although the load of each column changes continuously, due to the difference between the maximum and minimum values ​​of the load in the entire display area AA, it will also cause uneven display problems, affecting the display effect.

[0061] In view of this, an embodiment of the present disclosure provides a display substrate, in which the dummy line 01 and the data lead 00 in the display area AA form a loop circuit. This adaptive adjustment of the load of the corresponding column pixel unit 1 can make the total load of the adjacent column pixel units 1 approximately equal, thereby achieving load balancing within the display area AA surface, thereby enhancing the uniformity of the display and improving the display effect.

[0062] The specific structure of a display substrate provided by an embodiment of the present disclosure is described in detail below. Figure 2 is a schematic diagram of a display substrate provided by an embodiment of the present disclosure, Figure 3a is a schematic diagram of a first signal line electrically connected to a third signal line provided by an embodiment of the present disclosure, Figure 3b is a schematic diagram of an exemplary embodiment of the present disclosure, a first signal line electrically connected to multiple third signal lines, and Figure 3c is another exemplary embodiment of the present disclosure, a first signal line electrically connected to multiple third signal lines.

[0063] As shown in FIG2 , the display substrate includes a base substrate on which are arranged M rows and N columns of pixel units 1 in an array, where M and N are both positive integers, and M is not equal to N. Pixel units 1 in the same row are electrically connected to the same first signal line 21, and pixel units 1 in the same column are electrically connected to the same second signal line 22. With this one-to-one wiring arrangement, the first signal of the first signal line 21 in each row is the same, and the second signal of the second signal line 22 in each column is the same. Thus, each pixel unit 1 in the display area AA can independently emit light and display.

[0064] To facilitate understanding and avoid confusion between the second signal lines 22 and the third signal lines 23 arranged along the column direction Y, only the first signal lines 21 and the third signal lines 23 are shown in FIG. 3 a to FIG. 3 c , and the second signal lines 22 are not shown.

[0065] For any column of pixel units 1 , at least one third signal line 23 is provided on two opposite sides in the row direction X. Any first signal line 21 is electrically connected to at least one third signal line 23 , and multiple third signal lines 23 electrically connected to the same first signal line 21 are electrically connected.

[0066] As shown in FIG. 3 a , FIG. 3 b or FIG. 3 c , for any column of pixel units 1 , two opposite sides in the row direction X are each provided with a third signal line 23 .

[0067] For example, as shown in Figure 3a, the first signal line 21 is electrically connected to a third signal line 23. In this case, the capacitance formed from one end 21_a of the first signal line 21 to the connection node 3, and the sum of the capacitances formed by the third signal line 23 electrically connected to the first signal line 21 and the first signal lines 21 in other rows is recorded as the first load. The resistance formed from one end 21_a of the first signal line 21 to the connection node 3, and the sum of the resistance of the third signal line 23 electrically connected to the first signal line 21 from the connection node 3 to the signal input terminal 4 is recorded as the second load. The product of the first load and the second load can be used to represent the total load.

[0068] It should be noted that the capacitor is formed at the overlapping position of the first signal line 21 and the third signal line 23 .

[0069] Exemplarily, as shown in FIG3b, the first signal line 21 is electrically connected to two third signal lines 23, and the first third signal line 23_1 is electrically connected to the second third signal line 23_2. For example, the first end of the first third signal line 23_1 is connected to the connection pad (i.e., the location of the signal input terminal 4), the second end of the first third signal line 23_1 is connected to the first end of the connection line 24, the second end of the connection line 24 is connected to the first end of the second third signal line 23_2, and the second end of the second third signal line 23_2 is connected to the first signal line 21. In this case, the capacitance formed by one end 21_a of the first signal line 21 to the connection node 3 and the sum of the capacitances formed by each third signal line 23 are recorded as the first load. The resistance formed by one end 21_a of the first signal line 21 connected to the connection node 3 and the sum of the resistances formed by each third signal line 23 are recorded as the second load. It should be noted that in FIG3b, the two third signal lines 23 are partially connected in parallel through the connection line 24 and the first signal line 21 to which they are connected. The product of the first load and the second load can be used to represent the total load.

[0070] For example, as shown in FIG3c , the first signal line 21 electrically connects two third signal lines 23, and the first third signal line 23_1 is electrically connected to the second third signal line 23_2. For example, the first end of the first third signal line 23_1 is connected to the signal input terminal 4; the first end of the first third signal line 23_1 and the second end of the second third signal line 23_2 are electrically connected via a first connecting line 24_1; and the second end of the first third signal line 23_1 and the first end of the second third signal line 23_2 are electrically connected via a second connecting line 24_2. In this case, the capacitance formed from one end 21_a of the first signal line 21 to the connection node 3, and the sum of the capacitances formed by each third signal line 23, is denoted as the first load. The resistance formed from one end 21_a of the first signal line 21 to the connection node 3, and the sum of the resistances formed by each third signal line 23, is denoted as the second load. It should be noted that in FIG3c , the two third signal lines 23 are connected in parallel via the connecting line 24 and the first signal line 21 to which they are connected. The product of the first load and the second load can be used to represent the total load.

[0071] For ease of understanding, the present embodiment is described using an example in which each column of pixel units 1 is provided with a third signal line 23 on two opposite sides in the row direction X. Of course, the present embodiment can also be configured by rounding down M / N and adding 1 to set the number of lead lines per column of pixel units 1 (i.e., the number of third signal lines 23).

[0072] Here, the first signal line 21 can be a gate line Gate, and the second signal line 22 can be a data line Data; alternatively, the first signal line 21 can also be a data line Data, and the second signal line 22 can also be a gate line Gate. This disclosure takes the example where the first signal line 21 is a data line Data and the second signal line 22 is a gate line Gate.

[0073] Illustratively, for any two first signal lines 21 , the ratio of the product of the total capacitance and the total resistance formed by one end 21_a of the first signal line 21 and the third signal line 23 electrically connected thereto is in the range of 0.5 to 1.5.

[0074] Illustratively, for any two first signal lines 21 , the ratio of the product of the total capacitance and the total resistance formed by one end 21_a of the first signal line 21 and the third signal line 23 electrically connected thereto is in a range of 0.9 to 1.1.

[0075] The in-plane routing scheme of the display substrate shown in FIG2 employs, for example, at least two of the in-plane routing schemes shown in FIG3a, FIG3b, and FIG3c. For any two first signal lines 21, such as the routing schemes corresponding to the two first signal lines 21 shown in FIG3a and FIG3b, the product of the total capacitance and the total resistance is used to characterize the total load, as described in the above example. Through adaptive position adjustment, the two routing schemes are applied to first signal lines 21 in different rows of the display substrate, respectively, so that the resulting total loads are approximately equal, and the total load ratio approaches 1.

[0076] Exemplarily, for any two first signal lines 21 , the product of the total capacitance and the total resistance formed by one end 21_a of the first signal line 21 and the third signal line 23 electrically connected thereto is equal.

[0077] The display substrate provided in the embodiments of the present disclosure connects some of the third signal lines 23 within display area AA to form a loop circuit, achieving dynamic load adjustment. Subsequently, through adaptive position adjustment, a suitable routing scheme is selected from among several different in-plane routing schemes shown in Figures 3a, 3b, or 3c and applied to first signal lines 21 in different rows. This ensures that, for any two first signal lines 21, the total load formed by one end 21_a of a first signal line 21 and the third signal line 23 electrically connected thereto is approximately equal, achieving load balancing within display area AA, thereby enhancing display uniformity and improving display quality.

[0078] In some embodiments, as shown in FIG2 , the display substrate further includes an integrated chip IC disposed on the base substrate, and the integrated chip IC is located on one side of the display area where the M rows and N columns of pixel units 1 arranged in an array are located, opposite to each other along the column direction Y.

[0079] As shown in Figure 1a or Figure 1b, it should be noted that the third signal line 23 electrically connected to the first signal line 21 is all drawn out from the integrated chip IC. The farther the connection node 3 between the first signal line 21 and the third signal line 23 is from the integrated chip IC, the longer the path of the third signal line 23 from the integrated chip IC to the electrical connection with the first signal line 21, and the greater the resistance; conversely, the smaller. In addition, the farther the connection node 3 between the first signal line 21 and the third signal line 23 is from the integrated chip IC, the more rows of first signal lines 21 the third signal line 23 passes through from the integrated chip IC to the electrical connection with the first signal line 21, and the greater the sum of the capacitances formed at each overlapping position; conversely, the smaller. Therefore, the farther the first signal line 21 is from the integrated chip IC, the greater the total load of the third signal line 23 connected. Therefore, in the prior art, there is a large difference between the maximum and minimum load values ​​within the entire display area AA, resulting in uneven display effects.

[0080] For example, FIG4 is a schematic diagram of the routing of different rows of first signal lines 21 and the third signal lines 23 electrically connected thereto provided in an embodiment of the present disclosure. As shown in FIG4 , in order to further understand the resistance difference of the routing at different positions within the plane, a resistance simulation is performed, wherein the lengths and widths of the metal lines in FIG (a) to FIG (d) are equal. The longitudinal distance between the transverse metal lines (equivalent to the first signal lines 21) in two adjacent groups of simulation experiments is the distance between the first signal lines 21 in two adjacent rows. For example, the length of the metal line is 100 μm and the width is 10 μm. The resistance of the metal line Rab in the ab segment, the resistance of the metal line Rcd in the cd segment, the resistance of the metal line Ref in the ef segment, and the resistance of the metal line Rgh in the gh segment are measured respectively, and the simulation results show that the difference in adjacent resistances is between 15% Rs and 28% Rs. The difference between the maximum resistance Rab and the minimum resistance Rgh is 51% Rs. Rs represents the unit resistance of the metal line per 1 square micron. That is to say, the difference between the maximum and minimum values ​​of the load is large, and there is a large difference in brightness at the position of the maximum load and the position of the minimum load, which will cause uneven display and affect the display effect.

[0081] Figure 5 is a schematic diagram of the in-plane routing layout of Example 1 provided in an embodiment of the present disclosure, Figure 6 is a schematic diagram of the in-plane routing layout of Example 2 provided in an embodiment of the present disclosure, Figure 7 is a schematic diagram of the in-plane routing layout of Example 3 provided in an embodiment of the present disclosure, and Figure 8 is a schematic diagram of the in-plane routing layout of Example 4 provided in an embodiment of the present disclosure.

[0082] In some embodiments, as shown in Figures 5, 6, 7, or 8, the orthographic projections of multiple third signal lines 23 electrically connected to the same first signal line 21 on the substrate fall within the orthographic projections of the same column of pixel units 1 on the substrate. This eliminates the need for cross-line layout when electrically connecting multiple third signal lines 23, reducing wiring difficulty and improving process efficiency. Furthermore, the proximity connection can also relatively reduce the resistance of the connecting line 24, thereby balancing the load of two adjacent columns of pixel units 1.

[0083] Of course, if a larger resistance is required to balance the loads at adjacent positions, the plurality of third signal lines 23 electrically connected to the same first signal line 21 may also be distributed in different columns of pixel units 1 .

[0084] In some embodiments, as shown in FIG. 5 , 6 , 7 or 8 , the first signal line 21 electrically connected to one third signal line 23 is farther away from the integrated chip IC than the first signal line 21 electrically connected to multiple third signal lines 23 .

[0085] Since the lengths of the first signal lines 21 in each row are the same, the present disclosure ignores the statistics of the loads generated by the first signal lines 21 and only considers the loads generated by the third signal lines 23 electrically connected to the first signal lines 21 .

[0086] Illustratively, since the first signal line 21 electrically connected to one third signal line 23 is farther away from the integrated chip IC than the first signal line 21 electrically connected to multiple third signal lines 23, the total resistance R1 formed by one end 21_a of the first signal line 21 electrically connected to one third signal line 23 and the third signal line 23 electrically connected thereto is greater than the total resistance R2 formed by one end 21_a of the first signal line 21 electrically connected to multiple third signal lines 23 and the third signal line 23 electrically connected thereto, that is, R1>R2; here, by connecting multiple third signal lines 23, the total capacitance is increased, thereby balancing the load, achieving display uniformity, and improving the display effect.

[0087] Figure 9a is a schematic diagram of the T-shaped trace provided by the embodiment of the present disclosure without disconnection, and Figure 9b is a schematic diagram of the T-shaped trace provided by the embodiment of the present disclosure after disconnection. The difference between the disconnection and non-disconnection of the T-shaped trace is analyzed by simulation. In the simulation software, two metal wires with a length of 100um and a width of 10um are set respectively, and the two intersect vertically. Figure 9a shows the intersection pattern, and Figure 9b shows the pattern of the two metal wires disconnected at the intersection. The unit resistance of each square micron of metal wire is set to Rs = 100Ω. The resistance of the ij segment metal wire Rij and the resistance of the kl segment metal wire Rkl are measured respectively, and Rij = 1400Ω and Rkl = 1400Ω are obtained. It can be seen that whether the wire is disconnected has no effect on the metal resistance.

[0088] It should also be noted that the pixel capacitance includes the capacitance of the TFT in the pixel unit 1, the capacitance of the first signal line 21, the capacitance on the second signal line 22, and the capacitance on the third signal line 23 (i.e., the lead). Taking the resolution of 1200 (Data) × 800 (Gate) as an example, when the first signal is a Data signal, the capacitance of the first signal line 21 is calculated based on the TFT off state. The capacitance of the first signal line 21 accounts for 22% of the pixel capacitance, the capacitance of the third signal line 23 accounts for 27% of the pixel capacitance, and the TFT capacitance accounts for 51% of the pixel capacitance. When the first signal is a Gate signal, the capacitance of the first signal line 21 is calculated based on the TFT on state. The capacitance of the first signal line 21 accounts for 10% of the pixel capacitance, the capacitance of the third signal line 23 accounts for 10% of the pixel capacitance, and the TFT capacitance accounts for 80% of the pixel capacitance.

[0089] From the above analysis, it can be seen that when the third signal line 23 is disconnected and the first signal is the Data signal, the difference between the maximum and minimum values ​​of the pixel capacitance is 27%; when the third signal line 23 is disconnected and the first signal is the Gate signal, the difference between the maximum and minimum values ​​of the pixel capacitance is 10%. In other words, the disconnection has an impact on the metal capacitance. The difference between the maximum and minimum values ​​of the load is large, and there is a large difference in brightness at the location of the maximum load and the location of the minimum load, which will cause uneven display and affect the display effect.

[0090] Figure 10 is a schematic diagram of the in-plane routing layout of Example 5 provided in an embodiment of the present disclosure, Figure 11 is a schematic diagram of the in-plane routing layout of Example 6 provided in an embodiment of the present disclosure, Figure 12 is a schematic diagram of the in-plane routing layout of Example 7 provided in an embodiment of the present disclosure, and Figure 13 is a schematic diagram of the in-plane routing layout of Example 8 provided in an embodiment of the present disclosure.

[0091] In some embodiments, as shown in FIG. 10 , 11 , 12 or 13 , among at least one third signal line 23 electrically connected to some rows of first signal lines 21 , at least one third signal line 23 is disconnected at the connection node 3 with the first signal line 21 .

[0092] Exemplarily, M rows of pixel units 1 are divided into two parts arranged in parallel along the column direction Y, the first part is farther away from the integrated chip IC than the second part, the first part includes m1 rows of pixel units 1, 1≤m1<M, and m1 is an integer; the second part includes m2 rows of pixel units 1, 1≤m2<M, and m2 is an integer, m1+m2=M.

[0093] The first signal line 21 of the first portion is electrically connected to only one third signal line 23, and the third signal line 23 is disconnected at the connection node 3. The first signal line 21 of the second portion is electrically connected to multiple third signal lines 23. Except for the third signal line 23 directly connected to the integrated chip, at least one of the other third signal lines 23 is disconnected at the connection node 3 with the first signal line 21.

[0094] Since whether the line is broken has no effect on the resistance of the third signal line 23, only the capacitance effect needs to be considered. For example, in the direction close to the integrated chip IC, the first signal line 21 in the first row to the first signal line 21 in the Mth row are arranged in sequence. For the first signal line 21 in the first row, the total capacitance formed by one end 21_a of the first signal line 21 and the signal input terminal 4 of the third signal line 23 electrically connected thereto includes 5C, and the resistance includes 5R + the resistance R3 from one end 21_a of the first signal line 21 to the connection node 3, where C represents the capacitance at the overlapping position of the first signal line 21 and the third signal line 23, and R represents the resistance of the third signal line 23 between two adjacent rows of first signal lines 21. When the third signal line 23 electrically connected to the second-row first signal line 21 is intact, the total capacitance formed by one end 21_a of the first signal line 21 and the signal input terminal 4 of the third signal line 23 electrically connected thereto is 6C (including the capacitance formed by the overlap between the third signal line 23 and the first-row first signal line 21). The resistance is 4R + the resistance R4 from the one end 21_a of the first signal line 21 to the connection node 3, where R4>R3. Therefore, the total load of the first signal line 21 in the first row is approximately 5C × (5R + R3), and the total load of the first signal line 21 in the second row is approximately 6C × (4R + R4). Because 5R + R3 and 4R + R4 are approximately equal, the total load of the first signal line 21 in the first row is less than that of the first signal line 21 in the second row. At this time, if the third signal line 23 electrically connected to the first signal line 21 of the second row is broken, the capacitance formed by the third signal line 23 no longer includes the capacitance at the overlapping position with the first signal line 21 of the first row, and the total capacitance is reduced to 5C, thereby achieving that for any two first signal lines 21, the total load formed by one end 21_a of the first signal line 21 and the third signal line 23 electrically connected thereto is approximately equal.

[0095] In some embodiments, as shown in FIG. 3 c , FIG. 12 or FIG. 13 , among the plurality of third signal lines 23 connected to the same first signal line 21 , two adjacent third signal lines 23 are connected in parallel at both ends via a connecting line 24 .

[0096] Figure 14a is a schematic diagram of a single third signal line 23 provided in an embodiment of the present disclosure that is disconnected at the connection node 3, Figure 14b is a schematic diagram of multiple third signal lines 23 provided in an embodiment of the present disclosure that are disconnected at the connection node 3 and connected in parallel, and Figure 14c is a schematic diagram of multiple third signal lines 23 provided in an embodiment of the present disclosure that are connected in parallel end to end.

[0097] As shown in Figures 14a to 14c, resistance simulations were performed for three different wiring schemes, using a metal line length of 100 μm and a width of 10 μm. The resistance of the metal line in the mn segment, Rmn, the metal line in the op segment, Rop, and the metal line in the qr segment, Rqr, were measured. The final simulation results show that Rmn is 8% greater than Rop, and Rmn is 25% greater than Rqr. This indicates that wiring with additional branches is more effective in reducing resistance. In other words, the more loops (the greater the number of parallel third signal lines 23), the lower the resistance.

[0098] As shown in Figures 10 to 13, simulation tests show that when the first signal line 21 is the data line Data, the capacitance is increased in the range of 1%C to 27%C; when the first signal is the gate line Gate, the capacitance is increased in the range of 1%C to 10%C. Based on the product of the total resistance and the total capacitance, a connection method such as Figures 10, 11, 12, or 13 can be adaptively selected to ensure that the product of the total resistance and the total capacitance formed by one end 21_a of the first signal line 21 and the third signal line 23 electrically connected thereto is approximately equal, thereby achieving load balancing within the display area AA, thereby enhancing display uniformity and improving display effects.

[0099] In some embodiments, as shown in Figures 5, 6, 7 or 8, for the case where the line is not broken, for the first signal line 21 electrically connected to a third signal line 23, one end of the third signal line 23 electrically connected thereto is connected to the integrated chip IC, and the other end is connected to the anti-static unit or the reference voltage terminal.

[0100] Exemplarily, the anti-static unit is used to transfer static electricity on the long wire to the TFT channel in the anti-static unit.

[0101] Illustratively, the reference voltage terminal may be a terminal connected to a lower voltage, such as a ground terminal. In the embodiments of the present disclosure, the reference voltage terminal is described as an example of a ground terminal.

[0102] In some embodiments, as shown in Figures 5, 6, 7 or 8, for the case where the line is not broken, among the multiple third signal lines 23 connected to the same first signal line 21, one end of one third signal line 23 is electrically connected to the integrated chip IC, and one end of one third signal line 23 is electrically connected to the anti-static unit or the reference voltage terminal.

[0103] Exemplarily, if the first signal line 21 is electrically connected to two third signal lines 23 , one end of one third signal line 23 is electrically connected to the integrated chip IC, and one end of the other third signal line 23 is electrically connected to the anti-static unit or the reference voltage terminal.

[0104] Exemplarily, if the same first signal line 21 is electrically connected to multiple third signal lines 23, and the number of the multiple third signal lines 23 is greater than 2, one end of the first third signal line 23 is electrically connected to the integrated chip IC, one end of the last third signal line 23 is electrically connected to the anti-static unit or the reference voltage end, one end of the other third signal lines 23 is electrically connected to the other end of the first third signal line 23 (and the other end of the last third signal line 23), and one end of the other third signal lines 23 is electrically connected to the first signal line 21.

[0105] In some embodiments, as shown in Figure 10 or Figure 11, the first signal line 21 electrically connected to the plurality of third signal lines 23 includes multiple first signal lines 21; for each first signal line 21 electrically connected to the plurality of third signal lines 23, the connection line of the i-th connection node 3 of each first signal line 21 is located on the same first straight line, where i is a positive integer.

[0106] In some embodiments, as shown in FIG. 10 or FIG. 11 , the connection line of the i-th connection node 3 of each first signal line 21 and the connection line of the i+1-th connection node 3 of each first signal line 21 are parallel to each other.

[0107] The diagonal connection node 3 can balance the load within the display area AA, enhance the display uniformity, and improve the display effect.

[0108] In some embodiments, as shown in Figure 12 or Figure 13, the first signal line 21 electrically connected to the plurality of third signal lines 23 includes multiple first signal lines 21; for each first signal line 21 electrically connected to the plurality of third signal lines 23, the connection line of the i-th connection node 3 of each first signal line 21 is not located on the same first straight line, where i is a positive integer.

[0109] In some embodiments, as shown in Figure 12 or Figure 13, for some of the first signal lines 21 electrically connected to multiple third signal lines 23, the connection line of the i-th connection node 3 of each first signal line 21 is located on the same first straight line, and the connection line of the i-th connection node 3 of each first signal line 21 is parallel to the connection line of the i+1-th connection node 3 of each first signal line 21.

[0110] The first signal lines 21 electrically connected to a third signal line 23 are concentrated together, and the third signal lines 23 connected to the first signal lines 21 concentrated together divide the display area into a left half area 5 and a right half area 6. In the left half area 5, for each first signal line 21 electrically connected to multiple third signal lines 23, the connection line of the i-th connection node 3 of each first signal line 21 is located on the same first straight line; in the right half area 6, for each first signal line 21 electrically connected to multiple third signal lines 23, the connection line of the i-th connection node 3 of each first signal line 21 is located on the same second straight line.

[0111] Illustratively, there is a certain angle between the extension line of the first straight line and the extension line of the second straight line.

[0112] For example, in the left half region 5, the connection nodes of the first signal lines farther from the integrated chip IC are closer to the right half region 6; and in the right half region 6, the connection nodes of the first signal lines farther from the integrated chip IC are closer to the left half region 5. For the first signal lines 21 electrically connected to the plurality of third signal lines 23, the first signal lines with connection nodes are spaced apart in the left half region 5; and the first signal lines with connection nodes are spaced apart in the right half region 6.

[0113] Illustratively, in the left half region 5, for each first signal line 21 electrically connected to the plurality of third signal lines 23, the line connecting the i-th connection node 3 of each first signal line 21 is parallel to the line connecting the i+1-th connection node 3 of each first signal line 21. In the right half region 6, for each first signal line 21 electrically connected to the plurality of third signal lines 23, the line connecting the i-th connection node 3 of each first signal line 21 is parallel to the line connecting the i+1-th connection node 3 of each first signal line 21.

[0114] The spiral connection node 3 can balance the load within the display area AA, enhance the display uniformity, and improve the display effect.

[0115] In some embodiments, the display substrate further includes a first conductive layer, an insulating layer, and a second conductive layer sequentially arranged on the base substrate; the first signal line 21 is located in the first conductive layer; the second signal line 22 and the third signal line 23 are located in the second conductive layer; the third signal line 23 is electrically connected to the first signal line 21 through a connecting via penetrating the insulating layer.

[0116] In the embodiment of the present disclosure, the dummy line in the display area AA and the third signal line 23 with smaller resistance (that is, the third signal line 23 connected to the node 3 which is closer to the integrated IC) form a loop circuit to increase the capacitance of the third signal line 23 with smaller resistance. Therefore, this combination of small resistance and large capacitance can balance the product of capacitance and resistance within the display area AA surface, or balance the load within the display area AA surface, thereby enhancing the uniformity of the display and improving the display effect.

[0117] The display substrate provided in the embodiment of the present disclosure can be applied to display devices such as electrophoretic display ESL, mini LED, LCD with in-plane wiring, etc., which will not be described in detail in this disclosure. The embodiment of the present disclosure is described by taking the application of the display substrate to an electrophoretic display device as an example.

[0118] Specifically, the display substrate has an ESL architecture and further includes a display layer, which includes a stacked first electrode layer, an electronic ink layer, and a second electrode layer. The first electrode layer includes first electrodes of a plurality of pixel units 1, and the second electrode layer includes second electrodes of a plurality of pixel units 1. One of the first electrode and the second electrode is an ITO pixel electrode, and the other is a common electrode Vcom.

[0119] The electronic ink layer includes multiple microcapsules or multiple microcups, and a number of charged particles are arranged in the microcapsules or microcups. The charged particles include multiple colors; the pixel driving circuit in each pixel unit 1 is electrically connected to the first electrode to drive the display screen.

[0120] By applying voltage to the first and second electrodes to form an electric field, the charged particles of different colors are driven to move according to the current applied voltage, thereby displaying different colors on the surface of the electronic paper. For example, in the case of a microcapsule structure, when a negative electric field is applied to both ends of the microcapsule, the negatively charged white particles move to the top of the microcapsule under the action of the electric field. At the same time, the positively charged black particles move to the bottom of the microcapsule and "hide" there, and the surface will appear white. When a positive electric field is applied to both sides of the adjacent microcapsules, the black particles will move to the top of the microcapsule under the action of the electric field, and the surface will appear black. Simply put, the microcapsule structure uses charged particles to form a bistable state under the action of the electric field, so that the electronic paper can still display the state before the power is turned off after the power is turned off.

[0121] Each pixel driving circuit in the pixel units 1 located in the same row is connected to the same first signal line 21, and each pixel driving circuit in the pixel units 1 in different rows is connected to a different first signal line 21. Each pixel driving circuit in the pixel units 1 located in the same column is connected to the same second signal line 22, and each pixel driving circuit 21 in the pixel units 1 in different columns is connected to a different second signal line 22. Take the first signal line 21 as the data line Data and the second signal line 22 as the gate line Gate as an example. The data line Data and the gate line Gate are both electrically connected to the integrated chip IC, and the integrated chip IC provides a data signal (Data signal) to the pixel driving circuit connected thereto through the data line Data, thereby providing a driving voltage to the pixel electrode ITO, so that the pixel electrode ITO and the common electrode Vcom form a vertical electric field.

[0122] In addition, an embodiment of the present disclosure further provides an electrophoretic display device, which includes the display substrate of any one of the above embodiments.

[0123] The electrophoretic display device can be, for example, an electronic price tag, reader, outdoor bus stop sign, or other electrophoretic display product requiring a narrow frame. Other essential components of the electrophoretic display device are well understood by those skilled in the art and are not described here in detail and should not be construed as limiting the present disclosure.

[0124] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a base substrate, and pixel units arranged in an array of M rows and N columns on the base substrate, wherein M and N are both positive integers, and M is not equal to N; wherein: The pixel units located in the same row are electrically connected to the same first signal line, and the pixel units located in the same column are electrically connected to the same second signal line; For any column of the pixel units, at least one third signal line is respectively arranged on two opposite sides in the row direction; wherein, for any first signal line, at least one third signal line is electrically connected, and a plurality of third signal lines electrically connected to the same first signal line are electrically connected; For any two of the first signal lines, a ratio of a product of a total resistance and a total capacitance formed by one end of the first signal line and the third signal line electrically connected thereto is in a range of 0.5 to 1.

5.

2. The display substrate according to claim 1, wherein: The display substrate further comprises an integrated chip disposed on the base substrate, and the integrated chip is located on one side of the display area where the M rows and N columns of pixel units arranged in an array are located, which is opposite to each other along the column direction.

3. The display substrate according to claim 2, wherein: The first signal line electrically connected to one of the third signal lines is farther away from the integrated chip than the first signal line electrically connected to a plurality of the third signal lines.

4. The display substrate according to claim 1, wherein: At least one of the at least one third signal line electrically connected to the first signal line in some rows is disconnected at a connection node with the first signal line.

5. The display substrate according to claim 4, wherein: Among the plurality of third signal lines connected to the same first signal line, except for the third signal line directly connected to the integrated chip, at least one of the other third signal lines is disconnected at a connection node with the first signal line.

6. The display substrate according to claim 1, wherein: Among the plurality of third signal lines connected to the same first signal line, two ends of two adjacent third signal lines are connected in parallel via connection lines.

7. The display substrate according to claim 2, wherein: For the first signal line electrically connected to one of the third signal lines, one end of the third signal line electrically connected thereto is connected to the integrated chip, and the other end is connected to an antistatic unit or a reference voltage terminal.

8. The display substrate according to claim 2, wherein: Among the plurality of third signal lines connected to the same first signal line, one end of one third signal line is electrically connected to the integrated chip, and one end of one third signal line is electrically connected to the antistatic unit or the reference voltage terminal.

9. The display substrate according to any one of claims 1 to 8, wherein: The first signal lines electrically connected to the plurality of third signal lines include a plurality of lines; For each of the first signal lines electrically connected to the plurality of third signal lines, the connection lines of the i-th connection nodes of each of the first signal lines are located on the same first straight line; i is a positive integer.

10. The display substrate according to claim 9, wherein: The connection line of the i-th connection node of each of the first signal lines and the connection line of the i+1-th connection node of each of the first signal lines are parallel to each other.

11. The display substrate according to any one of claims 1 to 8, wherein: The first signal lines electrically connected to the plurality of third signal lines include a plurality of lines; For each of the first signal lines electrically connected to the plurality of third signal lines, the connection lines of the i-th connection nodes of each of the first signal lines are not located on the same first straight line; i is a positive integer.

12. The display substrate according to claim 11, wherein: For some of the first signal lines electrically connected to multiple third signal lines, the connection lines of the i-th connection nodes of each of the first signal lines are located on the same first straight line, and the connection lines of the i-th connection nodes of each of the first signal lines are parallel to the connection lines of the i+1-th connection nodes of each of the first signal lines.

13. The display substrate according to any one of claims 1 to 8, wherein: For any two of the first signal lines, the product of the total capacitance and the total resistance formed by one end of the first signal line and the signal input end of the third signal line electrically connected thereto is equal.

14. The display substrate according to any one of claims 1 to 8, wherein: For the plurality of third signal lines electrically connected to the same first signal line, their orthographic projections on the substrate fall into the orthographic projections of the pixel units in the same column on the substrate.

15. The display substrate according to any one of claims 1 to 8, wherein: The display substrate further comprises a first conductive layer, an insulating layer and a second conductive layer sequentially arranged on the base substrate; The first signal line is located in the first conductive layer; The second signal line and the third signal line are located in the second conductive layer; The third signal line is electrically connected to the first signal line through a connection via hole penetrating the insulating layer.

16. The display substrate according to claim 1, wherein: The display substrate is applied to an electrophoretic display device.

17. An electrophoretic display device, comprising the display substrate according to any one of claims 1 to 16.

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