Array substrate and manufacturing method therefor, display panel, and display device

Abstract

The present application relates to the technical field of display, and discloses an array substrate and a manufacturing method therefor, a display panel, and a display device. The array substrate comprises a base substrate, and a first light-emitting layer and a second light-emitting layer which are sequentially arranged on the base substrate. In at least one sub-pixel region in the array substrate, the first light-emitting layer emits light of a first brightness, and the second light-emitting layer emits light of a second brightness or does not emit light, wherein the second brightness is lower than the first brightness. The array substrate reduces the light-emitting brightness of the second light-emitting layer, thereby reducing the power consumption of the array substrate.

Description

Array substrate and manufacturing method thereof, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202310974012.3 filed on August 3, 2023, entitled “Array substrate, manufacturing method thereof, display panel and display device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel and a display device. Background Art

[0003] With the development of display technology, various display devices are being widely used. Display devices include: display panels, drivers, power supply units, etc. The display panel is composed of a cover plate and an array substrate stacked on top of each other.

[0004] In the related art, the array substrate includes two light-emitting layers, but the two light-emitting layers in the array substrate both emit light in a sub-pixel area, and different light-emitting effects are achieved through filters. The simultaneous emission of the two light-emitting layers causes the array substrate to consume more power.

[0005] Summary of the Invention

[0006] The present invention provides an array substrate and a manufacturing method thereof, a display panel, and a display device, which can be used to solve the problems existing in the related art. The technical solution is as follows:

[0007] In one aspect, an embodiment of the present application provides an array substrate, comprising: a base substrate, and a first light-emitting layer and a second light-emitting layer sequentially arranged on the base substrate;

[0008] In at least one sub-pixel region in the array substrate, the first light-emitting layer emits light with a first brightness, and the second light-emitting layer emits light with a second brightness or does not emit light, and the second brightness is lower than the first brightness.

[0009] In another aspect, a method for preparing an array substrate is provided, wherein the method is used to prepare the above array substrate, and the method comprises:

[0010] Depositing multiple layers of inorganic material on a side of the first electrode layer away from the substrate to form a multi-layer inorganic film, wherein the multi-layer inorganic film is formed into a desired shape after a patterning process, and the thickness of each film layer of the multi-layer inorganic film is related to the structure of the light-emitting device;

[0011] Depositing at least two layers of light-emitting devices on a side of the multi-layered inorganic film away from the first electrode layer;

[0012] A filter is arranged on the side of the packaged light emitting device away from the multi-layer inorganic film.

[0013] On the other hand, a display panel is provided, comprising a cover plate and the array substrate described in the above aspect; a portion of the array substrate except the base substrate is located between the base substrate and the cover plate.

[0014] On the other hand, the display device includes: a driver and the display panel described in the other hand; the driver is used to drive the display panel.

[0015] The technical solutions provided by the embodiments of the present application bring at least the following beneficial effects:

[0016] The technical solution provided by the embodiments of the present application is that the brightness of light emitted by the second light-emitting layer of the array substrate's two light-emitting layers is lower than that of the first light-emitting layer. By reducing the brightness of the second light-emitting layer, the power consumption of the array substrate can be reduced. Furthermore, when the second light-emitting layer is non-luminous, the first light-emitting layer still emits light in the sub-pixel area where the second light-emitting layer is non-luminous. This eliminates the need for filters in the non-luminous areas of the second light-emitting layer, further reducing the manufacturing cost of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] FIG1 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0019] FIG2 is a schematic structural diagram of a pixel definition layer provided in an embodiment of the present application;

[0020] FIG3 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0021] FIG4 is a schematic diagram of a phenomenon of a negative penetration provided by an embodiment of the present application;

[0022] FIG5 is a schematic diagram of a phenomenon of a negative penetration provided by an embodiment of the present application;

[0023] FIG6 is a schematic structural diagram of a light emitting device circuit provided in an embodiment of the present application;

[0024] FIG7 is a schematic structural diagram of a pixel definition layer provided in an embodiment of the present application;

[0025] FIG8 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0026] FIG9 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0027] FIG10 is a schematic structural diagram of a pixel definition layer provided in an embodiment of the present application;

[0028] FIG11 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0029] FIG12 is a flow chart of a method for preparing an array substrate provided in an embodiment of the present application;

[0030] FIG13 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0031] FIG14 is a schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0033] It should be noted that the terms "first," "second," and the like in the description of the present application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It should be understood that the data used in this manner are interchangeable where appropriate so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application.

[0034] Referring to FIG1 , an embodiment of the present application provides an array substrate, which includes:

[0035] A base substrate 110, and a first light-emitting layer 102 and a second light-emitting layer 104 sequentially arranged on the base substrate 110;

[0036] In at least one sub-pixel region in the array substrate, the first light-emitting layer 102 emits light of a first brightness, and the second light-emitting layer 104 emits light of a second brightness or does not emit light, and the second brightness is lower than the first brightness.

[0037] The base substrate 110 is a substrate used in the manufacture of microelectronic products such as semiconductor devices and electronic components. The materials of the base substrate 110 include, but are not limited to, single crystal silicon, polycrystalline silicon, quartz glass, or alumina ceramics. In the embodiments of this application, the material of the base substrate 110 is not limited. During the production and manufacturing of the array substrate, the base substrate 110 is used to support and secure structures other than the base substrate 110 located on at least one side of the base substrate 110.

[0038] The first light-emitting layer 102 and the second light-emitting layer 104 are two light-emitting layers in the array substrate. Within at least one sub-pixel region, the second light-emitting layer 104 emits light of a second brightness that is lower than the first brightness emitted by the first light-emitting layer 102. This is to reduce the brightness of the light emitted within the at least one sub-pixel region, thereby reducing the power consumption of the array substrate. Furthermore, when the second light-emitting layer 104 is not emitting light, the light emitted by the first light-emitting layer 102 displays a color within the sub-pixel region where the second light-emitting layer 104 is not emitting light, thereby eliminating the need for a filter within the sub-pixel region. The embodiments of the present application do not limit the method for preventing the second light-emitting layer 104 from emitting light or emitting light of the second brightness.

[0039] In one possible embodiment, the second light-emitting layer 104 does not emit light, or emits light of a second brightness, which can be achieved by the array substrate described in the embodiment of the present application. As shown in Figure 1, the array substrate includes: a first electrode layer 101, a first CGL (Charge Generation Laye) 103 and a second electrode layer 105, the first light-emitting layer 102 and the second light-emitting layer 104 are both located between the first electrode layer 101 and the second electrode layer 105, the second electrode layer 105 is located on the side of the first electrode layer 101 away from the base substrate 110, and the first CGL 103 is located between the first light-emitting layer 102 and the second light-emitting layer 104.

[0040] In at least one sub-pixel region, the first CGL 103 is short-circuited with the first electrode layer 101 or the second electrode layer 105. Under this structure, the current between the first CGL 103 and the first electrode layer 101 or the second electrode layer 105 is transmitted through the short-circuit region, that is, no current flows through the first light-emitting layer 102 between the first CGL 103 and the first electrode layer 101 or the second light-emitting layer 104 between the first CGL 103 and the second electrode layer 105, thereby making the first light-emitting layer 102 or the second light-emitting layer 104 4 does not emit light; or, there are two links between the first CGL103 and the first electrode layer 101 or the second electrode layer 105, the two links are connected in parallel, one link is a direct link between the first CGL103 and the first electrode layer 101 or the second electrode layer 105, and the other link is a link between the first CGL103 and the first light-emitting layer 102 and the first light-emitting layer 102 to the first electrode layer 101 or the first CGL103 to the second light-emitting layer 104 and the second light-emitting layer 104 to the second electrode layer 105.

[0041] Exemplarily, there are a first link and a second link between the first CGL103 and the first electrode layer 101, and the first link and the second link are connected in parallel. The first link is a direct link between the first CGL103 and the first electrode layer 101, and the second link is a link between the first CGL103 and the first light-emitting layer 102 and the first light-emitting layer 102 and the first electrode layer 101; under this structure, the current between the first CGL103 and the first electrode layer 101 is transmitted through the first link and the second link, the current passing through the first light-emitting layer 102 is the current in the second link, and the current passing through the second light-emitting layer 104 is the sum of the currents in the first link and the second link. Therefore, the luminous brightness of the first light-emitting layer 102 is less than the luminous brightness of the second light-emitting layer 104.

[0042] Alternatively, a third link and a fourth link are provided between the first CGL 103 and the second electrode layer 105. The third link is a direct link between the first CGL 103 and the second electrode layer 105, and the fourth link is a link between the first CGL 103 and the second light-emitting layer 104, and vice versa. In this structure, the current between the first CGL 103 and the second electrode layer 105 is transmitted via the third link and the fourth link. The current passing through the second light-emitting layer 104 is the current in the fourth link, and the current passing through the first light-emitting layer 102 is the sum of the currents in the third link and the fourth link. Therefore, the luminescence brightness of the second light-emitting layer 104 is lower than that of the first light-emitting layer 102.

[0043] In another possible embodiment, as shown in FIG1 , the array substrate further includes a pixel defining layer 109 for defining a sub-pixel area, and the pixel defining layer 109 is located on a base substrate 110. The first light-emitting layer 102, the second light-emitting layer 104, the first CGL 103, and the second electrode layer 105 in the array substrate are all located on a side of the pixel defining layer 109 away from the base substrate 110. In the embodiment of the present application, the pixel defining layer 109 can be as described above with respect to the array substrate, so that a link is formed between the first CGL 103 and the first electrode layer 101 or the second electrode layer 105, thereby achieving the effect of controlling the second light-emitting layer 104 to not emit light, or to emit light of a second brightness.

[0044] Referring to Figures 1 and 2, in the pixel defining layer structure shown in Figure 2, in the first sub-pixel region 111 in at least one sub-pixel region, the side surface of the pixel defining layer 109 close to the first sub-pixel region 111 has a slope angle α. The slope angle α is used to form an isolation column structure. Based on the isolation column structure, in the first sub-pixel region 111, the second electrode layer 105 and the first CGL 103 are short-circuited, thereby achieving the effect that the second light-emitting layer 104 does not emit light at all. Alternatively, in the case where there are two links described in the above embodiment between the second electrode layer 105 and the first CGL 103, the second brightness of light emitted by the second light-emitting layer 104 is less than the first brightness. Exemplarily, the slope angle α is ≥ 75°, and the slope angle α can be determined based on the design structure of the array substrate.

[0045] Referring to FIG3 , an embodiment of the present application provides an array substrate based on the above-described embodiment. In FIG1 , the first electrode layer 101 corresponds to the anode 301, the first light-emitting layer 102 corresponds to the lower light-emitting unit 302, the first CGL 103 corresponds to the CGL 303, the second light-emitting layer 104 corresponds to the upper light-emitting unit 304, the second electrode layer 105 corresponds to the cathode 305, the first sub-pixel region 111 corresponds to the first sub-pixel region 306, and the second sub-pixel region 112 corresponds to the second sub-pixel region 307 for illustration.

[0046] In the first sub-pixel region 306 of the array substrate, the film layer of the cathode 305 is thinner near the side of the first sub-pixel region 306 due to shadows during the evaporation process, and a cathode penetration phenomenon will occur when the cathode 305 is deposited, as shown in the schematic diagrams of the cathode penetration phenomenon in Figures 4 and 5. That is, there are two links between the CGL303 and the cathode 305 for current transmission. The embodiment of the present application is explained by taking the upper unit light-emitting layer 304 as a blue light-emitting layer and the lower unit light-emitting layer 302 as a red and green light-emitting layer as an example. In conjunction with the light-emitting device circuit diagram shown in Figure 6, the current between the CGL303 and the cathode 305 is transmitted through the third link and the fourth link. The third link is a direct link between the CGL303 and the cathode 305 (not shown in the figure), and the fourth link is a path between the CGL303 and the upper unit light-emitting layer 304 and the upper unit light-emitting layer 304 to the cathode 305. Therefore, the upper unit light emitting layer 304 , ie, the blue light emitting layer, emits light, but the brightness of the light is lower than the brightness of the lower unit light emitting layer 302 , ie, the red and green light emitting layers.

[0047] For example, if upper unit light-emitting layer 304 is a red and green light-emitting layer, and lower unit light-emitting layer 302 is a blue light-emitting layer, that is, the positions of the red and green light-emitting layers and the blue light-emitting layer are swapped, the current between CGL 303 and cathode 305 is transmitted through the third link and the fourth link. The third link is a direct link between CGL 303 and cathode 305, and the fourth link is the path from CGL 303 to upper unit light-emitting layer 304 and from upper unit light-emitting layer 304 to cathode 305. As a result, upper unit light-emitting layer 304, i.e., the red and green light-emitting layer, emits light, but the brightness of the light is lower than that of lower unit light-emitting layer 302, i.e., the blue light-emitting layer.

[0048] For example, in the second sub-pixel 307, due to the presence of an undercut structure, the CGL303 film layer is thinned at the location of the undercut structure during the deposition process. The charge generation layer CGL303 contains metals with good conductivity, such as lithium and calcium. The metal sinks in the organic layer, resulting in a short circuit between the CGL303 and the first electrode layer 301. As shown in FIG7 , a pixel definition layer structure diagram is shown. The pixel definition layer includes a second metal layer 501, thereby short-circuiting the CGL303, the first electrode layer 301, and the second metal layer 501. When the light-emitting device is operating, the current is short-circuited through this point. The short circuit between the first electrode layer 301 and the CGL303 causes the blue light-emitting layer 302 in the second sub-pixel area to not emit light, thereby reducing the voltage of the array substrate and reducing the power consumption of the array substrate.

[0049] In another possible embodiment, referring to the pixel defining layer structure shown in FIG. 2 , the pixel defining layer 109 further includes a first metal layer 201 . The first metal layer 201 is located on a side of the pixel defining layer 109 away from the base substrate 110 and close to the first sub-pixel region 111 .

[0050] The presence of the first metal layer 201 can facilitate the short circuit between the second electrode layer 105 and the first CGL 103 , or the existence of two links between the second electrode layer 105 and the first CGL 103 .

[0051] The present embodiment does not limit the material of the first metal layer 201. The thickness of the first metal layer 201 is determined based on the design requirements of the array substrate. For example, the material of the first metal layer 202 can be a conductive material such as Al (aluminum), Mo (molybdenum), or Ti (titanium).

[0052] Referring to FIG8 , an embodiment of the present application provides an array substrate based on the above-described embodiment. This is illustrated by taking FIG1 as an example, where the first CGL 103 corresponds to the CGL 604 , the second electrode layer 105 corresponds to the second electrode layer 605 , the second light-emitting layer 104 corresponds to the upper light-emitting layer 606 , and FIG2 as an example, where the first metal layer 201 corresponds to the first metal layer 601 , and the second metal layer 202 corresponds to the second metal layer 603 .

[0053] The pixel-defining layer includes a second metal layer 603 and a multi-layer inorganic film 602. For example, a first metal layer 601, such as Al, Mo, or Ti, is deposited after the multi-layer inorganic film 602 is formed. The undercut structure undergoes an etching process after the patterning of the first metal layer 601. After the undercut structure is completed, photoresist coating is not performed to prevent collapse or cracking of the upper layer of the undercut structure.

[0054] In this embodiment, due to the presence of the first metal layer 601, the first metal layer 601 can also form a three-way short-circuit path with the CGL604 and the second electrode layer 605. Through this short-circuit path, the current path of the upper light-emitting layer 606 mainly flows through the short-circuit path, thereby reducing the luminous brightness of the upper light-emitting layer 606 and further reducing the power consumption of the array substrate.

[0055] In another possible implementation, the array substrate further includes a pixel defining layer 109 for defining a sub-pixel area, and the pixel defining layer 109 is located on the base substrate 110 .

[0056] The first light-emitting layer 102 , the second light-emitting layer 104 , the first CGL 103 and the first electrode layer 101 in the array substrate are all located on a side of the pixel defining layer 109 away from the base substrate 110 .

[0057] In the second sub-pixel region 112 of at least one sub-pixel region, the side surface of the pixel defining layer 109 close to the second sub-pixel region 112 has an undercut structure. Referring to the pixel defining layer structure shown in FIG2 , the undercut structure has a slope angle β and a notch 203. The slope angle β and the notch are used to form the undercut structure. Based on the undercut structure, in the second sub-pixel region 112, the first electrode layer 101 and the first CGL 103 are short-circuited, thereby achieving the effect that the first light-emitting layer 101 does not emit light at all. Alternatively, when the above-mentioned two links exist between the first electrode layer 101 and the first CGL 103, the brightness of the light emitted by the first light-emitting layer 101 is less than the brightness of the light emitted by the second light-emitting layer 104. Exemplarily, the slope angle β is ≤45°, and the notch height b is between 200 and 2000 angstroms. The shape of the notch in the pixel defining layer structure shown in FIG2 is for illustration only, and the embodiment of the present application does not limit the shape of the notch.

[0058] Referring to FIG9 , an embodiment of the present application provides an array substrate based on the above-described embodiment. The following example illustrates the arrangement of FIG1 , in which the first electrode layer 101 corresponds to the first electrode layer 701 , the first light-emitting layer 102 corresponds to the red and green light-emitting layers 702 , the first CGL 103 corresponds to the CGL 703 , the second light-emitting layer 104 corresponds to the blue light-emitting layer 704 , the second electrode layer 105 corresponds to the second electrode layer 705 , the pixel defining layer 109 corresponds to the pixel defining layer 706 , and the second sub-pixel region 112 corresponds to the blue sub-pixel region 707 .

[0059] In the blue sub-pixel area 707, the film thickness and slope angle of the pixel defining layer 706 can be adjusted to control the short circuit between CGL703 and the first electrode layer 701, so that the red and green light-emitting layers 702 do not emit light at all. In this way, the blue filter here can be omitted, thereby reducing costs.

[0060] In one possible implementation, the thickness and slope angle of the pixel-defining layer 706 are related to the cavity length of the light-emitting device and the position of the CGL 703. Taking the blue light-emitting layer 704 as an example, with the cavity length of the light-emitting device at 3000 angstroms and the CGL 703 at 1000 angstroms, referring to the structure shown in FIG10 , the height of c1+c2+b must be less than 1000 angstroms. If c2 represents the second metal layer 801, then c1<c2, c2≥b, and the slope angle β≤40°. This allows the CGL 703 to short-circuit the second metal layer 801 at position c2. The height and slope angle β of the multi-layered inorganic film 706 also ensure a gently flat morphology for the second electrode layer 705, ensuring that the blue light-emitting layer 704 can emit light normally.

[0061] In another possible embodiment, referring to the pixel defining layer structure shown in FIG. 2 , the pixel defining layer 109 further includes a second metal layer 202 . The second metal layer 202 is located on a side of the pixel defining layer 109 close to the base substrate 110 and close to the second sub-pixel region 112 .

[0062] The existence of the second metal layer 202 facilitates the short circuit between the first electrode layer 101 and the first CGL 103 described in the above embodiment, or the occurrence of the situation in which two links exist between the first electrode layer 101 and the first CGL 103 described in the above embodiment.

[0063] The present embodiment does not limit the material of the second metal layer. The thickness of the second metal layer is determined based on the design requirements of the array substrate. For example, the thickness c1 of the second metal layer 202 is between 50 and 2000 angstroms. In the present embodiment, the material of the second metal layer 202 can be, for example, a conductive material such as Al, Mo, or Ti.

[0064] In another possible embodiment, referring to the array substrate shown in FIG1 , the array substrate further includes a green filter 106, a blue filter 107, and a red filter 108 as shown in the figure. The filters are used to filter out unwanted color light or select the desired color light. The filters use dyes and materials of different colors to absorb or reflect light of specific wavelengths. For example, the red filter 108 intercepts non-red light and allows red light to pass through, thereby causing the array substrate to emit red light; the blue filter 107 allows blue light to pass through and absorbs light of other colors except blue, thereby emitting blue light; the green filter 106 allows green light to pass through and absorbs light of other colors except green, thereby emitting green light. This allows the array substrate to achieve different display effects.

[0065] In another possible embodiment, referring to Figures 1 and 2, the pixel defining layer 109 includes a first metal layer 201 and a second metal layer 202; the first metal layer 201 is located on a side of the pixel defining layer 109 away from the base substrate 110 and close to the first sub-pixel 111 area; the second metal layer 202 is located on a side of the pixel defining layer 109 close to the base substrate 110 and close to the second sub-pixel area 112.

[0066] Referring to FIG. 11 , an embodiment of the present application provides an array substrate.

[0067] The first light-emitting layer and the second light-emitting layer in the array substrate provided in the embodiment of the present application include more than one light-emitting layer. The embodiment of the present application takes the structure of the light-emitting device using a three-layer or higher light-emitting device such as blue light, blue light, red and green light as an example to illustrate, and controls the short-circuit path by adjusting the height of the isolation column and the height of the undercut structure as well as the shrinkage amount, slope angle and other parameters, so that CGL1 and CGL2 are short-circuited with the first electrode layer, thereby controlling the two layers of blue light-emitting layers to not emit light.

[0068] The thickness and slope angle of the multi-layer inorganic film are determined based on the cavity length of the light-emitting device and the position of the CGL. For example, in a scenario where the blue light-emitting layer is located near the first electrode layer, the cavity length of the light-emitting device is 5400 angstroms, and CGL1 and CGL2 are located 1000 angstroms and 4000 angstroms from the first electrode layer, respectively, the height of c1+c2+b must be less than 4000 angstroms. If c2 is a metal layer, c1<c2 and c2≥b, the height b of the undercut notch 901 must ensure a slope angle of β≤40°. If the sub-pixel pitch is small and the height b exceeds the specified height, leaving insufficient space for the slope angle, CGL2 can be short-circuited at 4000 angstroms from the first electrode layer to c2. The specified height and slope angle of the multi-layer inorganic film also allow the second electrode layer to have a flat morphology, ensuring normal emission of the red and green light-emitting layers 902.

[0069] In summary, the brightness of light emitted by the second light-emitting layer of the two light-emitting layers of the array substrate provided by the embodiments of the present application is lower than that of the first light-emitting layer. By reducing the brightness of the second light-emitting layer, the power consumption of the array substrate can be reduced. Furthermore, when the second light-emitting layer is non-luminous, the first light-emitting layer still emits light in the sub-pixel region where the second light-emitting layer is non-luminous. This eliminates the need for filters in the non-luminous regions of the second light-emitting layer, further reducing the manufacturing cost of the array substrate.

[0070] 12 , an embodiment of the present application provides a method for preparing an array substrate. The method can be used to prepare the array substrate described in the above embodiment. The method includes:

[0071] In step 1001, multiple layers of inorganic material are deposited on the side of the first electrode layer away from the substrate to form a multi-layer inorganic film. The multi-layer inorganic film is patterned into a desired shape, and the thickness of each layer of the multi-layer inorganic film is related to the structure of the light-emitting device.

[0072] The operation of depositing a multi-layer inorganic film occurs on the side of the first electrode layer away from the substrate, that is, the deposition position of the first electrode layer is determined by the positional relationship between the deposition side and the substrate. The substrate refers to a material used in the manufacture of microelectronic products such as semiconductor devices and electronic components. The material of the substrate includes but is not limited to single crystal silicon, polycrystalline silicon, quartz glass or alumina ceramics. In the embodiment of the present application, the material of the substrate is not limited. In the production and manufacturing process of the array substrate, the substrate is used to support and fix the structure other than the substrate on at least one side of the substrate. For example, the substrate plays a structural supporting role for the first electrode layer, and the main function of the first electrode layer is to provide voltage for the sub-pixel unit in the array substrate.

[0073] In one possible embodiment, the first electrode layer is formed by depositing a metal film on one side of a substrate and subjecting the deposited metal film to a photolithography process, an etching process, and other steps. The photolithography process involves projecting a pattern on a photomask onto a metal film coated with photoresist. Ultraviolet light then exposes or dissociates the photoresist, forming a circuit pattern corresponding to the pattern. The unexposed photoresist is retained as a mask for a subsequent etching process. The etching process removes the exposed edges of the photoresist and chemically etches the circuit area indicated by the mask, thereby obtaining a first electrode layer structure in the shape of the circuit pattern corresponding to the pattern.

[0074] Illustratively, in a structure where a first electrode layer is formed on one side of a substrate, a planar layer is implemented on a side of the first electrode layer away from the substrate. The planar layer is used to ensure mutual isolation between each sub-pixel unit and stability of electrical performance.

[0075] In one possible implementation, the flat layer is realized by a thin film deposition process, and operations such as cleaning, removing impurities and dust are performed on the side of the base substrate close to the first electrode and the side of the first electrode away from the base substrate, thereby ensuring the cleanliness of the side of the base substrate close to the first electrode and the side of the first electrode away from the base substrate; a flat layer thin film material is selected, and the flat layer thin film material is thermally evaporated and deposited on the side of the first electrode layer away from the base substrate, thereby forming a flat layer. In the process of depositing the flat layer, the thickness and uniformity of the flat layer are ensured by controlling parameters such as temperature, flow rate and deposition time. In addition, by covering the side of the flat layer away from the base substrate with photoresist, a photolithography process and an etching process are performed, thereby exposing the circuit pattern area of ​​the first electrode layer covered by the flat layer. The highly uneven area of ​​the first electrode layer after the patterning process is flattened to facilitate the deposition operation of the subsequent film layer. In the embodiment of the present application, the characteristics of the flat layer are not limited.

[0076] In one possible embodiment, when the first electrode layer is formed or a flat layer is implemented, a second metal layer is deposited on the surface of the second metal layer base. The second metal layer base mentioned in the embodiment of the present application is the side of the base substrate close to the first electrode layer and the side of the first electrode layer away from the base substrate, or the side of the first electrode layer away from the base substrate and the side of the flat layer away from the base substrate. The material of the second metal layer can be, for example, a conductive material such as Al, Mo or Ti. The embodiment of the present application does not limit the material of the second metal layer.

[0077] For example, the deposition of the second metal layer requires cleaning the second metal layer substrate to remove surface impurities of the second metal layer substrate. After the surface impurities of the second metal layer substrate are removed, the second metal film is deposited on the second metal layer substrate using deposition techniques such as physical vapor deposition, chemical vapor deposition, or ion beam deposition. The embodiment of the present application does not limit the thickness of the second metal film, and the thickness of the second metal film can be determined according to the design requirements of the array substrate. After the second metal film is deposited, the second metal film is patterned. The second metal film is formed into the desired shape through processes such as photolithography and etching, so that the second metal film is patterned into the second metal layer. For example, in the embodiment of the present application, the second metal film retains a first edge region of the sub-pixel area on one side. The first edge region of the sub-pixel area on one side refers to the surrounding area around the inner periphery of the first sub-pixel area, and the first edge region is determined during the design process based on the function of the array substrate. For example, if the sub-pixel unit area is a rectangular area, the position of the second metal layer in the embodiment of the present application should be a hollow rectangular area within the sub-pixel unit in the pixel unit.

[0078] Exemplarily, a multi-layer inorganic film deposition operation is performed on the side of the first electrode layer away from the substrate. A multi-layer inorganic film refers to a thin film structure composed of multiple layers of inorganic materials stacked on top of each other. The inorganic materials forming the stacked thin film structure can be metals, oxides, nitrates, and other materials, and the thickness of the inorganic materials forming the stacked thin film structure can be in the nanometer to micrometer range. In the embodiments of the present application, the type of inorganic material constituting the multi-layer inorganic film structure is not limited; it only requires a structure that can form the desired multi-layer inorganic film.

[0079] Exemplarily, the operation of depositing a multi-layer inorganic film can be to clean the side of the first electrode layer away from the substrate and the side of the substrate close to the first electrode layer, thereby removing impurities on the side of the first electrode layer away from the substrate and the side of the substrate close to the first electrode layer. The first layer of inorganic film is deposited on the side of the first electrode layer away from the substrate and the side of the substrate close to the first electrode layer. The deposition of the first layer of inorganic film can be carried out by physical vapor deposition, chemical vapor deposition or ion beam deposition and other technical means. The specific deposition method of the operation of depositing the first layer of inorganic film is not limited in the embodiment of the present application. It is sufficient to be able to deposit the first layer of inorganic film on the side of the first electrode layer away from the substrate and the side of the substrate close to the first electrode layer.

[0080] On the basis of depositing the first layer of inorganic thin film, it is necessary to clean up the contamination, bubbles and other impurities generated during the deposition of the first layer of inorganic thin film to prevent the impurities from affecting the deposition process of the second layer of inorganic thin film. The deposition process of the remaining inorganic thin films except the first layer of inorganic thin film can refer to the deposition process of the first layer of inorganic thin film, and the deposition of the remaining inorganic thin films is carried out in the direction of the first layer of inorganic thin film away from the base substrate. The embodiment of the present application does not limit the number of layers of inorganic thin films included in the multi-layer inorganic thin film, and the specific number of layers is set accordingly according to the different functions required by the design of the array substrate. The thickness of the deposited inorganic thin film and the stability of the inorganic thin film need to be evaluated during the deposition cycle of the inorganic thin film. In the embodiment of the present application, the thickness of the inorganic thin film in the deposited multi-layer inorganic film is not limited, and the thickness of each layer of inorganic thin film can be set accordingly according to the design function required by the array substrate.

[0081] In one possible embodiment, the structure of the inorganic thin films in the multi-layer inorganic film deposited on the side of the first electrode layer away from the substrate and on the side of the substrate close to the first electrode layer is SiO (Silicon Oxide), SiN (Silicon Nitride), SiO, SiN, SiO and SiN inorganic thin films. For example, the first inorganic thin film is the first SiO layer, the second inorganic thin film is the first SiN layer, the third inorganic thin film is the second SiO layer, and the fourth inorganic thin film is the second SiN layer, and the subsequent inorganic thin films are repeatedly deposited. For example, in the embodiment of the present application, the film thickness of the first SiN layer is between 200 and 2000 angstroms, and the film thickness of the remaining inorganic thin films is between 100 and 500 angstroms.

[0082] After the multi-layer inorganic film is formed, a patterning process is performed on the multi-layer inorganic film to achieve the desired structure. In this embodiment of the present application, the multi-layer inorganic film structure is divided into two ends based on proximity to or distance from the first sub-pixel region. Hereinafter, the first sub-pixel region and the second sub-pixel region are distinguished. The end of the multi-layer inorganic film structure close to the first sub-pixel region is referred to as a spacer, and the end of the multi-layer inorganic film structure close to the second sub-pixel is referred to as an undercut structure.

[0083] Exemplarily, the side of the multi-layer inorganic film close to the first sub-pixel area is etched according to a first etching selectivity ratio to obtain an isolation column with a slope angle α≥75°; the side close to the second sub-pixel area is etched according to a second etching selectivity ratio to obtain an undercut structure with a slope angle β≤45° and a notch. The first etching selectivity ratio may be 1:1, and the second etching selectivity ratio may be greater than 1:10. The notch refers to a notch structure formed by etching the structure between the first electrode layer and the slope angle β of the multi-layer inorganic film close to the second sub-pixel area, and the embodiment of the present application does not limit the shape and size of the notch. In the embodiment of the present application, the angle of the slope angle α and the angle of the slope angle β are determined according to the structure of the array substrate device.

[0084] In one possible embodiment, when a multi-layer inorganic film is formed, a first metal layer deposition operation is performed. For example, after the multi-layer inorganic film deposition is completed, the first metal layer is deposited on the side of the multi-layer inorganic film away from the substrate. The material of the first metal layer can be, for example, a conductive material such as Al, Mo, or Ti. This embodiment of the present application does not limit the material of the first metal layer.

[0085] For example, the deposition of the first metal layer requires cleaning the first metal layer substrate, thereby removing surface impurities of the first metal layer substrate. The first metal layer substrate mentioned in the embodiment of the present application is the side of the first electrode layer away from the base substrate and the side of the multi-layer inorganic film away from the base substrate. After the surface impurities of the first metal layer substrate are removed, the first metal film is deposited on the first metal layer substrate by deposition techniques such as physical vapor deposition, chemical vapor deposition, or ion beam deposition. The embodiment of the present application does not limit the thickness of the first metal film, and the thickness of the first metal film is determined according to the design requirements of the array substrate. After the first metal film is deposited, the first metal film is patterned. The first metal film is formed into the desired shape through processes such as photolithography and etching, so that the first metal film is patterned into the first metal layer. For example, in the embodiment of the present application, the first metal film retains a reference portion of the multi-layer inorganic film within the first sub-pixel and away from the base substrate. The function of the reference portion based on the array substrate is determined during the design process. In addition, if the structure of the array substrate includes a first metal layer, the etching process of the undercut structure of the multi-layer inorganic film needs to be performed after the first metal layer is patterned to prevent the etched undercut structure from being corroded during the patterning of the first metal layer, thereby causing the upper unit of the undercut structure to collapse or crack. The upper unit refers to the area between the side of the notch in the undercut structure away from the base substrate and the side of the multi-layer inorganic film away from the base substrate.

[0086] Step 1002: depositing at least two layers of light-emitting devices on a side of the multi-layered inorganic film away from the first electrode layer.

[0087] If the isolation pillar structure and undercut structure of the multi-layered inorganic film are fabricated via etching processes with different etch selectivities as described in step 1001, deposition of the light-emitting device is performed. The light-emitting device is deposited on the side of the multi-layered inorganic film away from the first electrode layer. Furthermore, if a first metal layer is deposited during the fabrication of the multi-layered inorganic film as described in one possible embodiment of step 1001, the light-emitting device is deposited on both the side of the first metal layer away from the base substrate and the side of the multi-layered inorganic film away from the base substrate.

[0088] For example, the light-emitting device is deposited on the side of the multi-layer inorganic film away from the substrate using a deposition technique such as chemical vapor deposition or physical vapor deposition. Deposition techniques such as chemical vapor deposition or physical vapor deposition can deposit materials between the surface of the substrate and different layers, thereby forming a multi-layer structure. The present embodiment of the application does not limit the deposition technique used in the deposition process; it only requires that the light-emitting device be deposited on the side of the multi-layer inorganic film away from the substrate. Furthermore, the present embodiment of the application does not limit the number of layers of the light-emitting device.

[0089] In one possible embodiment, the structure of the light-emitting device is composed of a light-emitting diode and a CGL. The embodiment of the present application does not limit the type of light-emitting diode. For example, the light-emitting diode can be an organic light-emitting diode or a non-polarized light-emitting diode. The embodiment of the present application uses an organic light-emitting diode as an example for explanation. In addition, the structure of the light-emitting device can also include a film layer that can change the color of the light-emitting diode. The embodiment of the present application does not limit the structure and material of the film layer that changes the color of the light-emitting diode. It only needs to be able to change the color of the light-emitting diode. In the embodiment of the present application, there is a layer of CGL between every two layers of light-emitting diodes. The embodiment of the present application does not limit the manufacturing process of the light-emitting device.

[0090] For example, after depositing the light-emitting device, a second electrode layer is deposited on the side of the light-emitting device away from the substrate, thereby providing voltage to the light-emitting device together with the first electrode layer. The second electrode layer can be deposited through evaporation and laser etching processes. The present embodiment does not limit the process for depositing the second electrode or the material of the second electrode; it only needs to be able to provide voltage to the light-emitting device together with the first electrode layer.

[0091] Step 1003: Dispose a filter on the side of the packaged light-emitting device away from the multi-layer inorganic film.

[0092] After the second electrode layer deposition operation described in step 1002 is completed, the first electrode layer, the second electrode layer, the multi-layered inorganic film, and the light-emitting device are encapsulated. The encapsulation is used to protect the first electrode layer, the second electrode layer, the multi-layered inorganic film material, and the light-emitting device structure within the package. This embodiment of the application does not limit the encapsulation process or the materials used for the encapsulation; any materials that can protect the internal structure of the package are sufficient.

[0093] After encapsulation, the encapsulated light-emitting device needs to be placed away from the multi-layer inorganic film to perform the filter setting operation. The preparation process of the filter can be: selecting a suitable dye according to the required color; dissolving the dye in a solvent, and applying the solvent to the prepared filter substrate using a brush or spray; drying and hardening the filter to ensure sufficient strength and durability. Hardening usually requires high-temperature drying, ultraviolet exposure or other special chemical treatment processes; the hardened and dried filter is cut into units of the required size and shape to prepare a filter. Position the filter in the encapsulated light-emitting device and use transparent glue or other bonding methods to set the filter.

[0094] Among them, the filter is an optical component that can change the color of light emitted by a light-emitting device. The filter is composed of multiple layers of dyes and polymer films. The filter can achieve the desired color effect by absorbing or reflecting light of different wavelengths. The filter can achieve light emission in the form of monochrome, multi-color or full color, and can also be used to change the light-emitting characteristics of the light-emitting device. Exemplarily, the filter is used to filter unwanted color light or select the required color light. The filter uses dyes and materials of different colors to achieve absorption or reflection of specific wavelengths of light. For example, a red filter intercepts non-red light and allows red light to pass through, so that the array substrate emits red light; a blue-green filter allows blue and green light to penetrate, absorbs light of other colors except blue and green, and emits a mixture of blue and green light, thereby achieving different display effects.

[0095] Referring to FIG. 13 , an embodiment of the present application provides a display panel including a cover plate 1120 and the array substrate 1110 described in the third embodiment. The array substrate 1110 in the embodiment of the present application includes, but is not limited to, any of the array substrates described in the preceding embodiments and is not described in detail here. The portion of the array substrate 1110 excluding the base substrate 1111 is located between the base substrate 1111 and the cover plate 1120.

[0096] Referring to FIG. 14 , an embodiment of the present application provides a display device including a driver and a display panel 1210 . Display panel 1210 in this embodiment includes, but is not limited to, the display panel described in FIG. 13 , and is not described in detail here. A data driver 1230 and a scan driver 1220 are configured to drive display panel 1210 .

[0097] In a possible implementation, the display device further includes: a timing controller 1250 and a power supply unit 1240 .

[0098] The timing controller 1250 is supplied with data signals from the image processor, including a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc. The timing controller 1250 outputs a gate timing control signal 1251 for controlling the driving timing of the scan driver 1220 and a data timing control signal 1252 for controlling the driving timing of the data driver 1230.

[0099] In response to a data timing control signal 1252 received from the timing controller 1250, the data driver 1230 samples and latches the data signal supplied from the timing controller 1250, converts the digital data signal into an analog data signal (or data voltage) based on a gamma reference voltage, and outputs the analog data signal. The data driver 1230 outputs the data voltage through the data lines Y1 to Yn. In response to a strobe timing control signal 1251 received from the timing controller 1250, the scan driver 1220 outputs a scan signal. The scan driver 1220 outputs the scan signal through the scan lines X1 to Xm.

[0100] The power supply unit 1240 outputs a high-potential power voltage and a low-potential power voltage. The high-potential power voltage and the low-potential power voltage output from the power supply unit are supplied to the display panel 1210. The high-potential power voltage is supplied to the display panel 1210 through a first power line 1241, and the low-potential power voltage is supplied to the display panel 1210 through a second power line 1242.

[0101] The display panel 1210 displays an image based on a data voltage supplied from a data driver 1230, a scan signal supplied from a scan driver 1220, and power supplied from a power supply unit 1240. The display panel 1210 includes sub-pixels 1260 that emit light to display an image. The sub-pixels 1260 may include red, blue, and green sub-pixels, or white, red, blue, and green sub-pixels. The embodiments of the present application do not limit the types of sub-pixels included in the sub-pixels 1260 or the light-emitting colors of each sub-pixel.

[0102] It should be understood that the term "plurality" used herein refers to two or more. "And / or" describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates an "or" relationship between the associated objects.

[0103] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises: a base substrate, and a first light-emitting layer and a second light-emitting layer sequentially arranged on the base substrate; In at least one sub-pixel region in the array substrate, the first light-emitting layer emits light with a first brightness, the second light-emitting layer emits light with a second brightness or does not emit light, and the second brightness is less than the first brightness.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises: a first electrode layer, a first charge generation layer and a second electrode layer, the first light-emitting layer and the second light-emitting layer are both located between the first electrode layer and the second electrode layer, the second electrode layer is located on a side of the first electrode layer away from the base substrate, and the first charge generation layer is located between the first light-emitting layer and the second light-emitting layer; In the at least one sub-pixel area, the first charge generation layer is short-circuited with the first electrode layer or the second electrode layer; or, there are two links between the first charge generation layer and the first electrode layer or the second electrode layer, and the two links are connected in parallel, one link is a direct link between the first charge generation layer and the first electrode layer or the second electrode layer, and the other link is a link between the first charge generation layer to the first light-emitting layer and the first light-emitting layer to the first electrode layer or the second electrode layer.

3. The array substrate according to claim 2, characterized in that: The array substrate further comprises a pixel defining layer for defining the sub-pixel area, and the pixel defining layer is located on the base substrate; The first light-emitting layer, the second light-emitting layer, the first charge generation layer and the second electrode layer are all located on a side of the pixel defining layer away from the base substrate; In a first sub-pixel region of the at least one sub-pixel region, a side surface of the pixel defining layer close to the first sub-pixel region has a slope angle α.

4. The array substrate according to claim 3, characterized in that: The slope angle α is ≥75°.

5. The array substrate according to claim 3, characterized in that: The pixel definition layer further includes a first metal layer; The first metal layer is located on a side of the pixel defining layer away from the base substrate and close to the first sub-pixel region.

6. The array substrate according to claim 2, characterized in that: The array substrate further comprises a pixel defining layer for defining the sub-pixel area, and the pixel defining layer is located on the base substrate; The first light-emitting layer, the second light-emitting layer, the first charge generation layer and the first electrode layer are all located on a side of the pixel defining layer away from the base substrate; In a second sub-pixel region of the at least one sub-pixel region, a side surface of the pixel defining layer close to the second sub-pixel region has an undercut structure, and the undercut structure has a slope angle β and a notch.

7. The array substrate according to claim 6, characterized in that: The slope angle β is ≤45°.

8. The array substrate according to claim 6, characterized in that: The pixel definition layer further includes a second metal layer; The second metal layer is located on a side of the pixel defining layer close to the base substrate and close to the second sub-pixel region.

9. The array substrate according to claim 3, characterized in that: In a second sub-pixel region of the at least one sub-pixel region, a side surface of the pixel defining layer close to the second sub-pixel region has an undercut structure, and the undercut structure has a slope angle β and a notch; The pixel definition layer further includes a first metal layer and a second metal layer; The first metal layer is located on a side of the pixel defining layer away from the base substrate and close to the first sub-pixel region; The second metal layer is located on a side of the pixel defining layer close to the base substrate and close to the second sub-pixel region.

10. The array substrate according to any one of claims 1 to 9, characterized in that: The first light-emitting layer and the second light-emitting layer each include at least one light-emitting layer.

11. The array substrate according to any one of claims 1 to 9, characterized in that: The at least one sub-pixel region further includes: a filter, and the filter is located on a side of the second light-emitting layer away from the base substrate.

12. A display panel, characterized in that: The display panel comprises a cover plate and an array substrate according to any one of claims 1 to 11; The portion of the array substrate except the base substrate is located between the base substrate and the cover substrate.

13. A display device, characterized in that: The display device comprises: a driver and the display panel according to claim 12; The driver is used to drive the display panel.

14. A method for preparing an array substrate, characterized in that: The method is used to prepare the array substrate according to any one of claims 1 to 11, and the method comprises: Depositing multiple layers of inorganic material on the side of the first electrode layer away from the substrate to form a multi-layer inorganic film, wherein the multi-layer inorganic film is formed into a desired shape after a patterning process, and the thickness of each film layer of the multi-layer inorganic film is related to the structure of the light-emitting device; Depositing at least two layers of light-emitting devices on a side of the multi-layered inorganic film away from the first electrode layer; A filter is arranged on the side of the packaged light emitting device away from the multi-layer inorganic film.

15. The method according to claim 14, characterized in that The multi-layer inorganic film comprises an isolation column and an undercut structure; and the multi-layer inorganic film is formed by depositing multiple layers of inorganic materials on the side of the first electrode layer away from the substrate, comprising: The side of the multi-layer inorganic film close to the first sub-pixel area is etched according to a first etching selection ratio to obtain the isolation column with a slope angle α; the side close to the second sub-pixel area is etched according to a second etching selection ratio to obtain the undercut structure with a slope angle β and a notch.

16. The method according to claim 15, characterized in that After depositing multiple layers of inorganic materials on the side of the first electrode layer away from the substrate to form a multi-layer inorganic film, the method further includes: A first metal layer is deposited on a side of the multi-layer inorganic film away from the base substrate and close to the first sub-pixel region.

17. The method according to claim 15, characterized in that Before depositing multiple layers of inorganic materials on the side of the first electrode layer away from the substrate to form a multi-layer inorganic film, the method further includes: A second metal layer is deposited on one side of the multi-layer inorganic film close to the base substrate and close to the second sub-pixel region.

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