Display device

Abstract

A display device (10) comprises: a first substrate (driving substrate 20) including a pixel region in which a first subpixel (subpixel P1) that has a first reflection electrode (reflection electrode 411) and a second subpixel (subpixel P3) that has a light-emitting element (ED) are disposed; a second substrate (facing substrate 30) facing the first substrate; and a liquid crystal layer (42) disposed between the first substrate and the second substrate. The first substrate includes a first transistor (transistor T1) which is supplied with a video signal (DS) and which is connected to the first reflection electrode via a first latch circuit (latch circuit LC1), and a second transistor (transistor T3) which is supplied with a video signal and which is connected to the light-emitting element via a second latch circuit (latch circuit LC3).

Description

display device

[0001] The present disclosure relates to a display device.

[0002] Development of a display device that combines a reflective liquid crystal element and an EL element is underway (see Patent Documents 1 and 2). By appropriately switching between the reflective liquid crystal element and the organic EL element, it is possible to achieve a display with good visibility according to the surrounding conditions. The display device described in Patent Document 1 has a driving TFT that drives the liquid crystal element and the organic EL element, and a switching TFT that switches between the liquid crystal element and the organic EL element for display (see paragraphs 0024 and 0025).

[0003] Japanese Patent Application Publication No. 2018-173643 Japanese Patent Application Publication No. 2018-404873

[0004] In the above-described display device, it is difficult to independently drive the liquid crystal display element and the organic EL display element due to the off-leakage of the switching TFT. That is, when the light-emitting period of the organic EL display element becomes long, a voltage is applied to the liquid crystal display element due to the off-leakage of the switching TFT, and the liquid crystal display element and the organic EL display element simultaneously enter a display state, making it difficult to appropriately switch the display.

[0005] In contrast, in the display device of Patent Document 2, separate switches SW1 and SW2 are assigned to the liquid crystal display element and the organic EL display element, and they are controlled by separate signals. As a result, the liquid crystal display element and the organic EL display element can be operated more reliably and independently. However, controlling the liquid crystal display element and the organic EL display element by separate signals increases costs and power consumption.

[0006] The present disclosure aims to provide a display device that combines a reflective liquid crystal element and an EL element, and to independently drive the liquid crystal display element and the organic EL display element while suppressing an increase in power consumption.

[0007] The display device comprises a first substrate including a pixel region in which a first sub-pixel having a first reflective electrode and a second sub-pixel having a light-emitting element are arranged, a second substrate facing the first substrate, and a liquid crystal layer arranged between the first substrate and the second substrate, wherein the first substrate includes a first transistor to which a video signal is supplied and which is connected to the first reflective electrode via a first latch circuit, and a second transistor to which the video signal is supplied and which is connected to the light-emitting element via a second latch circuit.

[0008] The present disclosure makes it possible to independently drive a liquid crystal display element and an organic EL display element while suppressing an increase in power consumption in a display device that combines a reflective liquid crystal element and an EL element.

[0009] 1 is a plan view illustrating a display device of embodiment 1. FIG. 2 is a cross-sectional view illustrating a display device of embodiment 1. FIG. 3 is a circuit diagram illustrating an example of the configuration of a drive circuit that drives subpixels of the display device of embodiment 1. FIG. 4 is a diagram illustrating an example of temporal changes in signals that drive subpixels of the display device of embodiment 1. FIG. 5 is a diagram illustrating the relationship between the brightness of the subpixels and signals that drive the subpixels of the display device of embodiment 1. FIG. 6 is a diagram illustrating an example of a drive mode of the display device of embodiment 1. FIG. 7 is a plan view illustrating a display device of embodiment 2. FIG. 8 is a circuit diagram illustrating an example of the configuration of a drive circuit that drives subpixels of embodiment 2. FIG. 9 is a diagram illustrating an example of temporal changes in signals that drive subpixels of the display device of embodiment 2. FIG. 10 is a plan view illustrating an example of an arrangement of subpixels in a display device of a modified example.

[0010] [Embodiment 1] A display device 10 according to embodiment 1 will be described in detail below. Fig. 1 is a plan view showing the display device 10 of embodiment 1, as viewed from the positive direction of the Z axis. As shown in Fig. 1, the display device 10 includes a display unit 11, a driver circuit DRC, and a display control circuit DCC.

[0011] The display unit 11 displays images, text, and other video content, and includes a red (R) pixel region Pr, a green (G) pixel region Pg, and a blue (B) pixel region Pb. The pixel regions Pr, Pg, and Pb are examples of a first pixel region, a second pixel region, and a third pixel region. Hereinafter, the pixel regions Pr, Pg, and Pb may be collectively referred to as pixel region P. Red (R), green (G), and blue (B) are examples of a first display color, a second display color, and a third display color, which are different from each other. Hereinafter, full-color display using the three colors RGB is possible. Alternatively, the display device 10 may have one, two, or four or more display colors. An example of a single display color is monochrome black-and-white display.

[0012] Sub-pixels P1 to P3 are arranged in the pixel regions Pr, Pg, and Pb, respectively. The sub-pixels P1, P2, and P3 correspond to reflective liquid crystal elements LD1 and LD2 and light-emitting elements ED (e.g., organic light-emitting diodes), which will be described later.

[0013] The driver circuit DRC supplies the video signals DSr, DSg, DSb and gate signals GS1 to GS4 to the display unit 11 to drive the display unit 11. The display control circuit DCC controls the driver circuit DRC.

[0014] FIG. 2 is a cross-sectional view showing an example of a display device 10. FIG. 2 shows the display device 10 cut along line A-A in FIG. 1. As shown in FIG. 2, the display device 10 includes a drive substrate 20 (first substrate), a counter substrate 30 (second substrate) facing the drive substrate 20, and a liquid crystal layer 42 disposed between the drive substrate 20 and the counter substrate 30. The drive substrate 20 can be divided into regions corresponding to subpixels P1 (first subpixel), P2 (third subpixel), and P3 (second subpixel). As described below, the subpixels P1 and P2 correspond to reflective liquid crystal elements LD1 and LD2, respectively, and the subpixel P3 corresponds to a light-emitting element ED (e.g., an organic light-emitting diode).

[0015] The drive substrate 20 has an insulating substrate 21, a drive circuit section 22, an insulating layer 23, and an insulating layer 51a. The insulating substrate 21 is made of, for example, a glass substrate or a resin film. The drive circuit section 22 is a layer on the upper surface of the insulating substrate 21 on which drive circuits such as transistors T1 to T3 and wiring are formed. The insulating layer 23 is formed on the upper surface of the drive circuit section 22 and is a so-called planarizing layer that flattens the surface of the drive substrate 20. The insulating layer 51a is an insulating layer formed on the insulating layer 23.

[0016] The drive substrate 20 has reflective electrodes 41 (411, 412) corresponding to the subpixels P1 and P2, and a light-emitting element ED corresponding to the subpixel P3. The reflective electrode 41 is formed on an insulating layer 51a. That is, the drive substrate 20 (first substrate) includes a pixel region Pr in which the subpixel P1 (first subpixel) having the reflective electrode 411 (first reflective electrode) and the subpixel P3 (second subpixel) having the light-emitting element ED are arranged. The pixel region Pr also includes the subpixel P2 (third subpixel) having the reflective electrode 412 (second reflective electrode).

[0017] The liquid crystal element LD1 corresponding to the subpixel P1 (first subpixel) is composed of a reflective electrode 411, a liquid crystal layer 42, a counter electrode 43, and a polarizer 44. The liquid crystal element LD2 corresponding to the subpixel P2 (third subpixel) is composed of a reflective electrode 412, a liquid crystal layer 42, a counter electrode 43, and a polarizer 44. A color filter 45 provides a display color to the liquid crystal elements LD1 and LD2.

[0018] The polarizing plate 44 is, for example, a circular polarizing plate that transmits circularly polarized light. The circular polarizing plate can be configured by combining a linear polarizing plate and a quarter-wave retardation plate. In this case, it is preferable to set the orientation of the liquid crystal in the liquid crystal layer 42, for example, as follows. That is, when the voltage between the reflective electrode 41 and the counter electrode 43 is OFF and ON, the liquid crystal layer 42 is set to have a vertical orientation and a horizontal orientation. Note that when the liquid crystal layer 42 is horizontally oriented, it is preferable to set the phase of the linearly polarized light that has passed through the liquid crystal layer 42 to be shifted by a quarter wavelength from that before passing through.

[0019] In this configuration, when the voltage is OFF, external light that passes through the polarizer 44 and the liquid crystal layer 42, is reflected by the reflective electrode 41, and returns to the polarizer 44 does not substantially pass through the polarizer 44 (minimum transmission: black display). That is, the circularly polarized light emitted from the polarizer 44 does not change its polarization state in the liquid crystal layer 42, but is reflected by the reflective electrode 41, whereby the direction of rotation (counterclockwise or clockwise) of the circularly polarized light is reversed, and therefore does not pass through the polarizer 44. On the other hand, when the voltage is ON, external light that passes through the polarizer 44 and the liquid crystal layer 42, is reflected by the reflective electrode 41, and returns to the polarizer 44 passes through the polarizer 44 (maximum transmission: white display). That is, the phase of the circularly polarized light emitted from the polarizer 44 is shifted by a quarter wavelength in the liquid crystal layer 42, becoming linearly polarized light, and is reflected by the reflective electrode 41 as linearly polarized light, allowing it to pass through the polarizer 44.

[0020] The light-emitting element ED corresponding to the subpixel P3 (second subpixel) is composed of a reflective electrode 51, an organic layer 52, and an electrode 53, and the organic layer 52 emits light in response to an injected current. The reflective electrode 51 injects a current into the organic layer 52 and reflects light emitted from the organic layer 52 in the negative Z-axis direction. As a result, the emitted light is efficiently utilized. The light-emitting element ED can be colored by varying the coloring material of the color filter 45 or the light-emitting material of the organic layer 52 depending on the pixel regions Pr, Pg, and Pb.

[0021] The drive substrate 20 has drive circuits that drive the sub-pixels P1, P2, and P3. For ease of understanding, only transistors T1 to T3 are shown in Fig. 2, but latch circuits LC1 to LC3, voltage switching circuits VS1 and VS2, and current switching circuits CS1 and CS2 can also be formed on the drive substrate 20.

[0022] 3 is a circuit diagram showing the circuit configuration of a pixel of the display device 10. FIG. 3 shows a drive circuit 15 that drives sub-pixels P1, P2, and P3 of pixel regions Pr, Pg, and Pb. This drive circuit 15 has transistors T1 to T4, latch circuits LC1 to LC4, voltage switching circuits VS1 and VS2, and current switching circuits CS1 and CS2, and drives liquid crystal elements LD1 and LD2 and light-emitting element ED.

[0023] The drive circuit 15 is connected to the source lines SLr, SLg, and SLb and the gate lines GL1 to GL4. The driver circuit DRC supplies video (data) signals DSr, DSg, and DSb to the source lines SLr, SLg, and SLb, respectively. The driver circuit DRC supplies gate signals GS1 to GS4 to the gate lines GL1 to GL4, respectively. Hereinafter, the source lines SLr, SLg, and SLb and the video signals DSr, DSg, and DSb may be collectively referred to as the source lines SL and the video signals DS, respectively. The gate lines GL1 to GL4 and the gate signals GS1 to GS4 may be collectively referred to as the gate lines GL and the gate signals GS, respectively.

[0024] The video signal line SL is shared by the liquid crystal element LD (LD1, LD2) and the light emitting element ED, and it is not necessary to provide the video signal line SL and the video signal terminal for each of the liquid crystal element LD and the light emitting element ED.

[0025] The liquid crystal element LD1 is driven by the transistor T1, the latch circuit LC1, and the voltage switching circuit VS1 to change the brightness of the sub-pixel P1. The liquid crystal element LD2 is driven by the transistor T2, the latch circuit LC2, and the voltage switching circuit VS2 to change the brightness of the sub-pixel P2. The light-emitting element ED is driven by the transistors T3 and T4, the latch circuits LC3 and LC4, and the current switching circuits CS1 and CS2 to change the brightness of the sub-pixel P3.

[0026] The transistor T1 (first transistor) is supplied with a video signal DS and is connected to the reflective electrode 411 (first reflective electrode) of the liquid crystal element LD1 via a latch circuit LC1 (first latch circuit). The transistor T2 (third transistor) is supplied with a video signal DS and is connected to the reflective electrode 412 (second reflective electrode) of the liquid crystal element LD2 via a latch circuit LC2 (third latch circuit). The transistor T3 (second transistor) is supplied with a video signal DS and is connected to the light-emitting element ED via a latch circuit LC3 (second latch circuit). The transistor T4 (fourth transistor) is supplied with a video signal DS and is connected to the light-emitting element ED via a latch circuit LC4 (fourth latch circuit).

[0027] The transistors T1 to T4 are operated by gate signals GS1 to GS4 from the gate lines GL1 to GL4, respectively, and output a video signal DS from the source line SL to the latch circuits LC1 to LC4. The transistors T1 to T4 output the video signal DS when the gate signal GS is H, and do not output the video signal DS when the gate signal GS is L. As will be described later, by varying the H and L levels of the gate signals GS1 to DS4, it is possible to switch the brightness of each of the sub-pixels P1 to P3 in the pixel region P.

[0028] The latch circuits LC1 to LC4 hold the video signals DS output from the transistors T1 to T4, respectively. By holding the video signals DS in the latch circuits LC1 to LC4, it becomes possible to stop the supply of video signals from the transistors T1 to T4 to the liquid crystal elements LD1 and LD2 and the light-emitting element ED during the display period, thereby reducing power consumption.

[0029] The voltage switching circuit VS1 (first voltage switching circuit) switches the voltage applied to the first reflective electrode (reflective electrode 411) in accordance with the video signal DS output from the transistor T1 (first transistor) and held in the latch circuit LC1 (first latch circuit). The voltage switching circuit VS2 (second voltage switching circuit) switches the voltage applied to the reflective electrode 412 (second reflective electrode) in accordance with the video signal output from the transistor T2 (third transistor) and held in the latch circuit LC2 (third latch circuit).

[0030] The voltage switching circuit VS1 has switches SW1 and SW2 that operate in response to the video signal DS held in the latch circuit LC1. When the video signal DS is in the H state, the switch SW1 is in the ON state and the switch SW2 is in the OFF state, and a signal Von is applied to the reflective electrode 411 (liquid crystal element LD1). When the video signal DS is in the L state, the switch SW1 is in the OFF state and the switch SW2 is in the ON state, and a signal Voff is applied to the reflective electrode 411 (liquid crystal element LD1). As will be described later, the signal Voff is in phase with the signal Vcom applied to the counter electrode 43, and the signal Von is in opposite phase to the signal Vcom. Therefore, the brightness of the subpixel P1 (liquid crystal element LD1) changes depending on whether the video signal DS is in the H state or the L state. Similarly, the voltage switching circuit VS2 has switches SW1 and SW2 that operate in response to the video signal DS held in the latch circuit LC2, and the brightness of the sub-pixel P2 (liquid crystal element LD2) changes depending on whether the video signal DS is in the H state or the L state. In this way, the brightness of the entire sub-pixels P1 and P2 (liquid crystal elements LD1 and LD2) can be changed depending on the video signal DS.

[0031] The current switching circuit CS1 (first current switching circuit) switches the current supplied to the light-emitting element ED in accordance with the video signal DS output from the transistor T3 (second transistor) and held in the latch circuit LC3 (second latch circuit). The current switching circuit CS2 (second current switching circuit) switches the current supplied to the light-emitting element ED in accordance with the video signal DS output from the transistor T4 (fourth transistor) and held in the latch circuit LC4 (fourth latch circuit).

[0032] The current switching circuit CS1 includes a transistor T5 that operates in response to a video signal DS held in a latch circuit LC1. When the video signal DS is in an H state, the transistor T5 applies a voltage ELVDD to the light-emitting element ED, and a current corresponding to the voltages ELVDD and ELVSS is supplied to the light-emitting element ED. On the other hand, when the video signal DS is in an L state, the transistor T5 does not apply the voltage ELVDD to the light-emitting element ED, and no current is supplied to the light-emitting element ED. As a result, the current switching circuit CS1 switches the current supplied to the light-emitting element ED in response to the H state or L state of the video signal DS, thereby varying the brightness of the sub-pixel P3 (light-emitting element ED) between two levels.

[0033] The current switching circuit CS2 has a transistor T6 that operates in response to the video signal DS held in the latch circuit LC2. Depending on whether the video signal DS is in the H state or the L state, the current switching circuit CS2 switches the current supplied to the light-emitting element ED, thereby varying the brightness of the sub-pixel P3 (light-emitting element ED) in two stages.

[0034] In this way, the current switching circuits CS1 and CS2 switch the current supplied to the sub-pixel P3 (light-emitting element ED) between two levels depending on whether the video signal DS is in the H state or the L state. As a result, the current switching circuits CS1 and CS2 can change the brightness of the sub-pixel P3 (light-emitting element ED) in four levels.

[0035] As described above, the brightness of the sub-pixels P1 to P3 (pixel region P) can be changed in accordance with the video signal DS, thereby displaying an image on the display unit 11. This display can be performed in a reflective display mode M1, an emissive display mode M2, or a mixed display mode M3, and these display modes can be switched as appropriate. Details of this will be described later.

[0036] 4 is a diagram showing an example of temporal changes in signals that drive subpixels in the display device of embodiment 1. The signal Vcom represents the temporal changes in the signal applied to the counter electrodes 43 of the liquid crystal elements LD1 and LD2. The signals Von and Voff represent the temporal changes in the signals that are switched and applied to the reflective electrode 41 by the voltage switching circuit VS.

[0037] As shown in FIG. 4, the signal Voff is in phase with the signal Vcom. Therefore, when the signal Voff is applied to the reflective electrode 41 of the liquid crystal element LD, no voltage is applied to the liquid crystal element LD, and the liquid crystal element LD is in the OFF state. In contrast, the signal Von is in opposite phase to the signal Vcom. Therefore, when the signal Von is applied to the reflective electrode 41 of the liquid crystal element LD, a voltage is applied to the liquid crystal element LD, and the liquid crystal element LD is in the ON state. As a result, the voltage switching circuit VS switches the signals Von and Voff applied to the reflective electrode 41 in accordance with the video signal, thereby turning the liquid crystal element LD ON and OFF. Meanwhile, the current switching circuit VS switches the current supplied to the light-emitting element ED in accordance with the video signal, thereby turning the light-emitting element ED ON and OFF.

[0038] The video signal DSr is, for example, 5 [V] in the H state and 0 [V] in the L state. The voltages ELVDD and ELVSS of the light-emitting element ED are, for example, 3.5 [V] and −3.5 [V].

[0039] FIG. 5 is a diagram showing the relationship between the signal for driving the sub-pixel and the brightness of the sub-pixel in the display device of the first embodiment.

[0040] The brightness of the sub-pixels P1 and P2 as a whole, produced by the liquid crystal elements LD1 and LD2, can be changed in four stages by the ON / OFF states of the gate signals GS1 and GS2: (OFF, OFF), (ON, OFF), (OFF, ON), and (ON, ON). To achieve this, it is preferable that the areas A1 and A2 of the sub-pixels P1 and P2 are different from each other. This is because, when the areas A1 and A2 of the sub-pixels P1 and P2 are equal, the brightness of the sub-pixels P1 and P2 as a whole is the same in both the (ON, OFF) and (OFF, ON) states. For example, by making the area A2 of subpixel P2 twice the area A1 of subpixel P1, the brightness of the entire subpixels P1 and P2 can be changed to 0:1:2:3 when the combinations of gate signals GS1 and GS2 are (OFF, OFF), (ON, OFF), (OFF, ON), and (ON, ON).

[0041] The brightness of the sub-pixel P3 caused by the light-emitting element ED can also be changed in four stages depending on the ON / OFF states of the gate signals GS3 and GS4: (OFF, OFF), (ON, OFF), (OFF, ON), and (ON, ON). To achieve this, it is preferable that the current supply capabilities of the current switching circuits CS1 and CS2 are different from each other. This is because, when the current supply capabilities (currents I1 and I2) of the current switching circuits CS1 and CS2 are equal, the brightness of the sub-pixel P3 is the same whether the current is in the (ON, OFF) or (OFF, ON) state. For example, by doubling the current supply capability (supply current I2) of the current switching circuit CS2 compared to the current supply capability (supply current I1) of the current switching circuit CS1, the brightness of the subpixel P3 can be changed to a ratio of 0:1:2:3 when the combinations of the gate signals GS3 and GS4 are (OFF, OFF), (ON, OFF), (OFF, ON), and (ON, ON). Here, the luminance of the light-emitting element ED is roughly proportional to the current density supplied to the light-emitting element ED. Therefore, by doubling the supply current I2 compared to the supply current I1, the brightness of the subpixel P3 can be changed to a ratio of 0:1:2:3.

[0042] 6 is a diagram showing an example of the driving modes of the display device of Embodiment 1. Here, the driving modes shown are a reflective display mode M1, an emissive display mode M2, and a mixed display mode M3.

[0043] The gate lines GL1 to GL4 are scanned in sequence, and gate signals GS1 to GS4 are input. The gate signals GS1 and GS2 define a range of brightness for the sub-pixels P1 and P2 (liquid crystal elements LD1 and LD2), and the brightness of the sub-pixels P1 and P2 as a whole changes within that range in response to the video signal DS. The gate signals GS3 and GS4 define a range of brightness for the sub-pixel P3 (light-emitting element ED), and the brightness of the sub-pixel P3 changes within that range in response to the video signal DS.

[0044] In the reflective display mode M1, the display device 10 turns on both gate signals GS1 and GS2 and turns off both gate signals GS3 and GS4. At this time, the liquid crystal elements LD1 and LD2 are used to display images, but the light-emitting element ED is not used to display images. In this reflective display mode, visibility is good when the surroundings of the display device 10 are relatively bright.

[0045] In the luminous display mode M2, the display device 10 turns off both gate signals GS1 and GS2 and turns on both gate signals GS3 and GS4. At this time, the light-emitting element ED is used to display an image, but the liquid crystal elements LD1 and LD2 are not used to display an image. In this luminous display mode, visibility is good when the surroundings of the display device 10 are relatively dark.

[0046] In the mixed display mode M3, the display device 10 turns on the gate signals GS1 to GS4, and both the liquid crystal elements LD1 and LD (reflected light) and the light-emitting element ED (light-emitting element) are used to display images. In this mixed display mode, visibility is good when the surroundings of the display device 10 are of intermediate brightness.

[0047] In these display modes M1 to M3, the brightness of the pixel region may be adjusted in stages. For example, in the reflective display mode M1, one of the gate signals GS1 and GS2 may be turned OFF. In the emissive display mode M2, one of the gate signals GS3 and GS4 may be turned OFF. In the mixed display mode M3, at least one of the gate signals GS1 to GS4 may be turned OFF. The reflective display mode M1 and the emissive display mode M2 ​​each have four levels of brightness adjustment, and the display modes M1 to M3 as a whole have 16 (=4*4) levels of brightness adjustment. In this way, by further dividing the display modes M1 to M3, it is possible to more precisely respond to changes in the ambient brightness of the display device 10.

[0048] The display modes M1 to M3 can be switched on a pixel-by-pixel basis, so even if the brightness of external light on the display unit 11 is uneven, the entire display unit 11 can provide a display with good visibility.

[0049] As described above, the display device 10 of this embodiment has the reflective liquid crystal element LD (LD1, LD2) and the light-emitting element ED, and can switch between the reflective display mode M1, the emissive display mode M2, and the mixed display mode M3 for display, thereby enabling the display device 10 to flexibly respond to changes in the brightness of its surroundings.

[0050] Furthermore, the display device 10 has the following configurations (1) and (2), which enable the reflective liquid crystal element LD and the light-emitting element ED to be driven independently while suppressing an increase in power consumption. (1) The transistor T1 that drives the liquid crystal element LD1 is supplied with a video signal DS and is connected to the reflective electrode 411 of the liquid crystal element LD1 via a latch circuit LC1. (2) The transistor T3 that drives the light-emitting element ED is supplied with a video signal DS and is connected to the light-emitting element ED via a latch circuit LC3 (second latch circuit).

[0051] That is, the latch circuits LC1 and LC3 retain the video signal DS, thereby reducing the power consumption of the display device 10. Furthermore, because the transistors T1 and T3 operate using the same video signal DS, increases in cost and power consumption that would otherwise accompany the supply of different video signals DS are suppressed. Furthermore, the transistors T1 and T3 can be driven independently by the video signal DS, and the driving state of each transistor does not substantially affect the driving state of the other transistor.

[0052] The display device 10 of this embodiment can be used, for example, for advertising and information display with relatively low gradations outdoors, in public spaces, etc., as an example for signage applications.

[0053] [Embodiment 2] A display device 10 according to embodiment 2 will now be described in detail. Fig. 7 is a plan view showing the display device 10 of embodiment 2, as viewed from the positive direction of the Z axis. As shown in Fig. 7, the display device 10 includes a driver circuit DRC having a decode circuit DC, and an external light sensor LS.

[0054] The display control circuit DCC (controller) controls gate signals GS1, GS3, GS2, and GS4 (first gate signal, second gate signal, third gate signal, and fourth gate signal) in response to the amount of light received by the external light sensor LS (light receiving sensor). The driver circuit DRC (drive circuit) supplies the controlled gate signals GS1, GS3, GS2, and GS4 (first gate signal, second gate signal, third gate signal, and fourth gate signal) to the transistors T1, T3, T2, and T4 (first transistor, second transistor, third transistor, and fourth transistor), respectively. That is, the display control circuit DCC can set the display unit 11 to the emissive display mode M2 ​​if the amount of external light detected by the external light sensor LS is less than a threshold, and set the display unit 11 to the reflective display mode M1 if the amount of external light is equal to or greater than the threshold. As a result, it is possible to automatically prevent the display on the display unit 11 from becoming difficult to see under strong external light. Furthermore, it is possible to reduce the power consumption of the light emitting element ED (and ultimately the entire display device 10).

[0055] The display device 10 may have multiple external light sensors LS. The multiple external light sensors LS can be used to detect the distribution of external light on the display unit 11, and the display mode can be controlled for each pixel region P in accordance with the distribution of external light.

[0056] 8 is a circuit diagram showing an example of the configuration of a drive circuit for driving sub-pixels according to embodiment 2. Gate signals GS1 to GS4 are supplied to the gate lines GL1 to GL4 from a decode circuit DC. The decode circuit DC outputs the gate signals GS1 to GS4 based on a combination signal CS that indicates the ON / OFF combination of the gate signals GS1 to GS4.

[0057] The decode circuit DC simultaneously supplies a gate signal GS1 (first gate signal) and a gate signal GS3 (second gate signal) to the transistor T1 (first transistor) and the transistor T3 (second transistor), respectively. The decode circuit DC simultaneously supplies a gate signal GS1 (first gate signal, second gate signal, third gate signal, and fourth gate signal) to the transistors T1, T3, T2, and T4 (first transistor, second transistor, third transistor, and fourth transistor), respectively.

[0058] The combination signal CS is, for example, a 4-bit signal in which one bit represents the ON / OFF state of each of the gate signals GS1 to GS4. As an example, if the first to fourth bits are 1, 0, 1, 0 in order, the gate signals GS1 to GS4 are ON, OFF, ON, OFF in order.

[0059] In this way, by using the decode circuit DC, the driver circuit DRC does not need to scan the gate lines GL1 to GL4 in order, which reduces the wiring length of the gate lines GL1 to GL4 and reduces the power consumption of the driver circuit DRC.

[0060] 9 is a diagram showing an example of a drive mode of the display device of embodiment 2. Here, the display device 10 operates in a reflective display mode M1 in which both gate signals GS1 and GS2 are ON and both gate signals GS3 and GS4 are OFF. In FIG. 6, the gate lines GL1 to GL4 are scanned in sequence, whereas in FIG. 9, the gate lines GL1 to GL4 are not scanned, and the gate signals GS1 to GS4 can be supplied simultaneously.

[0061] [Modifications] Fig. 10 is a plan view showing an example of the arrangement of sub-pixels in a display device. Like Figs. 1 and 7, Fig. 10 shows the display unit 11 as viewed from the positive direction of the Z axis. Here, arrangement examples D1 to D8 are shown for the sub-pixels P1 to P3 in the pixel region Pr. Note that arrangement example D1 is the same as the arrangement in the first embodiment (Fig. 1).

[0062] In Arrangement Examples D1, D2, D5, and D6, the subpixel P1 (first subpixel) and the subpixel P2 (third subpixel) are aligned with the subpixel P3 (second subpixel) in a plan view. Among these, in Arrangement Examples D1 and D5, the areas of the subpixel P1 (first subpixel, here the reflective electrode 411) and the subpixel P2 (third subpixel, here the reflective electrode 412) are substantially the same. In Arrangement Examples D2 and D6, the area of ​​the subpixel P2 (third subpixel, here the reflective electrode 412) is larger than the area of ​​the subpixel P1 (first subpixel, here the reflective electrode 411). That is, the reflective electrodes 411 and 412 have different areas in a plan view. As described above, by making the areas of the reflective electrodes 411 and 412 different, it is possible to make the brightness of the sub-pixels P1 and P2 as a whole different when one of the liquid crystal elements LD1 and LD2 is turned on.

[0063] In Arrangement Examples D3 and D7, the subpixel P2 (third subpixel) is disposed between the subpixel P1 (first subpixel) and the subpixel P3 (second subpixel) in a planar view. In Arrangement Examples D4 and D8, the subpixel P3 (second subpixel) is disposed between the subpixel P1 (first subpixel) and the subpixel P2 (third subpixel) in a planar view. In this way, the subpixels P1 to P3 can be disposed in a variety of ways.

[0064] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present disclosure. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

[0065] 10 Display device 11 Display section 15 Drive circuit DRC Driver circuit DCC Display control circuit GS (GS1 to GS4) Gate signal DS (DSr, DSg, DSb) Video signal 20 Drive substrate 21 Insulating substrate 22 Drive circuit section 23 Insulating layer 30 Counter substrate 41 (411, 412) Reflective electrode 42 Liquid crystal layer 43 Counter electrode 44 Polarizer 45 Color filter 51, 53 Electrode 52 Organic layer Pr, Pg, Pb Pixel area P1, P2, P3 Sub-pixel T1 to T6 Transistor LC1 to LC4 Latch circuit CS1, CS1 Current switching circuit VS1, VS2 Voltage switching circuit LD1, LD2 Liquid crystal element ED Light-emitting element SLr, SLg, SLb Source line GL1 to GL4 Gate lines SW1, SW2 Switches Vcom, Voff, Von signals

Claims

1. A display device comprising: a first substrate including a pixel region in which a first sub-pixel having a first reflective electrode and a second sub-pixel having a light-emitting element are arranged; a second substrate facing the first substrate; and a liquid crystal layer arranged between the first substrate and the second substrate, wherein the first substrate includes a first transistor to which a video signal is supplied and which is connected to the first reflective electrode via a first latch circuit, and a second transistor to which the video signal is supplied and which is connected to the light-emitting element via a second latch circuit.

2. The display device according to claim 1, wherein the first substrate includes a first voltage switching circuit that switches the voltage applied to the first reflective electrode in response to a video signal output from the first transistor and held in the first latch circuit.

3. The display device according to claim 1 or 2, wherein the first substrate includes a first current switching circuit that switches the current supplied to the light-emitting element in response to a video signal output from the second transistor and held in the second latch circuit.

4. A display device as described in claim 1 or 3, wherein a third sub-pixel having a second reflective electrode is arranged in the pixel region, and the first substrate includes: a third transistor to which the video signal is supplied and which is connected to the second reflective electrode via a third latch circuit; and a second voltage switching circuit which switches the voltage applied to the second reflective electrode depending on the video signal output from the third transistor and held in the third latch circuit.

5. The display device according to claim 4, wherein the first reflective electrode and the second reflective electrode have mutually different areas in a plan view.

6. The display device according to claim 3, wherein the first substrate includes: a fourth transistor to which the video signal is supplied and which is connected to the light-emitting element via a fourth latch circuit; and a second current switching circuit which switches the current supplied to the light-emitting element in accordance with the video signal output from the fourth transistor and held in the fourth latch circuit.

7. The display device according to claim 6, wherein the second current switching circuit and the first current switching circuit have mutually different current supply capabilities.

8. The display device according to claim 4, wherein the first sub-pixel and the third sub-pixel are arranged along the second sub-pixel in a plan view.

9. The display device according to claim 4, wherein, in a plan view, the third sub-pixel is disposed between the first sub-pixel and the second sub-pixel.

10. The display device according to claim 4, wherein, in a plan view, the second sub-pixel is disposed between the first sub-pixel and the third sub-pixel.

11. The display device of claim 1, wherein the first substrate includes a first pixel region, a second pixel region, and a third pixel region corresponding to a first display color, a second display color, and a third display color, which are different from each other, respectively.

12. The display device according to claim 1, further comprising a drive circuit including a decode circuit that simultaneously supplies a first gate signal and a second gate signal to the first transistor and the second transistor, respectively.

13. The display device according to claim 6, further comprising a drive circuit including a decode circuit that simultaneously supplies a first gate signal, a second gate signal, a third gate signal, and a fourth gate signal to the first transistor, the second transistor, the third transistor, and the fourth transistor, respectively.

14. A display device as described in claim 6, comprising: a light receiving sensor; a control unit that controls a first gate signal, a second gate signal, a third gate signal, and a fourth gate signal in accordance with an amount of light received by the light receiving sensor; and a drive circuit that supplies the controlled first gate signal, second gate signal, third gate signal, and fourth gate signal to the first transistor, the second transistor, the third transistor, and the fourth transistor, respectively.

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