Display device, manufacturing method thereof, and head-mounted display device including display device

Abstract

Provided are a display device, a manufacturing method thereof, and a head-mounted display device including the display device. The display device comprises: a first single crystal semiconductor substrate including a plurality of first transistors; a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate and including a plurality of second transistors; and a light-emitting element layer disposed on the second single crystal semiconductor substrate and including a plurality of light-emitting elements, wherein the planar area of the first single crystal semiconductor substrate is smaller than the planar area of the second single crystal semiconductor substrate, and the length of a minimum line width of one of the first transistors is smaller than the length of a minimum line width of one of the second transistors.

Description

Display device, method for manufacturing the same, and head-mounted display device including the display device

[0001] The present invention relates to a display device, a method for manufacturing the same, and a head-mounted display device including the display device.

[0002] A head-mounted display device (HMD) is a device worn on the user's head, typically in the form of glasses or a helmet, that focuses images close to the user's eyes. HMDs can implement virtual reality (VR) or augmented reality (AR).

[0003] Head-mounted display devices magnify and display images displayed by a small display device using multiple lenses. Therefore, the display device applied to the head-mounted display device needs to provide high-resolution images, for example, images with a resolution of 3000 PPI (Pixels Per Inch) or higher. To this end, OLEDoS (Organic Light Emitting Diode on Silicon), a high-resolution, small organic light-emitting display device, is used as the display device applied to the head-mounted display device. OLEDoS is a device that displays images by arranging an organic light-emitting diode (OLED) on a semiconductor wafer substrate on which a CMOS (Complementary Metal Oxide Semiconductor) is arranged.

[0004] The problem to be solved by the present invention is to provide an ultra-small display device including a plurality of different single crystal semiconductor substrates and a head-mounted display device including the same.

[0005] The problem to be solved by the present invention is to provide a method for manufacturing a display device that can reduce manufacturing costs and improve manufacturing yield by performing a semiconductor process for forming elements of different sizes on different wafer substrates.

[0006] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0007] According to one embodiment of the present invention for solving the above problem, a display device includes a first single-crystal semiconductor substrate including a plurality of first transistors, a second single-crystal semiconductor substrate disposed on the first single-crystal semiconductor substrate and including a plurality of second transistors, and a light-emitting element layer disposed on the second single-crystal semiconductor substrate and including a plurality of light-emitting elements, wherein the first single-crystal semiconductor substrate has a planar area smaller than a planar area of ​​the second single-crystal semiconductor substrate, and a length of a minimum line width of any one of the first transistors is smaller than a length of a minimum line width of any one of the second transistors.

[0008] The minimum line width of any one of the first transistors may be less than 100 nm, and the minimum line width of any one of the second transistors may be 100 nm or more.

[0009] The second single crystal semiconductor substrate may include a plurality of through holes spaced apart from each other and a plurality of conductive vias respectively arranged within the plurality of through holes.

[0010] The device may further include a connection wiring layer disposed between the first single crystal semiconductor substrate and the light emitting element layer and including a plurality of connection wirings electrically connected to each of the plurality of conductive vias.

[0011] The above-mentioned connection wiring layer may be disposed between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate.

[0012] The above plurality of through holes may not overlap with the first single crystal semiconductor substrate in the thickness direction.

[0013] Some of the above plurality of connecting wires may overlap with the first single crystal semiconductor substrate in the thickness direction.

[0014] The first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate are each a silicon substrate or a silicon-germanium substrate, and each may have a thickness of 100 μm or less.

[0015] The light-emitting element layer includes a plurality of reflective layers arranged between the second single crystal semiconductor substrate and the light-emitting element and an interlayer insulating layer arranged between the reflective layer and the light-emitting element, and the plurality of reflective layers can be arranged to correspond to each of the plurality of light-emitting elements.

[0016] The light-emitting element includes a first light-emitting element arranged in a first light-emitting region that emits light of a first color, and a second light-emitting element arranged in a second light-emitting region that emits light of a second color different from the first color, and a thickness of the interlayer insulating layer arranged between the first light-emitting element and the reflective layer overlapping the first light-emitting element may be different from a thickness of the interlayer insulating layer arranged between the second light-emitting element and the reflective layer overlapping the second light-emitting element.

[0017] According to one embodiment of the present invention for solving the above problem, a display device includes a first single-crystal semiconductor substrate including a plurality of first transistors, a second single-crystal semiconductor substrate including a plurality of through-holes spaced apart from each other and disposed on the first single-crystal semiconductor substrate, and a plurality of conductive vias respectively disposed within the plurality of through-holes, a light-emitting element including a plurality of light-emitting elements disposed on the second single-crystal semiconductor substrate, and a connection wiring layer including connection wirings electrically connected to each of the plurality of conductive vias, wherein an area on a plane of the first single-crystal semiconductor substrate is smaller than an area on a plane of the second single-crystal semiconductor substrate.

[0018] The second single-crystal semiconductor substrate includes a plurality of second transistors electrically connected to the plurality of light-emitting elements, respectively, and the connection wiring layer can be disposed between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate.

[0019] The above plurality of through holes may not overlap with the first single crystal semiconductor substrate in the thickness direction.

[0020] Some of the above plurality of connecting wires may overlap with the first single crystal semiconductor substrate in the thickness direction.

[0021] The first single-crystal semiconductor substrate further includes a plurality of second transistors electrically connected to the plurality of light-emitting elements, respectively, and the connection wiring layer can be disposed between the first single-crystal semiconductor substrate and the light-emitting element layer.

[0022] The above-mentioned connection wiring layer may be disposed between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate.

[0023] At least some of the plurality of through holes may not overlap with the first single crystal semiconductor substrate in the thickness direction.

[0024] At least some of the above plurality of connecting wires may not overlap with the first single crystal semiconductor substrate in the thickness direction.

[0025] The above-mentioned connection wiring layer may be disposed between the second single crystal semiconductor substrate and the light emitting element layer.

[0026] The above plurality of through holes may overlap with the first single crystal semiconductor substrate in the thickness direction.

[0027] According to one embodiment of the present invention for solving the above problem, a display device includes a first single-crystal semiconductor substrate including a plurality of first transistors, a second single-crystal semiconductor substrate disposed on the first single-crystal semiconductor substrate, a light-emitting element layer disposed on the second single-crystal semiconductor substrate and including a plurality of light-emitting elements, and a protective layer surrounding the first single-crystal semiconductor substrate and partially in contact with the second single-crystal semiconductor substrate, wherein the first single-crystal semiconductor substrate has a smaller area on a plane than an area on a plane of the second single-crystal semiconductor substrate.

[0028] The side surface of the above protective layer may be parallel to the side surface of the second single crystal semiconductor substrate.

[0029] The thickness of the above protective layer may be greater than or equal to the thickness of the first single crystal semiconductor substrate.

[0030] The above protective layer can be in contact with the lower surface of the first single crystal semiconductor substrate and the lower surface of the second single crystal semiconductor substrate, respectively.

[0031] The second single crystal semiconductor substrate may further include a plurality of through holes spaced apart from each other, and a plurality of conductive vias respectively disposed within the plurality of through holes, and a connection wiring layer disposed between the first single crystal semiconductor substrate and the light emitting element layer and including a plurality of connection wirings electrically connected to each of the plurality of conductive vias.

[0032] The first single crystal semiconductor substrate further includes a plurality of second transistors electrically connected to the light emitting elements, and at least some of the plurality of connection wires may not overlap with the first single crystal semiconductor substrate in the thickness direction.

[0033] Each of the plurality of light-emitting elements can be electrically connected to one of the second transistors through the connecting wires and the conductive via.

[0034] The second single crystal semiconductor substrate includes a plurality of second transistors each electrically connected to the light emitting elements, and a minimum line width of any one of the first transistors may be smaller than a minimum line width of any one of the second transistors.

[0035] According to one embodiment of the present invention, a method for manufacturing a display device for solving the above problem includes the steps of preparing different first wafer substrates and second wafer substrates, forming a plurality of first transistors on the first wafer substrate, forming a plurality of through holes penetrating the second wafer substrate and a plurality of conductive vias respectively disposed within the plurality of through holes on the second wafer substrate, dividing the first wafer substrate into a plurality of first single-crystal semiconductor substrates and attaching the first single-crystal semiconductor substrates to one surface of the second wafer substrate, forming a planarizing layer covering the one surface of the second wafer substrate and the first single-crystal semiconductor substrates attached to the one surface, forming a light-emitting element layer including a plurality of light-emitting elements on the other surface of the second wafer substrate opposite the one surface, and dividing the second wafer substrate into a plurality of second single-crystal semiconductor substrates having the light-emitting element layer formed on the other surface and the first single-crystal semiconductor substrate attached to the one surface.

[0036] The area on the plane of the first single crystal semiconductor substrate may be smaller than the area on the plane of the second single crystal semiconductor substrate.

[0037] In the process of forming the above-mentioned flattening layer, the area on the plane of the above-mentioned flattening layer may be the same as the area on the plane of the above-mentioned second wafer substrate.

[0038] In the step of separating the second wafer substrate into the plurality of second single-crystal semiconductor substrates, the planarization layer is divided together with the second single-crystal semiconductor substrate to form a protective layer surrounding the first single-crystal semiconductor substrate, and in the display device, a side surface of the protective layer may be parallel to a side surface of the second single-crystal semiconductor substrate.

[0039] The method further includes forming a plurality of second transistors before forming the through holes in the second wafer substrate, wherein a minimum line width of any one of the first transistors may be smaller than a minimum line width of any one of the second transistors.

[0040] The minimum line width of any one of the first transistors may be less than 100 nm, and the minimum line width of any one of the second transistors may be 100 nm or more.

[0041] Before attaching the first single crystal semiconductor substrate to the second wafer substrate, the method may further include forming a connection wiring layer including connection wirings electrically connected to each of the plurality of conductive vias.

[0042] The above-mentioned connection wiring layer is formed on the one surface of the second single-crystal semiconductor substrate, and can be placed between the second single-crystal semiconductor substrate and the first single-crystal semiconductor substrate.

[0043] The above-mentioned connection wiring layer may be formed on the other surface of the second single-crystal semiconductor substrate and may be disposed between the second single-crystal semiconductor substrate and the light-emitting element layer.

[0044] The first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate may each be a silicon substrate or a silicon-germanium substrate, and each may have a thickness of 100 μm or less.

[0045] According to one embodiment of the present invention for solving the above problem, a head-mounted display device is provided that is mounted on a user's body and includes a frame corresponding to left and right eyes, a plurality of display devices disposed on the frame, and lenses disposed on each of the plurality of display devices, wherein the display devices include a first single-crystal semiconductor substrate including a plurality of first transistors, a second single-crystal semiconductor substrate disposed on the first single-crystal semiconductor substrate and including a plurality of through-holes spaced apart from each other and a plurality of conductive vias disposed within each of the plurality of through-holes, and a light-emitting element layer disposed on the second single-crystal semiconductor substrate and including a plurality of light-emitting elements, wherein an area on a plane of the first single-crystal semiconductor substrate is smaller than an area on a plane of the second single-crystal semiconductor substrate.

[0046] The display device may further include a protective layer surrounding the first single-crystal semiconductor substrate and partially in contact with the second single-crystal semiconductor substrate.

[0047] The display device may further include a connection wiring layer including a plurality of connection wirings electrically connected to each of the plurality of conductive vias.

[0048] The second single crystal semiconductor substrate of the display device includes a plurality of second transistors each electrically connected to the plurality of light emitting elements,

[0049] The above-mentioned connection wiring layer may be disposed between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate.

[0050] The display device may have a minimum line width of any one of the first transistors smaller than a minimum line width of any one of the second transistors.

[0051] The minimum line width of any one of the first transistors may be less than 100 nm, and the minimum line width of any one of the second transistors may be 100 nm or more.

[0052] The first single-crystal semiconductor substrate of the display device includes a plurality of second transistors electrically connected to the plurality of light-emitting elements, respectively, and the connection wiring layer can be disposed between the first single-crystal semiconductor substrate and the light-emitting element layer.

[0053] The above-mentioned connection wiring layer is disposed between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate, and at least some of the plurality of through holes may not overlap with the first single-crystal semiconductor substrate in the thickness direction.

[0054] The above-mentioned connection wiring layer is arranged between the second single-crystal semiconductor substrate and the light-emitting element layer, and the plurality of through holes can overlap with the first single-crystal semiconductor substrate in the thickness direction.

[0055] The display device may be configured such that the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate are each a silicon substrate or a silicon-germanium substrate, and each may have a thickness of 100 μm or less.

[0056] Specific details of other embodiments are included in the detailed description and drawings.

[0057] A display device according to one embodiment may include two different single-crystal semiconductor substrates. The display device may have a planar area of ​​a single-crystal semiconductor substrate disposed on the lower side thereof smaller than a planar area of ​​a single-crystal semiconductor substrate disposed on the upper side thereof.

[0058] Accordingly, the manufacturing process for the single-crystal semiconductor substrate positioned below can produce a large number of wafers per unit, thereby improving manufacturing yield. Furthermore, the manufacturing process for the single-crystal semiconductor substrate positioned above can minimize unnecessary area per unit area, enabling the implementation of high-resolution display devices per unit area.

[0059] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0060] Figure 1 is an exploded perspective view of a display device according to one embodiment.

[0061] Fig. 2 is a plan view showing an example of the driving unit illustrated in Fig. 1.

[0062] Fig. 3 is a plan view showing an example of the display unit illustrated in Fig. 1.

[0063] FIG. 4 is a block diagram showing a display device according to one embodiment.

[0064] Fig. 5 is an equivalent circuit diagram of a sub-pixel according to one embodiment.

[0065] FIG. 6 is a schematic cross-sectional view of a display device according to one embodiment.

[0066] Fig. 7 is a schematic cross-sectional view of a driving unit according to one embodiment.

[0067] FIG. 8 is a plan view showing the arrangement of pixels arranged in a display area of ​​a display unit according to one embodiment.

[0068] Figure 9 is a cross-sectional view taken along line A-A' of Figure 8.

[0069] FIG. 10 and FIG. 11 are plan views showing the arrangement of the display area of ​​the display unit according to another embodiment.

[0070] Fig. 12 is a flowchart showing a manufacturing process of a display device according to one embodiment.

[0071] Figures 13 to 18 are drawings sequentially showing a manufacturing process of a display device according to one embodiment.

[0072] Fig. 19 is a schematic cross-sectional view of a display device according to another embodiment.

[0073] Fig. 20 is a plan view showing an example of a display portion of the display device of Fig. 19.

[0074] Fig. 21 is a schematic cross-sectional view of a display device according to another embodiment.

[0075] Fig. 22 is a plan view showing an example of a driving unit of the display device of Fig. 21.

[0076] Fig. 23 is a plan view showing an example of a display portion of the display device of Fig. 21.

[0077] Fig. 24 is a cross-sectional view showing a part of the driving unit of Fig. 22.

[0078] Fig. 25 is a cross-sectional view showing a portion of the display unit of Fig. 23.

[0079] Fig. 26 is a cross-sectional view schematically showing the transistors of the driving unit and display unit of the display device of Fig. 21.

[0080] FIG. 27 is a perspective view showing a head-mounted display device according to one embodiment.

[0081] Fig. 28 is an exploded perspective view showing an example of the head-mounted display device of Fig. 27.

[0082] FIG. 29 is a perspective view showing a head-mounted display device according to one embodiment.

[0083] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0084] When an element or layer is referred to as "on" another element or layer, it includes both cases where it is directly above the other element or layer or where there is another layer or material intervening therebetween. Similarly, when an element or layer is referred to as "below," "left," and "right," it includes both cases where it is directly adjacent to the other element or where there is another layer or material intervening therebetween. Like reference numerals throughout the specification refer to like elements.

[0085] Although terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it should be understood that a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0086] Hereinafter, embodiments will be described with reference to the attached drawings.

[0087] Figure 1 is an exploded perspective view of a display device according to one embodiment.

[0088] Referring to FIG. 1, a display device (10) according to one embodiment is a device that displays a moving image or a still image. The display device (10) according to one embodiment can be applied to portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an ultra mobile PC (UMPC), etc. For example, the display device (10) can be applied as a display unit of a television, a laptop, a monitor, a billboard, or the Internet of Things (IOT). Alternatively, the display device (10) can be applied to a smart watch, a watch phone, a head mounted display device (HMD) for implementing virtual reality and augmented reality.

[0089] A display device (10) according to one embodiment may include a driving unit (100), a display unit (200), and a circuit board (300). The display device (10) may further include a protective layer (900) disposed around the driving unit (100).

[0090] The driving unit (100) may have a planar shape similar to a rectangle. For example, the driving unit (100) may have a planar shape similar to a square having one side in a first direction (DR1) and the other side in a second direction (DR2) intersecting the first direction (DR1). In the driving unit (100), the corner where the one side in the first direction (DR1) and the other side in the second direction (DR2) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The planar shape of the driving unit (100) is not limited to a rectangle, and may be formed similarly to other polygons, circles, or ovals. The planar shape of the display device (10) may follow the planar shape of the driving unit (100), but is not limited thereto.

[0091] The display unit (200) may be placed on the driving unit (100). In FIG. 1, the display unit (200) and the driving unit (100) are illustrated as being spaced apart, but this is merely an example in which they are separated to illustrate the driving unit (100). In the display device (10), the driving unit (100) and the display unit (200) may be joined to each other. The display unit (200) may have a shape substantially similar to that of the driving unit (100). For example, the driving unit (100) may have a planar shape similar to a square having one side in a first direction (DR1) and the other side in a second direction (DR2) intersecting the first direction (DR1). The planar shape of the display unit (200) is not limited to a square, and may be formed similarly to other polygons, circles, or ovals.

[0092] According to one embodiment, the display device (10) may have a larger area on a plane of the display unit (200) than a larger area on a plane of the driving unit (100). The display device (10) includes a driving unit (100) and a display unit (200) that include different substrates, and they may have different areas. The elements formed on the driving unit (100) and the elements formed on the display unit (200) may be different from each other, and the elements may be individually formed on different substrates. The display device (10) may be manufactured by forming a plurality of elements having different sizes, line widths, manufacturing processes, etc. on different substrates and then bonding them together, and has the advantage of improving product performance and manufacturing yield. A more detailed description thereof will be described later with reference to other drawings.

[0093] The circuit board (300) may be electrically connected to a plurality of pads in the pad area of ​​the display unit (200) using a conductive adhesive such as an anisotropic conductive film. The circuit board (300) may be a flexible printed circuit board made of a flexible material or a flexible film. In FIG. 1, the circuit board (300) is illustrated as being unfolded, but the circuit board (300) may be bent. In this case, one end of the circuit board (300) may be placed on the lower surface of the driving unit (100). The other end of the circuit board (300) may be connected to a plurality of pads in the pad area of ​​the display unit (200) using a conductive adhesive.

[0094] Although not illustrated in FIG. 1, the display device (10) may further include a heat dissipation layer overlapping the driving unit (100) and the display unit (200) in a third direction (DR3). The heat dissipation layer may be disposed on the lower surface of the driving unit (100) and may release heat generated from the driving unit (100) and the display unit (200). The heat dissipation layer may include a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al) having high thermal conductivity.

[0095] The protective layer (900) surrounds the driving unit (100) and can be placed on the lower surface of the display unit (200). The protective layer (900) can reduce the step caused by the difference in area between the driving unit (100) and the display unit (200), and can also protect the driving unit (100) and the display unit (200).

[0096] Fig. 2 is a plan view showing an example of the driving unit illustrated in Fig. 1. Fig. 3 is a plan view showing an example of the display unit illustrated in Fig. 1. Fig. 4 is a block diagram showing a display device according to one embodiment.

[0097] Referring to FIGS. 2 to 4, the driving unit (100) of the display device (10) may include driving circuit elements of the display device (10). The driving unit (100) may include a first single-crystal semiconductor substrate (110) and a driving circuit unit (400), a gate driving unit (600), a data driving unit (700), and a pixel circuit unit (800) formed on the first single-crystal semiconductor substrate (110).

[0098] The first single-crystal semiconductor substrate (110) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first single-crystal semiconductor substrate (110) may include transistors of driving circuit elements. For example, the first single-crystal semiconductor substrate (110) may include at least a portion of each of the transistors of the driving elements. In this case, at least a portion of each of the transistors of the driving elements may be disposed within the first single-crystal semiconductor substrate (110), and the remaining portion of each of the transistors of the driving elements may be formed on the first single-crystal semiconductor substrate (110). The plurality of transistors may be electrically connected to each other to form a driving circuit unit (400), a gate driving unit (600), a data driving unit (700), and a pixel circuit unit (800).

[0099] In FIG. 2, the pixel circuit unit (800) is arranged on the upper side of the driving unit (100), the gate driving unit (600) is arranged on the right side thereof, and the data driving unit (700) and the driving circuit unit (400) are arranged on the lower side of the pixel circuit unit (800). However, this is not limited thereto. The positions of the driving circuit unit (400), the gate driving unit (600), the data driving unit (700), and the pixel circuit unit (800) in the driving unit (100) may be variously modified depending on the design structure of the plurality of circuit elements included in the first single crystal semiconductor substrate (110).

[0100] The driving circuit unit (400) may include a timing control circuit (410) and a power supply circuit (420). In addition, the driving circuit unit (400) may further include various circuits involved in driving the display device (10), such as a gamma circuit and a logic circuit. The driving circuit unit (400) may include a plurality of transistors included in a first single-crystal semiconductor substrate (110). For example, at least a portion of each of the plurality of transistors of the driving circuit unit (400) may be included in the first single-crystal semiconductor substrate (110). In this case, at least a portion of each of the transistors of the driving circuit unit (400) may be formed within the first single-crystal semiconductor substrate (110), and the remaining portion of each of the transistors of the driving circuit unit (400) may be formed on the first single-crystal semiconductor substrate (110).

[0101] The above transistors may be formed using a semiconductor process. For example, the plurality of transistors may be formed using CMOS (Complementary Metal Oxide Semiconductor) transistors.

[0102] The timing control circuit (410) can receive digital video data and timing signals from the outside. The timing control circuit (410) can generate a scan timing control signal (SCS), an emission timing control signal (ECS), and a data timing control signal (DCS) for controlling the display unit (200) according to the timing signals. The timing control circuit (410) can output the scan timing control signal (SCS) to the scan driving unit (610) of the gate driving unit (600) and output the emission timing control signal (ECS) to the emission driving unit (620) of the gate driving unit (600). The timing control circuit (410) can output digital video data and a data timing control signal (DCS) to the data driving unit (700).

[0103] The power supply circuit (420) can generate a plurality of panel driving voltages according to an external power voltage. For example, the power supply circuit (420) can generate a first driving voltage (VSS), a second driving voltage (VDD), and a third driving voltage (VINT) and supply them to the pixel circuit unit (800). The first driving voltage (VSS), the second driving voltage (VDD), and the third driving voltage (VINT) will be described later with reference to FIG. 5.

[0104] The scan timing control signal (SCS), the emission timing control signal (ECS), the digital video data (DATA), and the data timing control signal (DCS) of the timing control circuit (410) can be supplied to the pixel circuit unit (800). The first driving voltage (VSS), the second driving voltage (VDD), and the third driving voltage (VINT) of the power supply circuit (420) can also be supplied to the pixel circuit unit (800). The driving unit (100) is connected to the lower surface of the display unit (200), and the driving circuit unit (400) of the driving unit (100) can be electrically connected to the display unit (200).

[0105] The gate driver (600) may include a scan driver (610) and a light emitting driver (620). The scan driver (610) includes a plurality of scan transistors included in a first single-crystal semiconductor substrate (110), and the light emitting driver (620) includes a plurality of light emitting transistors included in the first single-crystal semiconductor substrate (110). For example, at least a portion of each of the plurality of scan transistors of the scan circuit unit (610) may be included in the first single-crystal semiconductor substrate (110). In this case, at least a portion of each of the plurality of scan transistors of the scan circuit unit (610) may be formed within the first single-crystal semiconductor substrate (110), and the remaining portions of each of the plurality of scan transistors may be formed on the first single-crystal semiconductor substrate (110). In addition, at least a portion of each of the plurality of light emitting transistors of the light emitting driver (620) may be included in the first single-crystal semiconductor substrate (110). In this case, at least a portion of each of the plurality of light-emitting transistors of the light-emitting circuit unit (620) may be formed within the first single-crystal semiconductor substrate (110), and the remaining portion of each of the plurality of light-emitting transistors may be formed on the first single-crystal semiconductor substrate (110).

[0106] The plurality of scan transistors and the plurality of light-emitting transistors can be formed using a semiconductor process. For example, the plurality of scan transistors and the plurality of light-emitting transistors can be formed using CMOS transistors.

[0107] The scan driving unit (610) may include a write scan signal output unit (611), a control scan signal output unit (612), and a bias scan signal output unit (613). Each of the write scan signal output unit (611), the control scan signal output unit (612), and the bias scan signal output unit (613) may receive a scan timing control signal (SCS) from the timing control circuit (410). The write scan signal output unit (611) may generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (410) and sequentially output the same to the write scan lines (GWL). The control scan signal output unit (612) may generate control scan signals according to the scan timing control signal (SCS) and sequentially output the same to the write control lines (GCL). The bias scan signal output unit (613) can generate bias scan signals according to a scan timing control signal (SCS) and sequentially output them to bias scan lines (GBL).

[0108] The light emitting driver (620) includes a first light emitting control driver (621) and a second light emitting control driver (622). Each of the first light emitting control driver (621) and the second light emitting control driver (622) can receive a light emitting timing control signal (ECS) from the timing control circuit (410). The first light emitting control driver (621) can generate first light emitting control signals according to the light emitting timing control signal (ECS) and sequentially output the same to the first light emitting control lines (EL1). The second light emitting control driver (622) can generate second light emitting control signals according to the light emitting timing control signal (ECS) and sequentially output the same to the second light emitting control lines (EL2).

[0109] The data driving unit (700) includes a plurality of data transistors included in a first single-crystal semiconductor substrate (110). For example, at least a portion of each of the plurality of data transistors of the data driving unit (700) may be included in the first single-crystal semiconductor substrate (110). In this case, at least a portion of each of the plurality of data transistors of the data driving unit (700) may be formed within the first single-crystal semiconductor substrate (110), and the remaining portion of each of the plurality of data transistors may be formed on the first single-crystal semiconductor substrate (110).

[0110] The plurality of data transistors may be formed by a semiconductor process. For example, the plurality of data transistors may be formed by CMOS transistors. The data driving unit (700) may receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (410). The data driving unit (700) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs the analog data voltages to the data lines (DL). In this case, the sub-pixels (SP) are selected by the write scan signal of the scan driving unit (610), and the data voltages may be supplied to the selected sub-pixels (SP).

[0111] The first pad area (PDA1) may include a plurality of first pads (PD1) arranged in a first direction (DR1). The plurality of first pads (PD1) may be electrically connected to a plurality of second pads (PD2) of the display unit (200), and may be electrically connected to the circuit board (300) through these. The first pads (PD1) may transmit an electric signal applied from the circuit board (300) to the driving circuit unit (400), the gate driving unit (600), the data driving unit (700), and the pixel circuit unit (800).

[0112] The pixel circuit unit (800) includes a plurality of pixel transistors included in a first single-crystal semiconductor substrate (110). For example, at least a portion of each of the plurality of pixel transistors of the pixel circuit unit (800) may be included in the first single-crystal semiconductor substrate (110). In this case, at least a portion of each of the plurality of pixel transistors of the pixel circuit unit (800) may be formed within the first single-crystal semiconductor substrate (110), and the remaining portion of each of the plurality of pixel transistors may be formed on the first single-crystal semiconductor substrate (110).

[0113] The plurality of pixel transistors may be formed using a semiconductor process. For example, the plurality of pixel transistors may be formed using CMOS transistors.

[0114] A plurality of data lines (DL), a plurality of scan lines (SL), and a plurality of light emission control lines (EL) may be arranged in the pixel circuit unit (800). The plurality of scan lines (SL) and the plurality of light emission control lines (EL) may extend in a first direction (DR1) and may be arranged in a second direction (DR2). The plurality of data lines (DL) may extend in the second direction (DR2) and may be arranged in the first direction (DR1).

[0115] The plurality of scan lines (SL) include a plurality of write scan lines (GWL), a plurality of write control lines (GCL), and a plurality of bias scan lines (GBL). The plurality of light emission control lines (EL) include a plurality of first light emission control lines (EL1) and a plurality of second light emission control lines (EL2). The plurality of scan lines (SL), the plurality of light emission control lines (EL), and the plurality of data lines (DL) may be electrically connected to a plurality of pixel transistors, and the pixel circuit unit (800) may be electrically connected to the pixels (PX) of the display unit (200) to transmit an electrical signal required for light emission of the light emitting element.

[0116] The display unit (200) may include a display area (DAA) in which light-emitting elements that emit light are arranged to display an image. The display unit (200) may include a second single-crystal semiconductor substrate (210) and a display element layer ('230' in FIG. 6) arranged on the second single-crystal semiconductor substrate (210).

[0117] The second single-crystal semiconductor substrate (210) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The second single-crystal semiconductor substrate (210) may not have transistor elements formed thereon. However, the present invention is not limited thereto. In another embodiment, the second single-crystal semiconductor substrate (210) may also include circuit elements necessary for driving the display device (10).

[0118] A display area (DAA) may have a plurality of pixels (PX) including light-emitting elements arranged thereon. The plurality of pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). Each of the plurality of pixels (PX) may include a plurality of sub-pixels (SP), and the sub-pixels (SP) may be electrically connected to a pixel circuit unit (800) of a driving unit (100). Each of the sub-pixels (SP) may include light-emitting elements, and the light-emitting elements may emit light according to an electrical signal applied from the pixel circuit unit (800). Some of the pixels (PX) arranged in the display area (DAA) of the display unit (200) may overlap with the pixel circuit unit (800) of the driving unit (100) in the thickness direction. However, they may be arranged on different single-crystal semiconductor substrates (110, 210), and they may be electrically connected through a connection wiring layer ('220' in FIG. 6) arranged therebetween.

[0119] Each of the plurality of sub-pixels (SP) may be connected to one of the plurality of write scan lines (GWL) of the pixel circuit unit (800), one of the plurality of write control lines (GCL), one of the plurality of bias scan lines (GBL), one of the plurality of first light emission control lines (EL1), one of the plurality of second light emission control lines (EL2), and one of the plurality of data lines (DL). Each of the plurality of sub-pixels (SP) may be supplied with a data voltage of the data line (DL) according to a write scan signal of the write scan line (GWL), and may emit light through a light-emitting element according to the data voltage.

[0120] The second pad area (PDA2) may include a plurality of second pads (PD2) arranged in the first direction (DR1). The plurality of second pads (PD2) may be electrically connected to a plurality of first pads (PD1) of the driving unit (100), and a circuit board (300) may be attached thereon. The second pads (PD2) are electrically connected to the circuit board (300) and may transmit an electrical signal applied from the circuit board (300) to the driving unit (100).

[0121] Fig. 5 is an equivalent circuit diagram of a sub-pixel according to one embodiment.

[0122] Referring to FIG. 5, a sub-pixel (SP) may be connected to a write scan line (GWL), a write control line (GCL), a bias scan line (GBL), a first emission control line (EL1), a second emission control line (EL2), and a data line (DL). In addition, the sub-pixel (SP) may be connected to a first driving voltage line (VSL) to which a first driving voltage (VSS) corresponding to a low potential voltage is applied, a second driving voltage line (VDL) to which a second driving voltage (VDD) corresponding to a high potential voltage is applied, and a third driving voltage line (VIL) to which a third driving voltage (VINT) corresponding to an initialization voltage is applied. That is, the first driving voltage line (VSL) may be a low potential voltage line, the second driving voltage line (VDL) may be a high potential voltage line, and the third driving voltage line (VIL) may be an initialization voltage line. In this case, the first driving voltage (VSS) may be a voltage lower than the third driving voltage (VINT). The second driving voltage (VDD) may be a higher voltage than the third driving voltage (VINT).

[0123] The sub-pixel (SP) includes a plurality of transistors (T1 to T6), a light emitting element (LE), a first capacitor (C1), and a second capacitor (C2).

[0124] The light-emitting element (LE) emits light according to a source-drain current (Ids, hereinafter referred to as “driving current”) flowing in a channel of the first transistor (T1). The amount of light emitted by the light-emitting element (LE) may be proportional to the driving current (Ids). The light-emitting element (LE) may be disposed between the fourth transistor (T4) and the first driving voltage line (VSL). A first electrode of the light-emitting element (LE) may be connected to a drain electrode of the fourth transistor (T4), and a second electrode may be connected to the first driving voltage line (VSL). The first electrode of the light-emitting element (LE) may be an anode electrode, and the second electrode of the light-emitting element (LE) may be a cathode electrode. The light-emitting element (LE) may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but is not limited thereto. For example, the light emitting element (LE) may be an inorganic light emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, in which case the light emitting element (LE) may be a micro light emitting diode.

[0125] The first transistor (T1) may be a driving transistor that controls a driving current (Ids) flowing between the source electrode and the drain electrode according to a voltage applied to the gate electrode. The first transistor (T1) includes a gate electrode connected to a first node (N1), a source electrode connected to the drain electrode of the sixth transistor (T6), and a drain electrode connected to a second node (N2).

[0126] The second transistor (T2) may be disposed between one electrode of the first capacitor (C1) and the data line (DL). The second transistor (T2) is turned on by a write scan signal of the write scan line (GWL) to connect one electrode of the first capacitor (C1) to the data line (DL). As a result, the data voltage of the data line (DL) may be applied to one electrode of the first capacitor (C1). The second transistor (ST2) includes a gate electrode connected to the write scan line (GWL), a source electrode connected to the data line (DL), and a drain electrode connected to one electrode of the first capacitor (C1).

[0127] A third transistor (T3) may be placed between a first node (N1) and a second node (N2). The third transistor (T3) is turned on by a write control signal of a write control line (GCL) to connect the first node (N1) to the second node (N2). Accordingly, since the gate electrode and the source electrode of the first transistor (T1) are connected, the first transistor (T1) can operate like a diode. The third transistor (T3) includes a gate electrode connected to the write control line (GCL), a source electrode connected to the second node (N2), and a drain electrode connected to the first node (N1).

[0128] The fourth transistor (T4) can be connected between the second node (N2) and the third node (N3). The fourth transistor (ST4) is turned on by the first light emission control signal of the first light emission control line (EL1) to connect the second node (N2) to the third node (N3). As a result, the driving current of the first transistor (T1) can be supplied to the light emitting element (LE). The fourth transistor (T4) includes a gate electrode connected to the first light emission control line (EL1), a source electrode connected to the second node (N2), and a drain electrode connected to the third node (N3).

[0129] The fifth transistor (T5) may be arranged between the third node (N3) and the third driving voltage line (VIL). The fifth transistor (T5) is turned on by a bias scan signal of the bias scan line (GBL) to connect the third node (N3) to the third driving voltage line (VIL). As a result, the third driving voltage (VINT) of the third driving voltage line (VIL) may be applied to the first electrode of the light emitting element (LE). The fifth transistor (T5) includes a gate electrode connected to the bias scan line (GBL), a source electrode connected to the third node (N3), and a drain electrode connected to the third driving voltage line (VIL).

[0130] The sixth transistor (T6) may be disposed between the source electrode of the first transistor (T1) and the second driving voltage line (VDL). The sixth transistor (T6) is turned on by the second emission control signal of the second emission control line (EL2) to connect the source electrode of the first transistor (T1) to the second driving voltage line (VDL). As a result, the second driving voltage (VDD) of the second driving voltage line (VDL) may be applied to the source electrode of the first transistor (T1). The sixth transistor (T6) includes a gate electrode connected to the second emission control line (EL2), a source electrode connected to the second driving voltage line (VDL), and a drain electrode connected to the source electrode of the first transistor (T1).

[0131] A first capacitor (C1) is formed between a first node (N1) and a drain electrode of a second transistor (T2). The first capacitor (C1) includes one electrode connected to the drain electrode of the second transistor (T2) and the other electrode connected to the first node (N1).

[0132] A second capacitor (C2) is formed between the gate electrode of the first transistor (T1) and the second driving voltage line (VDL). The second capacitor (C2) includes one electrode connected to the gate electrode of the first transistor (T1) and the other electrode connected to the second driving voltage line (VDL).

[0133] The first node (N1) is a contact point of the gate electrode of the first transistor (T1), the drain electrode of the third transistor (T3), the other electrode of the first capacitor (C1), and one electrode of the second capacitor (C2). The second node (N2) is a contact point of the drain electrode of the first transistor (T1), the source electrode of the third transistor (T3), and the source electrode of the fourth transistor (T4). The third node (N3) is a contact point of the drain electrode of the fourth transistor (T4), the source electrode of the fifth transistor (T5), and the first electrode of the light emitting element (LE).

[0134] Each of the first to sixth transistors (T1 to T6) may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first to sixth transistors (T1 to T6) may be a P-type MOSFET, but is not limited thereto. Each of the first to sixth transistors (T1 to T6) may be an N-type MOSFET. Alternatively, among the first to sixth transistors (T1 to T6), some of the transistors may be P-type MOSFETs, and the remaining transistors may be N-type MOSFETs.

[0135] Although Fig. 5 illustrates that the sub-pixel (SP) includes six transistors (T1 to T6) and two capacitors (C1, C2), it should be noted that the equivalent circuit diagram of the sub-pixel (SP) is not limited to that illustrated in Fig. 5. For example, the number of transistors and the number of capacitors of the sub-pixel (SP) are not limited to those illustrated in Fig. 5.

[0136] FIG. 6 is a schematic cross-sectional view of a display device according to one embodiment.

[0137] Referring to FIG. 6, a display device (10) according to one embodiment may include a driving unit (100) including a first single-crystal semiconductor substrate (110) and a driving circuit layer (120) disposed on the first single-crystal semiconductor substrate (110), and a display unit (200) including a second single-crystal semiconductor substrate (210) and a display element layer (230) disposed on the second single-crystal semiconductor substrate (210). The display device (10) may include two different single-crystal semiconductor substrates (110, 210) that overlap each other in a third direction (DR3), which is a thickness direction of the display device (10).

[0138] The driving unit (100) may include circuit elements required for the light emitting elements included in the display element layer (230) of the display unit (200) to emit light. As described above, the driving circuit layer (120) of the driving unit (100) may include a driving circuit unit (400), a gate driving unit (600), a data driving unit (700), etc., and the circuit elements constituting these, such as transistors and capacitors, may be formed as CMOS on the first single crystal semiconductor substrate (110). The display unit (200) may include a plurality of light emitting elements that emit light so as to display an image of the display device (10). The light emitting elements may be electrically connected to the circuit elements formed in the driving unit (100) to emit light.

[0139] The display device (10) can form light-emitting elements and circuit elements on two different substrates, respectively, and can efficiently utilize the space of each substrate. For example, the display element layer (230) and the second pad (PD2) can be arranged on the second single-crystal semiconductor substrate (210) of the display unit (200), and the circuit elements electrically connected thereto can be arranged on the first single-crystal semiconductor substrate (110) of the driving unit (100). Since the second single-crystal semiconductor substrate (210) does not require space for arranging the circuit elements, unnecessary areas other than the display area (DAA) where the light-emitting elements are not arranged can be minimized.

[0140] According to one embodiment, the display device (10) may have a smaller area on a plane of the driving unit (100) or the first single-crystal semiconductor substrate (110) than the area on a plane of the display unit (200) or the second single-crystal semiconductor substrate (210). The plurality of transistors formed in the driving unit (100) may be formed through a semiconductor micro-process and may have very small sizes or line widths. The driving unit (100) has the advantage of allowing a large number of circuit elements to be arranged with a high degree of integration, and reducing power consumption due to miniaturization of the elements.

[0141] In addition, since the driving unit (100) includes only circuit elements formed as CMOS on the first single-crystal semiconductor substrate (110) and does not include light-emitting elements, it may be sufficient to secure only a space sufficient to allow elements formed by a fine process to be arranged. Since the first single-crystal semiconductor substrate (110) is sufficient even if it has a smaller area than the second single-crystal semiconductor substrate (210), a large number of driving units (100) can be manufactured on a single wafer substrate on which a process for forming a driving circuit layer (120) is performed, thereby improving the manufacturing yield. In particular, since the driving unit (100) is performed using a high-cost semiconductor process, it may also have the effect of reducing costs due to an improvement in the manufacturing yield of the driving unit (100). In addition, the display unit (200) can form a large number of light-emitting elements on a relatively large area of ​​the second single-crystal semiconductor substrate (210), thereby enabling the implementation of a high-resolution display device.

[0142] According to one embodiment, the display device (10) may include a connection wiring layer (220) disposed between a second single-crystal semiconductor substrate (210) of the display unit (200) and a single-crystal semiconductor substrate of a driving circuit layer (120) of the driving unit (100). The connection wiring layer (220) may be disposed on a lower surface of the second single-crystal semiconductor substrate (210). The connection wiring layer (220) includes a plurality of routing wirings (RM1, RM2), and the routing wirings (RM1, RM2) may connect light-emitting elements of a display element layer (230) disposed on the display unit (200) and a circuit board (300) to the driving unit (100). The driving circuit layer (120) of the driving unit (100) may be electrically connected to the display unit (200) and the circuit board (300) through the routing wirings (RM1, RM2) of the connection wiring layer (220) to transmit an electric signal for light emission.

[0143] The first routing wire (RM1) may be connected to the display element layer (230) arranged in the display unit (200). The first routing wire (RM1) may be electrically connected to the light-emitting element of the display element layer (230) and the pixel circuit unit (800) of the driver (100), respectively. The second routing wire (RM2) may be connected to the circuit board (300). The second routing wire (RM2) may be electrically connected to the first pad (PD1) of the driver (100) and the second pad (PD2) of the display unit (200), respectively. The first routing wire (RM1) may be a wire that transmits a circuit signal required for the light-emitting elements included in the display element layer (230) to emit light. The second routing wire (RM2) may be a wire that transmits a signal applied from the circuit board (300) to the driver (100).

[0144] According to one embodiment, the display unit (200) of the display device (10) includes a plurality of through holes formed in a second single-crystal semiconductor substrate (210), and the routing wires (RM1, RM2) of the connection wiring layer (220) can be electrically connected to the light-emitting element layer (230) through the through holes of the second single-crystal semiconductor substrate (210), respectively. The second single-crystal semiconductor substrate (210) is disposed between the display element layer (230) and the driving circuit layer (120) and can include at least one or more plurality of through holes to provide an electrical connection path of the routing wires (RM1, RM2).

[0145] The routing wires (RM1, RM2) may include connecting wires ('RML' in FIG. 9) arranged on the connecting wire layer (220) and conductive vias arranged in the through holes of the second single-crystal semiconductor substrate (210). The routing wires (RM1, RM2) are wires that electrically connect layers arranged above and below the second single-crystal semiconductor substrate (210), and the arrangement and design of the through holes formed in the second single-crystal semiconductor substrate (210) may vary depending on the arrangement of the layers electrically connected to the routing wires (RM1, RM2).

[0146] For example, in the embodiment of FIG. 6, the first routing wire (RM1) can connect each of the light-emitting elements arranged in the plurality of pixels (PX) of the display element layer (230) to the pixel circuit unit (800) of the driver unit (100). Since the second single-crystal semiconductor substrate (210) has a larger planar area than the first single-crystal semiconductor substrate (110), some of the pixels (PX) included in the display element layer (230) of the display unit (200) may overlap with the pixel circuit unit (800) in the thickness direction, while other some of the pixels (PX) may not overlap with the pixel circuit unit (800) in the thickness direction.

[0147] The conductive vias of the first routing wire (RM1) are arranged to overlap with the pixel circuit unit (800) in the thickness direction, and the through holes in which the first routing wire (RM1) is arranged among the plurality of through holes formed in the second single crystal semiconductor substrate (210) can also overlap with the pixel circuit unit (800) in the thickness direction. The connection wire of the first routing wire (RM1) is formed over the entire surface of the second single crystal semiconductor substrate (210) so as to be electrically connected to the pixels (PX) of the display element layer (230), respectively, and the conductive vias of the first routing wire (RM1) can be arranged to be concentrated in an area overlapping with the pixel circuit unit (800).

[0148] On the other hand, the conductive vias of the second routing wire (RM2) are arranged to overlap with the first pad (PD1) of the driving unit (100), and the through holes in which the second routing wire (RM2) is arranged among the plurality of through holes formed in the second single crystal semiconductor substrate (210) may also overlap with the first pad (PD1) in the thickness direction. The connection wires of the second routing wire (RM2) may be electrically connected to the second pad (PD2) of the display unit (200) to form an electrical connection path with the conductive vias connected to the first pad (PD1). However, the present invention is not limited thereto. The arrangement and connection design of the connection wires of the first routing wire (RM1) and the second routing wire (RM2) may be variously modified.

[0149] The protective layer (900) may be disposed around the driving unit (100). The protective layer (900) may surround the driving unit (100) and may be disposed on the lower surface of the display unit (200). The protective layer (900) is formed to cover the driving unit (100) during the manufacturing process of the display device (10) and may fill the step between the driving unit (100) and the display unit (200). When the first single-crystal semiconductor substrate (110) is attached to the lower surface of the second single-crystal semiconductor substrate (210) having a different area during the manufacturing process of the display device (10), the protective layer (900) may fill the step between the first single-crystal semiconductor substrate (110) and the second single-crystal semiconductor substrate (210), and an additional process may be performed on the second single-crystal semiconductor substrate (210).

[0150] In one embodiment, the thickness of the protective layer (900) may be greater than or thicker than the thickness of the first single-crystal semiconductor substrate (110). The protective layer (900) may be thicker than or equal to the sum of the thicknesses of the first single-crystal semiconductor substrate (110) of the driving unit (100) and the driving circuit layer (120) disposed thereon. The protective layer (900) may be formed thicker than the driving unit (100), such that a portion thereof may be in direct contact with the lower surface of the display unit (200), and a portion thereof may be in direct contact with the lower surface of the driving unit (100). Accordingly, the driving unit (100) and the display unit (200) may be completely covered by the protective layer (900) on the lower surface of the display device (10).

[0151] In addition, the protective layer (900) may have the same planar area as the second single-crystal semiconductor substrate (210), and the side surface of the protective layer (900) may be parallel to the side surface of the second single-crystal semiconductor substrate (210). The protective layer (900) may be divided together when the second single-crystal semiconductor substrate (210) is divided from the wafer substrate ('WF2' in FIG. 18) in the manufacturing process of the display device (10), and the planar area of ​​the protective layer (900) may be the same as the planar area of ​​the second single-crystal semiconductor substrate (210). Even if the display device (10) includes the first single-crystal semiconductor substrate (110) and the second single-crystal semiconductor substrate (210) having different planar areas, partial steps may be compensated for by the protective layer (900), thereby ensuring structural stability.

[0152] Hereinafter, the structure of the driving circuit layer (120) of the driving unit (100) and the display element layer (230) of the display unit (200) will be described in detail with reference to other drawings.

[0153] Fig. 7 is a schematic cross-sectional view of a driving unit according to one embodiment.

[0154] Referring to FIG. 7, the driving unit (100) may include a first single crystal semiconductor substrate (110) and a driving circuit layer (120) disposed thereon. FIG. 7 roughly illustrates the cross-sectional structure of a pixel circuit unit (800) and a data driving unit (700) among the circuit units disposed in the driving unit (100).

[0155] The first single-crystal semiconductor substrate (110) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first single-crystal semiconductor substrate (110) may be a substrate doped with a first-type impurity. A plurality of well regions may be arranged on an upper surface of the first single-crystal semiconductor substrate (110). The plurality of well regions may be regions doped with a second-type impurity. The second-type impurity may be different from the first-type impurity described above. For example, when the first-type impurity is a p-type impurity, the second-type impurity may be an n-type impurity. Alternatively, when the first-type impurity is an n-type impurity, the second-type impurity may be a p-type impurity.

[0156] A first single-crystal semiconductor substrate (110) and a driving circuit layer disposed on the first single-crystal semiconductor substrate (110) may include a plurality of transistors (PTR) constituting a plurality of circuit elements of a driving unit (100). A plurality of well regions disposed within the first single-crystal semiconductor substrate (110) may each include a source region (SA) corresponding to a source electrode of the transistor (PTR), a drain region (DA) corresponding to a drain electrode, and a channel region (CH) disposed between the source region (SA) and the drain region (DA).

[0157] In an embodiment where the first single-crystal semiconductor substrate (110) is a substrate doped with a first type impurity, each of the source region (SA) and the drain region (DA) may be a region doped with a first type impurity. The gate electrode (GE) may be arranged to overlap a well region between the source region (SA) and the drain region (DA), and a channel region (CH) may be formed between the source region (SA) and the drain region (DA). A portion of the semiconductor insulating layer (SINS) may overlap the gate electrode (GE) and be arranged between the gate electrode (GE) and the well region. The source region (SA), the channel region (CH), and the drain region (DA) of the transistor (PTR) may be arranged within the first single-crystal semiconductor substrate (110), and the gate electrode (GE) of the transistor (PTR) may be arranged on the first single-crystal semiconductor substrate (110).

[0158] In some embodiments, the gate electrode (GE) and a portion of the semiconductor insulating layer (SINS) overlapping the gate electrode (GE) may partially overlap the source region (SA) and the drain region (DA) at both ends, respectively. The transistors (PTRs) constituting the pixel circuit unit (800) illustrated in FIG. 7 may be the first to sixth transistors (T1 to T6) described above with reference to FIG. 5. The transistors (PTRs) of the data driver unit (700) may be transistors constituting circuits such as the timing control circuit (410) and the power supply circuit (420).

[0159] When a driving circuit layer (120) is formed on a silicon wafer substrate, a process for reducing the thickness of the first single-crystal semiconductor substrate (110) may be performed. The first single-crystal semiconductor substrate (110) may have a thickness thinner than a wafer substrate on which a semiconductor process for forming the driving circuit layer (120) is performed. In some embodiments, the thickness of the first single-crystal semiconductor substrate (110) may be 100 μm or less, for example, in a range of 80 μm to 100 μm.

[0160] The driving circuit layer (120) may include a semiconductor insulating layer (SINS), a plurality of contact electrodes (CTEs), a first interlayer insulating layer (INS1), a second interlayer insulating layer (INS2), a plurality of conductive layers (ML1 to ML8), and a plurality of vias (VA1 to VA8). The driving circuit layer (120) may include wirings electrically connected to a plurality of transistors (PTRs) included in the first single crystal semiconductor substrate (110).

[0161] A semiconductor insulating layer (SINS) may be disposed on a first single-crystal semiconductor substrate (110). The semiconductor insulating layer (SINS) may be formed of an inorganic film of silicon nitride carbon (SiCN) or silicon oxide (SiOx) series, but is not limited thereto. In the drawing, the semiconductor insulating layer (SINS) is exemplified as being formed as a single layer having a predetermined thickness, but is not limited thereto. The semiconductor insulating layer (SINS) may have a structure in which at least one or more layers are stacked on top of each other.

[0162] A plurality of contact electrodes (CTEs) may be arranged on a first single-crystal semiconductor substrate (110). The plurality of contact electrodes (CTEs) may be connected to any one of a gate electrode (GE), a source region (SA), and a drain region (DA) of each of the transistors (PTRs) formed on the first single-crystal semiconductor substrate (110) through a hole penetrating a semiconductor insulating layer (SINS). The plurality of contact electrodes (CTEs) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these. The plurality of contact electrodes (CTEs) may have upper surfaces that are not covered by the semiconductor insulating layer (SINS) and may be exposed.

[0163] The first interlayer insulating layer (INS1) may be disposed on a plurality of contact electrodes (CTEs) and a semiconductor insulating layer (SINS). The second interlayer insulating layer (INS2) may be disposed on the first interlayer insulating layer (INS1). The first interlayer insulating layer (INS1) and the second interlayer insulating layer (INS2) may each be formed of an inorganic film of silicon carbon nitride (SiCN) or silicon oxide (SiOx) series, but are not limited thereto. In the drawing, the first interlayer insulating layer (INS1) and the second interlayer insulating layer (INS2) are each formed as one layer, but are not limited thereto. The first interlayer insulating layer (INS1) and the second interlayer insulating layer (INS2) may each have a structure in which at least one or more layers are laminated with each other, and they may be disposed between a plurality of first to eighth conductive layers (ML1 to ML8) described below.

[0164] The first to eighth conductive layers (ML1 to ML8) and the first to eighth vias (VA1 to VA8) are electrically connected to a plurality of contact electrodes (CTE) and can form circuit parts or driving parts of the driving unit (100). A plurality of transistors (PTR) included in the first single crystal semiconductor substrate (110) are electrically connected to each other through the first to eighth conductive layers (ML1 to ML8) and the first to eighth vias (VA1 to VA8) and can form a driving circuit part (400), a gate driving part (600), a data driving part (700), and a pixel circuit part (800) of the driving unit (100). For example, the first to sixth transistors (T1 to T6) included in the pixel circuit of the sub-pixel (SP) illustrated in FIG. 5 are a plurality of transistors (PTR) included in the first single-crystal semiconductor substrate (110), and the connection of the first to sixth transistors (T1 to T6) and the first capacitor (C1) and the second capacitor (C2) can be formed through the first to eighth conductive layers (ML1 to ML8).

[0165] A first conductive layer (ML1) can be connected to a contact electrode (CTE) through a first via (VA1). The first conductive layer (ML1) is disposed on the contact electrode (CTE), and the first via (VA1) is disposed between the first conductive layer (ML1) and the contact electrode (CTE) to contact them, respectively. A second conductive layer (ML2) can be connected to the first conductive layer (ML1) through a second via (VA2). The second conductive layer (ML2) is disposed on the first conductive layer (ML1), and the second via (VA2) is disposed between the first conductive layer (ML1) and the second conductive layer (ML2) to contact them, respectively.

[0166] The third conductive layer (ML3) may be connected to the second conductive layer (ML2) via a third via (VA3). The fourth conductive layer (ML4) may be connected to the third conductive layer (ML3) via the fourth via (VA4), the fifth conductive layer (ML5) may be connected to the fourth conductive layer (ML4) via the fifth via (VA5), and the sixth conductive layer (ML6) may be connected to the fifth conductive layer (ML5) via the sixth via (VA6). The third conductive layer (ML3), the fourth conductive layer (ML4), the fifth conductive layer (ML5), and the sixth conductive layer (ML6) may be sequentially arranged on the second conductive layer (ML2), and the third via (VA3), the fourth via (VA4), the fifth via (VA5), and the sixth via (VA6) may be arranged therebetween. The third to sixth vias (VA6) may each contact different metal layers disposed above and below them. The seventh via (VA7) may be disposed on the sixth conductive layer (ML6). The seventh via (VA7) may each contact the seventh conductive layer (ML7) and the sixth conductive layer (ML6) disposed thereon.

[0167] The first to sixth conductive layers (ML1 to ML6) and the first to seventh vias (VA1 to VA7) may be arranged on a first interlayer insulating layer (INS1). The first to sixth conductive layers (ML1 to ML6) and the first to seventh vias (VA1 to VA7) may constitute a first driving circuit layer arranged on the first interlayer insulating layer (INS1) among the driving circuit layers (120).

[0168] The seventh conductive layer (ML7) can be connected to the sixth conductive layer (ML6) through a seventh via (VA7). The seventh conductive layer (ML7) is disposed on the first interlayer insulating layer (INS1) and the sixth conductive layer (ML6), and the seventh via (VA7) is disposed between the sixth conductive layer (ML6) and the seventh conductive layer (ML7) to contact them, respectively. The eighth conductive layer (ML8) can be connected to the seventh conductive layer (ML7) through the eighth via (VA8). The eighth conductive layer (ML8) is disposed on the seventh conductive layer (ML7), and the eighth via (VA8) is disposed between the seventh conductive layer (ML7) and the eighth conductive layer (ML8) to contact them, respectively. The eighth conductive layer (ML8) may be exposed without being covered by the second interlayer insulating layer (INS2) on its upper surface, and may be electrically connected to the routing wires (RM1, RM2) arranged in the display portion (200) described above.

[0169] The seventh conductive layer (ML7), the eighth via (VA8), and the eighth conductive layer (ML8) may be disposed on the second interlayer insulating layer (INS2). The seventh conductive layer (ML7), the eighth via (VA8), and the eighth conductive layer (ML8) may constitute a second driving circuit layer disposed on the second interlayer insulating layer (INS2) among the driving circuit layers (120).

[0170] Although the drawing illustrates a structure in which the first to eighth conductive layers (ML1 to ML8) and the first to eighth vias (VA1 to VA8) are sequentially stacked, their arrangement and connection may be variously modified depending on the circuits of the driving circuit unit (400), the gate driving unit (600), the data driving unit (700), and the pixel circuit unit (800) of the driving unit (100). The connection structure illustrated in the drawing is only one example, and the connection of the driving circuit layer (120) arranged in the driving unit (100) of the display device (10) is not limited thereto. In addition, the driving circuit layer (120) may not necessarily include the first to eighth conductive layers (ML1 to ML8) and the first to eighth vias (VA1 to VA8), and some of these layers may be omitted or a greater number of layers may be arranged.

[0171] The first to eighth conductive layers (ML1 to ML8) and the first to eighth vias (VA1 to VA8) may be formed of substantially the same material. For example, the first to eighth conductive layers (ML1 to ML8) and the first to eighth vias (VA1 to VA8) may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these.

[0172] Each of the thickness of the first conductive layer (ML1), the thickness of the second conductive layer (ML2), the thickness of the third conductive layer (ML3), the thickness of the fourth conductive layer (ML4), the thickness of the fifth conductive layer (ML5), and the thickness of the sixth conductive layer (ML6) may be greater than each of the thickness of the first via (VA1), the thickness of the second via (VA2), the thickness of the third via (VA3), the thickness of the fourth via (VA4), the thickness of the fifth via (VA5), and the thickness of the sixth via (VA6). Each of the thickness of the second conductive layer (ML2), the thickness of the third conductive layer (ML3), the thickness of the fourth conductive layer (ML4), the thickness of the fifth conductive layer (ML5), and the thickness of the sixth conductive layer (ML6) may be greater than the thickness of the first conductive layer (ML1). The thickness of the second conductive layer (ML2), the thickness of the third conductive layer (ML3), the thickness of the fourth conductive layer (ML4), the thickness of the fifth conductive layer (ML5), and the thickness of the sixth conductive layer (ML6) may be substantially the same. For example, the thickness of the first conductive layer (ML1) may be approximately 1360 Å, the thickness of the second conductive layer (ML2), the thickness of the third conductive layer (ML3), the thickness of the fourth conductive layer (ML4), the thickness of the fifth conductive layer (ML5), and the thickness of the sixth conductive layer (ML6) may each be approximately 1440 Å, and the thickness of the first via (VA1), the thickness of the second via (VA2), the thickness of the third via (VA3), the thickness of the fourth via (VA4), the thickness of the fifth via (VA5), and the thickness of the sixth via (VA6) may each be approximately 1150 Å.

[0173] The thickness of the seventh conductive layer (ML7) and the thickness of the eighth conductive layer (ML8) may each be greater than the thickness of the first conductive layer (ML1), the thickness of the second conductive layer (ML2), the thickness of the third conductive layer (ML3), the thickness of the fourth conductive layer (ML4), the thickness of the fifth conductive layer (ML5), and the thickness of the sixth conductive layer (ML6). The thickness of the seventh conductive layer (ML7) and the thickness of the eighth conductive layer (ML8) may each be greater than the thickness of the seventh via (VA7) and the thickness of the eighth via (VA8). The thickness of the seventh via (VA7) and the thickness of the eighth via (VA8) may each be greater than the thickness of the first via (VA1), the thickness of the second via (VA2), the thickness of the third via (VA3), the thickness of the fourth via (VA4), the thickness of the fifth via (VA5), and the thickness of the sixth via (VA6). The thickness of the seventh conductive layer (ML7) and the thickness of the eighth conductive layer (ML8) may be substantially the same. For example, the thickness of the seventh conductive layer (ML7) and the thickness of the eighth conductive layer (ML8) may each be approximately 9000 Å. The thickness of the seventh via (VA7) and the thickness of the eighth via (VA8) may each be approximately 6000 Å.

[0174] Fig. 8 is a plan view showing the arrangement of pixels arranged in a display area of ​​a display unit according to one embodiment. Fig. 9 is a cross-sectional view taken along line A-A' of Fig. 8.

[0175] Referring to FIGS. 8 and 9, each of the plurality of pixels (PX) may include a first light-emitting area (EA1), a second light-emitting area (EA2), and a third light-emitting area (EA3), which are light-emitting areas of different plurality of sub-pixels (SP).

[0176] Each of the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may have a rectangular planar shape, such as a rectangle, a square, or a rhombus. For example, the first light-emitting area (EA1) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). In addition, the second light-emitting area (EA2) and the third light-emitting area (EA3) may each have a rectangular planar shape having a long side in the first direction (DR1) and a short side in the second direction (DR2).

[0177] The length of the first light-emitting area (EA1) in the first direction (DR1) may be shorter than the length of the second light-emitting area (EA2) in the first direction (DR1) and may be shorter than the length of the third light-emitting area (EA3) in the first direction (DR1). The length of the second light-emitting area (EA2) in the first direction (DR1) and the length of the third light-emitting area (EA3) in the first direction (DR1) may be substantially the same.

[0178] The length of the first light-emitting area (EA1) in the second direction (DR2) may be greater than the sum of the length of the second light-emitting area (EA2) in the second direction (DR2) and the length of the third light-emitting area (EA3) in the second direction (DR2). The length of the second light-emitting area (EA2) in the second direction (DR2) may be less than the length of the third light-emitting area (EA3) in the second direction (DR2).

[0179] In Fig. 8, each of the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) has a rectangular planar shape, but is not limited thereto. For example, each of the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may have a polygonal, circular, or elliptical planar shape other than a rectangular shape.

[0180] In each of the plurality of pixels (PX), the first light-emitting area (EA1) and the second light-emitting area (EA2) may be adjacent in the first direction (DR1). In addition, the first light-emitting area (EA1) and the third light-emitting area (EA3) may be adjacent in the first direction (DR1). In addition, the second light-emitting area (EA2) and the third light-emitting area (EA3) may be adjacent in the second direction (DR2). The area of ​​the first light-emitting area (EA1), the area of ​​the second light-emitting area (EA2), and the area of ​​the third light-emitting area (EA3) may be different.

[0181] The first light-emitting area (EA1) can emit light of a first color, the second light-emitting area (EA2) can emit light of a second color, and the third light-emitting area (EA3) can emit light of a third color. Here, the light of the first color can be light in a blue wavelength band, the second light can be light in a green wavelength band, and the third light can be light in a red wavelength band. For example, the blue wavelength band can refer to a light whose main peak wavelength is included in a wavelength band of about 370 nm to 460 nm, the green wavelength band can refer to a light whose main peak wavelength is included in a wavelength band of about 480 nm to 560 nm, and the red wavelength band can refer to a light whose main peak wavelength is included in a wavelength band of about 600 nm to 750 nm.

[0182] In Fig. 8, it is exemplified that each of the plurality of pixels (PX) includes three light-emitting areas (EA1, EA2, EA3), but this is not limited thereto. That is, each of the plurality of pixels (PX) may include four light-emitting areas.

[0183] In addition, the arrangement of the light-emitting areas of the plurality of pixels (PX) is not limited to that illustrated in FIG. 8. For example, the light-emitting areas of the plurality of pixels (PX) may be arranged in a stripe structure in which the light-emitting areas are arranged in the first direction (DR1), a PenTile® structure in which the light-emitting areas have a diamond arrangement, or a hexagonal structure in which the light-emitting areas have a hexagonal planar shape.

[0184] FIG. 10 and FIG. 11 are plan views showing the arrangement of the display area of ​​the display unit according to another embodiment.

[0185] Referring to FIGS. 10 and 11, the display device (10) according to one embodiment may have a different arrangement of the light-emitting areas (EA1, EA2, EA3) of the display unit (200) from that illustrated in FIG. 8. For example, in the display device (10) of FIG. 10, the first light-emitting area (EA1) and the second light-emitting area (EA2) in each of the plurality of pixels (PX) may be adjacent in the second direction (DR2). In addition, the first light-emitting area (EA1) and the third light-emitting area (EA3) may be adjacent in the second direction (DR2). In addition, the second light-emitting area (EA2) and the third light-emitting area (EA3) may be adjacent in the first direction (DR1). The area of ​​the first light-emitting area (EA1), the area of ​​the second light-emitting area (EA2), and the area of ​​the third light-emitting area (EA3) may be different. In the display device (10) of FIG. 8, the first light-emitting area (EA1) has a shape extending in the second direction (DR2), but in the display device (10) of FIG. 10, the first light-emitting area (EA1) may have a shape extending in the first direction (DR1). In the display device (10) of FIG. 11, the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may each have a hexagonal planar shape and may be arranged diagonally spaced apart from each other. In the drawing, the first light-emitting area (EA1) and the second light-emitting area (EA2) are arranged horizontally spaced apart from each other, and the third light-emitting area (EA3) is arranged diagonally spaced apart from the first light-emitting area (EA1) and the second light-emitting area (EA2). However, the arrangement of the plurality of light-emitting areas (EA1, EA2, EA3) is not limited thereto.

[0186] The display unit (200) may include a second single-crystal semiconductor substrate (210), a reflective layer (MIL), a light-emitting element layer (EML), an encapsulation layer (TFE), an optical layer (OPL), and a cover layer (CVL), as shown in FIG. 9. A connection wiring layer (220) may be disposed between the light-emitting element layer (EML) and the first single-crystal semiconductor substrate (110).

[0187] The second single-crystal semiconductor substrate (210) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The second single-crystal semiconductor substrate (210) may be a substrate doped with impurities. However, the present invention is not limited thereto. The second single-crystal semiconductor substrate (210) may also be a silicon substrate that is not doped with impurities. Unlike the first single-crystal semiconductor substrate (110), the second single-crystal semiconductor substrate (210) may or may not include a plurality of transistors. The second single-crystal semiconductor substrate (210) may be a base member on which a light-emitting element layer (EML) is disposed, and unlike the first single-crystal semiconductor substrate (110), circuit elements may not be formed.

[0188] The second single-crystal semiconductor substrate (210) may include a plurality of spaced-apart through holes (SVA). The through holes (SVA) may penetrate from the upper surface to the lower surface of the second single-crystal semiconductor substrate (210), and conductive vias (RVA) of routing lines (RM1, RM2) may be arranged. The through holes (SVA) may form connection passages of the routing lines (RM1, RM2) that electrically connect circuit elements of the driving unit (100) and light-emitting elements of the display unit (200). In some embodiments, the through holes (SVA) of the second single-crystal semiconductor substrate (210) may be formed through a TSV (Through Silicon Via) process that forms holes that penetrate a wafer substrate. The display element layer (230) and the driving unit (100) can be electrically connected to each other through routing wires (RM1, RM2) without a separate wire through a through hole (SVA) formed in the second single crystal semiconductor substrate (210).

[0189] The second single-crystal semiconductor substrate (210) may undergo a process of reducing its thickness after the driving unit (100) is bonded onto the silicon wafer substrate. The second single-crystal semiconductor substrate (210) may have a thickness thinner than the wafer substrate on which the process for forming the conductive layers is performed. In some embodiments, the thickness of the second single-crystal semiconductor substrate (210) may be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0190] The connection wiring layer (220) may be arranged on the lower surface of the second single crystal semiconductor substrate (210). The connection wiring layer (220) may include a third interlayer insulating layer (INS3), a plurality of connection wirings (RML), and a ninth via (VA9).

[0191] The third interlayer insulating layer (INS3) may be disposed on the lower surface of the second single-crystal semiconductor substrate (210). The third interlayer insulating layer (INS3) may be formed of an inorganic film of silicon nitride carbon (SiCN) or silicon oxide (SiOx) series, but is not limited thereto. In the drawing, the third interlayer insulating layer (INS3) is exemplified as being formed of a single layer, but is not limited thereto and may have a structure in which at least one or more layers are stacked on top of each other, and these may be disposed between the connection lines (RML).

[0192] The connecting wires (RML) may form a routing wire (RM) of the connecting wire layer (220) together with the ninth via (VA9) and the conductive via (RVA). The connecting wire (RML) may include at least one conductive layer and one or more vias connecting them to each other. The connection and structure of the connecting wires (RML) may be the same as the description of the plurality of conductive layers (ML1 to ML8) and vias (VA1 to VA8) described above. The connecting wire (RML) may be electrically connected to a light-emitting element of the light-emitting element layer (EML) through a conductive via (RVA) arranged in a through hole (SVA) of the second single crystal semiconductor substrate (210), and may be electrically connected to a driving circuit layer (120) of the driving unit (100) through the ninth via (VA9).

[0193] According to one embodiment, at least some of the plurality of through holes (SVA), connecting lines (RML) and conductive vias (RVA) may overlap with the display area (DAA) in the thickness direction, respectively. For example, at least some of the through holes (SVA), connecting lines (RML) and conductive vias (RVA) may overlap with the light-emitting areas (EA1, EA2, EA3) of the light-emitting element layer (EML) in the thickness direction, respectively. Since each of the light-emitting elements arranged in the light-emitting areas (EA1, EA2, EA3) of the light-emitting element layer (EML) is connected to the pixel circuit unit (800) through the routing lines (RM1, RM2), the connecting lines (RML) may overlap with each of the light-emitting elements in the thickness direction and be electrically connected thereto.

[0194] Since the routing wiring (RM) electrically connects the light emitting elements (LE) arranged on the second single crystal semiconductor substrate (210) to the pixel circuit portion (800) of the first single crystal semiconductor substrate (110), the arrangement of the connection wiring (RML), through holes (SVA), and conductive vias (RVA) can be variously modified depending on the relative arrangement of the light emitting element layer (EML) and the first single crystal semiconductor substrate (110).

[0195] For example, as the connection wiring layer (220) is disposed on the lower surface of the second single-crystal semiconductor substrate (210), the through holes (SVA) and the conductive vias (RVA) are disposed over the entire light emitting element layer (EML), and the connection wirings (RML) are disposed over the entire surface of the second single-crystal semiconductor substrate (210), but may be concentrated in the area where the first single-crystal semiconductor substrate (110) is located. According to one embodiment, the display device (10) may have a plurality of through holes (SVA) and conductive vias (RVA) overlap with the light emitting element layer (EML) in the thickness direction, and at least a portion of each of them may not overlap with the first single-crystal semiconductor substrate (110) in the thickness direction. As described above, the area on the plane of the first single crystal semiconductor substrate (110) may be smaller than the area on the plane of the second single crystal semiconductor substrate (210), and only some of the plurality of through holes (SVA) and conductive vias (RVA) arranged across the entire surface of the second single crystal semiconductor substrate (210) may overlap with the first single crystal semiconductor substrate (110) in the thickness direction.

[0196] At least some of the connection wirings (RMLs) may not overlap with the first single-crystal semiconductor substrate (110) in the thickness direction. The connection wirings (RMLs) may electrically connect a plurality of through holes (SVAs) and conductive vias (RVAs) arranged across the entire surface of the second single-crystal semiconductor substrate (210) to the pixel circuit unit (800) of the first single-crystal semiconductor substrate (110). Accordingly, some of the connection wirings (RMLs) may not overlap with the first single-crystal semiconductor substrate (110) in the thickness direction, but ends of the connection wirings (RMLs) composed of multiple layers may overlap with the first single-crystal semiconductor substrate (110) in the thickness direction. The connection wirings (RMLs) may form a path for electrically connecting light-emitting elements arranged across the entire surface of the display area (DAA) with a larger area to the pixel circuit unit (800) with a relatively smaller area.

[0197] A reflective layer (MIL) may be disposed on a second single-crystal semiconductor substrate (210). The reflective layer (MIL) may include one or more reflective electrodes (RL1, RL2, RL3, RL4). The plurality of reflective electrodes (RL1, RL2, RL3, RL4) of the reflective layer (MIL) may be disposed to overlap light-emitting areas (EA1, EA2, EA3), respectively. The reflective layer (MIL) may reflect light emitted from a light-emitting element layer (EML) disposed thereon toward the second single-crystal semiconductor substrate (210) toward an upper direction of the display unit (200). In addition, the reflective layer (MIL) may be formed of a conductive metal layer and may be electrically connected to a first electrode (AND) and a connection wire (RML) of the light-emitting element, respectively.

[0198] Each of the first reflective electrodes (RL1) is disposed on the third interlayer insulating layer (INS3) and can be connected to the ninth via (VA9). The first reflective electrodes (RL1) can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these.

[0199] Each of the second reflective electrodes (RL2) may be disposed on the first reflective electrode (RL1). The second reflective electrodes (RL2) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these. For example, the second reflective electrodes (RL2) may be titanium nitride (TiN).

[0200] A step layer (STPL) may be disposed on the second reflective electrode (RL2) overlapping the first light-emitting area (EA1). The step layer (STPL) may not be disposed on the second reflective electrode (RL2) overlapping the second light-emitting area (EA2) and the third light-emitting area (EA3). The thickness of the step layer (STPL) may be set in consideration of the wavelength of light and the distance from the second electrode (CAT) of the light-emitting element to the fourth reflective electrode (RL4) so ​​as to advantageously reflect light emitted from the intermediate layer (IL). The step layer (STPL) may be formed of an inorganic film of the silicon nitride carbon (SiCN) or silicon oxide (SiOx) series, but is not limited thereto. The thickness of the step layer (STPL) may be approximately 400 Å.

[0201] In the first light-emitting area (EA1), the third reflective electrode (RL3) may be disposed on the second reflective electrode (RL2) and the step layer (STPL). In the second light-emitting area (EA2) and the third light-emitting area (EA3), the third reflective electrode (RL3) may be disposed on the second reflective electrode (RL2). The third reflective electrodes (RL3) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these.

[0202] At least one of the first reflective electrode (RL1), the second reflective electrode (RL2), and the third reflective electrode (RL3) may be omitted.

[0203] Each of the fourth reflective electrodes (RL4) may be disposed on the third reflective electrode (RL3). The fourth reflective electrodes (RL4) may be layers that reflect light from the first to third intermediate layers (IL1, IL2, IL3). At least the fourth reflective electrode (RL4) of the uppermost layer among the plurality of reflective electrodes (RL1, RL2, RL3, RL4) may include a metal having a high reflectivity to facilitate light reflection. The fourth reflective electrodes (RL4) may be formed of, but are not limited to, aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy which is an alloy of silver (Ag), palladium (Pd), and copper (Cu), and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The thickness of each of the fourth reflective electrodes (RL4) may be approximately 850 Å.

[0204] Meanwhile, the method of setting the light emitted from the intermediate layer (IL) to be advantageously reflected by the reflective layer (RL) is not limited to arranging the step layer (STPL). Reflection of the light emitted from the intermediate layer (IL) may also be advantageous depending on the thickness of the fourth interlayer insulating layer (INS4) arranged between the first electrode (AND) of the light-emitting element and the fourth reflective electrode (RL4). In the display device (10), the thickness of the fourth interlayer insulating layer (INS4) arranged between the first electrode (AND) of the light-emitting element and the fourth reflective electrode (RL4) in several light-emitting areas (EA1, EA2, EA3) can be adjusted in consideration of the wavelengths of the light emitted from different light-emitting areas (EA1, EA2, EA3).

[0205] The display device (10) of FIG. 9 is an embodiment in which a step layer (STPL) overlapping the light-emitting element of the first light-emitting area (EA1) is disposed, while no step layer (STPL) is disposed in the second light-emitting area (EA2) and the third light-emitting area (EA3). However, the present invention is not limited thereto, and a step layer (STPL) may be further disposed in at least one of the second light-emitting area (EA2) and the third light-emitting area (EA3). Alternatively, the step layer (STPL) may not be disposed, and the thicknesses of the fourth interlayer insulating layer (INS4) between the first electrode (AND) of the light-emitting element and the fourth reflective electrode (RL4) may be different from each other.

[0206] The fourth interlayer insulating layer (INS4) may be disposed on the third interlayer insulating layer (INS3) and the fourth reflective electrodes (RL4). The fourth interlayer insulating layer (INS4) may be formed of an inorganic film of silicon nitride carbon (SiCN) or silicon oxide (SiOx) series, but is not limited thereto. In the drawing, the fourth interlayer insulating layer (INS4) is exemplified as being formed as a single layer, but is not limited thereto. The fourth interlayer insulating layer (INS4) may also have a structure in which at least one or more layers are laminated on top of each other.

[0207] The tenth via (VA10) may be disposed between the fourth reflective electrode (RL4) and the light emitting element layer (EML). The tenth via (VA10) may be disposed between the fourth reflective electrode (RL4) and the first electrode (AND) of the light emitting element layer (EML) and may be connected to them, respectively. The tenth via (VA10) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy including any one of these. Due to the step layer (STPL), the thickness of the tenth via (VA10) overlapping the first light emitting area (EA1) may be smaller than the thickness of the tenth via (VA10) in each of the second light emitting area (EA2) and the third light emitting area (EA3). For example, the thickness of the tenth via (VA10) in the first light-emitting area (EA1) may be approximately 800 Å, and the thicknesses of the second light-emitting area (EA2) and the third light-emitting area (EA3) may be approximately 1200 Å.

[0208] The light emitting element layer (EML) may be disposed on the fourth interlayer insulating layer (INS4). The light emitting element layer (EML) may include light emitting elements (LEs) each including a first electrode (AND), an intermediate layer (IL), and a second electrode (CAT), a pixel defining layer (PDL), and a plurality of trenches (TRC).

[0209] The first electrode (AND) of each of the light emitting elements (LE) is disposed on the fourth interlayer insulating layer (INS4) and can be connected to the tenth via (VA10). The first electrode (AND) of each of the light emitting elements (LE) can be electrically connected to the pixel circuit unit (800) of the driver unit (100) through the tenth via (VA10), the first to fourth reflective electrodes (RL1 to RL4), and the connection wiring (RML) of the connection wiring layer (220). The first electrode (AND) of each of the light emitting elements (LE) can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these. For example, the first electrode (AND) of each of the light emitting elements (LE) can be titanium nitride (TiN).

[0210] A pixel defining layer (PDL) may be disposed on a portion of the first electrode (AND) of each of the light emitting elements (LE). The pixel defining layer (PDL) may cover an edge of the first electrode (AND) of each of the light emitting elements (LE). The pixel defining layer (PDL) may define first light emitting areas (EA1), second light emitting areas (EA2), and third light emitting areas (EA3).

[0211] The first light-emitting area (EA1) may be defined as an area in which a first electrode (AND), an intermediate layer (IL), and a second electrode (CAT) are sequentially stacked in a first sub-pixel and emit light. The second light-emitting area (EA2) may be defined as an area in which a first electrode (AND), an intermediate layer (IL), and a second electrode (CAT) are sequentially stacked in a second sub-pixel and emit light. The third light-emitting area (EA3) may be defined as an area in which a first electrode (AND), an intermediate layer (IL), and a second electrode (CAT) are sequentially stacked in a third sub-pixel and emit light.

[0212] The pixel defining layer (PDL) may include first to third pixel defining layers (PDL1, PDL2, and PDL3). The first pixel defining layer (PDL1) may be disposed on the edge of the first electrode (AND) of each of the light emitting elements (LE), the second pixel defining layer (PDL2) may be disposed on the first pixel defining layer (PDL1), and the third pixel defining layer (PDL3) may be disposed on the second pixel defining layer (PDL2). The first pixel defining layer (PDL1), the second pixel defining layer (PDL2), and the third pixel defining layer (PDL3) may be formed of an inorganic layer of a silicon oxide (SiOx) series, but are not limited thereto. The thickness of the first pixel defining layer (PDL1), the thickness of the second pixel defining layer (PDL2), and the thickness of the third pixel defining layer (PDL3) may each be approximately 500 Å.

[0213] Each of the plurality of trenches (TRC) may penetrate the first pixel defining layer (PDL1), the second pixel defining layer (PDL2), and the third pixel defining layer (PDL3). In each of the plurality of trenches (TRC), a portion of the fourth interlayer insulating layer (INS4) may have a fine shape.

[0214] At least one trench (TRC) may be arranged between adjacent light-emitting areas (EA1, EA2, EA3). In Fig. 9, two trenches (TRC) are arranged between adjacent light-emitting areas (EA1, EA2, EA3), but the present invention is not limited thereto. The trench (TRC) may prevent the material of the intermediate layer (IL) from being connected between different light-emitting areas (EA1, EA2, EA3) or between openings of the pixel defining film (PDL) in the formation process of the intermediate layer (IL) described below.

[0215] The intermediate layer (IL) may include a first intermediate layer (IL1), a second intermediate layer (IL2), and a third intermediate layer (IL3).

[0216] The intermediate layer (IL) may have a tandem structure including a plurality of intermediate layers (IL1, IL2, IL3) that emit different light. For example, the intermediate layer (IL) may include a first intermediate layer (IL1) that emits light of a first color, a second intermediate layer (IL2) that emits light of a third color, and a third intermediate layer (IL3) that emits light of the second color. The first intermediate layer (IL1), the second intermediate layer (IL2), and the third intermediate layer (IL3) may be sequentially stacked. The stacking order of the first to third intermediate layers (IL1, IL2, IL3) that emit light of different colors may be modified differently.

[0217] The first intermediate layer (IL1) may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially laminated. The second intermediate layer (IL2) may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially laminated. The third intermediate layer (IL3) may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a second color, and a third electron transport layer are sequentially laminated.

[0218] A first charge generation layer may be arranged between the first intermediate layer (IL1) and the second intermediate layer (IL2) to supply charges to the second intermediate layer (IL2) and electrons to the first intermediate layer (IL1). A second charge generation layer may be arranged between the second intermediate layer (IL2) and the third intermediate layer (IL3) to supply charges to the third intermediate layer (IL3) and electrons to the second intermediate layer (IL2).

[0219] A first intermediate layer (IL1) is disposed on the first electrodes (AND) and the pixel defining layer (PDL), and may be disposed on the bottom surface of each trench (TRC). Due to the trench (TRC), the first intermediate layer (IL1) may be disconnected between adjacent light-emitting areas (EA1, EA2, EA3). A second intermediate layer (IL2) may be disposed on the first intermediate layer (IL1). Due to the trench (TRC), the second intermediate layer (IL2) may be disconnected between adjacent light-emitting areas (EA1, EA2, EA3). A third intermediate layer (IL3) may be disposed on the second intermediate layer (IL2). Due to the trench (TRC), the third intermediate layer (IL3) may be disconnected between adjacent light-emitting areas (EA1, EA2, EA3). That is, each of the plurality of trenches (TRC) may be a structure for cutting the first to third intermediate layers (IL1, IL2, IL3) of the light emitting element layer (EML) between adjacent light emitting regions (EA1, EA2, EA3).

[0220] In order to stably disconnect the first to third intermediate layers (IL1, IL2, IL3) of the light emitting element layer (EML) between adjacent light emitting areas (EA1, EA2, EA3), the depth of each of the plurality of trenches (TRC) may be greater than the height of the pixel defining layer (PDL). The depth of each of the plurality of trenches (TRC) may be the length of the trench (TRC) measured in the third direction (DR3). The height of the pixel defining layer (PDL) may be the length of the pixel defining layer (PDL) measured in the third direction (DR3).

[0221] In some embodiments, other structures may be arranged instead of the trenches (TRC) to separate the first to third intermediate layers (IL1, IL2, IL3) of the light emitting element layer (EML) between adjacent light emitting areas (EA1, EA2, EA3). For example, a reverse-tapered barrier rib may be arranged on the pixel defining layer (PDL) between adjacent light emitting areas (EA1, EA2, EA3).

[0222] The number of intermediate layers (IL1, IL2, IL3) that emit different light is not limited to that illustrated in FIG. 9. For example, the intermediate layer (IL) may include two intermediate layers. In this case, one of the two intermediate layers may be substantially identical to the first intermediate layer (IL1), and the other may include a second hole transport layer, a second organic light-emitting element layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer may be disposed between the two intermediate layers to supply electrons to one of the intermediate layers and charges to the other intermediate layer.

[0223] In addition, although FIG. 9 illustrates that the first to third intermediate layers (IL1, IL2, IL3) are disposed in the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3), the present invention is not limited thereto. For example, the first intermediate layer (IL1) may be disposed in the first light-emitting area (EA1) and may not be disposed in the second light-emitting area (EA2) and the third light-emitting area (EA3). In addition, the second intermediate layer (IL2) may be disposed in the third light-emitting area (EA3) and may not be disposed in the first light-emitting area (EA1) and the second light-emitting area (EA2). In addition, the third intermediate layer (IL3) may be disposed in the second light-emitting area (EA2) and may not be disposed in the first light-emitting area (EA1) and the third light-emitting area (EA3). In this case, the first to third color filters (CF1, CF2, CF3) of the optical layer (OPL) may be omitted.

[0224] The second electrode (CAT) may be disposed on the third intermediate layer (IL3). The second electrode (CAT) may be disposed on the third intermediate layer (IL3) in each of the plurality of trenches (TRC). The second electrode (CAT) may be formed of a transparent conductive material (TCO) that can transmit light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode (CAT) is formed of a semi-transmissive metallic material, the light emission efficiency in each of the light-emitting areas (EA1, EA2, EA3) may be improved by a micro cavity.

[0225] An encapsulation layer (TFE) may be disposed on a light-emitting element layer (EML). The encapsulation layer (TFE) may include at least one inorganic film (TFE1, TFE3) to prevent oxygen or moisture from penetrating into the light-emitting element layer (EML). In addition, the encapsulation layer (TFE) may include at least one organic film (TFE2) to protect the light-emitting element layer (EML) from foreign substances such as dust. For example, the encapsulation layer (TFE) may include a first encapsulation inorganic film (TFE1), an encapsulation organic film (TFE2), and a second encapsulation inorganic film (TFE3).

[0226] A first encapsulating inorganic film (TFE1) may be disposed on a second electrode (CAT), an encapsulating organic film (TFE2) may be disposed on the first encapsulating inorganic film (TFE1), and a second encapsulating inorganic film (TFE3) may be disposed on the encapsulating organic film (TFE2). The first encapsulating inorganic film (TFE1) and the second encapsulating inorganic film (TFE3) may be formed as a multi-film in which one or more inorganic films of silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxide (SiOx), titanium oxide (TiOx), and aluminum oxide layers (AlOx) are alternately laminated. The encapsulating organic film (TFE2) may be a monomer. Alternatively, the encapsulating organic film (TFE2) may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0227] The adhesive layer (ADL) may be a layer for bonding the encapsulation layer (TFE) and the optical layer (OPL). The adhesive layer (ADL) may be a double-sided adhesive material. In addition, the adhesive layer (ADL) may be a transparent adhesive material, such as a transparent adhesive or transparent adhesive resin.

[0228] The optical layer (OPL) may include a plurality of color filters (CF1, CF2, CF3), a plurality of lenses (LNS), and a filling layer (FIL). The plurality of color filters (CF1, CF2, CF3) may include first to third color filters (CF1, CF2, CF3). The first to third color filters (CF1, CF2, CF3) may be disposed on an adhesive layer (ADL).

[0229] The first color filter (CF1) may overlap with the first light-emitting area (EA1). The first color filter (CF1) may transmit light of a first color, i.e., light in a blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm. The first color filter (CF1) may transmit light of the first color among the light emitted from the first light-emitting area (EA1).

[0230] The second color filter (CF2) may overlap with the second emission area (EA2). The second color filter (CF2) may transmit light of a second color, i.e., light in a green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. The second color filter (CF2) may transmit light of a second color among the light emitted from the second emission area (EA2).

[0231] The third color filter (CF3) may overlap with the third emission area (EA3). The third color filter (CF3) may transmit light of a third color, i.e., light in a red wavelength band. The blue wavelength band may be approximately 600 nm to 750 nm. The third color filter (CF3) may transmit light of a third color among the light emitted from the third emission area (EA3).

[0232] Each of the plurality of lenses (LNS) may be disposed on each of the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3). Each of the plurality of lenses (LNS) may be a structure for increasing the proportion of light directed toward the front of the display device (10). Each of the plurality of lenses (LNS) may have a convex shape (CVX) in a cross-sectional shape that is convex in the upward direction.

[0233] A filling layer (FIL) may be disposed on a plurality of lenses (LNS). The filling layer (FIL) may have a predetermined refractive index so that light may propagate in a third direction (DR3) at an interface between the plurality of lenses (LNS) and the filling layer (FIL). In addition, the filling layer (FIL) may be a planarizing layer. The filling layer (FIL) may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0234] The cover layer (CVL) may be disposed on the filler layer (FIL). The cover layer (CVL) may be a glass substrate or a polymer resin such as resin. If the cover layer (CVL) is a glass substrate, it may be attached to the filler layer (FIL). In this case, the filler layer (FIL) may serve to adhere the cover layer (CVL). If the cover layer (CVL) is a glass substrate, it may serve as an encapsulation substrate. If the cover layer (CVL) is a polymer resin such as resin, it may be applied directly on the filler layer (FIL).

[0235] Although not shown in the drawing, the display unit (200) may further include a polarizing plate disposed on the cover layer (CVL). The polarizing plate may be disposed on one surface of the cover layer (CVL). The polarizing plate may be a structure for preventing a decrease in visibility due to external light reflection. The polarizing plate may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter-wave plate), but is not limited thereto. However, if visibility due to external light reflection is sufficiently improved by the first to third color filters (CF1, CF2, CF3), the polarizing plate may be omitted.

[0236] Below, a schematic manufacturing method of the display device (10) is described.

[0237] Fig. 12 is a flowchart showing a manufacturing process of a display device according to one embodiment.

[0238] Referring to FIG. 12, a method for manufacturing a display device (10) according to one embodiment may include a step of preparing first and second wafer substrates (S10), a step of forming first transistors on the first wafer substrate and forming through holes and conductive vias on the second wafer substrate (S20), a step of dividing the first wafer substrate into first single-crystal semiconductor substrates and attaching the first single-crystal semiconductor substrate to the second wafer substrate (S30), a step of forming a planarization layer covering the first single-crystal semiconductor substrate on one surface of the second wafer substrate and forming a light-emitting element layer on the other surface opposite to one surface of the second wafer substrate (S40), and a step of dividing the second wafer substrate into second single-crystal semiconductor substrates (S50).

[0239] A method for manufacturing a display device (10) may include performing processes suitable for forming a configuration of the display device (10) on two different wafer substrates, respectively, and bonding them together. On a first wafer substrate, a driving unit (100) including a driving circuit layer (120) may be manufactured by forming elements having a fine size, and then bonding these to a second wafer substrate, and then forming a display element layer (230) including a light-emitting element layer (EML), thereby manufacturing a display unit (200). Accordingly, on the first wafer substrate, fine elements are formed with a high degree of integration, thereby improving the manufacturing yield and reducing the manufacturing cost, and on the second wafer substrate, circuits other than light-emitting elements are not arranged, thereby reducing an unnecessary area and enabling the implementation of a high-resolution display device.

[0240] Figures 13 to 18 are drawings sequentially showing a manufacturing process of a display device according to one embodiment.

[0241] Referring to FIG. 13, a first wafer substrate (WF1) and a second wafer substrate (WF2) are prepared (S10). The first wafer substrate (WF1) and the second wafer substrate (WF2) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate, respectively. The first single-crystal semiconductor substrate (110) and the second single-crystal semiconductor substrate (210) may be substrates doped with first-type impurities. A plurality of well regions may be arranged on the upper surface of the first single-crystal semiconductor substrate (110). These may be mother substrates of the first single-crystal semiconductor substrate (110) and the second single-crystal semiconductor substrate (210) of the display device (10).

[0242] Referring to FIG. 14, a driving unit (100) is manufactured by forming a plurality of transistors (PTR) (e.g., a first transistor) and a driving circuit layer (120) on one surface of a first wafer substrate (WF1). A temporary single crystal semiconductor substrate (210') is formed on a second wafer substrate (WF2) by forming a plurality of through holes (SVA) penetrating the second wafer substrate (WF2) and conductive vias (RVA) arranged therein.

[0243] The process of forming a plurality of transistors (PTRs) and a driving circuit layer (120) on the first wafer substrate (WF1) may be a micro semiconductor process. On the other hand, the process of forming a through hole (SVA) on the second wafer substrate (WF2) may be a process having a larger line width than the semiconductor process performed on the first wafer substrate (WF1). Although the first wafer substrate (WF1) and the second wafer substrate (WF2) have the same area, the driving unit (100) and the temporary single crystal semiconductor substrate (210') formed in this process may have different areas. Accordingly, the number of driving units (100) formed on the first wafer substrate (WF1) may be greater than the number of temporary single crystal semiconductor substrates (210') formed on the second wafer substrate (WF2). The process of manufacturing the driving unit (100) on the first wafer substrate (WF1) is a high-cost semiconductor process, but has the advantage of having a relatively high yield.

[0244] A method for manufacturing a display device (10) according to one embodiment can manufacture a display device in which a pixel circuit unit (800) necessary for driving a light-emitting element of a display unit (200) is arranged on a driving circuit layer (120) of a driving unit (100), and in a process of forming a driving circuit layer (120) on a first wafer substrate (WF1), the driving circuit layer (120) can include a pixel circuit unit (800) in addition to a driving circuit unit (400), a gate driving unit (600), and a data driving unit (700).

[0245] The connection wiring layer (220) formed on the temporary single crystal semiconductor substrate (210') can be formed on the upper or lower surface of the temporary single crystal semiconductor substrate (210').

[0246] Next, referring to FIG. 15, the first wafer substrate (WF1) is divided into a plurality of first single-crystal semiconductor substrates (110), and the first single-crystal semiconductor substrates (110) are attached to the lower surface of the second wafer substrate (WF2). The first wafer substrate (WF1) may be divided into a plurality of first single-crystal semiconductor substrates (110) on which a driving circuit layer (120) is formed. In some embodiments, the driving circuit layer (120) disposed on the first single-crystal semiconductor substrate (110) may be bonded to the lower surface of a temporary single-crystal semiconductor substrate (210'). The process of bonding the first single-crystal semiconductor substrate (110) to the lower surface of the second wafer substrate (WF2) may be a process of separating the first single-crystal semiconductor substrate (110) from the first wafer substrate (WF1) and then bonding it to another second wafer substrate (WF2), rather than bonding two different wafer substrates together. A plurality of first single crystal semiconductor substrates (110) can be bonded to a plurality of temporary single crystal semiconductor substrates (210') formed on a second wafer substrate (WF2), respectively.

[0247] The process of bonding the first single-crystal semiconductor substrate (110) to the second wafer substrate (WF2) may be performed under conditions of higher temperature than the process of forming the light-emitting element layer described later. According to one embodiment, the process of bonding the first single-crystal semiconductor substrate (110) to the second wafer substrate (WF2) may be performed before the process of forming the light-emitting element layer including the light-emitting element on the second wafer substrate (WF2). The method of manufacturing the display device (10) may not be a method of manufacturing the driving unit (100) including the first single-crystal semiconductor substrate (110) and the display unit (200) including the second single-crystal semiconductor substrate (210) separately and then bonding them. The method of manufacturing the display device (10) may involve a process of dividing the first wafer substrate (WF1) into the driving unit (100) and bonding it to the second wafer substrate (WF2) on which the light-emitting elements are not formed.

[0248] In some embodiments, before performing the bonding process of FIG. 15, a connection wiring layer (220) may be formed on a temporary single-crystal semiconductor substrate (210'). The connection wiring layer (220) may be formed on a lower surface of a second wafer substrate (WF2), and the first single-crystal semiconductor substrate (110) may be attached to the lower surface of the second wafer substrate (WF2) on which the connection wiring layer (220) is formed. Accordingly, the driving circuit layer (120) formed on the first single-crystal semiconductor substrate (110) may be electrically connected to the connection wiring layer (220). However, the present invention is not limited thereto. The first single-crystal semiconductor substrate (110) may also be attached to an upper surface of the second wafer substrate (WF2) on which the connection wiring layer (220) is not formed. In this case, the planarization layer (910) described later is formed on the upper surface of the second wafer substrate (WF2), and the light emitting element layer (EML) may be formed on the connection wiring layer (220) or on the lower surface of the second wafer substrate (WF2).

[0249] Next, referring to FIG. 16, a planarization layer (910) is formed on the lower surface of the second wafer substrate (WF2). The planarization layer (910) can planarize the steps caused by the plurality of first single crystal semiconductor substrates (110) arranged on the lower surface of the second wafer substrate (WF2). As the planarization layer (910) is arranged, subsequent processes can be smoothly performed on the upper surface of the second wafer substrate (WF2). The planarization layer (910) can be divided together when the second wafer substrate (WF2) is divided to form a protective layer (900) of the display device (10).

[0250] Next, referring to FIG. 17, a light emitting element layer (EML) is formed on the upper surface opposite to the lower surface to which the driving unit (100) is attached, of the second wafer substrate (WF2). The process of forming the light emitting element layer (EML) may be performed as a different process from the semiconductor process of forming the driving circuit layer (120) on the first wafer substrate (WF1). For example, the process of forming the light emitting element layer (EML) may be performed as a semiconductor process having a relatively large line width, and may be a relatively low-cost process compared to the process of forming the driving circuit layer (120).

[0251] In the process of forming the light emitting element layer (EML), a plurality of light emitting elements of the light emitting element layer (EML) can be electrically connected to conductive vias and connection wiring of the connection wiring layer (220), respectively, and can be electrically connected to the driving circuit layer (120) of the driving unit (100) or the pixel circuit unit (800) through the conductive vias and connection wiring. In addition, in this process, a display element layer (230) including the light emitting element layer (EML), a reflective layer (MIL), an encapsulation layer (TFE), etc. can be formed. As the display element layer (230) is formed on the second wafer substrate (WF2), a display unit (200) including these can be formed.

[0252] Next, referring to FIG. 18, the second wafer substrate (WF2) can be divided into a second single-crystal semiconductor substrate (210) on which a light-emitting element layer (EML) is formed. A display element layer (230) including the light-emitting element layer (EML) is formed on the upper surface of the divided second single-crystal semiconductor substrate (210), and a connection wiring layer (220), a first single-crystal semiconductor substrate (110), and a protective layer (900) can be attached to the lower surface thereof. Although not illustrated in the drawing, a circuit board (300) can be attached on one surface of the display unit (200) to manufacture a display device (10).

[0253] In a method for manufacturing a display device (10) according to one embodiment, a process for forming elements of a circuit portion and a process for forming light-emitting elements can be performed on different wafer substrates (WF1, WF2). In the display device (10), the elements of the circuit portion and the light-emitting elements may have different optimized manufacturing processes, and taking this into consideration, they can be formed through individual processes that can increase the manufacturing yield on different wafer substrates. In particular, the process for forming the driving circuit layer (120) included in the driving unit (100) of the display device (10) is performed using a fine semiconductor process, and thus has the advantage of improving the yield per unit area on the first wafer substrate (WF1). In addition, the process for forming the display portion (200) of the display device (10) can minimize the space occupied by unnecessary elements other than the light-emitting elements, and has the advantage of enabling the implementation of a high-resolution display device per unit area.

[0254] Hereinafter, various embodiments of the display device (10) will be described with reference to other drawings.

[0255] Fig. 19 is a schematic cross-sectional view of a display device according to another embodiment. Fig. 20 is a plan view showing an example of a display portion of the display device of Fig. 19.

[0256] Referring to FIGS. 19 and 20, a display device (10_1) according to one embodiment may have a connection wiring layer (220) including a plurality of connection wirings (RML) disposed between a second single-crystal semiconductor substrate (210) and a light-emitting element layer (EML). Since the connection wiring layer (220) is disposed on the upper surface rather than the lower surface of the second single-crystal semiconductor substrate (210), the positions of the connection wirings (RML), conductive vias (RVA), and through holes (SVA) are different from the embodiments of FIGS. 6 and 9.

[0257] The connection wiring layer (220) may be disposed on the upper surface of the second single-crystal semiconductor substrate (210). The connection wiring layer (220) may include a third interlayer insulating layer (INS3), a plurality of connection wirings (RML), and a ninth via (VA9). The third interlayer insulating layer (INS3) may be disposed on the upper surface of the second single-crystal semiconductor substrate (210).

[0258] According to one embodiment, at least some of the plurality of through holes (SVA), connecting lines (RML) and conductive vias (RVA) may overlap with the display area (DAA) in the thickness direction, respectively. For example, at least some of the through holes (SVA), connecting lines (RML) and conductive vias (RVA) may overlap with the light-emitting areas (EA1, EA2, EA3) of the light-emitting element layer (EML) in the thickness direction, respectively. Since each of the light-emitting elements arranged in the light-emitting areas (EA1, EA2, EA3) of the light-emitting element layer (EML) is connected to the pixel circuit unit (800) through the routing lines (RM1, RM2), the connecting lines (RML) may overlap with each of the light-emitting elements in the thickness direction and be electrically connected thereto.

[0259] Since the routing wiring (RM) electrically connects the light emitting elements (LE) arranged on the second single crystal semiconductor substrate (210) to the pixel circuit portion (800) of the first single crystal semiconductor substrate (110), the arrangement of the connection wiring (RML), through holes (SVA), and conductive vias (RVA) can be variously modified depending on the relative arrangement of the light emitting element layer (EML) and the first single crystal semiconductor substrate (110).

[0260] For example, as the connection wiring layer (220) is disposed on the upper surface of the second single-crystal semiconductor substrate (210), the through holes (SVA) and the conductive vias (RVA) may be disposed to overlap with the first single-crystal semiconductor substrate (110). The connection wirings (RML) may be disposed over the entire light emitting element layer (EML), but may be concentrated in the area where the first single-crystal semiconductor substrate (110) is located. According to one embodiment, the display device (10_1) may have a plurality of through holes (SVA) and conductive vias (RVA) overlap with the first single-crystal semiconductor substrate (110) in the thickness direction, respectively. On the other hand, at least some of the connection wirings (RML) may not overlap with the first single-crystal semiconductor substrate (110) in the thickness direction.

[0261] As described above, the area on the plane of the first single-crystal semiconductor substrate (110) may be smaller than the area on the plane of the second single-crystal semiconductor substrate (210), and only some of the connection lines (RML) arranged across the entire surface of the second single-crystal semiconductor substrate (210) may overlap with the first single-crystal semiconductor substrate (110) in the thickness direction. Accordingly, the connection lines (RML) are arranged across the entire surface of the second single-crystal semiconductor substrate (210), and the ends of the connection lines (RML) composed of multiple layers overlap with the first single-crystal semiconductor substrate (110) in the thickness direction and may be connected to a plurality of through holes (SVA) and conductive vias (RVA). The connection lines (RML) may form a path for electrically connecting the light-emitting elements arranged across the entire surface of the display area (DAA) with a larger area to the pixel circuit unit (800) with a relatively smaller area.

[0262] The reflective layer (MIL) of the display unit (200) may be placed on the connection wiring layer (220). Hereinafter, the description of each layer of the display unit (200) is the same as described above.

[0263] In the present embodiment, during the manufacturing process of the display device (10_1), when attaching the first single-crystal semiconductor substrate (110) to one side of the second wafer substrate (WF2), the first single-crystal semiconductor substrate (110) can be manufactured by attaching the first single-crystal semiconductor substrate (110) to a side on which the connection wiring layer (220) is not formed. In the embodiment of FIG. 6, the first single-crystal semiconductor substrate (110) is attached to one side of both sides of the second wafer substrate (WF2) on which the connection wiring layer (220) is formed, whereas in the present embodiment, the first single-crystal semiconductor substrate (110) can be attached to the other side of both sides of the second wafer substrate (WF2) opposite to the one side on which the connection wiring layer (220) is formed. In a subsequent process, a planarization layer (910) may be formed on the other surface of the second wafer substrate (WF2) to cover the first single-crystal semiconductor substrate (110), and a light-emitting element layer (EML) may be formed on the one surface of the second wafer substrate (WF2) on which the connection wiring layer (220) is formed. Depending on the method of the process of forming the connection wiring layer (220) and attaching the first single-crystal semiconductor substrate (110), the relative arrangement of the connection wiring layer (220) and the second single-crystal semiconductor substrate (210) and the first single-crystal semiconductor substrate (110) arranged in the display device (10_1) may vary.

[0264] Fig. 21 is a schematic cross-sectional view of a display device according to another embodiment. Fig. 22 is a plan view showing an example of a driving unit of the display device of Fig. 21. Fig. 23 is a plan view showing an example of a display unit of the display device of Fig. 21.

[0265] Referring to FIGS. 21 to 23, a display device (10_2) according to one embodiment may include a pixel circuit unit (800) electrically connected to a display element layer (230) disposed on a second single-crystal semiconductor substrate (210), and a connection wiring layer (220) electrically connecting the pixel circuit unit (800) and the driving circuit layer (120) of the driving unit (100) may be disposed between the second single-crystal semiconductor substrate (210) and the first single-crystal semiconductor substrate (110). This embodiment differs from the embodiment of FIG. 6 in that the second single-crystal semiconductor substrate (210) also includes a well region like the first single-crystal semiconductor substrate (110), and pixel transistors constituting the pixel circuit unit (800) are formed, and the pixel circuit unit (800) electrically connecting the pixel transistors to each other is disposed on the second single-crystal semiconductor substrate (210). Hereinafter, redundant descriptions will be omitted and the differences will be mainly described.

[0266] The driving unit (100) may not have a pixel circuit unit (800) formed thereon, but may have other circuit units formed thereon, for example, a driving circuit unit (400), a gate driving unit (600), and a data driving unit (700). As illustrated in FIG. 22, the driving unit (100) may include a driving circuit unit (400), a gate driving unit (600), and a data driving unit (700) formed on a first single-crystal semiconductor substrate (110) and a plurality of first pads (PD1), and the display unit (200) may include a pixel circuit unit (800) disposed on a second single-crystal semiconductor substrate (210), second pads (PD2), and a display area (DAA) on which a plurality of pixels (PX) are disposed.

[0267] The display unit (200) may have a pixel circuit unit (800) and a display element layer (230) disposed on a second single-crystal semiconductor substrate (210). The pixel circuit unit (800) and the display element layer (230) may be sequentially laminated and electrically connected to each other on the second single-crystal semiconductor substrate (210). Accordingly, the display device (10_2) may include a connection wiring layer (220) that connects the pixel circuit unit (800) disposed on the second single-crystal semiconductor substrate (210) and the driving circuit layer (120) disposed on the driving unit (100).

[0268] In an exemplary embodiment, a connection wiring layer (220) may be disposed on a lower surface of a second single-crystal semiconductor substrate (210) and may be disposed between the second single-crystal semiconductor substrate (210) and the first single-crystal semiconductor substrate (110). The connection wiring layer (220) may include connection wirings (RML) of routing wirings (RM1, RM2), and conductive vias (RVA) of the routing wirings (RM1, RM2) may be disposed in through holes penetrating the second single-crystal semiconductor substrate (210).

[0269] The display unit (200) may be arranged so that the display area (DAA) and the pixel circuit units (800) overlap each other, and may include a through-hole area (PA) which is an area other than the display area (DAA), the pixel circuit unit (800), and the second pad area (PDA2). The through-hole area (PA) may be an area where terminals of routing wires (RM1, RM2) for electrically connecting the pixel circuit unit (800) and the driving circuit layer (120) of the driving unit (100) are arranged. Unlike the embodiment of FIG. 6, the light-emitting elements included in the pixels (PX) of the display unit (200) are electrically connected to the pixel circuit unit (800) on the second single-crystal semiconductor substrate (210), and therefore the routing wires (RM1, RM2) may electrically connect the driving circuit layer (120) of the driving unit (100) and the pixel circuit unit (800). Since the display device (10_2) includes routing wires (RM1, RM2) that form an electrical connection between the pixel circuit unit (800) and the driving circuit layer (120), the conductive vias (RVA) of the routing wires (RM1, RM2) can be placed in a through hole area (PA) located at the outer portion of the display area (DAA).

[0270] According to one embodiment, a plurality of through holes (SVA) formed in a second single-crystal semiconductor substrate (210) of a display unit (200) may be arranged so as not to overlap with a display area (DAA) of the second single-crystal semiconductor substrate (210), and may be formed in a through hole area (PA), which is an outer area of ​​a pixel circuit unit (800). Since the second single-crystal semiconductor substrate (210) has a larger area than the first single-crystal semiconductor substrate (110), and the display area (DAA) also has a larger area than the first single-crystal semiconductor substrate (110), the plurality of through holes (SVA) of the second single-crystal semiconductor substrate (210) may not overlap with the first single-crystal semiconductor substrate (110) in the thickness direction. The connecting wiring (RML) of the connecting wiring layer (220) is arranged so that the routing wiring (RM1, RM2) extends from the through hole area (PA) to the area overlapping the driving unit (100), so that at least a portion of it can overlap with the first single crystal semiconductor substrate (110) in the thickness direction.

[0271] Fig. 24 is a cross-sectional view showing a part of the driving unit of Fig. 22. Fig. 25 is a cross-sectional view showing a part of the display unit of Fig. 23.

[0272] Referring to FIGS. 24 and 25, in a display device (10_2) according to one embodiment, the pixel circuit unit (800) may not be disposed in the driver unit (100), but may be included in the second single-crystal semiconductor substrate (210). At least a portion of the pixel circuit unit (800) may be included in the second single-crystal semiconductor substrate (210). For example, at least a portion of the pixel circuit unit (800) may be disposed within the second single-crystal semiconductor substrate (210), and the remaining portion of the pixel circuit unit (800) may be disposed on the second single-crystal semiconductor substrate (210).

[0273] The pixel circuit unit (800) may include a plurality of conductive layers (ML1 to ML8) and a plurality of vias (VA1 to VA8) as described above with reference to FIG. 9. The pixel circuit unit (800) may include wirings electrically connected to a plurality of second transistors (PTR2) included in the second single-crystal semiconductor substrate (210). Since the arrangement structure and connection relationship thereof are the same as described above, a duplicate description will be omitted.

[0274] The driving unit (100) may include a plurality of first transistors (PTR1) included in a first single-crystal semiconductor substrate (110). At least a portion of each of the plurality of first transistors (PTR1) may be included in the first single-crystal semiconductor substrate (110). For example, at least a portion of each of the plurality of first transistors (PTR1) may be disposed within the first single-crystal semiconductor substrate (110), and the remaining portion of each of the plurality of first transistors (PTR1) may be partially disposed on the first single-crystal semiconductor substrate (110). For example, a source region (SA), a channel region (CH), and a drain region (DA) of the first transistor (PTR1) may be disposed within the first single-crystal semiconductor substrate (110), and a gate electrode (GE) of the first transistor (PTR1) may be disposed on the first single-crystal semiconductor substrate (110).

[0275] The first transistors (PTR1) may be CMOS transistors formed through a semiconductor process on a first wafer substrate. The plurality of first transistors (PTR1) may be transistors constituting a driving circuit unit (400), a gate driving unit (600), and a data driving unit (700) disposed in a driving unit (100). A driving circuit layer (120) including a plurality of first contact electrodes (CTE1), a first semiconductor insulating layer (SINS1), a first interlayer insulating layer (INS1), and a plurality of circuit conductive layers (CML) may be disposed on the first single-crystal semiconductor substrate (110). The driving circuit layer (120) may include wirings electrically connected to the plurality of first transistors (PTR1) included in the first single-crystal semiconductor substrate (110). The driving circuit unit (400), gate driving unit (600), and data driving unit (700) of the driving unit (100) can be formed through a plurality of first transistors (PTR1) and first contact electrodes (CTE1) and circuit conductive layers (CML) of the driving circuit layer (120).

[0276] The display unit (200) may include a plurality of second transistors (PTR2) formed on a second single-crystal semiconductor substrate (210). At least a portion of each of the plurality of second transistors (PTR2) may be included in the second single-crystal semiconductor substrate (210). For example, at least a portion of each of the plurality of second transistors (PTR2) may be disposed within the second single-crystal semiconductor substrate (210), and the remaining portion of each of the plurality of second transistors (PTR2) may be disposed on the single-crystal semiconductor substrate (210). For example, a source region (SA), a channel region (CH), and a drain region (DA) of the second transistor (PTR2) may be disposed within the second single-crystal semiconductor substrate (210), and a gate electrode (GE) of the second transistor (PTR2) may be disposed on the second single-crystal semiconductor substrate (210).

[0277] A plurality of second transistors (PTR2) may be transistors constituting a pixel circuit unit (800) arranged in a display unit (200). A plurality of second contact electrodes (CTE2), a second semiconductor insulating layer (SINS2), third to fifth interlayer insulating layers (INS3, INS4, INS5) and a plurality of conductive layers (ML1 to ML8) may be arranged on a second single-crystal semiconductor substrate (210). The pixel circuit unit (800) of the display unit (200) may be formed through a plurality of second transistors (PTR2), the second contact electrodes (CTE2) and a plurality of conductive layers (ML1 to ML8). The pixel circuit unit (800) may include wirings electrically connected to a plurality of second transistors (PTR2) included in the second single-crystal semiconductor substrate (210).

[0278] The connection wiring layer (220) may be arranged on the lower surface of the second single crystal semiconductor substrate (210). The connection wiring layer (220) may include a second interlayer insulating layer (INS2), a plurality of connection wirings (RML), and a portion of a conductive via (RVA). The description of the second interlayer insulating layer (INS2) and the connection wiring (RML) is the same as described above.

[0279] According to one embodiment, the display device (10_2) may include a plurality of through holes (SVA) penetrating the second single crystal semiconductor substrate (210) in the through hole area (PA) of the display unit (200). The through holes (SVA) may be formed to penetrate not only the second single crystal semiconductor substrate (210) but also third to fifth interlayer insulating layers (INS3, INS4, INS5) disposed thereon. The display unit (200) may include a connection pad (PIN) disposed in the through hole area (PA) and electrically connected to elements and wirings of the pixel circuit unit (800). The through holes (SVA) are formed to extend from the connection wiring (RML) of the connection wiring layer (220) to the connection pad (PIN), and conductive vias (RVA) of the routing wirings (RM1, RM2) may be disposed within the through holes (SVA). A connection pad (PIN) arranged on a display unit (200) can be electrically connected to a connection wiring (RML) through a conductive via (RVA). Output pins of circuit units can be formed on a driving circuit layer (120), and the conductive via (RVA) can be electrically connected by being bonded to the output pin. The pixel circuit unit (800) can be electrically connected to the driving circuit layer (120) of the driving unit (100) through a connection pad (PIN) and a routing wiring (RM) formed in a through-hole area (PA).

[0280] Meanwhile, the display device (10_2) may include a first transistor (PTR1) included in a first single-crystal semiconductor substrate (110) of the driving unit (100), and a second transistor (PTR2) included in a second single-crystal semiconductor substrate (210) of the display unit (200). At least a part of the first transistor (PTR1) may be disposed within the first single-crystal semiconductor substrate (110), and the remaining part of the first transistor (PTR1) may be disposed on the first single-crystal semiconductor substrate (110). At least a part of the second transistor (PTR2) may be disposed within the second single-crystal semiconductor substrate (210), and the remaining part of the second transistor (PTR2) may be disposed on the second single-crystal semiconductor substrate (110).

[0281] The first transistor (PTR1) and the second transistor (PTR2) are respectively disposed on different single-crystal semiconductor substrates (110, 210), and the wafer substrates on which the transistors (PTR1, PTR2) are formed in the manufacturing process of the display device (10_2) may also be different. According to one embodiment, the display device (10_2) may have different sizes and line widths, etc., of the first transistor (PTR1) formed on the first single-crystal semiconductor substrate (110) and the second transistor (PTR2) formed on the second single-crystal semiconductor substrate (210).

[0282] Fig. 26 is a cross-sectional view schematically showing the transistors of the driving unit and display unit of the display device of Fig. 21.

[0283] Referring to FIG. 23, in the display device (10_2), the minimum line width of the first transistor (PTR1) of the first single-crystal semiconductor substrate (110) may be smaller than the minimum line width of the second transistor (PTR2) of the second single-crystal semiconductor substrate (210). The semiconductor process performed on the first wafer substrate to form the first transistor (PTR1) is a process having a higher resolution than the semiconductor process performed on the second wafer substrate to form the second transistor (PTR2), and accordingly, the size of a device such as a manufactured transistor may be smaller. In other words, the semiconductor process performed on the first wafer substrate may be a finer process than the semiconductor process performed on the second wafer substrate.

[0284] As described above, the first single-crystal semiconductor substrate (110) of the driving unit (100) may have a smaller planar area than the second single-crystal semiconductor substrate (210) of the display unit (200), and small-sized elements may be arranged with a high degree of integration to reduce power consumption and improve manufacturing yield. On the other hand, the second single-crystal semiconductor substrate (210) of the display unit (200) may have a larger planar area than the first single-crystal semiconductor substrate (110), and the manufacturing process for forming the light-emitting element may require a lower resolution than the process for forming a fine element such as the first transistor (PTR1). The pixel circuit unit (800) arranged on the second single-crystal semiconductor substrate (210) may also secure a larger area than when formed on the first single-crystal semiconductor substrate (110), and the second transistors (PTR2) constituting the pixel circuit unit (800) may not require a high degree of integration. Accordingly, the semiconductor process performed on the first wafer substrate can be performed as a high-cost process with a small line width, and the semiconductor process performed on the second wafer substrate can be performed as a low-cost process with a relatively large line width.

[0285] The display device (10_2) may have a plurality of transistors (PTR1, PTR2) of the first single-crystal semiconductor substrate (110) and the second single-crystal semiconductor substrate (210) having different minimum line widths. In an exemplary embodiment, the plurality of transistors (PTR1, PTR2) may have different lengths of channel regions (CH), and the minimum line width or the length W1 of the channel region (CH) of the first transistor (PTR1) may be smaller than the minimum line width or the length W2 of the channel region (CH) of the second transistor (PTR2). The minimum line width or the length W1 of the channel region (CH) of the first transistor (PTR1) may be 100 nm or less, or in a range of 2 nm to 80 nm. The minimum line width or the length W2 of the channel region (CH) of the second transistor (PTR2) may be 100 nm or more, or in a range of 100 nm to 5 μm.

[0286] In the drawings, the minimum line widths of the transistors (PTR1, PTR2) are compared with the lengths (W1, W2) of the channel regions (CH), but this is not limited thereto. The minimum line widths of the transistors (PTR1, PTR2) may not be compared with the lengths (W1, W2) of the channel regions (CH), but may be compared with other configurations. For example, the minimum line widths of the transistors (PTR1, PTR2) may be compared with the wiring widths of the gate electrodes (GE) of the transistors (PTR1, PTR2). Alternatively, the minimum line widths of the transistors (PTR1, PTR2) may be the minimum line widths of the wiring of the gate electrodes (GE) of the transistors (PTR1, PTR2). In addition, in the drawings, the lengths (W1, W2) of the channel regions (CH) are depicted as the gaps between the source regions (SA) and the drain regions (DA) formed on the single crystal semiconductor substrates (110, 210), but this is not limited thereto.

[0287] The display device (10_2) can be formed with a high degree of integration on a small area first single crystal semiconductor substrate (110) by forming the circuit units formed in the driving unit (100) using a high-cost micro semiconductor process. The manufacturing process of the driving unit (100) can have a high yield per unit wafer substrate, and power consumption can also be reduced because the circuit elements (e.g., the first transistor) have a small size. The display device (10_2) can reduce the manufacturing cost by performing the circuit elements of the display element layer (230) and the pixel circuit unit (800) formed in the display unit (200) using a relatively low-cost semiconductor process. Nevertheless, since some of the circuit units for emitting light of the light-emitting elements of the display device (10_2) are arranged in the driving unit (100), there is still an advantage in that a high-resolution display device can be implemented.

[0288] Fig. 27 is a perspective view showing a head-mounted display device according to one embodiment. Fig. 28 is an exploded perspective view showing an example of the head-mounted display device of Fig. 27.

[0289] Referring to FIGS. 27 and 28, a head-mounted display device (1000) according to one embodiment includes a first display device (11), a second display device (12), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece lens (1210), a second eyepiece lens (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), a control circuit board (1600), and a connector.

[0290] The first display device (11) provides an image to the user's left eye, and the second display device (12) provides an image to the user's right eye. Since each of the first display device (11) and the second display device (12) is substantially the same as the display devices (10, 10_1, 10_2) described in conjunction with FIG. 1, descriptions of the first display device (11) and the second display device (12) are omitted.

[0291] The first optical member (1510) may be positioned between the first display device (11) and the first eyepiece lens (1210). The second optical member (1520) may be positioned between the second display device (12) and the second eyepiece lens (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0292] The middle frame (1400) is disposed between the first display device (11) and the control circuit board (1600), and may be disposed between the second display device (12) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (11), the second display device (12), and the control circuit board (1600).

[0293] A control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to a first display device (11) and a second display device (12) via connectors. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (11) and the second display device (12) via the connectors.

[0294] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (11) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (12). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (11) and the second display device (12).

[0295] The display device storage unit (1100) serves to store the first display device (11), the second display device (12), the middle frame (1400), the first optical member (1510), the second optical member (1520), the control circuit board (1600), and the connector. The storage unit cover (1200) is arranged to cover an open surface of the display device storage unit (1100). The storage unit cover (1200) may include a first eyepiece (1210) for placing the user's left eye and a second eyepiece (1220) for placing the user's right eye. In FIGS. 24 and 25, the first eyepiece (1210) and the second eyepiece (1220) are exemplified as being placed separately, but the present invention is not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0296] The first eyepiece (1210) can be aligned with the first display device (11) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (12) and the second optical member (1520). Accordingly, the user can view an image of the first display device (11) enlarged into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view an image of the second display device (12) enlarged into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0297] The head-mounted band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be positioned respectively for the user's left and right eyes. If the display device storage unit (1200) is implemented in a lightweight and compact form, the head-mounted display device (1000) may be equipped with a glasses frame as shown in FIG. 26 instead of the head-mounted band (1300).

[0298] In addition, the head-mounted display device (1000) may further include a battery for supplying power, an external memory slot for storing external memory, and an external connection port and wireless communication module for receiving a video source. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0299] FIG. 29 is a perspective view showing a head-mounted display device according to one embodiment.

[0300] Referring to FIG. 29, a head-mounted display device (1000_1) according to one embodiment may be a glasses-type display device in which a display device storage unit (1200_1) is implemented in a lightweight and compact manner. The head-mounted display device (1000_1) according to one embodiment may include a display device (13), a left-eye lens (1010), a right-eye lens (1020), a support frame (1030), eyeglass frame legs (1040, 1050), an optical member (1060), an optical path conversion member (1070), and a display device storage unit (1200_1).

[0301] The display device housing (1200_1) may include a display device (13), an optical member (1060), and an optical path conversion member (1070). An image displayed on the display device (13) may be magnified by the optical member (1060), and the optical path may be converted by the optical path conversion member (1070) to be provided to the user's right eye through the right eye lens (1020). As a result, the user may view an augmented reality image that is a combination of a virtual image displayed on the display device (13) through the right eye and a real image seen through the right eye lens (1020).

[0302] In Fig. 29, the display device storage unit (1200_1) is exemplified as being arranged at the right end of the support frame (1030), but is not limited thereto. For example, the display device storage unit (1200_1) may be arranged at the left end of the support frame (1030), in which case the image of the display device (13) may be provided to the user's left eye. Alternatively, the display device storage unit (1200_1) may be arranged at both the left end and the right end of the support frame (1030), in which case the user may view the image displayed on the display device (13) through both the left and right eyes.

[0303] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. A first single crystal semiconductor substrate including a plurality of first transistors; A second single-crystal semiconductor substrate disposed on the first single-crystal semiconductor substrate and including a plurality of second transistors; A light emitting element layer disposed on the second single crystal semiconductor substrate and including a plurality of light emitting elements, The first single crystal semiconductor substrate has a smaller area on a plane than the area on a plane of the second single crystal semiconductor substrate, A display device wherein the length of the minimum line width of any one of the first transistors is smaller than the length of the minimum line width of any one of the second transistors.

2. In paragraph 1, The minimum line width of any one of the above first transistors is less than 100 nm, A display device wherein the minimum line width of any one of the above second transistors is 100 nm or more.

3. In paragraph 1, A display device wherein the second single crystal semiconductor substrate includes a plurality of through holes spaced apart from each other and a plurality of conductive vias respectively arranged within the plurality of through holes.

4. In paragraph 3, A display device further comprising a connection wiring layer disposed between the first single crystal semiconductor substrate and the light emitting element layer and including a plurality of connection wirings each electrically connected to the plurality of conductive vias.

5. In paragraph 4, A display device in which the above-mentioned connection wiring layer is disposed between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate.

6. In paragraph 4, A display device in which the above plurality of through holes do not overlap with the first single crystal semiconductor substrate in the thickness direction.

7. In paragraph 7, A display device in which some of the above plurality of connecting wires overlap with the first single crystal semiconductor substrate in the thickness direction.

8. In paragraph 1, A display device in which the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate are each a silicon substrate or a silicon-germanium substrate, and each has a thickness of 100 μm or less.

9. In paragraph 1, The light-emitting element layer includes a plurality of reflective layers arranged between the second single crystal semiconductor substrate and the light-emitting element, and an interlayer insulating layer arranged between the reflective layer and the light-emitting element. A display device in which the plurality of reflective layers are respectively arranged to correspond to the plurality of light-emitting elements.

10. In paragraph 9, The light-emitting element includes a first light-emitting element arranged in a first light-emitting region that emits light of a first color, and a second light-emitting element arranged in a second light-emitting region that emits light of a second color different from the first color. A display device wherein the thickness of the interlayer insulating layer disposed between the first light-emitting element and the reflective layer overlapping the first light-emitting element is different from the thickness of the interlayer insulating layer disposed between the second light-emitting element and the reflective layer overlapping the second light-emitting element.

11. A first single crystal semiconductor substrate including a plurality of first transistors; A second single-crystal semiconductor substrate including a plurality of through-holes arranged on the first single-crystal semiconductor substrate and spaced apart from each other, and a plurality of conductive vias arranged within each of the plurality of through-holes; A light-emitting element layer disposed on the second single crystal semiconductor substrate and including a plurality of light-emitting elements; and A connection wiring layer including connection wirings electrically connected to each of the plurality of conductive vias, A display device wherein the area on a plane of the first single crystal semiconductor substrate is smaller than the area on a plane of the second single crystal semiconductor substrate.

12. In paragraph 11, The second single crystal semiconductor substrate includes a plurality of second transistors each electrically connected to the plurality of light emitting elements, A display device in which the above-mentioned connection wiring layer is disposed between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate.

13. In paragraph 12, A display device in which the above plurality of through holes do not overlap with the first single crystal semiconductor substrate in the thickness direction.

14. In paragraph 12, A display device in which some of the above plurality of connecting wires overlap with the first single crystal semiconductor substrate in the thickness direction.

15. In paragraph 11, The above first single crystal semiconductor substrate further includes a plurality of second transistors each electrically connected to the plurality of light emitting elements, A display device in which the above-mentioned connecting wiring layer is disposed between the first single crystal semiconductor substrate and the above-mentioned light emitting element layer.

16. In paragraph 15, A display device in which the above-mentioned connection wiring layer is disposed between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate.

17. In paragraph 16, A display device wherein at least some of the plurality of through holes do not overlap with the first single crystal semiconductor substrate in the thickness direction.

18. In paragraph 16, A display device wherein at least some of the plurality of connecting wires do not overlap with the first single crystal semiconductor substrate in the thickness direction.

19. In paragraph 15, A display device in which the above-mentioned connecting wiring layer is disposed between the second single crystal semiconductor substrate and the above-mentioned light emitting element layer.

20. In paragraph 19, A display device in which the above plurality of through holes overlap with the first single crystal semiconductor substrate in the thickness direction.

21. A first single crystal semiconductor substrate including a plurality of first transistors; A second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate; A light-emitting element layer disposed on the second single crystal semiconductor substrate and including a plurality of light-emitting elements; and A protective layer surrounding the first single crystal semiconductor substrate and partially in contact with the second single crystal semiconductor substrate, A display device in which the first single crystal semiconductor substrate has a smaller area on a plane than the area on a plane of the second single crystal semiconductor substrate.

22. In paragraph 21, A display device in which the side of the above protective layer is parallel to the side of the second single crystal semiconductor substrate.

23. In paragraph 21, A display device wherein the thickness of the protective layer is greater than or equal to the thickness of the first single crystal semiconductor substrate.

24. In paragraph 21, A display device in which the above protective layer is in contact with the lower surface of the first single crystal semiconductor substrate and the lower surface of the second single crystal semiconductor substrate, respectively.

25. In paragraph 21, The second single crystal semiconductor substrate includes a plurality of through holes spaced apart from each other, and a plurality of conductive vias respectively arranged within the plurality of through holes, A display device further comprising a connection wiring layer disposed between the first single crystal semiconductor substrate and the light emitting element layer and including a plurality of connection wirings each electrically connected to the plurality of conductive vias.

26. In paragraph 25, The above first single crystal semiconductor substrate further includes a plurality of second transistors each electrically connected to the light emitting elements, A display device wherein at least some of the plurality of connecting wires do not overlap with the first single crystal semiconductor substrate in the thickness direction.

27. In paragraph 26, A display device wherein each of the plurality of light-emitting elements is electrically connected to one of the plurality of second transistors through the connecting wires and the conductive vias.

28. In paragraph 25, The second single crystal semiconductor substrate includes a plurality of second transistors each electrically connected to the light emitting elements, A display device wherein the minimum line width of any one of the plurality of first transistors is smaller than the minimum line width of any one of the plurality of second transistors.

29. A step of preparing different first wafer substrates and second wafer substrates; A step of forming a plurality of first transistors on the first wafer substrate, forming a plurality of through holes penetrating the second wafer substrate on the second wafer substrate, and forming a plurality of conductive vias respectively disposed within the plurality of through holes; A step of dividing the first wafer substrate into a plurality of first single-crystal semiconductor substrates and attaching the first single-crystal semiconductor substrate to one surface of the second wafer substrate; A step of forming a planarizing layer covering the first surface of the second wafer substrate and the first single crystal semiconductor substrates attached to the first surface; A step of forming a light-emitting element layer including a plurality of light-emitting elements on the other side opposite to the one side of the second wafer substrate; and A method for manufacturing a display device, comprising the step of dividing the second wafer substrate into a plurality of second single-crystal semiconductor substrates having the light-emitting element layer formed on the other surface and the first single-crystal semiconductor substrate attached to one surface.

30. In paragraph 29, A method for manufacturing a display device, wherein the area on a plane of the first single crystal semiconductor substrate is smaller than the area on a plane of the second single crystal semiconductor substrate.

31. In paragraph 29, A method for manufacturing a display device, wherein in the process of forming the above-mentioned flattening layer, the area on the plane of the above-mentioned flattening layer is the same as the area on the plane of the above-mentioned second wafer substrate.

32. In paragraph 29, In the step of separating the second wafer substrate into the plurality of second single-crystal semiconductor substrates, the planarization layer is divided together with the second single-crystal semiconductor substrate to form a protective layer surrounding the first single-crystal semiconductor substrate, A method for manufacturing a display device, wherein a side of the protective layer in the display device is parallel to a side of the second single crystal semiconductor substrate.

33. In paragraph 29, Further comprising a step of forming a plurality of second transistors before forming the through holes in the second wafer substrate; A method for manufacturing a display device, wherein the minimum line width of any one of the first transistors is smaller than the minimum line width of any one of the second transistors.

34. In paragraph 33, The minimum line width of any one of the above first transistors is less than 100 nm, A method for manufacturing a display device, wherein the minimum line width of any one of the above second transistors is 100 nm or more.

35. In paragraph 29, A method for manufacturing a display device further comprising, before attaching the first single crystal semiconductor substrate to the second wafer substrate, a step of forming a connection wiring layer including connection wirings electrically connected to each of the plurality of conductive vias.

36. In paragraph 35, A method for manufacturing a display device, wherein the connecting wiring layer is formed on the one surface of the second single-crystal semiconductor substrate and is positioned between the second single-crystal semiconductor substrate and the first single-crystal semiconductor substrate.

37. In paragraph 35, A method for manufacturing a display device, wherein the connecting wiring layer is formed on the other surface of the second single-crystal semiconductor substrate and is positioned between the second single-crystal semiconductor substrate and the light-emitting element layer.

38. In paragraph 29, A method for manufacturing a display device, wherein the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate are each a silicon substrate or a silicon-germanium substrate, and each has a thickness of 100 ㎛ or less.

39. Multiple display devices; A display device storage unit in which the plurality of display devices are stored; and It includes an optical member that enlarges the display image of the plurality of display devices or converts the optical path, The display device comprises a first single crystal semiconductor substrate including a plurality of first transistors; A second single crystal semiconductor substrate including a plurality of through holes arranged on the first single crystal semiconductor substrate and spaced apart from each other and a plurality of conductive vias arranged within each of the plurality of through holes; and A light emitting element layer disposed on the second single crystal semiconductor substrate and including a plurality of light emitting elements, A head-mounted display device, wherein the area on a plane of the first single-crystal semiconductor substrate is smaller than the area on a plane of the second single-crystal semiconductor substrate.

40. In paragraph 39, A head-mounted display device, wherein the display device further includes a protective layer surrounding the first single-crystal semiconductor substrate and partially in contact with the second single-crystal semiconductor substrate.

41. In paragraph 39, A head-mounted display device, wherein the display device further includes a connection wiring layer including a plurality of connection wirings electrically connected to each of the plurality of conductive vias.

42. In paragraph 41, The second single crystal semiconductor substrate of the display device includes a plurality of second transistors each electrically connected to the plurality of light emitting elements, A head-mounted display device, wherein the above-mentioned connection wiring layer is disposed between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate.

43. In paragraph 42, The display device is a head-mounted display device, wherein the minimum line width of any one of the first transistors is smaller than the minimum line width of any one of the second transistors.

44. In paragraph 43, The minimum line width of any one of the above first transistors is less than 100 nm, A head-mounted display device, wherein the minimum line width of any one of the second transistors is 100 nm or more.

45. In paragraph 41, The first single crystal semiconductor substrate of the display device includes a plurality of second transistors each electrically connected to the plurality of light emitting elements, A head-mounted display device, wherein the above-mentioned connection wiring layer is disposed between the first single-crystal semiconductor substrate and the above-mentioned light-emitting element layer.

46. ​​In paragraph 45, The above-mentioned connecting wiring layer is arranged between the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate, A head-mounted display device wherein at least some of the plurality of through holes do not overlap with the first single-crystal semiconductor substrate in the thickness direction.

47. In paragraph 45, The above-mentioned connecting wiring layer is arranged between the second single crystal semiconductor substrate and the light emitting element layer, A head-mounted display device in which the plurality of through holes overlap with the first single crystal semiconductor substrate in the thickness direction.

48. In paragraph 39, The above display device is a head-mounted display device, wherein the first single-crystal semiconductor substrate and the second single-crystal semiconductor substrate are each a silicon substrate or a silicon-germanium substrate, and each has a thickness of 100 μm or less.

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