Semiconductor packaging structure and preparation method therefor

Abstract

The present invention provides a semiconductor packaging structure and a preparation method therefor. Cylindrical capacitors and three-dimensional inductors that are electrically connected are prepared on two sides of a redistribution layer, so that the power supply integrity of the packaging structure can be achieved, and the transmission distance between a chip and passive elements is shortened; the cylindrical capacitors and the three-dimensional inductors can be prepared in a small size of the packaging structure, and the capacitance and the inductance can be increased; by preparing a magnetic metal layer, three-dimensional magnetic core inductors can be constructed, so as to further increase the inductance; by bonding large-capacity passive elements on the side wall of the packaging structure, the capacitance and / or inductance of the packaging structure can be further increased; by providing heat dissipation members on the passive elements and / or forming dummy metal pumps between the chip and a third redistribution layer, the heat dissipation performance of the packaging structure can be improved; and by forming EMI shielding members between the three-dimensional inductors, electromagnetic shielding can be carried out, thereby improving the reliability and quality of the semiconductor packaging structure.

Description

Semiconductor packaging structure and preparation method thereof Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging and relates to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] 2.5D packaging technology enables the homogeneous or heterogeneous integration of multiple chips. In a 2.5D packaging structure, chips are interconnected via a through-silicon via (TSV) interposer, enabling high-density interconnection. The manufacturing process typically involves chip processing, ball placement, interconnection between the TSV interposer and the redistribution layer (RDL), bonding between the chip and passive components, and plastic encapsulation. Due to the long transmission distance between the chip and passive components, IR voltage drop often occurs, reducing electrical performance.

[0003] Existing solutions generally involve increasing the platform voltage source, for example, from 0.9V to 1.1V, to ensure electrical performance, but this approach increases the overall power consumption of the chip.

[0004] Therefore, it is necessary to provide a semiconductor packaging structure and a manufacturing method thereof.

[0005] Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor packaging structure and a preparation method thereof, so as to solve the problem of difficulty in effectively performing signal transmission in the prior art.

[0007] To achieve the above object, the present invention provides a method for preparing a semiconductor packaging structure, comprising the following steps:

[0008] Providing a supporting substrate, and forming a first encapsulation layer on the supporting substrate;

[0009] patterning the first packaging layer to form a groove in the first packaging layer;

[0010] forming a patterned capacitor metal layer, wherein the capacitor metal layer covers the groove and a portion of the surface of the first packaging layer;

[0011] forming a first redistribution layer, the first redistribution layer comprising a first dielectric layer and a first metal wiring layer, the first dielectric layer filling the trench, and the first metal wiring layer being electrically connected to the capacitor metal layer;

[0012] forming inductor metal pillars spaced apart on the first redistribution layer, the inductor metal pillars comprising a first end and an opposite second end, wherein the first end of the inductor metal pillar is electrically connected to the first metal wiring layer;

[0013] forming a second packaging layer covering the first redistribution layer on the first redistribution layer, wherein the second packaging layer encapsulates the inductor metal pillar and exposes the second end of the inductor metal pillar;

[0014] forming a second redistribution layer on the second packaging layer, the second redistribution layer comprising a second dielectric layer and a second metal wiring layer, wherein the second metal wiring layer is electrically connected to the second end of the inductor metal pillar, and the first metal wiring layer, the inductor metal pillar, the second metal wiring layer, and the second packaging layer are combined to form a three-dimensional inductor;

[0015] forming a metal bump on the second redistribution layer, wherein the metal bump is electrically connected to the second metal wiring layer;

[0016] The supporting substrate is removed and ground to remove the capacitor metal layer at the bottom of the trench, and the capacitor metal layer and the first dielectric layer at the sidewall of the trench are combined to form a cylindrical capacitor electrically connected to the three-dimensional inductor;

[0017] forming a third redistribution layer on the first packaging layer, wherein the third redistribution layer is electrically connected to the cylindrical capacitor;

[0018] A chip is bonded on the third redistribution layer, and the chip is electrically connected to the third redistribution layer.

[0019] Optionally, the method further includes forming a magnetic metal layer in the second packaging layer to form a three-dimensional magnetic core inductor; the method of forming the inductor metal column includes electroplating; the method of forming the magnetic metal layer includes electroplating.

[0020] Optionally, the method further includes bonding a passive component to the side wall of the semiconductor package structure, wherein both ends of the passive component are electrically connected to the second redistribution layer and the third redistribution layer respectively, and the passive component includes one or a combination of an inductor and a capacitor.

[0021] Optionally, a heat sink is bonded to the surface of the passive component.

[0022] Optionally, the method further includes forming a dummy metal bump between the chip and the third redistribution layer, and the dummy metal bump is connected to the passive component through a metal wiring layer in the third redistribution layer.

[0023] Optionally, the method further includes forming an EMI shielding member between the three-dimensional inductors; the EMI shielding member includes a plate-shaped EMI shielding member or a ring-shaped EMI shielding member.

[0024] The present invention further provides a semiconductor package structure, comprising:

[0025] a first encapsulation layer, wherein the first encapsulation layer has a groove penetrating the first encapsulation layer;

[0026] a capacitor metal layer, wherein the capacitor metal layer covers the sidewalls of the trench and a portion of the surface of the first packaging layer;

[0027] a first rewiring layer, the first rewiring layer comprising a first dielectric layer and a first metal wiring layer, the first dielectric layer filling the trench, the first metal wiring layer being electrically connected to the capacitor metal layer, and the capacitor metal layer and the first dielectric layer being combined to form a cylindrical capacitor;

[0028] Inductor metal pillars are arranged at intervals, each of the inductor metal pillars includes a first end and an opposite second end, and the first end of the inductor metal pillar is electrically connected to the first metal wiring layer;

[0029] a second packaging layer, the second packaging layer covering the first re-distribution layer, encapsulating the inductor metal column and exposing the second end of the inductor metal column;

[0030] a second redistribution layer, the second redistribution layer being located on the second packaging layer and comprising a second dielectric layer and a second metal wiring layer, wherein the second metal wiring layer is electrically connected to the second end of the inductor metal column, and the first metal wiring layer, the inductor metal column, the second metal wiring layer, and the second packaging layer are combined to form a three-dimensional inductor, and the three-dimensional inductor is electrically connected to the cylindrical capacitor;

[0031] a metal bump, the metal bump being located on the second redistribution layer and electrically connected to the second metal wiring layer;

[0032] a third redistribution layer, the third redistribution layer being located on the first packaging layer and electrically connected to the cylindrical capacitor;

[0033] A chip is located on the third redistribution layer and is electrically connected to the third redistribution layer.

[0034] Optionally, the second packaging layer further includes a magnetic metal layer to form a three-dimensional magnetic core inductor.

[0035] Optionally, a passive element is further included on the side wall of the semiconductor package structure, with two ends of the passive element electrically connected to the second redistribution layer and the third redistribution layer respectively, and the passive element includes one or a combination of an inductor and a capacitor.

[0036] Optionally, a heat sink is further provided on the surface of the passive component.

[0037] Optionally, a dummy metal bump is further included between the chip and the third redistribution layer, and the dummy metal bump is connected to the passive component through the metal wiring layer in the third redistribution layer.

[0038] Optionally, an EMI shielding member located between the three-dimensional inductors is further included; the EMI shielding member includes a plate-shaped EMI shielding member or a ring-shaped EMI shielding member.

[0039] As described above, the semiconductor packaging structure and preparation method of the present invention prepare electrically connected cylindrical capacitors and three-dimensional inductors on both sides of the rewiring layer, which can achieve the power integrity of the packaging structure and shorten the transmission distance between the chip and the passive components; cylindrical capacitors and three-dimensional inductors can be prepared in a smaller packaging structure size, and the capacitance and inductance can be improved; through the preparation of the magnetic metal layer, a three-dimensional magnetic core inductor can be constructed to further improve the inductance; by bonding large-capacity passive components on the side walls of the packaging structure, the capacitance and / or inductance of the packaging structure can be further expanded; by arranging heat sinks on the passive components and / or forming virtual metal bumps between the chip and the third rewiring layer, the heat dissipation performance of the packaging structure can be improved; by forming EMI shielding components between the three-dimensional inductors, electromagnetic shielding can be performed, thereby improving the reliability and quality of the semiconductor packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a flow chart showing a process for preparing a semiconductor package structure according to an embodiment of the present invention.

[0041] FIG. 2 is a schematic diagram showing a structure after forming a first encapsulation layer in an embodiment of the present invention.

[0042] FIG. 3 is a schematic diagram showing a structure after grooves are formed in an embodiment of the present invention.

[0043] FIG. 4 is a schematic structural diagram showing a structure after a patterned capacitor metal layer is formed according to an embodiment of the present invention.

[0044] FIG. 5 is a schematic structural diagram showing a structure after forming a first redistribution layer according to an embodiment of the present invention.

[0045] FIG. 6 is a schematic structural diagram showing the structure after forming the inductor metal pillar and the magnetic metal layer according to an embodiment of the present invention.

[0046] FIG. 7 is a schematic diagram showing a structure after forming a second redistribution layer and metal bumps according to an embodiment of the present invention.

[0047] FIG8 is a schematic diagram showing the three-dimensional structure of the three-dimensional magnetic core inductor in area A of FIG7 .

[0048] FIG9 is a schematic diagram showing the structure after the support substrate is removed and polishing is performed in an embodiment of the present invention.

[0049] FIG. 10 is a schematic diagram showing a top view of the cylindrical capacitor in area B in FIG. 9 .

[0050] FIG. 11 is a schematic structural diagram showing a structure after a third redistribution layer is formed according to an embodiment of the present invention.

[0051] FIG12 is a schematic diagram showing the structure of the chip after bonding in an embodiment of the present invention.

[0052] FIG. 13 is a schematic structural diagram of a semiconductor package structure having passive components and dummy metal bumps formed in an embodiment of the present invention.

[0053] FIG. 14 is a schematic structural diagram of a semiconductor package structure having a plate-shaped EMI shielding member formed in an embodiment of the present invention.

[0054] FIG. 15 is a schematic structural diagram of a semiconductor package structure having an annular EMI shielding member formed in accordance with an embodiment of the present invention.

[0055] Explanation of component numbers 100 - supporting substrate; 200 - separation layer; 310 - first packaging layer; 320 - second packaging layer; 311 - groove; 400 - capacitor metal layer; 510 - first redistribution layer; 511 - first dielectric layer; 512 - first metal wiring layer; 520 - second redistribution layer; 521 - second dielectric layer; 522 - second metal wiring layer; 530 - third redistribution layer; 531 - third dielectric layer; 532 - third metal wiring layer; 600 - inductor metal column; 700 - magnetic metal layer; 800 - C4 metal bump; 900 - chip; 111 - metal bump; 112 - dummy metal bump; 120 - passive component; 130 - heat sink; 141 - plate-shaped EMI shield; 142 - annular EMI shield. DETAILED DESCRIPTION

[0056] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0058] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "over," and the like may be used herein to describe the relationship of one element or feature to other elements or features illustrated in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0059] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0060] As shown in FIG1 , this embodiment provides a method for preparing a semiconductor package structure, comprising the following steps:

[0061] S1: providing a supporting substrate, and forming a first encapsulation layer on the supporting substrate;

[0062] S2: patterning the first packaging layer to form a groove in the first packaging layer;

[0063] S3: forming a patterned capacitor metal layer, wherein the capacitor metal layer covers the groove and a portion of the surface of the first packaging layer;

[0064] S4: forming a first redistribution layer, the first redistribution layer comprising a first dielectric layer and a first metal wiring layer, the first dielectric layer filling the trench, and the first metal wiring layer being electrically connected to the capacitor metal layer;

[0065] S5: forming inductor metal pillars spaced apart on the first redistribution layer, wherein the inductor metal pillars include a first end and an opposite second end, and the first end of the inductor metal pillars is electrically connected to the first metal wiring layer;

[0066] S6: forming a second packaging layer on the first redistribution layer to cover the first redistribution layer, wherein the second packaging layer encapsulates the inductor metal pillar and exposes the second end of the inductor metal pillar;

[0067] S7: forming a second redistribution layer on the second packaging layer, wherein the second redistribution layer includes a second dielectric layer and a second metal wiring layer, and the second metal wiring layer is electrically connected to the second end of the inductor metal pillar, and the first metal wiring layer, the inductor metal pillar, the second metal wiring layer, and the second packaging layer are combined to form a three-dimensional inductor;

[0068] S8: forming a metal bump on the second redistribution layer, wherein the metal bump is electrically connected to the second metal wiring layer;

[0069] S9: removing the supporting substrate and performing grinding to remove the capacitor metal layer at the bottom of the trench, and combining the capacitor metal layer and the first dielectric layer at the sidewall of the trench to form a cylindrical capacitor electrically connected to the three-dimensional inductor;

[0070] S10: forming a third redistribution layer on the first packaging layer, wherein the third redistribution layer is electrically connected to the cylindrical capacitor;

[0071] S11: bonding a chip on the third redistribution layer, and electrically connecting the chip to the third redistribution layer.

[0072] The method for preparing the semiconductor packaging structure in this embodiment prepares the electrically connected cylindrical capacitor and the three-dimensional inductor on both sides of the first rewiring layer, which can achieve the power integrity of the packaging structure and shorten the transmission distance between the chip and the cylindrical capacitor and the three-dimensional inductor; the cylindrical capacitor and the three-dimensional inductor can be prepared in a smaller packaging structure size, and the capacitance and inductance can be increased.

[0073] The following further describes the preparation of the semiconductor packaging structure in conjunction with FIG. 2 to FIG. 15 , as follows:

[0074] First, referring to FIG. 1 and FIG. 2 , step S1 is performed to provide a support substrate 100 , and to form a first encapsulation layer 310 on the support substrate 100 .

[0075] Specifically, the support substrate 100 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so as to provide support for subsequent processes through the support substrate 100. The size of the support substrate 100 is not limited here, and is preferably wafer-level.

[0076] The method of forming the first encapsulation layer 310 includes but is not limited to compression molding, transfer molding and spin coating. The material of the first encapsulation layer 310 includes but is not limited to epoxy resin and polyamide, and may also be other suitable materials.

[0077] To facilitate the subsequent removal of the supporting substrate 100, in this embodiment, a separation layer 200 is preferably formed between the supporting substrate 100 and the first packaging layer 310. The separation layer 200 includes but is not limited to a tape and a polymer layer. For example, the separation layer 200 may optionally use a photothermal conversion layer so that the separation layer 200 can be subsequently heated by a laser or the like to separate the supporting substrate 100 from the first packaging layer 310, thereby improving operational convenience.

[0078] Next, referring to FIG. 1 and FIG. 3 , step S2 is performed to pattern the first encapsulation layer 310 to form a trench 311 in the first encapsulation layer 310 .

[0079] The size of the groove 311 can be selected according to the requirements of the cylindrical capacitor to be prepared subsequently, and is not overly limited here.

[0080] As an example, a method of patterning the first packaging layer 310 includes but is not limited to mechanical grooving or laser grooving, which can be selected according to needs.

[0081] Next, referring to FIG. 1 and FIG. 4 , step S3 is performed to form a patterned capacitor metal layer 400 . The capacitor metal layer 400 covers the groove 311 and a portion of the surface of the first packaging layer 310 .

[0082] Specifically, a metal seed layer (not shown) can be first formed on the surface of the groove 311 and the first packaging layer 310 by a sputtering method, and then a metal layer can be formed on the metal seed layer by an electroplating method, and then patterned by photolithography and etching to form the capacitor metal layer 400, wherein a portion of the capacitor metal layer 400 located on the surface of the first packaging layer 310 serves as the electrical lead-out end of the cylindrical capacitor to facilitate subsequent electrical connection.

[0083] The material of the capacitor metal layer 400 includes but is not limited to copper, and can be selected according to specific needs and is not limited here. The thickness and height of the capacitor metal layer 400 are not limited here.

[0084] Next, referring to Figures 1 and 5, step S4 is performed to form a first rewiring layer 510, wherein the first rewiring layer 510 includes a first dielectric layer 511 and a first metal wiring layer 512, wherein the first dielectric layer 511 fills the groove 311, and the first metal wiring layer 512 is electrically connected to the capacitor metal layer 400.

[0085] Specifically, the first dielectric layer 511 located within and filling the trench 311 serves as the capacitor dielectric of the cylindrical capacitor. The first dielectric layer 511 may be made of, for example, silicon oxide, silicon nitride, fluorine-containing glass, PI, PBO, and BCB, or a combination thereof. The first metal wiring layer 512 may be made of, for example, copper, aluminum, nickel, gold, and silver, or a combination thereof. The material, number of wiring layers, and wiring distribution of the first rewiring layer 510 are not limited herein and may be selected as needed.

[0086] 1 and 6 , step S5 is performed to form spaced apart inductor metal pillars 600 on the first redistribution layer 510 . The inductor metal pillars 600 include a first end and an opposite second end, and the first end of the inductor metal pillars 600 is electrically connected to the first metal wiring layer 512 .

[0087] As an example, a method of forming the inductor metal pillar 600 includes but is not limited to electroplating, and a material of the inductor metal pillar 600 includes but is not limited to copper.

[0088] Furthermore, the step of forming a magnetic metal layer 700 can be included, so that the magnetic metal layer 700 can be combined to form a three-dimensional magnetic core inductor such as area A in Figures 7 and 8, using the magnetic metal layer 700 as a magnetic core to increase electromagnetic flux. The method of forming the magnetic metal layer 700 includes, but is not limited to, electroplating, and the material of the magnetic metal layer 700 includes, but is not limited to, nickel, zinc, etc.

[0089] The order of forming the inductor metal pillar 600 and the magnetic metal layer 700 is not limited here and can be selected according to needs.

[0090] 1 and 7 , step S6 is performed to form a second packaging layer 320 covering the first redistribution layer 510 on the first redistribution layer 510 . The second packaging layer 320 encapsulates the inductor metal pillar 600 and exposes the second end of the inductor metal pillar 600 .

[0091] Specifically, methods for forming the second encapsulation layer 320 include but are not limited to compression molding, transfer molding, and spin coating. The material of the second encapsulation layer 320 includes but is not limited to epoxy resin and polyamide, and may also be other suitable materials.

[0092] Preferably, after forming the second packaging layer 320 , a grinding process such as CMP is used to expose the second end of the inductor metal pillar 600 and provide the second packaging layer 320 with a relatively flat surface to facilitate subsequent processes.

[0093] Next, referring to Figures 1 and 7, step S7 is performed to form a second redistribution layer 520 on the second packaging layer 320. The second redistribution layer 520 includes a second dielectric layer 521 and a second metal wiring layer 522, and the second metal wiring layer 522 is electrically connected to the second end of the inductor metal column 600. The first metal wiring layer 512, the inductor metal column 600, the second metal wiring layer 522 and the second packaging layer 320 are combined to form a three-dimensional inductor.

[0094] Specifically, the second dielectric layer 521 can be made of, for example, silicon oxide, silicon nitride, fluorine-containing glass, PI, PBO, and BCB, or a combination thereof. The second metal wiring layer 522 can include, for example, copper, aluminum, nickel, gold, and silver, or a combination thereof. The material, number of wiring layers, and wiring distribution of the second rewiring layer 520 are not limited herein and can be selected as needed.

[0095] Referring to FIG8 , a schematic diagram of the three-dimensional structure of the three-dimensional magnetic core inductor in area A of FIG7 is shown. As can be seen from FIG8 , the first metal wiring layer 512 is electrically connected to the first end of the inductor metal pillar 600, and the second metal wiring layer 522 is electrically connected to the second end of the inductor metal pillar 600. In addition, the inductor metal pillar 600, in combination with the first metal wiring layer 512 and the second metal wiring layer 522, forms an interconnected metal path, thereby forming a three-dimensional inductor after being combined with the second packaging layer 320.

[0096] Next, referring to FIG. 1 and FIG. 7 , step S8 is performed to form metal bumps on the second redistribution layer 520 . The metal bumps are electrically connected to the second metal wiring layer 522 .

[0097] Specifically, as shown in FIG7 , in this embodiment, the metal bumps on the second redistribution layer 520 are C4 metal bumps 800 . The preparation of the C4 metal bumps 800 is not limited here, and reference may be made to the existing preparation of the C4 metal bumps 800 .

[0098] Next, referring to Figures 1, 9 and 10, step S9 is performed to remove the supporting substrate 100 and perform grinding to remove the capacitor metal layer 400 located at the bottom of the groove 311, and combine the capacitor metal layer 400 located on the side wall of the groove 311 and the first dielectric layer 511 to form a cylindrical capacitor electrically connected to the three-dimensional inductor.

[0099] Specifically, the grinding method may adopt a CMP process, but is not limited thereto. Referring to FIG. 10 , after the capacitor metal layer 400 at the bottom of the groove 311 is removed by grinding, the cylindrical capacitor electrically connected to the three-dimensional magnetic core inductor can be formed, wherein the capacitor metal layer 400 serves as the electrode plate of the cylindrical capacitor, and the first dielectric layer 511 serves as the capacitor dielectric of the cylindrical capacitor.

[0100] Next, referring to FIG. 1 and FIG. 11 , step S10 is performed to form a third redistribution layer 530 on the first packaging layer 310 . The third redistribution layer 530 is electrically connected to the cylindrical capacitor.

[0101] Specifically, the third redistribution layer 530 is composed of a third dielectric layer 531 and a third metal wiring layer 532. The third dielectric layer 531 can be made of, for example, silicon oxide, silicon nitride, fluorine-containing glass, PI, PBO, and BCB, or a combination thereof. The third metal wiring layer 532 can be made of, for example, copper, aluminum, nickel, gold, and silver, or a combination thereof. The material, number of wiring layers, and wiring distribution of the third redistribution layer 530 are not limited herein and can be selected as needed.

[0102] Next, referring to FIG. 1 and FIG. 12 , step S11 is performed to bond a chip 900 on the third redistribution layer 530 , and the chip 900 is electrically connected to the third redistribution layer 530 .

[0103] Specifically, the chip 900 may be a logic chip, but is not limited thereto and may be selected according to specific needs. The chip 900 may be electrically connected to the third redistribution layer 530 via metal bumps 111 such as solder balls.

[0104] Furthermore, an underfill layer (not shown) may be formed between the chip 900 and the third rewiring layer 530 , so that the underfill layer can be used as a protection layer.

[0105] It is understandable that a cutting process step may also be included, such as mechanical cutting, to divide the wafer-level packaging structure into single small unit packaging structures, thereby completing the preparation of the semiconductor packaging structure.

[0106] Furthermore, as shown in Figure 13, it may also include a step of bonding a passive component 120 to the side wall of the prepared semiconductor packaging structure, where the two ends of the passive component 120 are electrically connected to the second rewiring layer 520 and the third rewiring layer 530 respectively, and the passive component 120 includes one or a combination of an inductor and a capacitor.

[0107] Specifically, as shown in FIG13 , by bonding the passive component 120, the semiconductor package structure's need for large-capacity capacitance and / or electromagnetic energy can be further met. Furthermore, after the passive component 120 is vertically electrically connected to the second rewiring layer 520 and the third rewiring layer 530, the space occupied by the passive component 120 can be reduced, thereby providing large-capacity capacitance and / or electromagnetic energy even in a small-size package. It is understood that, in order to achieve electrical connection of the passive component 120, metal parts for electrical connection to the passive component 120 can be reserved in advance when preparing the rewiring layer and the inductor metal pillar 600, and the specific details are not limited here.

[0108] Furthermore, in order to improve the heat dissipation capability, it is preferred that a heat sink 130 is bonded to the surface of the passive component 120 , wherein the heat sink 130 may be made of a thermally conductive adhesive made of a non-metallic material.

[0109] Furthermore, it may also include a step of forming a virtual metal bump 112 between the chip 900 and the third rewiring layer 530, and the virtual metal bump 112 is connected to the passive component 120 through the third metal wiring layer 532 in the third rewiring layer 530, so as to improve the heat dissipation capacity of the chip 900 through the heat sink 130 on the surface of the passive component 120.

[0110] The dummy metal bumps 112 may be prepared when the metal bumps 111 are prepared, but are not limited thereto. For example, they may also be formed by photolithography, electroplating, and etching.

[0111] Furthermore, the method may further include forming an EMI shielding member between the three-dimensional inductors, wherein the EMI shielding member may include a plate-shaped EMI shielding member 141 as shown in FIG. 14 , or a ring-shaped EMI shielding member 142 as shown in FIG. 15 .

[0112] Specifically, the EMI shielding component prevents the 3D inductor from external interference and external magnetic fields from interfering with its normal operation, thereby enhancing reliability and improving product quality. The EMI shielding component can be prepared as needed during the production of the 3D inductor, and the preparation steps are not detailed here.

[0113] As shown in Figure 12, this embodiment also provides a semiconductor packaging structure, which includes a first packaging layer 310, a capacitor metal layer 400, a first redistribution layer 510, an inductor metal column 600, a second packaging layer 320, a second redistribution layer 520, a metal bump, a third redistribution layer 530 and a chip 900.

[0114] The semiconductor packaging structure in this embodiment is directly prepared using the above-mentioned preparation process, so the materials, structure, etc. of the semiconductor packaging structure can be referred to the above content and will not be elaborated here. Of course, according to needs, the semiconductor packaging structure can also be prepared using other preparation processes.

[0115] Furthermore, referring to FIG. 12 , the second packaging layer 320 may further include a magnetic metal layer 700 to form a three-dimensional magnetic core inductor to increase the inductance.

[0116] Furthermore, as shown in Figure 13, it may also include a passive component 120 located on the side wall of the semiconductor packaging structure, and the two ends of the passive component 120 are electrically connected to the second rewiring layer 520 and the third rewiring layer 530 respectively. The passive component 120 may include one or a combination of inductors and capacitors to further meet the semiconductor packaging structure's requirements for large-capacity capacitance and / or electromagnetic quantities.

[0117] Furthermore, as shown in FIG13 , a heat sink 130 may be provided on the surface of the passive component 120 to improve heat dissipation capability.

[0118] Furthermore, as shown in Figure 13, it may also include a virtual metal bump 112 located between the chip 900 and the third rewiring layer 530, and the virtual metal bump 112 is connected to the passive component 120 through the third metal wiring layer 532 in the third rewiring layer 530, so as to improve the heat dissipation capacity of the chip 900 through the heat sink 130 on the surface of the passive component 120.

[0119] Furthermore, an EMI shielding member may be included between the three-dimensional inductors to prevent the three-dimensional inductors from being interfered with by the outside world and to prevent the external magnetic field from interfering with the normal operation of the three-dimensional inductors, thereby enhancing reliability and improving product quality.

[0120] The EMI shielding member may include a plate-shaped EMI shielding member 141 as shown in FIG. 14 , or a ring-shaped EMI shielding member 142 as shown in FIG. 15 .

[0121] In summary, the semiconductor packaging structure and preparation method of the present invention prepare electrically connected cylindrical capacitors and three-dimensional inductors on both sides of the rewiring layer, which can achieve the power integrity of the packaging structure and shorten the transmission distance between the chip and the passive components; cylindrical capacitors and three-dimensional inductors can be prepared in a smaller packaging structure size, and the capacitance and inductance can be improved; through the preparation of the magnetic metal layer, a three-dimensional magnetic core inductor can be constructed to further improve the inductance; by bonding large-capacity passive components on the side walls of the packaging structure, the capacitance and / or inductance of the packaging structure can be further expanded; by arranging a heat sink on the passive component and / or forming a virtual metal bump between the chip and the third rewiring layer, the heat dissipation performance of the packaging structure can be improved; by forming an EMI shielding component between the three-dimensional inductors, electromagnetic shielding can be performed, thereby improving the reliability and quality of the semiconductor packaging structure.

[0122] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor packaging structure, characterized in that: The following steps are involved: Providing a supporting substrate, and forming a first encapsulation layer on the supporting substrate; Patterning the first packaging layer to form a groove in the first packaging layer; forming a patterned capacitor metal layer, wherein the capacitor metal layer covers the groove and a portion of the surface of the first packaging layer; forming a first rewiring layer, wherein the first rewiring layer comprises a first dielectric layer and a first metal wiring layer, wherein the first dielectric layer fills the groove, and the first metal wiring layer is electrically connected to the capacitor metal layer; forming inductor metal pillars spaced apart on the first rewiring layer, wherein the inductor metal pillars include a first end and an opposite second end, and the first end of the inductor metal pillars is electrically connected to the first metal wiring layer; forming a second packaging layer covering the first re-distribution layer on the first re-distribution layer, wherein the second packaging layer encapsulates the inductor metal column and exposes the second end of the inductor metal column; Forming a second rewiring layer on the second packaging layer, wherein the second rewiring layer includes a second dielectric layer and a second metal wiring layer, and the second metal wiring layer is electrically connected to the second end of the inductor metal column, and the first metal wiring layer, the inductor metal column, the second metal wiring layer and the second packaging layer are combined to form a three-dimensional inductor; forming a metal bump on the second rewiring layer, wherein the metal bump is electrically connected to the second metal wiring layer; The support substrate is removed and ground to remove the capacitor metal layer at the bottom of the groove, and the capacitor metal layer and the first dielectric layer at the sidewall of the groove are combined to form a cylindrical capacitor electrically connected to the three-dimensional inductor; forming a third rewiring layer on the first packaging layer, wherein the third rewiring layer is electrically connected to the cylindrical capacitor; A chip is bonded on the third rewiring layer, and the chip is electrically connected to the third rewiring layer.

2. The method for preparing a semiconductor package structure according to claim 1, wherein: The method also includes the step of forming a magnetic metal layer in the second packaging layer to form a three-dimensional magnetic core inductor; the method of forming the inductor metal column includes electroplating; the method of forming the magnetic metal layer includes electroplating.

3. The method for preparing a semiconductor package structure according to claim 1, wherein: The method further includes bonding a passive component to the side wall of the semiconductor packaging structure, wherein two ends of the passive component are electrically connected to the second rewiring layer and the third rewiring layer respectively, and the passive component includes one or a combination of an inductor and a capacitor.

4. The method for preparing a semiconductor package structure according to claim 3, wherein: A heat sink is also bonded to the surface of the passive component.

5. The method for preparing a semiconductor packaging structure according to claim 4, wherein: The method further includes forming a dummy metal bump between the chip and the third rewiring layer, and the dummy metal bump is connected to the passive component through the metal wiring layer in the third rewiring layer.

6. The method for preparing a semiconductor package structure according to claim 1, wherein: The method further includes the step of forming an EMI shielding member between the three-dimensional inductors; the EMI shielding member includes a plate-shaped EMI shielding member or a ring-shaped EMI shielding member.

7. A semiconductor packaging structure, characterized in that: The semiconductor packaging structure comprises: A first encapsulation layer, wherein the first encapsulation layer has a groove penetrating the first encapsulation layer; A capacitor metal layer, wherein the capacitor metal layer covers the sidewall of the groove and a portion of the surface of the first packaging layer; A first rewiring layer, wherein the first rewiring layer includes a first dielectric layer and a first metal wiring layer, wherein the first dielectric layer fills the groove, and the first metal wiring layer is electrically connected to the capacitor metal layer, and the capacitor metal layer and the first dielectric layer are combined to form a cylindrical capacitor; Inductor metal pillars are arranged at intervals, wherein the inductor metal pillars include a first end and an opposite second end, and the first end of the inductor metal pillar is electrically connected to the first metal wiring layer; a second packaging layer, the second packaging layer covers the first rewiring layer, encapsulates the inductor metal column and exposes the second end of the inductor metal column; A second rewiring layer, the second rewiring layer is located on the second packaging layer, and includes a second dielectric layer and a second metal wiring layer, and the second metal wiring layer is electrically connected to the second end of the inductor metal column, and the first metal wiring layer, the inductor metal column, the second metal wiring layer and the second packaging layer are combined to form a three-dimensional inductor, and the three-dimensional inductor is electrically connected to the cylindrical capacitor; a metal bump, the metal bump being located on the second rewiring layer and electrically connected to the second metal wiring layer; a third rewiring layer, the third rewiring layer being located on the first packaging layer and electrically connected to the cylindrical capacitor; A chip is located on the third rewiring layer and is electrically connected to the third rewiring layer.

8. The semiconductor package structure according to claim 7, wherein: The second packaging layer also has a magnetic metal layer to form a three-dimensional magnetic core inductor.

9. The semiconductor package structure according to claim 7, wherein: It also includes a passive component located on the side wall of the semiconductor packaging structure, wherein two ends of the passive component are electrically connected to the second rewiring layer and the third rewiring layer respectively, and the passive component includes one or a combination of an inductor and a capacitor.

10. The semiconductor package structure according to claim 9, wherein: The surface of the passive component also has a heat sink.

11. The semiconductor package structure according to claim 10, wherein: It also includes a virtual metal bump located between the chip and the third rewiring layer, and the virtual metal bump is connected to the passive component through the metal wiring layer in the third rewiring layer.

12. The semiconductor package structure according to claim 7, wherein: The invention also comprises an EMI shielding component located between the three-dimensional inductors; the EMI shielding component comprises a plate-shaped EMI shielding component or a ring-shaped EMI shielding component.

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