Scanning driving circuit and display panel

Abstract

The present invention relates to the field of display panels, and provides a scanning driving circuit and a display panel. The scanning driving circuit comprises multiple stages of shift register unit and a timing controller, wherein each stage of shift register unit comprises 10 or 11 transistors and two capacitors, and the timing controller comprises three timing control signal lines. According to the scanning driving circuit and the display panel of the present invention, by providing a new shift register unit circuit and increasing the number of components, under the conditions of process fluctuations in the display panel, power signal noise in an integrated circuit, a long-term operation and the like, the stability of an output signal waveform of the shift register units is enhanced, the tolerance of the shift register unit circuit is improved, and the reliability of the display panel is increased.

Description

Scan driving circuit and display panel Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a scan drive circuit and a display panel. Background Art

[0002] The display panel includes a pixel array and a scanning drive circuit and a light-emitting drive circuit that control the pixel array. The display panel adopts a row-by-row scanning display mode, wherein the scanning drive circuit is used to generate a scanning signal to turn on each row of pixels in sequence.

[0003] The scan drive circuit includes a plurality of cascaded shift register units, wherein the circuit of each shift register unit is usually mainly composed of several transistors. By inputting a clock signal and a start pulse signal into the circuit, a scan signal is output at the output end.

[0004] U.S. Patent No. 10019930B2 provides a scanning circuit. Figure 1 shows a circuit diagram of a prior art shift register unit. As shown in Figure 1, this circuit has a limited number of components and, when the output terminal VOUT is high, not all voltage sources at the N1' node maintain a high level to turn off T8'. This results in a low tolerance and lack of reliability in conditions such as display panel process fluctuations, IC power supply signal noise, and long-term operation.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in this field.

[0006] Summary of the Invention

[0007] In view of this, the present invention provides a scan driving circuit and a display panel to at least solve the above problems.

[0008] One aspect of the present invention provides a scan driving circuit, comprising a multi-stage shift register unit, wherein the shift register unit comprises:

[0009] a first transistor, wherein a first electrode of the first transistor is connected to the third node, a second electrode is connected to the signal input terminal, and a gate is connected to the third timing control terminal;

[0010] a second transistor, wherein a first electrode of the second transistor is connected to the first power supply, a second electrode is connected to the third node, and a gate is connected to the first timing control terminal;

[0011] a third transistor, wherein a first electrode of the third transistor is connected to the third timing control terminal, a second electrode of the third transistor is connected to the first node, and a gate of the third transistor is connected to the third node;

[0012] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third node, a second electrode of the fourth transistor is connected to the second node, and a gate of the fourth transistor is connected to the second power supply;

[0013] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply, and a gate of the fifth transistor is connected to the second timing control terminal;

[0014] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the fifth transistor, a second electrode of the sixth transistor is connected to the second node, and a gate of the sixth transistor is connected to the first node;

[0015] a seventh transistor, wherein a second electrode of the seventh transistor is connected to the second power supply, and a gate of the seventh transistor is connected to the first timing control terminal;

[0016] an eighth transistor, wherein a first electrode of the eighth transistor is connected to the first node, a second electrode of the eighth transistor is connected to the second power supply, and a gate of the eighth transistor is connected to the third timing control terminal;

[0017] a ninth transistor, wherein a first electrode of the ninth transistor is connected to the first power supply, a second electrode of the ninth transistor is connected to the signal output terminal, and a gate of the ninth transistor is connected to the first node;

[0018] a tenth transistor, wherein a first electrode of the tenth transistor is connected to the signal output terminal, a second electrode of the tenth transistor is connected to the second timing control terminal, and a gate of the tenth transistor is connected to the second node;

[0019] a first capacitor, wherein a first electrode of the first capacitor is connected to the first power supply, and a second electrode of the first capacitor is connected to the first node;

[0020] A second capacitor, wherein a first electrode of the second capacitor is connected to the second node, and a second electrode is connected to the signal output end.

[0021] In some embodiments, a first electrode of the seventh transistor is connected to the first node.

[0022] In some embodiments, the shift register unit further includes:

[0023] an eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the first node, a second electrode is connected to the first electrode of the seventh transistor, and a gate is connected to the first node.

[0024] In some embodiments, the scan driving circuit further includes a timing controller, and the timing controller includes a first timing control signal line, a second timing control signal line, and a third timing control signal line.

[0025] In some embodiments, the first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal; and the third timing control signal line is used to output a third timing control signal.

[0026] In some embodiments, the first timing control signal, the second timing control signal, and the third timing control signal are square wave signals with the same output frequency and a continuous low potential occupying 1 / 3 of a period.

[0027] In some embodiments, the shift register unit is used to delay the signal received from the signal input end under the control of the first timing control signal, the second timing control signal and the third timing control signal, and the processed signal is output by the signal output end.

[0028] In some embodiments, the shift register unit at the previous stage outputs a scan signal to the shift register unit at the next stage, and the shift register unit at the last stage outputs a scan signal.

[0029] In some embodiments, in the 3N-2 stage shift register unit, the first timing control terminal is connected to the first timing control signal line, the second timing control terminal is connected to the second timing control signal line, and the third timing control terminal is connected to the third timing control signal line, where N is a positive integer.

[0030] In some embodiments, in the 3N-1th level shift register unit, the first timing control terminal is connected to the third timing control signal line, the second timing control terminal is connected to the first timing control signal line, and the third timing control terminal is connected to the second timing control signal line, where N is a positive integer.

[0031] In some embodiments, in the 3N-th level shift register unit, the first timing control terminal is connected to the second timing control signal line, the second timing control terminal is connected to the third timing control signal line, and the third timing control terminal is connected to the first timing control signal line, where N is a positive integer.

[0032] In some embodiments, the first to eleventh transistors are all P-type MOS transistors.

[0033] Another aspect of the present invention further provides a display panel, comprising any one of the above-mentioned scan driving circuits.

[0034] The beneficial effects of the present invention compared with the prior art include at least:

[0035] The scan drive circuit and display panel of the present invention provide a new shift register unit circuit to increase the number of components. This enhances the stability of the shift register unit output signal waveform under conditions such as display panel process fluctuations, integrated circuit power supply signal noise, and long-term operation, thereby improving the tolerance of the shift register unit circuit and increasing the reliability of the display panel.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are incorporated into and constitute a part of this specification, illustrate embodiments consistent with the present invention, and together with the description, serve to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0038] FIG1 shows a circuit diagram of a shift register unit in the prior art;

[0039] FIG2 is a schematic diagram showing a display panel of the present invention;

[0040] FIG3 shows a schematic diagram of the cascade connection of the scan driving circuit of the present invention;

[0041] FIG4 shows a circuit diagram of a shift register unit according to a first embodiment of the present invention;

[0042] FIG5 shows a waveform diagram of the shift register unit shown in FIG4 when it is working;

[0043] FIG6 is a schematic diagram showing the conduction state of the shift register unit at stage t1 in FIG5 ;

[0044] FIG7 is a schematic diagram showing the conduction state of the shift register unit at stage t2 in FIG5 ;

[0045] FIG8 is a schematic diagram showing the conduction state of the shift register unit at stage t3 in FIG5 ;

[0046] FIG9 is a schematic diagram showing the conduction state of the shift register unit at stage t4 in FIG5 ;

[0047] FIG10 is a schematic diagram showing the conduction state of the shift register unit at stage t5 in FIG5 ;

[0048] FIG11 is a schematic diagram showing the conduction state of the shift register unit at stage t6 in FIG5 ;

[0049] FIG. 12 shows a circuit diagram of a shift register unit according to a second embodiment of the present invention.

[0050] Reference Signs: 10 display panel 11 display area 20 timing controller 30 scan driving circuit CKV1 first timing control signal line CKV2 second timing control signal line CKV3 third timing control signal line c1 first timing control terminal c2 second timing control terminal c3 third timing control terminal IN signal input terminal Gout signal output terminal T1 first transistor T2 second transistor T3 third transistor T4 fourth transistor T5 fifth transistor T6 sixth transistor T7 seventh transistor T8 eighth transistor T9 ninth transistor T10 tenth transistor T11 eleventh transistor C1 first capacitor C2 second capacitor VDD first power supply VEE second power supply N1 first node N2 second node N3 third node DETAILED DESCRIPTION

[0051] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Identical reference numerals in the figures represent identical or similar structures, and thus a repeated description thereof will be omitted.

[0052] The terms "first," "second," and similar terms used in the specific description do not denote any order, quantity, or importance, but are simply used to distinguish different components. Furthermore, in the description of the present invention, the terms "upper," "lower," and similar terms indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings. These terms are used solely for ease of description and do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0053] It should be noted that, in the absence of conflict, the embodiments of the present invention and features in different embodiments may be combined with each other.

[0054] Through careful and in-depth research, the inventors of this case have provided a solution to the problems existing in the prior art, namely the shift register circuit in Figure 1. As shown in Figures 2 to 4 and Figure 12, Figure 2 shows a schematic diagram of the display panel of the present invention; Figure 3 shows a cascade schematic diagram of the scan drive circuit of the present invention; Figure 4 shows a circuit diagram of the shift register unit of the first embodiment of the present invention; and Figure 12 shows a circuit diagram of the shift register unit of the second embodiment of the present invention. The present invention discloses a scan drive circuit 30 and a display panel 10. The scan drive circuit 30 includes a multi-stage shift register unit and a timing controller 20, wherein each stage of the shift register unit includes 10 or 11 transistors, 2 capacitors, a signal input terminal IN, a signal output terminal Gout, and three timing control terminals. The timing controller 20 includes three timing control signal lines. The scan drive circuit and display panel of the present invention provide a new shift register unit circuit to increase the number of components. This enhances the stability of the shift register unit output signal waveform under conditions such as display panel process fluctuations, integrated circuit power supply signal noise, and long-term operation, thereby improving the tolerance of the shift register unit circuit and increasing the reliability of the display panel.

[0055] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0056] As shown in FIG2 , the present invention provides a display panel 10 comprising a display area 11 and a non-display area. A scan driver circuit 30, a data driver, and a light-emitting driver circuit are located in the non-display area of ​​the display panel 10. The display area 11 includes an array of light-emitting pixels and pixel circuits. The light-emitting pixels emit light under the combined action of the scan driver circuit 30, the data driver, the light-emitting driver circuit, and the pixel circuits.

[0057] As shown in FIG. 2 and FIG. 3 , the present invention further provides a scan driving circuit 30 , which includes a multi-stage shift register unit and a timing controller 20 .

[0058] In some embodiments, as shown in Figures 4 and 12, the shift register unit includes 10 or 11 transistors, 2 capacitors, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, a second timing control terminal c2, and a third timing control terminal c3. Each stage of the shift register unit outputs a scan signal, which is input to a row of pixel circuits in the display area 11 of the display panel 10 to drive the pixels in that row to emit light. The previous stage of the shift register unit also outputs the scan signal to the signal input terminal IN of the next stage of the shift register unit as a start signal. Since the last stage of the shift register unit does not have a next stage, the scan signal it outputs is only input to the pixel circuit in that row.

[0059] Specifically, in FIG3 , five cascaded shift register units are used as an example. The signal input terminal IN1 of the first-stage shift register unit S1 inputs a start pulse signal STV as an input signal. The signal output terminal Gout1 of the first-stage shift register unit S1 outputs a scan signal as an input signal for the second-stage shift register unit S2. The signal output terminal Gout1 of the first-stage shift register unit S1 is connected to the signal input terminal IN2 of the second-stage shift register unit S2. The signal output terminal Gout2 of the second-stage shift register unit S2 outputs a scan signal as an input signal for the third-stage shift register unit S3. The signal output terminal Gout2 of the second-stage shift register unit S2 is connected to the signal input terminal IN3 of the third-stage shift register unit S3. The signal output terminal Gout3 of the third-stage shift register unit S3 outputs a scan signal as an input signal for the fourth-stage shift register unit S4. The signal output terminal Gout3 of the third-stage shift register unit S3 is connected to the signal input terminal IN4 of the fourth-stage shift register unit S4. The signal output terminal Gout4 of the fourth-stage shift register unit S4 outputs the scan signal as the input signal of the fifth-stage shift register unit S5. The signal output terminal Gout4 of the fourth-stage shift register unit S4 is connected to the signal input terminal IN5 of the fifth-stage shift register unit S5. The subsequent-stage shift register units are repeated in this way to form a scan driving circuit 30.

[0060] In some embodiments, as shown in FIG3 , the timing controller 20 includes a first timing control signal line CKV1, a second timing control signal line CKV2, and a third timing control signal line CKV3. The first timing control signal line CKV1 is used to output a first timing control signal. The second timing control signal line CKV2 is used to output a second timing control signal. The third timing control signal line CKV3 is used to output a third timing control signal. The first, second, and third timing control signals are square wave signals with the same output frequency and a continuous low voltage level occupying 1 / 3 of the period.

[0061] In some optional embodiments, with continued reference to FIG3 , further, in the 3N-2 stage shift register unit, the first timing control terminal c1 is connected to the first timing control signal line CKV1 for receiving the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKV2 for receiving the second timing control signal. The third timing control terminal c3 is connected to the third timing control signal line CKV3 for receiving the third timing control signal. Wherein, N is a positive integer. In the 3N-1 stage shift register unit, the first timing control terminal c1 is connected to the third timing control signal line CKV3 for receiving the third timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKV1 for receiving the first timing control signal. The third timing control terminal c3 is connected to the second timing control signal line CKV2 for receiving the second timing control signal. Wherein, N is a positive integer. In the 3N-stage shift register unit, the first timing control terminal c1 is connected to the second timing control signal line CKV2 for receiving the second timing control signal. The second timing control terminal c2 is connected to the third timing control signal line CKV3 for receiving the third timing control signal. The third timing control terminal c3 is connected to the first timing control signal line CKV1 for receiving the first timing control signal. Where N is a positive integer. Each stage of the shift register unit in the scan drive circuit 30 receives the three timing control signals according to the above rule.

[0062] In the first embodiment of the present invention, referring to Figures 4 to 11, Figure 5 shows a waveform diagram of the shift register unit shown in Figure 4 when it is working; Figure 6 shows a schematic diagram of the conduction state of the shift register unit in stage t1 of Figure 5; Figure 7 shows a schematic diagram of the conduction state of the shift register unit in stage t2 of Figure 5; Figure 8 shows a schematic diagram of the conduction state of the shift register unit in stage t3 of Figure 5; Figure 9 shows a schematic diagram of the conduction state of the shift register unit in stage t4 of Figure 5; Figure 10 shows a schematic diagram of the conduction state of the shift register unit in stage t5 of Figure 5; and Figure 11 shows a schematic diagram of the conduction state of the shift register unit in stage t6 of Figure 5.

[0063] As shown in FIG5 , the shift register unit of the first embodiment of the present invention includes first to tenth transistors T1 to T10, a first capacitor C1 and a second capacitor C2, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, and a second timing control terminal c2. The first transistor T1 has a first electrode connected to a third node N3, a second electrode connected to the signal input terminal IN, and a gate connected to the third timing control terminal c3. The second transistor T2 has a first electrode connected to a first power supply VDD, a second electrode connected to a third node N3, and a gate connected to the first timing control terminal c1. The third transistor T3 has a first electrode connected to the third timing control terminal c3, a second electrode connected to the first node N1, and a gate connected to the third node N3. The fourth transistor T4 has a first electrode connected to the third node N3, a second electrode connected to the second node N2, and a gate connected to the second power supply VEE. The fifth transistor T5 has a first electrode connected to the first power supply VDD, and a gate connected to the second timing control terminal c2. The sixth transistor T6 has a first electrode connected to the second electrode of the fifth transistor T5, a second electrode connected to the second node N2, and a gate connected to the first node N1. The seventh transistor T7 has a second electrode connected to the second power supply VEE, and a gate connected to the first timing control terminal c1. The eighth transistor T8 has a first electrode connected to the first node N1, a second electrode connected to the second power supply VEE, and a gate connected to the third timing control terminal c3. The ninth transistor T9 has a first electrode connected to the first power supply VDD, a second electrode connected to the signal output terminal Gout, and a gate connected to the first node N1. The tenth transistor T10 has a first electrode connected to the signal output terminal Gout, a second electrode connected to the second timing control terminal c2, and a gate connected to the second node N2. The first capacitor C1 has a first electrode connected to the first power supply VDD, and a second electrode connected to the first node N1. The second capacitor C2 has a first electrode connected to the second node N2, and a second electrode connected to the signal output terminal Gout. In particular, in this embodiment, the first electrode of the seventh transistor T7 is connected to the first node N1. The first power supply VDD provides a positive voltage signal, and the second power supply VEE provides a negative voltage signal.

[0064] In this embodiment, the first transistor T1 to the tenth transistor T10 are all P-type MOS transistors. The control terminal of the PMOS transistor is the gate, the first terminal is the source, and the second terminal is the drain, or the first terminal is the drain and the second terminal is the source. The on-state potential of the PMOS transistor is a low potential, and the off-state potential is a high potential. In other embodiments, those skilled in the art can easily modify the shift register unit provided by the present invention to be composed entirely of N-type MOS transistors or CMOS transistors.

[0065] In this embodiment, referring to FIG5 , the waveform diagram shown in FIG5 includes six processes: t1 to t6. In these six processes, the output signal of the signal output terminal Gout of the shift register unit completes a process from set to reset. It should be noted that, for ease of understanding, the high potential signal is represented by "H" and the low potential signal is represented by "L". The relationship between the input and output of the shift register unit in the above six processes is analyzed below in conjunction with the waveform diagram of FIG5 and the circuit diagram of FIG4:

[0066] During process t1, referring to Figures 5 and 6, the start pulse signal STV or the signal input terminal IN inputs a low potential, the first timing control signal line CKV1 inputs a high potential, the second timing control signal line CKV2 inputs a high potential, and the third timing control signal line CKV3 inputs a low potential. At this time, the second transistor T2 and the seventh transistor T7 are turned off by the high potential input from the first timing control signal line CKV1, while the first transistor T1 and the eighth transistor T8 are turned on by the low potential input from the third timing control signal line CKV3. The start pulse signal STV or the low potential input from the signal input terminal IN is written to the third node N3, turning on the third transistor T3. The fifth transistor T5 is turned off by the high potential input from the second timing control signal line CKV2. The fourth transistor T4 is turned on by the low potential input from the second power supply VEE and remains on throughout the process. Furthermore, the low potential input from the third timing control signal line CKV3 and the second power supply VEE is written to the first node N1. The start pulse signal STV or the low potential input from the signal input terminal IN is written to the second node N2. Thus, the ninth transistor T9 and the tenth transistor T10 are both turned on. Finally, the signal output terminal Gout outputs the high potential of the first power supply VDD and the second timing control signal line CKV2.

[0067] During process t2, referring to Figures 5 and 7, a high voltage is input to the start pulse signal STV or the signal input terminal IN, a high voltage is input to the first timing control signal line CKV1, a low voltage is input to the second timing control signal line CKV2, and a high voltage is input to the third timing control signal line CKV3. At this point, the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off by the high voltages input to the first and third timing control signal lines CKV1 and CKV3. The third node N3 maintains the low voltage level from the previous process, the third transistor T3 is turned on, the high voltage of the third timing control signal line CKV3 is written to the first node N1, and the sixth transistor T6 is turned off. The fourth transistor T4 is turned on by the low voltage of the second power supply VEE, and the low voltage of the third node N3 is written to the second node N2. Consequently, the high voltage of the first node N1 turns off the ninth transistor T9, and the low voltage of the second node N2 turns on the tenth transistor T10. Finally, the signal output terminal Gout outputs the low voltage of the second timing control signal line CKV2.

[0068] During process t3, referring to Figures 5 and 8, a high potential is input to the start pulse signal STV or the signal input terminal IN, a low potential is input to the first timing control signal line CKV1, a high potential is input to the second timing control signal line CKV2, and a high potential is input to the third timing control signal line CKV3. At this time, the high potentials input to the second and third timing control signal lines CKV2 and CKV3 turn off the first transistor T1, the third transistor T3, the fifth transistor T5, and the eighth transistor T8. The low potentials input to the first timing control signal line CKV1 and the second power supply VEE turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. Furthermore, the low potential of the second power supply VEE is written to the first node N1. The high potential of the first power supply VDD is written to the second node N2. Consequently, the low potential of the first node N1 turns on the ninth transistor T9, and the high potential of the second node N2 turns off the tenth transistor T10. Finally, the signal output terminal Gout outputs the high potential of the first power supply VDD.

[0069] During process t4, referring to Figures 5 and 9, the start pulse signal STV or the signal input terminal IN inputs a high potential, the first timing control signal line CKV1 inputs a high potential, the second timing control signal line CKV2 inputs a high potential, and the third timing control signal line CKV3 inputs a low potential. At this time, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned off by the high potential input from the first and second timing control signal lines CKV1 and CKV2. The first transistor T1, the fourth transistor T4, and the eighth transistor T8 are turned on by the low potential input from the third timing control signal line CKV3 and the second power supply VEE. Furthermore, the start pulse signal STV or the signal input terminal IN writes a high potential to the third node N3, turning off the third transistor T3. Furthermore, the low potential of the second power supply VEE is written to the first node N1. The high potential of the third node N3 is written to the second node N2. Consequently, the low potential of the first node N1 turns on the ninth transistor T9, and the high potential of the second node N2 turns off the tenth transistor T10. Finally, the signal output terminal Gout outputs a high potential from the first power supply VDD.

[0070] During process t5, referring to Figures 5 and 10, a high potential is input to the start pulse signal STV or the signal input terminal IN, a high potential is input to the first timing control signal line CKV1, a low potential is input to the second timing control signal line CKV2, and a high potential is input to the third timing control signal line CKV3. At this point, the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off by the high potentials input to the first timing control signal line CKV1 and the third timing control signal line CKV3. The third node N3 maintains the high potential from the previous process, and the third transistor T3 is turned off. The fifth transistor T5 is input to the low potential from the second timing control signal line CKV2. The first node N1 maintains the low potential from the previous process, and the sixth transistor T6 is turned on. The high potential of the first power supply VDD is written to the second node N2. As a result, the low potential of the first node N1 turns on the ninth transistor T9, and the high potential of the second node N2 turns off the tenth transistor T10. Ultimately, the signal output terminal Gout outputs the high potential of the first power supply VDD.

[0071] During process t6, referring to Figures 5 and 11, a high voltage is input to the start pulse signal STV or the signal input terminal IN, a low voltage is input to the first timing control signal line CKV1, a high voltage is input to the second timing control signal line CKV2, and a high voltage is input to the third timing control signal line CKV3. At this time, the high voltage input to the third timing control signal line CKV3 turns off the first transistor T1 and the eighth transistor T8. The low voltage input to the first timing control signal line CKV1 turns on the second transistor T2 and the seventh transistor T7. The high voltage input to the first timing control signal line CKV1 writes to the third node N3, turning off the third transistor T3. The high voltage input to the second timing control signal line CKV2 turns off the fifth transistor T5. The low voltage input to the second timing control signal line CKV2 turns off the fourth transistor T4. Furthermore, the low voltage input to the first node N1 writes to the second power supply VEE. The high voltage input to the second node N2 writes to the first power supply VDD. Consequently, the low voltage input to the first node N1 turns on the ninth transistor T9, and the high voltage input to the second node N2 turns off the tenth transistor T10. Finally, the signal output terminal Gout outputs the high potential of the first power supply VDD.

[0072] The shift register unit repeats the working steps from t4 to t5 after t6 until the next frame begins to be displayed, when the start pulse signal STV or the signal input terminal IN inputs a low potential and re-enters the next round of t1 process.

[0073] In this embodiment, the relationship between the input and output of the shift register unit is as follows: if the start pulse signal STV or the signal input terminal IN is at a low level in a certain process, then under the action of the first timing control signal line CKV1, the second timing control signal line CKV2, and the third timing control signal line CKV3, the signal output terminal Gout also outputs a low level in the next process. In other processes, the start pulse signal STV or the signal input terminal IN and the signal output terminal Gout both maintain a high level until the start pulse signal STV or the signal input terminal IN inputs a low level again, at which point the signal output terminal Gout outputs a low level again. This is equivalent to the shift register unit delaying the low-level signal from the start pulse signal STV or the signal input terminal IN and outputting it from the signal output terminal Gout.

[0074] In this embodiment, the 10T2C circuit of the shift register unit adds two transistors compared to the prior art, changes some wiring arrangements, and eliminates the N2' node in the prior art circuit. This ensures that when the output terminal VOUT of the N1' node outputs a high level, the voltage source maintains a high level, turning off the tenth transistor T10. This prevents potential drift and effectively provides a stable output signal waveform under conditions such as display panel process fluctuations, integrated circuit power supply signal noise, and long-term operation. This improves the tolerance of the shift register unit circuit and increases the reliability of the display panel.

[0075] In a second embodiment of the present invention, referring to Figures 2, 3, and 12, the shift register unit of this embodiment includes first to eleventh transistors T1 to T11, a first capacitor C1 and a second capacitor C2, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, and a second timing control terminal c2. In particular, the first electrode of the eleventh transistor T11 is connected to the first node N1, the second electrode is connected to the first electrode of the seventh transistor T7, and the gate is connected to the first node N1. The connection method of the other components is the same as that of the first embodiment of the present invention.

[0076] In this embodiment, the operation process of the shift register unit is also divided into six processes. During these six processes, the output signal of the signal output terminal Gout of the shift register unit completes a process from set to reset. The output result of this embodiment is the same as that of the first embodiment. In particular, in the third process of this embodiment, the first node N1 maintains the high potential at the previous moment, the ninth transistor T9 is in the off state, and the signal output terminal Gout maintains the high potential at the previous moment.

[0077] In this embodiment, the relationship between the input and output of the shift register unit is the same as that in the first embodiment, that is, the shift register unit delays the low-voltage signal from the start pulse signal STV or the signal input terminal IN and outputs it from the signal output terminal Gout.

[0078] In this embodiment, the 11T2C circuit of the shift register unit adds three transistors and changes some wiring settings compared to the prior art. The technical effects achieved are the same as those of the first embodiment and will not be repeated here.

[0079] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel 10 described above. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. The implementation of the display device can be referenced to the embodiments of the display panel 10 described above, and any repetitive details will not be repeated here.

[0080] The scan drive circuit and display panel of the present invention provide a new shift register unit circuit to increase the number of components. This enhances the stability of the shift register unit output signal waveform under conditions such as display panel process fluctuations, integrated circuit power supply signal noise, and long-term operation, thereby improving the tolerance of the shift register unit circuit and increasing the reliability of the display panel.

[0081] The above is a further detailed description of the present invention in conjunction with specific optional embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A scanning driving circuit, characterized in that: A multi-stage shift register unit is included, wherein the shift register unit includes: A first transistor, wherein a first electrode of the first transistor is connected to the third node, a second electrode is connected to the signal input terminal, and a gate is connected to the third timing control terminal; a second transistor, wherein a first electrode of the second transistor is connected to the first power supply, a second electrode is connected to the third node, and a gate is connected to the first timing control terminal; a third transistor, wherein a first electrode of the third transistor is connected to the third timing control terminal, a second electrode of the third transistor is connected to the first node, and a gate of the third transistor is connected to the third node; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third node, a second electrode of the fourth transistor is connected to the second node, and a gate of the fourth transistor is connected to a second power supply; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply, and a gate of the fifth transistor is connected to the second timing control terminal; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the fifth transistor, a second electrode of the sixth transistor is connected to the second node, and a gate of the sixth transistor is connected to the first node; a seventh transistor, wherein a second electrode of the seventh transistor is connected to the second power supply, and a gate of the seventh transistor is connected to the first timing control terminal; an eighth transistor, wherein a first electrode of the eighth transistor is connected to the first node, a second electrode of the eighth transistor is connected to the second power supply, and a gate of the eighth transistor is connected to the third timing control terminal; a ninth transistor, wherein a first electrode of the ninth transistor is connected to the first power supply, a second electrode of the ninth transistor is connected to the signal output terminal, and a gate of the ninth transistor is connected to the first node; a tenth transistor, wherein a first electrode of the tenth transistor is connected to the signal output terminal, a second electrode of the tenth transistor is connected to the second timing control terminal, and a gate of the tenth transistor is connected to the second node; A first capacitor, wherein a first electrode of the first capacitor is connected to the first power supply, and a second electrode of the first capacitor is connected to the first node; A second capacitor, wherein a first electrode of the second capacitor is connected to the second node, and a second electrode is connected to the signal output end.

2. The scanning driving circuit according to claim 1, characterized in that: A first electrode of the seventh transistor is connected to the first node.

3. The scanning driving circuit according to claim 1, characterized in that: The shift register unit also includes: An eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the first node, a second electrode of the eleventh transistor is connected to the first electrode of the seventh transistor, and a gate of the eleventh transistor is connected to the first node.

4. The scanning driving circuit according to claim 2 or 3, characterized in that: The system also includes a timing controller, which includes a first timing control signal line, a second timing control signal line and a third timing control signal line.

5. The scanning driving circuit according to claim 4, characterized in that: The first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal; and the third timing control signal line is used to output a third timing control signal.

6. The scanning driving circuit according to claim 5, characterized in that: The first timing control signal, the second timing control signal and the third timing control signal are square wave signals with the same output frequency and a continuous low potential occupying 1 / 3 of a period.

7. The scanning driving circuit according to claim 5, characterized in that: The shift register unit is used to perform delay processing on the signal received from the signal input end under the control of the first timing control signal, the second timing control signal and the third timing control signal, and the processed signal is output from the signal output end.

8. The scanning driving circuit according to claim 4, characterized in that: The shift register unit of the previous stage outputs a scan signal to the shift register unit of the next stage, and the shift register unit of the last stage outputs a scan signal.

9. The scanning driving circuit according to claim 5, characterized in that: In the 3N-2th level shift register unit, the first timing control terminal is connected to the first timing control signal line, the second timing control terminal is connected to the second timing control signal line, and the third timing control terminal is connected to the third timing control signal line, wherein N is a positive integer.

10. The scanning driving circuit according to claim 9, characterized in that: In the 3N-1th level shift register unit, the first timing control terminal is connected to the third timing control signal line, the second timing control terminal is connected to the first timing control signal line, and the third timing control terminal is connected to the second timing control signal line, wherein N is a positive integer.

11. The scanning driving circuit according to claim 10, characterized in that: In the 3Nth stage shift register unit, the first timing control terminal is connected to the second timing control signal line, the second timing control terminal is connected to the third timing control signal line, and the third timing control terminal is connected to the first timing control signal line, wherein N is a positive integer.

12. The scanning driving circuit according to claim 2 or 3, characterized in that: The first transistor to the eleventh transistor are all P-type MOS transistors.

13. A display panel, characterized in that: The invention comprises a scanning driving circuit according to any one of claims 1 to 12.

Images