Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprise a display area and a non-display area. The display area comprises: a plurality of subpixels and a plurality of control signal lines; each of the plurality of subpixels comprises a pixel circuit; each pixel circuit comprises: a light-emitting device (L), a driving transistor (M0), a data writing circuit (110) and a pixel control circuit; each driving transistor (M0) is separately coupled to a data writing circuit (110) and a pixel control circuit; a pixel circuit in at least one row of subpixels among the plurality of subpixels is coupled to one of the plurality of control signal lines; and control signal lines corresponding to at least two adjacent rows of subpixels are mutually coupled. The non-display area comprises: a drive control circuit, the drive control circuit comprising a plurality of shift register units, the mutually-coupled control signal lines being coupled to one of the plurality of shift register units, and the shift register units being configured to transmit signals to the pixel circuits via the control signal lines.

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on August 24, 2023, with application number 202311077017.2 and invention name "Display Panel and Display Device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] Light-emitting devices such as organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) offer advantages such as self-luminescence and low energy consumption, making them a hot topic in current display device application research. Display devices typically use pixel circuits to drive the light-emitting devices.

[0005] Summary of the Invention

[0006] The embodiment of the present disclosure provides a display panel, comprising: a display area and a non-display area;

[0007] The display area includes: a plurality of sub-pixels and a plurality of control signal lines, wherein each of the plurality of sub-pixels includes a pixel circuit, and the pixel circuit includes: a light-emitting device, a driving transistor, a data writing circuit, and a pixel control circuit; the driving transistor is coupled to the data writing circuit and the pixel control circuit, respectively, and the data writing circuit is configured to provide a data voltage at a data signal terminal to a gate of the driving transistor in response to a scan signal at a scan signal terminal; and the pixel control circuit is configured to control the driving transistor to generate a driving current for driving the light-emitting device to emit light;

[0008] The pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one control signal line among the plurality of control signal lines, and the control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to each other;

[0009] The non-display area includes: a driving control circuit, the driving control circuit includes a plurality of shift register units, mutually coupled control signal lines are coupled to one of the plurality of shift register units, and the shift register unit is configured to transmit a signal to the pixel circuit through the control signal line.

[0010] In some embodiments, the pixel circuit includes: a first light emitting control circuit, the first light emitting control circuit being coupled to the first electrode of the driving transistor, a first light emitting control signal terminal, and a first power supply terminal, the first light emitting control circuit being configured to provide a signal from the first power supply terminal to the first electrode of the driving transistor in response to a first light emitting control signal from the first light emitting control signal terminal;

[0011] The display area further includes: a plurality of first light emitting control signal lines, and a first light emitting control signal terminal of a pixel circuit in at least one row of sub-pixels among the plurality of sub-pixels is coupled to a first light emitting control signal line among the plurality of first light emitting control signal lines.

[0012] In some embodiments, the pixel control circuit includes the first light emitting control circuit, the drive control circuit includes: a first light emitting drive control circuit, the first light emitting drive control circuit includes a plurality of first light emitting shift register units, the shift register units include the first light emitting shift register unit, and the control signal line includes the first light emitting control signal line;

[0013] The first light emitting control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to each other and then coupled to one of the first light emitting shift register units among the plurality of first light emitting shift register units.

[0014] In some embodiments, the display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along a column direction of the sub-pixels, the plurality of first light-emitting shift register units include a plurality of first light-emitting register groups, the plurality of first light-emitting register groups correspond one-to-one to the plurality of display sub-areas, and the plurality of first light-emitting register groups are coupled to the first light-emitting control signal lines in the corresponding display sub-areas;

[0015] The multiple first light-emitting register groups correspond one-to-one to the multiple first light-emitting trigger signal terminals, and the input signal terminal of the first-stage first light-emitting shift register unit in the first light-emitting register group is coupled to the corresponding first light-emitting trigger signal terminal; or, the multiple first light-emitting register groups correspond to one first light-emitting trigger signal terminal, the input signal terminal of the first-stage first light-emitting shift register unit in the first first light-emitting register group of the multiple first light-emitting register groups is coupled to the first light-emitting trigger signal terminal, and the driving output terminal of the last-stage first light-emitting shift register unit of the upper first light-emitting register group of two adjacent first light-emitting register groups is coupled to the input signal terminal of the first-stage first light-emitting shift register unit of the next first light-emitting register group.

[0016] In some embodiments, the non-display area further includes: a second light emitting drive control circuit, the second light emitting drive control circuit including a plurality of second light emitting shift register units;

[0017] The first light emitting control signal line corresponding to the pixel circuit in each row of sub-pixels in the plurality of sub-pixels is coupled to one of the first light emitting shift register units among the plurality of second light emitting shift register units.

[0018] In some embodiments, the display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along a column direction of the sub-pixels, the plurality of second light-emitting shift register units include a plurality of second light-emitting register groups, the plurality of second light-emitting register groups correspond one-to-one to the plurality of display sub-areas, and the plurality of second light-emitting register groups are coupled to the first light-emitting control signal lines in the corresponding display sub-areas;

[0019] The multiple second light-emitting register groups correspond one-to-one to the multiple second light-emitting trigger signal terminals, and the input signal terminal of the first-stage second light-emitting shift register unit in the second light-emitting register group is coupled to the corresponding second light-emitting trigger signal terminal; or, the multiple second light-emitting register groups correspond to one second light-emitting trigger signal terminal, the input signal terminal of the first-stage second light-emitting shift register unit in the first second light-emitting register group of the multiple second light-emitting register groups is coupled to the second light-emitting trigger signal terminal, and the driving output terminal of the last-stage second light-emitting shift register unit of the upper second light-emitting register group of two adjacent second light-emitting register groups is coupled to the input signal terminal of the first-stage second light-emitting shift register unit of the next second light-emitting register group.

[0020] In some embodiments, the pixel circuit includes: a second light-emitting control circuit, the second light-emitting control circuit being coupled to the second electrode of the driving transistor, the light-emitting device, and a second light-emitting control signal terminal, the second light-emitting control circuit being configured to conduct the second electrode of the driving transistor and the light-emitting device in response to a second light-emitting control signal at the second light-emitting control signal terminal;

[0021] The display area further includes: a plurality of second light emitting control signal lines, and the second light emitting control signal terminals of the pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one second light emitting control signal line among the plurality of second light emitting control signal lines.

[0022] In some embodiments, the pixel control circuit includes the second light emitting control circuit, the drive control circuit includes: a third light emitting drive control circuit, the third light emitting drive control circuit includes a plurality of third light emitting shift register units, and the shift register units include the third light emitting shift register unit;

[0023] The control signal lines include the second light emitting control signal lines. The second light emitting control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to each other and then coupled to one of the third light emitting shift register units.

[0024] In some embodiments, the display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along a column direction of the sub-pixels, the plurality of third light-emitting shift register units include a plurality of third light-emitting register groups, the plurality of third light-emitting register groups correspond one-to-one to the plurality of display sub-areas, and the plurality of third light-emitting register groups are coupled to the second light-emitting control signal lines in the corresponding display sub-areas;

[0025] The multiple third light-emitting register groups correspond one-to-one to multiple third light-emitting trigger signal terminals, and the input signal terminal of the first-level third light-emitting shift register unit in the third light-emitting register group is coupled to the corresponding third light-emitting trigger signal terminal; or, the multiple third light-emitting register groups correspond to one third light-emitting trigger signal terminal, the input signal terminal of the first-level third light-emitting shift register unit in the first third light-emitting register group of the multiple third light-emitting register groups is coupled to the third light-emitting trigger signal terminal, and the driving output terminal of the last-level third light-emitting shift register unit of the upper third light-emitting register group of two adjacent third light-emitting register groups is coupled to the input signal terminal of the first-level third light-emitting shift register unit of the next third light-emitting register group.

[0026] In some embodiments, the non-display area further includes: a fourth light emitting drive control circuit, the fourth light emitting drive control circuit including a plurality of fourth light emitting shift register units;

[0027] The second light emitting control signal line corresponding to the pixel circuit in each row of sub-pixels in the plurality of sub-pixels is coupled to one of the fourth light emitting shift register units among the plurality of fourth light emitting shift register units.

[0028] In some embodiments, the display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along a column direction of the sub-pixels, the plurality of fourth light-emitting shift register units include a plurality of fourth light-emitting register groups, the plurality of fourth light-emitting register groups correspond one-to-one to the plurality of display sub-areas, and the plurality of fourth light-emitting register groups are coupled to the second light-emitting control signal lines in the corresponding display sub-areas;

[0029] The multiple fourth light-emitting register groups correspond one-to-one to the multiple fourth light-emitting trigger signal terminals, and the input signal terminal of the first-stage fourth light-emitting shift register unit in the fourth light-emitting register group is coupled to the corresponding fourth light-emitting trigger signal terminal; or, the multiple fourth light-emitting register groups correspond to one fourth light-emitting trigger signal terminal, the input signal terminal of the first-stage fourth light-emitting shift register unit in the first fourth light-emitting register group of the multiple fourth light-emitting register groups is coupled to the fourth light-emitting trigger signal terminal, and the driving output terminal of the last-stage fourth light-emitting shift register unit of the upper fourth light-emitting register group of two adjacent fourth light-emitting register groups is coupled to the input signal terminal of the first-stage fourth light-emitting shift register unit of the next fourth light-emitting register group.

[0030] In some embodiments, the pixel circuit includes: a first reset control circuit, the first reset control circuit being coupled to the gate of the driving transistor, a first reset control signal terminal, and a reference signal terminal, the first reset control circuit being configured to provide a signal at the reference signal terminal to the gate of the driving transistor in response to a first reset control signal at the first reset control signal terminal;

[0031] The display area further includes: a plurality of first reset control signal lines, and the first reset control signal terminals of the pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one of the plurality of first reset control signal lines.

[0032] In some embodiments, the pixel control circuit includes the first reset control circuit, and the drive control circuit includes: a first reset drive control circuit, the first reset drive control circuit includes a plurality of first reset shift register units, and the shift register units include the first reset shift register unit;

[0033] The control signal lines include the first reset control signal lines. The first reset control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to each other and then coupled to one of the plurality of first reset shift register units.

[0034] In some embodiments, the display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along a column direction of the sub-pixels, the plurality of first reset shift register units include a plurality of first reset register groups, the plurality of first reset register groups correspond one-to-one to the plurality of display sub-areas, and the plurality of first reset register groups are coupled to first reset control signal lines in corresponding display sub-areas;

[0035] The multiple first reset register groups correspond one-to-one to the multiple first reset trigger signal terminals, and the input signal terminal of the first-level first reset shift register unit in the first reset register group is coupled to the corresponding first reset trigger signal terminal; or, the multiple first reset register groups correspond to one first reset trigger signal terminal, the input signal terminal of the first-level first reset shift register unit in the first first reset register group of the multiple first reset register groups is coupled to the first reset register group, and the driving output terminal of the last-level first reset shift register unit of the previous first reset register group in two adjacent first reset register groups is coupled to the input signal terminal of the first-level first reset shift register unit of the next first reset register group.

[0036] In some embodiments, the non-display area further includes: a second reset drive control circuit, the second reset drive control circuit including a plurality of second reset shift register units;

[0037] The first reset control signal line corresponding to the pixel circuit in each row of sub-pixels in the plurality of sub-pixels is coupled to one of the first reset shift register units among the plurality of second reset shift register units.

[0038] In some embodiments, the display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along a column direction of the sub-pixels, the plurality of second reset shift register units include a plurality of second reset register groups, the plurality of second reset register groups correspond one-to-one to the plurality of display sub-areas, and the plurality of second reset register groups are coupled to the first reset control signal lines in the corresponding display sub-areas;

[0039] The multiple second reset register groups correspond one-to-one to the multiple second reset trigger signal terminals, and the input signal terminal of the first-level second reset shift register unit in the second reset register group is coupled to the corresponding second reset trigger signal terminal; or, the multiple second reset register groups correspond to one second reset trigger signal terminal, the input signal terminal of the first-level second reset shift register unit in the first second reset register group of the multiple second reset register groups is coupled to the second reset register group, and the driving output terminal of the last-level second reset shift register unit of the previous second reset register group in two adjacent second reset register groups is coupled to the input signal terminal of the first-level second reset shift register unit of the next second reset register group.

[0040] In some embodiments, the pixel circuit includes: a second reset control circuit, the second reset control circuit being coupled to the second electrode of the driving transistor, a second reset control signal terminal, and a first initialization signal terminal, the second reset control circuit being configured to provide a signal from the first initialization signal terminal to the second electrode of the driving transistor in response to a second reset control signal from the second reset control signal terminal;

[0041] The display area further includes: a plurality of second reset control signal lines, and the second reset control signal terminals of the pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one second reset control signal line among the plurality of second reset control signal lines.

[0042] In some embodiments, the pixel control circuit includes the second reset control circuit, the drive control circuit includes: a third reset drive control circuit, the third reset drive control circuit includes a plurality of third reset shift register units, and the shift register unit includes the third reset shift register unit;

[0043] The control signal lines include the second reset control signal lines. The second reset control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to each other and then coupled to one of the third reset shift register units.

[0044] In some embodiments, the display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along a column direction of the sub-pixels, the plurality of third reset shift register units include a plurality of third reset register groups, the plurality of third reset register groups correspond one-to-one to the plurality of display sub-areas, and the plurality of third reset register groups are coupled to the second reset control signal lines in the corresponding display sub-areas;

[0045] The multiple third reset register groups correspond one-to-one to multiple third reset trigger signal terminals, and the input signal terminal of the first-level third reset shift register unit in the third reset register group is coupled to the corresponding third reset trigger signal terminal; or, the multiple third reset register groups correspond to one third reset trigger signal terminal, the input signal terminal of the first-level third reset shift register unit in the first third reset register group of the multiple third reset register groups is coupled to the third reset register group, and the driving output terminal of the last-level third reset shift register unit of the previous third reset register group in two adjacent third reset register groups is coupled to the input signal terminal of the first-level third reset shift register unit of the next third reset register group.

[0046] In some embodiments, the non-display area further includes: a fourth reset drive control circuit, the fourth reset drive control circuit including a plurality of fourth reset shift register units;

[0047] The second reset control signal line corresponding to the pixel circuit in each row of sub-pixels in the plurality of sub-pixels is coupled to one of the plurality of fourth reset shift register units.

[0048] In some embodiments, the display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along a column direction of the sub-pixels, the plurality of fourth reset shift register units include a plurality of fourth reset register groups, the plurality of fourth reset register groups correspond one-to-one to the plurality of display sub-areas, and the plurality of fourth reset register groups are coupled to the second reset control signal lines in the corresponding display sub-areas;

[0049] The multiple fourth reset register groups correspond one-to-one to multiple fourth reset trigger signal terminals, and the input signal terminal of the first-level fourth reset shift register unit in the fourth reset register group is coupled to the corresponding fourth reset trigger signal terminal; or, the multiple fourth reset register groups correspond to one fourth reset trigger signal terminal, the input signal terminal of the first-level fourth reset shift register unit in the first fourth reset register group of the multiple fourth reset register groups is coupled to the fourth reset register group, and the driving output terminal of the last-level fourth reset shift register unit of the previous fourth reset register group in two adjacent fourth reset register groups is coupled to the input signal terminal of the first-level fourth reset shift register unit of the next fourth reset register group.

[0050] In some embodiments, the pixel circuit includes: a third reset control circuit, the third reset control circuit coupled to the light-emitting device, a third reset control signal terminal, and a second initialization signal terminal, the third reset control circuit configured to provide a signal from the second initialization signal terminal to the light-emitting device in response to a third reset control signal from the third reset control signal terminal;

[0051] The display area further includes: a plurality of third reset control signal lines, and the third reset control signal terminals of the pixel circuits in a row of sub-pixels among the plurality of sub-pixels are coupled to one third reset control signal line among the plurality of third reset control signal lines.

[0052] In some embodiments, the third reset control signal terminal and the second reset control signal terminal are connected to the same signal, and the third reset control signal line and the second reset control signal line are the same signal line.

[0053] In some embodiments, the pixel circuit further includes: at least one of a first capacitor and a second capacitor;

[0054] A first terminal of the first capacitor is coupled to the gate electrode of the driving transistor, and a second terminal of the first capacitor is coupled to the second electrode of the driving transistor;

[0055] A first terminal of the second capacitor is coupled to the second electrode of the driving transistor, and a second terminal of the second capacitor is coupled to a fixed voltage terminal.

[0056] In some embodiments, the light emitting device is further coupled to a second power supply terminal;

[0057] The fixed voltage terminal is connected to the same signal as one of the first power terminal, the reference signal terminal, the first initialization signal terminal, the second initialization signal terminal, and the second power terminal.

[0058] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] FIG1 is a schematic diagram of some structures of pixel circuits in an embodiment of the present disclosure;

[0060] FIG2 is a schematic diagram of some further structures of pixel circuits in an embodiment of the present disclosure;

[0061] FIG3 a is a schematic diagram of some further structures of the pixel circuit in the embodiment of the present disclosure;

[0062] FIG3 b is a timing diagram of some signals in an embodiment of the present disclosure;

[0063] FIG4 a is a schematic diagram of some further structures of the pixel circuit in the embodiment of the present disclosure;

[0064] FIG4 b is a timing diagram of some further signals in an embodiment of the present disclosure;

[0065] FIG5 a is a schematic diagram of some structures of a display panel in an embodiment of the present disclosure;

[0066] FIG5 b is a schematic diagram of some further structures of the display panel in the embodiment of the present disclosure;

[0067] FIG6 is a timing diagram of some further signals in an embodiment of the present disclosure;

[0068] FIG7 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0069] FIG8 a is a timing diagram of some further signals in an embodiment of the present disclosure;

[0070] FIG8b is a timing diagram of some further signals in an embodiment of the present disclosure;

[0071] FIG9a is a timing diagram of some further signals in an embodiment of the present disclosure;

[0072] FIG9 b is a timing diagram of some further signals in an embodiment of the present disclosure;

[0073] FIG10 a is a timing diagram of some further signals in an embodiment of the present disclosure;

[0074] FIG10 b is a timing diagram of some further signals in an embodiment of the present disclosure;

[0075] FIG11a is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0076] FIG11 b is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0077] FIG12 is a timing diagram of some further signals in an embodiment of the present disclosure;

[0078] FIG13a is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0079] FIG13 b is a schematic diagram of some further structures of the display panel in the embodiment of the present disclosure;

[0080] FIG14 is a timing diagram of some further signals in an embodiment of the present disclosure;

[0081] FIG15a is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0082] FIG15 b is a schematic diagram of some further structures of the display panel in the embodiment of the present disclosure;

[0083] FIG16 is a timing diagram of some further signals in an embodiment of the present disclosure;

[0084] FIG17a is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0085] FIG17 b is a schematic diagram of some further structures of the display panel in the embodiment of the present disclosure;

[0086] FIG18a is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0087] FIG18 b is a schematic diagram of some further structures of the display panel in the embodiment of the present disclosure;

[0088] FIG19a is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0089] FIG19 b is a schematic diagram of some further structures of the display panel in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0090] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0091] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "coupled" or "connected" are not limited to physical or mechanical coupling, but may include electrical coupling, whether direct or indirect.

[0092] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0093] In some embodiments of the present disclosure, the display device provided by the embodiments of the present disclosure may include a display panel. The display panel may include a display area and a non-display area (i.e., an area other than the area surrounded by the display area). The display area may include a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes sub-pixels of the same color or sub-pixels of multiple different colors. For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here. The following is an example of a pixel unit including a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0094] In some embodiments of the present disclosure, each sub-pixel may include a pixel circuit, which may include a driving transistor M0 and a light-emitting device L. The driving transistor M0 generates a driving current to drive the light-emitting device L to emit light, thereby enabling the display panel to realize the function of displaying a picture.

[0095] For example, as shown in FIG1 , the pixel circuit includes a light-emitting device L, and the cathode of the light-emitting device L can be coupled to the second power supply terminal ELVSS. For example, the light-emitting device L can be an electroluminescent diode. For example, the light-emitting device L can include at least one of a micro light-emitting diode (Micro LED), an organic light-emitting diode (OLED), and a quantum dot light-emitting diode (QLED). In actual applications, the specific structure of the light-emitting device can be designed and determined according to the actual application environment, and is not limited here.

[0096] For example, as shown in FIG1 , the pixel circuit includes a data write circuit 110 configured to provide a data voltage at a data signal terminal DA to the gate of a driving transistor M0 in response to a scan signal at a scan signal terminal GA. Furthermore, the display area includes a plurality of scan signal lines GAL. A row of sub-pixels in the plurality of sub-pixels corresponds to one of the plurality of scan signal lines GAL, and the scan signal terminals GA of the data write circuits 110 in the row of sub-pixels are coupled to the corresponding scan signal line GAL.

[0097] For example, as shown in FIG1 , the pixel circuit includes a first emission control circuit 120 coupled to a first electrode of the driving transistor M0. The first emission control circuit 120 is configured to provide a signal from a first power supply terminal ELVDD to the first electrode of the driving transistor M0 in response to a first emission control signal from a first emission control signal terminal EM1. Furthermore, the display area further includes a plurality of first emission control signal lines EML1. The first emission control signal terminal EM1 of the pixel circuit in a row of sub-pixels among the plurality of sub-pixels is coupled to one of the plurality of first emission control signal lines EML1.

[0098] For example, as shown in FIG1 , the pixel circuit includes a second light-emitting control circuit 130, which is coupled to the second electrode of the driving transistor M0 and the light-emitting device L. The second light-emitting control circuit 130 is configured to conduct electricity between the second electrode of the driving transistor M0 and the light-emitting device L in response to a second light-emitting control signal at a second light-emitting control signal terminal EM2. Furthermore, the display area further includes a plurality of second light-emitting control signal lines EML2, wherein the second light-emitting control signal terminal EM2 of the pixel circuit in a row of sub-pixels among the plurality of sub-pixels is coupled to one of the plurality of second light-emitting control signal lines EML2.

[0099] For example, as shown in FIG1 , the pixel circuit includes a first reset control circuit 140 coupled to the gate of the driving transistor M0. The first reset control circuit 140 is configured to provide a signal from a reference signal terminal VREF to the gate of the driving transistor M0 in response to a first reset control signal from a first reset control signal terminal RE1. Furthermore, the display area further includes a plurality of first reset control signal lines REL1, wherein the first reset control signal terminal RE1 of the pixel circuits in a row of sub-pixels among the plurality of sub-pixels is coupled to one of the plurality of first reset control signal lines REL1.

[0100] For example, as shown in FIG1 , the pixel circuit includes a second reset control circuit 150 coupled to the second electrode of the driving transistor M0. The second reset control circuit 150 is configured to provide a signal from the first initialization signal terminal VINT1 to the second electrode of the driving transistor M0 in response to a second reset control signal from the second reset control signal terminal RE2. Furthermore, the display area further includes a plurality of second reset control signal lines REL2, wherein the second reset control signal terminal RE2 of the pixel circuits in a row of sub-pixels among the plurality of sub-pixels is coupled to one of the plurality of second reset control signal lines REL2.

[0101] For example, as shown in FIG1 , the pixel circuit includes a third reset control circuit 160 coupled to the light-emitting device L. The third reset control circuit 160 is configured to provide the signal of the second initialization signal terminal VINT2 to the light-emitting device L in response to a third reset control signal at a third reset control signal terminal RE3. Furthermore, the display area further includes a plurality of third reset control signal lines REL3, wherein the third reset control signal terminal RE3 of the pixel circuits in a row of sub-pixels among the plurality of sub-pixels is coupled to one of the plurality of third reset control signal lines REL3.

[0102] For example, as shown in FIG1 , the pixel circuit further includes: a first capacitor C1 and a second capacitor C2, wherein a first end of the first capacitor C1 is coupled to the gate of the driving transistor M0, a second end of the first capacitor C1 is coupled to the second electrode of the driving transistor M0, a first end of the second capacitor C2 is coupled to the second electrode of the driving transistor M0, and a second end of the second capacitor C2 is coupled to the fixed voltage terminal VG. For example, the fixed voltage terminal VG can be connected to the same signal as the first power supply terminal ELVDD. Of course, the fixed voltage terminal VG can also be connected to the same signal as one of the reference signal terminal VREF, the first initialization signal terminal, the second initialization signal terminal, and the second power supply terminal ELVSS, which is not limited here.

[0103] In some embodiments of the present disclosure, the first power supply terminal ELVDD can be configured to load a constant first power supply voltage, which is generally a positive value. Furthermore, the second power supply terminal ELVSS can be configured to load a constant second power supply voltage, which is generally a ground voltage or a negative value. In actual applications, the specific values ​​of the first power supply voltage and the second power supply voltage can be designed and determined based on the actual application environment and are not limited here.

[0104] In some embodiments of the present disclosure, as shown in FIG1 , the driving transistor M0 can be configured as an N-type transistor; wherein the first electrode of the driving transistor M0 can be its drain, the second electrode of the driving transistor M0 can be its source, and when the driving transistor M0 is in a saturated state, current flows from the drain of the driving transistor M0 to its source. Of course, the driving transistor M0 can also be configured as a P-type transistor, which is not limited here.

[0105] Exemplarily, as shown in FIG2 , the data write circuit 110 includes: a data write transistor M1, a gate of the data write transistor M1 coupled to the scan signal terminal GA, a first electrode of the data write transistor M1 coupled to the data signal terminal DA, and a second electrode of the data write transistor M1 coupled to the gate of the drive transistor M0.

[0106] Exemplarily, as shown in FIG2 , the first light-emitting control circuit 120 includes: a first light-emitting control transistor M2, a gate of the first light-emitting control transistor M2 coupled to the first light-emitting control signal terminal EM1, a first electrode of the first light-emitting control transistor M2 coupled to the first power supply terminal ELVDD, and a second electrode of the first light-emitting control transistor M2 coupled to the first electrode of the driving transistor M0.

[0107] Exemplarily, as shown in Figure 2, the second light-emitting control circuit 130 includes: a second light-emitting control transistor M3, the gate of the second light-emitting control transistor M3 is coupled to the second light-emitting control signal terminal EM2, the first electrode of the second light-emitting control transistor M3 is coupled to the second electrode of the driving transistor M0, and the second electrode of the first light-emitting control transistor M2 is coupled to the anode of the light-emitting device L.

[0108] Exemplarily, as shown in FIG2 , the first reset control circuit 140 includes: a first reset control transistor M4, a gate of the first reset control transistor M4 coupled to the first reset control signal terminal RE1, a first electrode of the first reset control transistor M4 coupled to the reference signal terminal VREF, and a second electrode of the first reset control transistor M4 coupled to the gate of the driving transistor M0.

[0109] Exemplarily, as shown in Figure 2, the second reset control circuit 150 includes: a second reset control transistor M5, the gate of the second reset control transistor M5 is coupled to the second reset control signal terminal RE2, the first electrode of the second reset control transistor M5 is coupled to the first initialization signal terminal, and the second electrode of the second reset control transistor M5 is coupled to the second electrode of the driving transistor M0.

[0110] Illustratively, as shown in FIG2 , the third reset control circuit 160 includes: a third reset control transistor M6, a gate of the third reset control transistor M6 coupled to the third reset control signal terminal RE3, a first electrode of the third reset control transistor M6 coupled to the second initialization signal terminal, and a second electrode of the third reset control transistor M6 coupled to the anode of the light-emitting device L.

[0111] Furthermore, as shown in FIG3a , the third reset control signal terminal RE3 and the second reset control signal terminal RE2 are connected to the same signal, and the third reset control signal line REL3 and the second reset control signal line REL2 are the same signal line. This can reduce the number of signal lines, eliminate the need for an additional drive control circuit to input a signal to the third reset control signal terminal RE3, and further reduce the bezel.

[0112] The signal timing diagram corresponding to the pixel circuit shown in FIG3a is shown in FIG3b, wherein em1 represents the first light-emitting control signal transmitted by the first light-emitting control signal line EML1 to the first light-emitting control signal terminal EM1, em2 represents the second light-emitting control signal transmitted by the second light-emitting control signal line EML2 to the second light-emitting control signal terminal EM2, re1 represents the first reset control signal transmitted by the first reset control signal line REL1 to the first reset control signal terminal RE1, re2 represents the second reset control signal transmitted by the second reset control signal line REL2 to the second reset control signal terminal RE2, and ga represents the scan signal transmitted by the scan signal line GAL to the scan signal terminal GA. Furthermore, inputting signals em1, em2, re1, re2, and ga into the pixel circuit respectively enables the first light-emitting control transistor M2, the second light-emitting control transistor M3, the first reset control transistor M4, the second reset control transistor M5, the third reset control transistor M6, and the data writing transistor M1 to cooperate with each other, causing the driving transistor M0 to generate a driving current, and inputting the driving current into the light-emitting device L, thereby driving the light-emitting device L to emit light.

[0113] Specifically, in the initialization stage T1, the first reset control transistor M4, the second reset control transistor M5 and the third reset control transistor M6 are all turned on, and can provide the signal of the reference signal terminal VREF to the gate of the driving transistor M0 to reset the gate of the driving transistor M0, provide the signal of the first initialization signal terminal VINT1 to the second electrode of the driving transistor M0 to initialize the second electrode of the driving transistor M0, and provide the signal of the second initialization signal terminal VINT2 to the anode of the light-emitting device L to initialize the anode of the light-emitting device L.

[0114] During the threshold compensation phase T2, the first light-emitting control transistor M2 and the first reset control transistor M4 are both turned on, providing the signal from the reference signal terminal VREF to the gate of the driving transistor M0, causing the potential of the gate of the driving transistor M0 to be equal to the potential Vref of the signal from the reference signal terminal VREF. Furthermore, the signal from the first power supply ELVDD is input to the first electrode of the driving transistor M0, turning the driving transistor M0 on, causing the potential of the second electrode of the driving transistor M0 to be Vref-Vth. Vth is the threshold voltage of the driving transistor M0.

[0115] During the signal writing phase T3, the data writing transistor M1 is turned on, supplying the data voltage at the data signal terminal DA to the gate of the driving transistor M0, causing the gate potential of the driving transistor M0 to be equal to the data voltage Vda. Furthermore, through the action of the first capacitor C1 and the second capacitor C2, the potential of the second electrode of the driving transistor M0 changes to: Vref - Vth + c1 (Vda - Vref) / (c1 + c2). Here, c1 represents the capacitance of the first capacitor C1, and c2 represents the capacitance of the first capacitor C2.

[0116] During the light-emitting phase T4, the first light-emitting control transistor M2 and the second light-emitting control transistor M3 are turned on. The signal from the first power supply ELVDD is input to the first electrode of the driving transistor M0, which generates a driving current IL, causing the potential of the second electrode of the driving transistor M0 to change to Vel. Through the action of the first capacitor C1 and the second capacitor C2, the potential of the gate of the driving transistor M0 changes to Vth + Vel + c2 (Vda - Vref) / (c1 + c2). Therefore, IL = K [Vel + c2 (Vda - Vref) / (c1 + c2) - Velvdd]. 2 The driving current IL is input into the light emitting device to drive the light emitting device L to emit light.

[0117] Furthermore, as shown in FIG4a , the second capacitor C2, the second emission control transistor M3, and the third reset control transistor M6 may not be provided in the pixel circuit. This can reduce the area occupied by the pixel circuit and the number of signal lines, eliminate the need for an additional drive control circuit for inputting signals to the second emission control signal terminal EM2 and the third reset control signal terminal RE3, and further reduce the bezel.

[0118] The signal timing diagram corresponding to the pixel circuit shown in FIG4a is shown in FIG4b, wherein em1 represents the first light-emitting control signal transmitted by the first light-emitting control signal line EML1 to the first light-emitting control signal terminal EM1, re1 represents the first reset control signal transmitted by the first reset control signal line REL1 to the first reset control signal terminal RE1, re2 represents the second reset control signal transmitted by the second reset control signal line REL2 to the second reset control signal terminal RE2, and ga represents the scan signal transmitted by the scan signal line GAL to the scan signal terminal GA. Furthermore, inputting the signals em1, re1, re2, and ga into the pixel circuit respectively enables the first light-emitting control transistor M2, the first reset control transistor M4, the second reset control transistor M5, and the data writing transistor M1 to cooperate with each other, causing the driving transistor M0 to generate a driving current, and inputting the driving current into the light-emitting device L, thereby driving the light-emitting device L to emit light.

[0119] Specifically, in the initialization stage T1, the first reset control transistor M4 and the second reset control transistor M5 are both turned on, and can provide the signal of the reference signal terminal VREF to the gate of the driving transistor M0 to reset the gate of the driving transistor M0, provide the signal of the first initialization signal terminal VINT1 to the second electrode of the driving transistor M0 to initialize the second electrode of the driving transistor M0, and provide the signal of the first initialization signal terminal VINT1 to the anode of the light-emitting device L to initialize the anode of the light-emitting device L.

[0120] During the threshold compensation phase T2, the first light-emitting control transistor M2 and the first reset control transistor M4 are both turned on, providing the signal from the reference signal terminal VREF to the gate of the driving transistor M0, causing the potential of the gate of the driving transistor M0 to be equal to the potential Vref of the signal from the reference signal terminal VREF. Furthermore, the signal from the first power supply ELVDD is input to the first electrode of the driving transistor M0, turning the driving transistor M0 on, causing the potential of the second electrode of the driving transistor M0 to be Vref-Vth. Vth is the threshold voltage of the driving transistor M0.

[0121] During the signal writing phase T3, the data writing transistor M1 is turned on, supplying the data voltage at the data signal terminal DA to the gate of the driving transistor M0, causing the gate potential of the driving transistor M0 to be equal to the data voltage Vda. Furthermore, through the action of the first capacitor C1 and the second capacitor C2, the potential of the second electrode of the driving transistor M0 changes to: Vref - Vth + c1 (Vda - Vref) / (c1 + coled). Here, c1 represents the capacitance of the first capacitor C1, and coled represents the parasitic capacitance of the light-emitting device L.

[0122] During the light-emitting phase T4, the first light-emitting control transistor M2 and the second light-emitting control transistor M3 are turned on. The signal of the first power supply ELVDD is input to the first electrode of the driving transistor M0, which generates a driving current IL, causing the potential of the second electrode of the driving transistor M0 to change to Vel. Through the action of the first capacitor C1 and the second capacitor C2, the potential of the gate of the driving transistor M0 changes to Vth + Vel + coled (Vda - Vref) / (c1 + coled). Therefore, IL = K [Vel + coled (Vda - Vref) / (c1 + coled) - Velvdd]. 2 The driving current IL is input into the light emitting device to drive the light emitting device L to emit light.

[0123] In a specific implementation, the transistor may be an N-type transistor. Furthermore, in a specific implementation, depending on the type of the transistor and the signal of its gate, the first electrode of the transistor may be used as its source and the second electrode as its drain; or vice versa, the first electrode of the transistor may be used as its drain and the second electrode as its source. This can be designed and determined according to the actual application environment and is not specifically distinguished here.

[0124] It should be noted that the transistors mentioned in the embodiments of the present disclosure may be thin film transistors (TFT) or metal oxide semiconductor field effect transistors (MOS), which are not limited here.

[0125] The above is merely an example to illustrate the specific structure of each circuit in the pixel circuit provided in the embodiment of the present disclosure. In specific implementation, the specific structure of the above circuit is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art. These are all within the scope of protection of the present disclosure and are not specifically limited here.

[0126] In practical applications, the aforementioned transistors require input of control signals via shift register units in a driver control circuit. The driver control circuit is typically located in a non-display area, also known as a border area. If the driver control circuit has a large number of shift register units, they occupy a larger area, which in turn results in a larger area occupied by the border area, hindering the narrow-border design of the display panel. Therefore, embodiments of the present disclosure provide a display panel that addresses the issue of a driver control circuit occupying a large area, hindering the narrow-border design of the display panel.

[0127] The following describes a display panel provided by an embodiment of the present disclosure, taking the pixel circuit shown in FIG3a as an example. The present disclosure provides some pixel circuits, for example, including a pixel control circuit configured to control a drive transistor M0 to generate a drive current that drives a light-emitting device L to emit light. Furthermore, a display area of ​​the display panel includes multiple control signal lines, wherein the pixel circuits in at least one row of sub-pixels among the multiple sub-pixels are coupled to one of the multiple control signal lines, and the control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to each other. Furthermore, a non-display area includes a drive control circuit, which includes multiple shift register units, wherein the mutually coupled control signal lines are coupled to one of the multiple shift register units, and the shift register unit is configured to transmit a signal to the pixel circuit via the control signal line. With this arrangement, by coupling the control signal lines corresponding to at least two adjacent rows of sub-pixels to each other and then to one shift register unit, the number of shift register units can be reduced, the area occupied by the drive control circuit can be reduced, and the area occupied by the border area can be reduced, thereby achieving a narrow-border design for the display panel.

[0128] In some examples, in combination with Figure 3a, Figure 5a and Figure 5b, the pixel control circuit can include a first light-emitting control circuit 120 (i.e., a first light-emitting control transistor M2), the drive control circuit includes a first light-emitting drive control circuit 211, and the first light-emitting drive control circuit 211 includes a plurality of first light-emitting shift register units GEM1_1 to GEM1_A (A is an integer greater than 0). The plurality of first light-emitting shift register units GEM1_1 to GEM1_A can be cascaded, that is, the input signal terminal of the first-stage first light-emitting shift register unit GEM1_1 among the plurality of first light-emitting shift register units GEM1_1 to GEM1_A is coupled to the first light-emitting trigger signal terminal ESTV1, and the drive output terminal of the upper-stage first light-emitting shift register unit among the plurality of first light-emitting shift register units GEM1_1 to GEM1_A is coupled to the input signal terminal of the next-stage first light-emitting shift register unit. For example, the driving output terminal of the first light emitting shift register unit GEM1_k / 2 is coupled to the input signal terminal of the first light emitting shift register unit GEM1_(k+2) / 2.

[0129] Furthermore, the shift register unit includes a first light-emitting shift register unit, and the control signal line includes a first light-emitting control signal line EML1. Furthermore, the first light-emitting control signal lines EML1 corresponding to at least two adjacent rows of sub-pixels are coupled to each other and then coupled to one of the plurality of first light-emitting shift register units. This configuration can reduce the number of first light-emitting shift register units, thereby reducing the occupied area of ​​the border area, thereby achieving a narrow-border design for the display panel. For example, the first light-emitting control signal lines EML1 corresponding to two adjacent rows of sub-pixels can be coupled to each other and then coupled to one of the plurality of first light-emitting shift register units. For example, as shown in Figures 5a, 5b and 6, the first light-emitting control signal line EML1_k-1 corresponding to the sub-pixels in the k-1th row and the first light-emitting control signal line EML1_k corresponding to the sub-pixels in the kth row are coupled to each other and then coupled to the driving output end of the first light-emitting shift register unit GEM1_k / 2. The first light-emitting control signal em1_k-1 is input to the first light-emitting control signal line EML1_k-1 and the first light-emitting control signal line EML1_k through the first light-emitting shift register unit GEM1_k / 2. Furthermore, the first light-emission control signal line EML1_k+1 corresponding to the sub-pixels in the k+1th row and the first light-emission control signal line EML1_k+2 corresponding to the sub-pixels in the k+2th row are coupled to each other and then coupled to the driving output terminal of the first light-emission shift register unit GEM1_(k+2) / 2. The first light-emission control signal em1_k+1 is input to the first light-emission control signal line EML1_k+1 and the first light-emission control signal line EML1_k+2 via the first light-emission shift register unit GEM1_(k+2) / 2. This configuration can reduce the number of first light-emission shift register units by half. Of course, in practical applications, the first light-emission control signal lines EML1 corresponding to three, four, or more adjacent rows of sub-pixels can also be coupled to each other and then coupled to a single first light-emission shift register unit, but this is not limited here.

[0130] It should be noted that, taking the kth row of sub-pixels as an example, during the threshold compensation phase T2, both the first emission control transistor M2 and the first reset control transistor M4 are turned on, i.e., during the period when both the em1_k and re1_k signals are valid signals (e.g., high level). Furthermore, during the signal writing phase T3, i.e., after the threshold compensation phase T2, the ga_k signal is valid (e.g., high level), and the data writing transistor M1 is turned on. Therefore, the threshold voltage compensation time is determined by the period between the rising edge of the em1_k signal and the falling edge of the re1_k signal. Therefore, if the rising edge of re1_k+n corresponding to the k+nth row sub-pixel occurs before the falling edge of em1_k corresponding to the kth row sub-pixel, but does not affect other normal timing operations, the first emission control signal line EML1 corresponding to the kth row sub-pixel to the first emission control signal line EML1 corresponding to the k+nth row sub-pixel can be electrically connected to each other; where n is an integer greater than or equal to 2.

[0131] In a specific implementation, as shown in FIG5a and FIG5b, the non-display area further includes: a fourth light-emitting drive control circuit 214, which includes a plurality of fourth light-emitting shift register units GEM4_1 to GEM4_B (B is an integer greater than 0). The plurality of fourth light-emitting shift register units GEM4_1 to GEM4_B can be cascaded, that is, the input signal terminal of the first-stage fourth light-emitting shift register unit GEM4_1 among the plurality of fourth light-emitting shift register units GEM4_1 to GEM4_B is coupled to the fourth light-emitting trigger signal terminal ESTV4, and the driving output terminal of the previous-stage fourth light-emitting shift register unit among the plurality of fourth light-emitting shift register units GEM4_1 to GEM4_B is coupled to the input signal terminal of the next-stage fourth light-emitting shift register unit. For example, the driving output terminal of the fourth light-emitting shift register unit GEM4_k is coupled to the input signal terminal of the fourth light-emitting shift register unit GEM4_k+1.

[0132] Furthermore, the second light-emitting control signal line EML2 corresponding to each row of sub-pixels is coupled to one of the plurality of fourth light-emitting shift register units. For example, referring to Figures 5a, 5b, and 6, the fourth light-emitting shift register unit GEM4_k-1 is coupled to the driving output terminal of the second light-emitting control signal line EML2_k-1 corresponding to the sub-pixels in the k-1th row, and the second light-emitting control signal em2_k-1 is input to the second light-emitting control signal line EML2_k-1 via the fourth light-emitting shift register unit GEM4_k-1. The driving output terminal of the fourth light-emitting shift register unit GEM4_k is coupled to the second light-emitting control signal line EML2_k corresponding to the sub-pixels in the kth row, and the second light-emitting control signal em2_k is input to the second light-emitting control signal line EML2_k via the fourth light-emitting shift register unit GEM4_k. A driving output terminal of the fourth light-emitting shift register unit GEM4_k+1 is coupled to the second light-emitting control signal line EML2_k+1 corresponding to the sub-pixels in the k+1th row, and the second light-emitting control signal em2_k+1 is input to the second light-emitting control signal line EML2_k+1 through the fourth light-emitting shift register unit GEM4_k+1. A driving output terminal of the fourth light-emitting shift register unit GEM4_k+2 is coupled to the second light-emitting control signal line EML2_k+2 corresponding to the sub-pixels in the k+2th row, and the second light-emitting control signal em2_k+2 is input to the second light-emitting control signal line EML2_k+2 through the fourth light-emitting shift register unit GEM4_k+2.

[0133] In a specific implementation, as shown in FIG5a and FIG5b, the non-display area further includes: a second reset drive control circuit 222, which includes a plurality of second reset shift register units GRE2_1 to GRE2_C. The plurality of second reset shift register units GRE2_1 to GRE2_C can be cascaded, that is, the input signal terminal of the first-stage second reset shift register unit GRE2_1 among the plurality of second reset shift register units GRE2_1 to GRE2_C is coupled to the second reset trigger signal terminal RSTV2, and the driving output terminal of the previous-stage second reset shift register unit among the plurality of second reset shift register units GRE2_1 to GRE2_C is coupled to the input signal terminal of the next-stage second reset shift register unit. For example, the driving output terminal of the second reset shift register unit GRE2_k is coupled to the input signal terminal of the second reset shift register unit GRE2_k+1.

[0134] Furthermore, the first reset control signal line REL1 corresponding to each row of sub-pixels is coupled to one of the plurality of second reset shift register units. For example, referring to Figures 5a, 5b, and 6, the drive output of the second reset shift register unit GRE2_k-1 is coupled to the first reset control signal line REL1_k-1, and the first reset control signal re1_k-1 is input to the first reset control signal line REL1_k-1 via the second reset shift register unit GRE2_k-1. The drive output of the second reset shift register unit GRE2_k is coupled to the first reset control signal line REL1_k, and the first reset control signal re1_k is input to the first reset control signal line REL1_k via the second reset shift register unit GRE2_k. A driving output terminal of the second reset shift register unit GRE2_k+1 is coupled to the first reset control signal line REL1_k+1, and the first reset control signal re1_k+1 is input to the first reset control signal line REL1_k+1 through the second reset shift register unit GRE2_k+1. A driving output terminal of the second reset shift register unit GRE2_k+2 is coupled to the first reset control signal line REL1_k+2, and the first reset control signal re1_k+2 is input to the first reset control signal line REL1_k+2 through the second reset shift register unit GRE2_k+2.

[0135] In a specific implementation, as shown in FIG5a and FIG5b, the non-display area further includes: the non-display area further includes: a fourth reset drive control circuit 224, the fourth reset drive control circuit 224 includes a plurality of fourth reset shift register units GRE4_1 to GRE4_D, and the plurality of fourth reset shift register units GRE4_1 to GRE4_D can be cascaded, that is, the input signal terminal of the first-stage fourth reset shift register unit GRE4_1 among the plurality of fourth reset shift register units GRE4_1 to GRE4_D is coupled to the fourth reset trigger signal terminal RSTV4, and the driving output terminal of the previous-stage fourth reset shift register unit among the plurality of fourth reset shift register units GRE4_1 to GRE4_D is coupled to the input signal terminal of the next-stage fourth reset shift register unit. For example, the driving output terminal of the fourth reset shift register unit GRE4_k is coupled to the input signal terminal of the fourth reset shift register unit GRE4_k+1.

[0136] Furthermore, the second reset control signal line REL2 corresponding to each row of sub-pixels is coupled to one of the plurality of fourth reset shift register units. For example, referring to Figures 5a, 5b, and 6, the drive output terminal of the fourth reset shift register unit GRE4_k-1 is coupled to the second reset control signal line REL2_k-1, and the second reset control signal re2_k-1 is input to the second reset control signal line REL2_k-1 via the fourth reset shift register unit GRE4_k-1. The drive output terminal of the fourth reset shift register unit GRE4_k is coupled to the second reset control signal line REL2_k, and the second reset control signal re2_k is input to the second reset control signal line REL2_k via the fourth reset shift register unit GRE4_k. A driving output terminal of the fourth reset shift register unit GRE4_k+1 is coupled to the second reset control signal line REL2_k+1, and the second reset control signal re2_k+1 is input to the second reset control signal line REL2_k+1 through the fourth reset shift register unit GRE4_k+1. A driving output terminal of the fourth reset shift register unit GRE4_k+2 is coupled to the second reset control signal line REL2_k+2, and the second reset control signal re2_k+2 is input to the second reset control signal line REL2_k+2 through the fourth reset shift register unit GRE4_k+2.

[0137] In a specific implementation, as shown in Figures 5a and 5b, the non-display area further includes: the non-display area further includes: a scan control circuit 230, the scan control circuit 230 includes a plurality of scan shift register units GGA_1 to GGA_E, and the scan signal line GAL corresponding to each row of sub-pixels is coupled to one of the plurality of scan shift register units. For example, in conjunction with Figures 5a, 5b and 6, the drive output end of the scan shift register unit GGA_k-1 is coupled to the scan signal line GAL_k-1, and the scan signal ga_k-1 is input to the scan signal line GAL_k-1 through the scan shift register unit GGA_k-1. The drive output end of the scan shift register unit GGA_k is coupled to the scan signal line GAL_k, and the scan signal ga_k is input to the scan signal line GAL_k through the scan shift register unit GGA_k. The drive output terminal of the scan shift register unit GGA_k+1 is coupled to the scan signal line GAL_k+1, and the scan signal ga_k+1 is input to the scan control signal line GAL_k+1 through the scan shift register unit GGA_k+1. The drive output terminal of the scan shift register unit GGA_k+2 is coupled to the scan control signal line GAL_k+2, and the scan signal ga_k+2 is input to the scan control signal line GAL_k+2 through the scan shift register unit GGA_k+2.

[0138] In actual applications, the display panel can operate at multiple refresh frequencies, for example, it can operate at 1Hz, 60Hz, 90Hz and 120Hz. In addition, with the development of science and technology, display schemes that support different refresh frequencies in different areas have emerged. In a specific implementation, the display area includes multiple display sub-areas, and the multiple display sub-areas are arranged along the column direction of the sub-pixels, and the refresh frequencies of any two display sub-areas in the multiple display sub-areas may be the same or different. For example, as shown in FIG7 , the display area is divided into two display sub-areas Aa and Ab. The refresh frequency corresponding to the display sub-area Aa can be 60Hz, and the refresh frequency corresponding to the display sub-area Ab can be 1Hz. Alternatively, the refresh frequency corresponding to the display sub-area Aa can be 1Hz, and the refresh frequency corresponding to the display sub-area Ab can be 60Hz.

[0139] In some embodiments, the plurality of first light-emitting shift register units may include a plurality of first light-emitting register groups, the plurality of first light-emitting register groups corresponding one-to-one to the plurality of display sub-regions, and the plurality of first light-emitting register groups coupled to the first light-emitting control signal lines in the corresponding display sub-regions. Furthermore, the plurality of first light-emitting register groups correspond to a first light-emitting trigger signal terminal, the input signal terminal of the first-stage first light-emitting shift register unit in a first first light-emitting register group of the plurality of first light-emitting register groups is coupled to the first light-emitting trigger signal terminal, and the driving output terminal of the last-stage first light-emitting shift register unit of the previous first light-emitting register group of two adjacent first light-emitting register groups is coupled to the input signal terminal of the first-stage first light-emitting shift register unit of the next first light-emitting register group. For example, as shown in Figure 7, taking the display area including two display sub-areas Aa and Ab as an example, the display sub-area Aa corresponds to the first light-emitting register group 211a, and the first light-emitting register group 211a includes the first-level first light-emitting shift register unit GEM1_1 to the k / 2-level first light-emitting shift register unit GEM1_k / 2, the input signal end of the first-level first light-emitting shift register unit GEM1_1 is coupled to the first light-emitting trigger signal end ESTV1, and the driving output end of the previous level first light-emitting shift register unit among the first-level first light-emitting shift register unit GEM1_1 to the k / 2-level first light-emitting shift register unit GEM1_k / 2 is coupled to the input signal end of the next level first light-emitting shift register unit. Furthermore, the display sub-region Ab corresponds to the first light-emitting register group 211b, which includes the first-stage first light-emitting shift register unit GEM1_(k+2) / 2 to the A-stage first light-emitting shift register unit GEM1_A. The driving output end of the previous-stage first light-emitting shift register unit in the first-stage first light-emitting shift register unit GEM1_(k+2) / 2 to the A-stage first light-emitting shift register unit GEM1_A is coupled to the input signal end of the next-stage first light-emitting shift register unit, and the driving output end of the k / 2-stage first light-emitting shift register unit GEM1_k / 2 in the display sub-region Aa is coupled to the input signal end of the first-stage first light-emitting shift register unit GEM1_(k+2) / 2 in the display sub-region Ab.

[0140] Of course, it is also possible to have a one-to-one correspondence between multiple first light-emitting register groups and multiple first light-emitting trigger signal terminals, and to couple the input signal terminals of the first-stage first light-emitting shift register units in the first light-emitting register groups to the corresponding first light-emitting trigger signal terminals. Furthermore, the first light-emitting shift register units in the same first light-emitting register group are cascaded.

[0141] In some embodiments, the plurality of fourth light-emitting shift register units can include a plurality of fourth light-emitting register groups, the plurality of fourth light-emitting register groups correspond one-to-one to the plurality of display sub-areas, and the plurality of fourth light-emitting register groups are coupled to the second light-emitting control signal line in the corresponding display sub-areas, and the plurality of fourth light-emitting register groups correspond to a fourth light-emitting trigger signal terminal, the input signal terminal of the first-stage fourth light-emitting shift register unit in the first fourth light-emitting register group of the plurality of fourth light-emitting register groups is coupled to the fourth light-emitting trigger signal terminal, and the driving output terminal of the last-stage fourth light-emitting shift register unit of the upper fourth light-emitting register group of two adjacent fourth light-emitting register groups is coupled to the input signal terminal of the first-stage fourth light-emitting shift register unit of the next fourth light-emitting register group. For example, as shown in Figure 7, taking the display area including two display sub-areas Aa and Ab as an example, the display sub-area Aa corresponds to the fourth light-emitting register group 214a, and the fourth light-emitting register group 214a includes the first-level fourth light-emitting shift register unit GEM4_1 to the k-th level fourth light-emitting shift register unit GEM4_k. The input signal terminal of the first-level fourth light-emitting shift register unit GEM4_1 is coupled to the fourth light-emitting trigger signal terminal ESTV4, and the driving output terminal of the previous level fourth light-emitting shift register unit among the first-level fourth light-emitting shift register unit GEM4_1 to the k-th level fourth light-emitting shift register unit GEM4_k is coupled to the input signal terminal of the next level fourth light-emitting shift register unit. In addition, the display sub-area Ab corresponds to the fourth light-emitting register group 214b, which includes the first-stage fourth light-emitting shift register unit GEM4_k+1 to the B-stage fourth light-emitting shift register unit GEM4_B. The driving output end of the previous-stage fourth light-emitting shift register unit in the first-stage fourth light-emitting shift register unit GEM4_k+1 to the B-stage fourth light-emitting shift register unit GEM4_B is coupled to the input signal end of the next-stage fourth light-emitting shift register unit.

[0142] Of course, multiple fourth light-emitting register groups can also correspond to multiple fourth light-emitting trigger signal terminals one by one, and the input signal terminal of the first stage fourth light-emitting shift register unit in the fourth light-emitting register group can be coupled to the corresponding fourth light-emitting trigger signal terminal.

[0143] In some embodiments, the plurality of second reset shift register units may include a plurality of second reset register groups, the plurality of second reset register groups corresponding one-to-one to the plurality of display sub-regions, and the plurality of second reset register groups coupled to the first reset control signal lines in the corresponding display sub-regions. Furthermore, the plurality of second reset register groups correspond one-to-one to the plurality of second reset trigger signal terminals, and the input signal terminal of the first-stage second reset shift register unit in the second reset register group is coupled to the corresponding second reset trigger signal terminal. For example, as shown in Figure 7, taking the display area including two display sub-areas Aa and Ab as an example, the display sub-area Aa corresponds to the second reset register group 222a, and the second reset register group 222a includes the first-level second reset shift register unit GRE2_1 to the k-th level second reset shift register unit GRE2_k, the input signal end of the first-level second reset shift register unit GRE2_1 is coupled to the second reset trigger signal end RSTV2a, and the driving output end of the previous level second reset shift register unit among the first-level second reset shift register unit GRE2_1 to the k-th level second reset shift register unit GRE2_k is coupled to the input signal end of the next level second reset shift register unit. Furthermore, the display sub-area Ab corresponds to the second reset register group 222b, and the second reset register group 222b includes the first-level second reset shift register unit GRE2_k+1 to the C-level second reset shift register unit GRE2_C, the input signal end of the first-level second reset shift register unit GRE2_k+1 is coupled to the second reset trigger signal end RSTV2b, and the driving output end of the previous-level second reset shift register unit in the first-level second reset shift register unit GRE2_k+1 to the C-level second reset shift register unit GRE2_C is coupled to the input signal end of the next-level second reset shift register unit.

[0144] Of course, multiple second reset register groups can also correspond to a second reset trigger signal end, the input signal end of the first-level second reset shift register unit in the first second reset register group of the multiple second reset register groups is coupled to the second reset register group, and the driving output end of the last-level second reset shift register unit of the previous second reset register group in the two adjacent second reset register groups is coupled to the input signal end of the first-level second reset shift register unit of the next second reset register group.

[0145] In some embodiments, the plurality of scan shift register units can include a plurality of scan register groups, each of which corresponds one-to-one to a plurality of display sub-regions, and each of which is coupled to the scan signal lines in the corresponding display sub-regions. Furthermore, the plurality of scan register groups corresponds one-to-one to a plurality of scan trigger signal terminals, and the input signal terminals of the first-stage scan shift register units in the scan register groups are coupled to the corresponding scan trigger signal terminals. For example, as shown in FIG7 , taking the display region as including two display sub-regions Aa and Ab as an example, display sub-region Aa corresponds to scan register group 230a, and scan register group 230a includes first-stage scan shift register units GGA_1 to k-th stage scan shift register units GGA_k. The input signal terminals of the first-stage scan shift register units GGA_1 are coupled to the scan trigger signal terminal GSTVa, and the drive output terminals of the previous-stage scan shift register units in the first-stage scan shift register units GGA_1 to k-th stage scan shift register units GGA_k are coupled to the input signal terminals of the next-stage scan shift register units. Furthermore, the display sub-area Ab corresponds to the scanning register group 230b, and the scanning register group 230b includes the first-level scanning shift register unit GGA_k+1 to the E-level scanning shift register unit GGA_E, the input signal end of the first-level scanning shift register unit GGA_k+1 is coupled to the scanning trigger signal end GSTVb, and the driving output end of the previous-level scanning shift register unit in the first-level scanning shift register unit GGA_k+1 to the E-level scanning shift register unit GGA_E is coupled to the input signal end of the next-level scanning shift register unit.

[0146] In some embodiments, the plurality of fourth reset shift register units may include a plurality of fourth reset register groups, the plurality of fourth reset register groups corresponding one-to-one to the plurality of display sub-regions, and the plurality of fourth reset register groups coupled to the second reset control signal lines in the corresponding display sub-regions. Furthermore, the plurality of fourth reset register groups correspond to a fourth reset trigger signal terminal, the input signal terminal of the first stage of the fourth reset shift register unit in a first fourth reset register group of the plurality of fourth reset register groups is coupled to the fourth reset register group, and the driving output terminal of the last stage of the fourth reset shift register unit in the previous fourth reset register group of two adjacent fourth reset register groups is coupled to the input signal terminal of the first stage of the fourth reset shift register unit in the next fourth reset register group. For example, as shown in Figure 7, taking the display area including two display sub-areas Aa and Ab as an example, the display sub-area Aa corresponds to the fourth reset register group 224a, and the fourth reset register group 224a includes the first-level fourth reset shift register unit GRE4_1 to the k-th level fourth reset shift register unit GRE4_k, the input signal end of the first-level fourth reset shift register unit GRE4_1 is coupled to the fourth reset trigger signal end RSTV4, and the driving output end of the previous level fourth reset shift register unit among the first-level fourth reset shift register unit GRE4_1 to the k-th level fourth reset shift register unit GRE4_k is coupled to the input signal end of the next level fourth reset shift register unit. Furthermore, the display sub-area Ab corresponds to the fourth reset register group 224b, and the fourth reset register group 224b includes the first-level fourth reset shift register unit GRE4_k+1 to the D-level fourth reset shift register unit GRE4_D, and the driving output end of the previous-level fourth reset shift register unit in the first-level fourth reset shift register unit GRE4_k+1 to the D-level fourth reset shift register unit GRE4_D is coupled to the input signal end of the next-level fourth reset shift register unit, and the input signal end of the first-level fourth reset shift register unit GRE4_k+1 in the fourth reset register group 224b is coupled to the driving output end of the k-th level fourth reset shift register unit GRE4_k in the fourth reset register group 224a.

[0147] Of course, the plurality of fourth reset register groups may also correspond one-to-one to the plurality of fourth reset trigger signal terminals, and the input signal terminal of the first stage fourth reset shift register unit in the fourth reset register group may be coupled to the corresponding fourth reset trigger signal terminal.

[0148] The following describes the operation of the display panel in accordance with an embodiment of the present disclosure, taking the structure of the display panel shown in FIG7 as an example, and in conjunction with FIG8a through FIG10b . In FIG8a , FIG8b , FIG9b , and FIG10a , F_1 ​​through F_60 represent display frames within one second, respectively. In FIG9a and FIG10b , F_1 ​​represents a display frame within one second, and F_2 through F_60 represent hold frames within one second, respectively.

[0149] By combining Figures 8a and 8b , the refresh frequencies of the display sub-area Aa and the display sub-area Ab can be made the same. For example, the refresh frequencies of the display sub-area Aa and the display sub-area Ab are both 60 Hz. Furthermore, by controlling the operation of the first light-emitting register group 211a and the first light-emitting register group 211b, the first light-emitting control signal em1_k can be input to the first light-emitting control signal line EML1_k, and the first light-emitting control signal em1_k+1 can be input to the first light-emitting control signal line EML1_k+1. By controlling the operation of the fourth light-emitting register group 214a and the fourth light-emitting register group 214b, the second light-emitting control signal em2_k can be input to the second light-emitting control signal line EML2_k, and the second light-emitting control signal em2_k+1 can be input to the second light-emitting control signal line EML2_k+1. By controlling the operations of the second reset register group 222a and the second reset register group 222b, the first reset control signal re1_k can be input to the first reset control signal line REL1_k, and the first reset control signal re1_k+1 can be input to the first reset control signal line REL1_k+1. By controlling the operations of the fourth reset register group 224a and the fourth reset register group 224b, the second reset control signal re2_k can be input to the second reset control signal line REL2_k, and the second reset control signal re2_k+1 can be input to the second reset control signal line REL2_k+1. By controlling the operations of the scan register group 230a and the scan register group 230b, the scan signal ga_k can be input to the scan signal line GAL_k, and the scan signal ga_k+1 can be input to the scan signal line GAL_k+1.

[0150] By combining Figures 9a and 9b , the refresh frequency of display sub-area Aa can be lower than that of display sub-area Ab. For example, the refresh frequency of display sub-area Aa is 1 Hz, while the refresh frequency of display sub-area Ab is 60 Hz. Furthermore, by controlling the operation of the first light-emitting register group 211a and the first light-emitting register group 211b, the first light-emitting control signal em1_k can be input to the first light-emitting control signal line EML1_k, and the first light-emitting control signal em1_k+1 can be input to the first light-emitting control signal line EML1_k+1. By controlling the operation of the fourth light-emitting register group 214a and the fourth light-emitting register group 214b, the second light-emitting control signal em2_k can be input to the second light-emitting control signal line EML2_k, and the second light-emitting control signal em2_k+1 can be input to the second light-emitting control signal line EML2_k+1. By controlling the operations of the second reset register group 222a and the second reset register group 222b, the first reset control signal re1_k can be input to the first reset control signal line REL1_k, and the first reset control signal re1_k+1 can be input to the first reset control signal line REL1_k+1. By controlling the operations of the fourth reset register group 224a and the fourth reset register group 224b, the second reset control signal re2_k can be input to the second reset control signal line REL2_k, and the second reset control signal re2_k+1 can be input to the second reset control signal line REL2_k+1. By controlling the operations of the scan register group 230a and the scan register group 230b, the scan signal ga_k can be input to the scan signal line GAL_k, and the scan signal ga_k+1 can be input to the scan signal line GAL_k+1.

[0151] By combining Figures 10a and 10b , the refresh frequency of display sub-area Aa can be made greater than the refresh frequency of display sub-area Ab. For example, the refresh frequency of display sub-area Aa is 60 Hz, while the refresh frequency of display sub-area Ab is 1 Hz. Furthermore, by controlling the operation of the first light-emitting register group 211a and the first light-emitting register group 211b, the first light-emitting control signal em1_k can be input to the first light-emitting control signal line EML1_k, and the first light-emitting control signal em1_k+1 can be input to the first light-emitting control signal line EML1_k+1. By controlling the operation of the fourth light-emitting register group 214a and the fourth light-emitting register group 214b, the second light-emitting control signal em2_k can be input to the second light-emitting control signal line EML2_k, and the second light-emitting control signal em2_k+1 can be input to the second light-emitting control signal line EML2_k+1. By controlling the operations of the second reset register group 222a and the second reset register group 222b, the first reset control signal re1_k can be input to the first reset control signal line REL1_k, and the first reset control signal re1_k+1 can be input to the first reset control signal line REL1_k+1. By controlling the operations of the fourth reset register group 224a and the fourth reset register group 224b, the second reset control signal re2_k can be input to the second reset control signal line REL2_k, and the second reset control signal re2_k+1 can be input to the second reset control signal line REL2_k+1. By controlling the operations of the scan register group 230a and the scan register group 230b, the scan signal ga_k can be input to the scan signal line GAL_k, and the scan signal ga_k+1 can be input to the scan signal line GAL_k+1.

[0152] The present disclosure provides some further structural diagrams of display panels, as shown in Figure 11a, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0153] In the disclosed embodiment, as shown in Figures 11a and 11b, the pixel control circuit includes a second light-emitting control circuit 130, and the drive control circuit includes a third light-emitting drive control circuit. The third light-emitting drive control circuit includes a plurality of third light-emitting shift register units GEM3_1 to GEM3_F (F is an integer greater than 0). The plurality of third light-emitting shift register units GEM3_1 to GEM3_F can be cascaded, and the shift register units include a third light-emitting shift register unit. Furthermore, the control signal line includes a second light-emitting control signal line EML2. The second light-emitting control signal lines EML2 corresponding to two adjacent rows of sub-pixels are coupled to each other and then to one of the plurality of third light-emitting shift register units. For example, as shown in Figures 11a to 12, the second light-emitting control signal line EML2_k-1 corresponding to the sub-pixels in the k-1th row and the second light-emitting control signal line EML2_k corresponding to the sub-pixels in the kth row are coupled to each other and then coupled to the driving output end of the third light-emitting shift register unit GEM3_k / 2. The second light-emitting control signal em2_k-1 is input to the second light-emitting control signal line EML2_k-1 and the second light-emitting control signal line EML2_k through the third light-emitting shift register unit GEM3_k / 2. Furthermore, the second light-emitting control signal line EML2_k+1 corresponding to the sub-pixels in the k+1th row and the second light-emitting control signal line EML2_k+2 corresponding to the sub-pixels in the k+2th row are coupled to each other and then coupled to the driving output terminal of the third light-emitting shift register unit GEM3_(k+2) / 2. The second light-emitting control signal em2_k+1 is input to the second light-emitting control signal line EML2_k+1 and the second light-emitting control signal line EML2_k+2 via the third light-emitting shift register unit GEM3_(k+2) / 2. This configuration can reduce the number of third light-emitting shift register units by half. Of course, in practical applications, the second light-emitting control signal lines EML2 corresponding to three, four, or more adjacent rows of sub-pixels can also be coupled to each other and then coupled to a single third light-emitting shift register unit, but this is not limited here.

[0154] It should be noted that, taking the sub-pixels in the k-1th and k-th rows as an example, during the threshold compensation phase T2_k-1 corresponding to the sub-pixels in the k-1th row, both the first emission control transistor M2 and the first reset control transistor M4 are turned on, i.e., the period during which both the em1_k-1 and re1_k-1 signals are valid signals (e.g., high level). Furthermore, during the signal writing phase T3_k-1, the ga_k-1 signal is valid (e.g., high level), and the data writing transistor M1 is turned on. During the threshold compensation phase T2_k corresponding to the sub-pixels in the k-th row, both the first emission control transistor M2 and the first reset control transistor M4 are turned on, i.e., the period during which both the em1_k and re1_k signals are valid signals (e.g., high level). Furthermore, during the signal writing phase T3_k, the ga_k signal is valid (e.g., high level), and the data writing transistor M1 is turned on. Therefore, if the falling edge of ga_k+m corresponding to the sub-pixel in the k+mth row is before the rising edge of em2_k corresponding to the sub-pixel in the kth row, but does not affect the normal operation of other timings, the second light-emitting control signal line EML2 corresponding to the sub-pixel in the kth row to the second light-emitting control signal line EML2 corresponding to the sub-pixel in the k+mth row can be electrically connected to each other; wherein m is an integer greater than or equal to 2.

[0155] Furthermore, the structures shown in Figures 11a and 11b can also support multiple display sub-areas. In a specific implementation, the multiple third light-emitting shift register units include multiple third light-emitting register groups. The multiple third light-emitting register groups correspond one-to-one to the multiple display sub-areas, and the multiple third light-emitting register groups are coupled to the second light-emitting control signal lines EML2 in the corresponding display sub-areas. Furthermore, the multiple third light-emitting register groups correspond one-to-one to multiple third light-emitting trigger signal terminals, and the input signal terminals of the first-stage third light-emitting shift register units in the third light-emitting register groups are coupled to the corresponding third light-emitting trigger signal terminals. Alternatively, the multiple third light-emitting register groups correspond to one third light-emitting trigger signal terminal, the input signal terminal of the first-stage third light-emitting shift register unit in the first third light-emitting register group of the multiple third light-emitting register groups is coupled to the third light-emitting trigger signal terminal, and the driving output terminal of the last-stage third light-emitting shift register unit in the previous third light-emitting register group of two adjacent third light-emitting register groups is coupled to the input signal terminal of the first-stage third light-emitting shift register unit in the next third light-emitting register group. The non-display area further includes a second light-emitting drive control circuit, the second light-emitting drive control circuit including a plurality of second light-emitting shift register units. The first light-emitting control signal line EML1 corresponding to each row of sub-pixels is coupled to one of the plurality of second light-emitting shift register units. The plurality of second light-emitting shift register units include a plurality of second light-emitting register groups, each of the plurality of second light-emitting register groups corresponding one-to-one to the plurality of display sub-areas, and each of the plurality of second light-emitting register groups is coupled to the first light-emitting control signal line EML1 in the corresponding display sub-area. Multiple second light-emitting register groups correspond one-to-one to multiple second light-emitting trigger signal terminals, and the input signal terminal of the first-stage second light-emitting shift register unit in the second light-emitting register group is coupled to the corresponding second light-emitting trigger signal terminal; or, multiple second light-emitting register groups correspond to one second light-emitting trigger signal terminal, the input signal terminal of the first-stage second light-emitting shift register unit in the first second light-emitting register group of the multiple second light-emitting register groups is coupled to the second light-emitting trigger signal terminal, and the driving output terminal of the last-stage second light-emitting shift register unit of the upper second light-emitting register group in two adjacent second light-emitting register groups is coupled to the input signal terminal of the first-stage second light-emitting shift register unit of the next second light-emitting register group.

[0156] For example, as shown in FIG11a and FIG11b, sub-areas Aa and Ab are displayed. Sub-area Aa corresponds to scan register group 230a, second reset register group 222a, fourth reset register group 224a, third light-emitting register group 213a, and second light-emitting register group 212a. Sub-area Ab corresponds to scan register group 230b, second reset register group 222b, fourth reset register group 224b, third light-emitting register group 213b, and second light-emitting register group 212b. The second light-emitting shift register unit GEM2_1 is coupled to the second light-emitting trigger signal terminal ESTV2, and the third light-emitting shift register unit GEM3_1 is coupled to the third light-emitting trigger signal terminal ESTV3. Furthermore, the signal timing diagram corresponding to the structures shown in FIG11a and FIG11b is shown in FIG12. The specific operation process can be referred to the description in the above embodiment and will not be repeated here.

[0157] The present disclosure provides some further structural diagrams of display panels, as shown in FIG13a, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0158] In the disclosed embodiment, as shown in Figures 13a and 13b, the pixel control circuit includes a first reset control circuit 140, and the drive control circuit includes a first reset drive control circuit, which includes a plurality of first reset shift register units GRE1_1 to GRE1_G (G is an integer greater than 0). Furthermore, the shift register unit includes a first reset shift register unit. The control signal line includes a first reset control signal line REL1. The first reset control signal lines REL1 corresponding to two adjacent rows of sub-pixels are coupled to each other and then coupled to one of the plurality of first reset shift register units. For example, as shown in Figures 13a to 14, the first reset control signal line REL1_k-1 corresponding to the sub-pixel in the k-1th row and the first reset control signal line REL1_k corresponding to the sub-pixel in the kth row are coupled to each other and then coupled to the driving output end of the first reset shift register unit GRE1_k / 2, and the first reset control signal re1_k-1 is input to the first reset control signal line REL1_k-1 and the first reset control signal line REL1_k through the first reset shift register unit GRE1_k / 2. Furthermore, the first reset control signal line REL1_k+1 corresponding to the sub-pixels in the k+1th row and the first reset control signal line REL1_k+2 corresponding to the sub-pixels in the k+2th row are coupled to each other and then coupled to the driving output terminal of the first reset shift register unit GRE1_(k+2) / 2. The first reset control signal re1_k+1 is input to the first reset control signal line REL1_k+1 and the first reset control signal line REL1_k+2 via the first reset shift register unit GRE1_(k+2) / 2. This configuration can reduce the number of first reset shift register units by half. Of course, in practical applications, the first reset control signal lines REL1 corresponding to three, four, or more adjacent rows of sub-pixels can also be coupled to each other and then coupled to one first reset shift register unit, but this is not limited here.

[0159] It should be noted that, taking the sub-pixels in the k-1th and k-th rows as an example, during the threshold compensation phase T2_k-1 corresponding to the sub-pixels in the k-1th row, both the first emission control transistor M2 and the first reset control transistor M4 are turned on, i.e., the period during which both the em1_k-1 and re1_k-1 signals are valid signals (e.g., high level). Furthermore, during the signal writing phase T3_k-1, the ga_k-1 signal is valid (e.g., high level), and the data writing transistor M1 is turned on. During the threshold compensation phase T2_k corresponding to the sub-pixels in the k-th row, both the first emission control transistor M2 and the first reset control transistor M4 are turned on, i.e., the period during which both the em1_k and re1_k signals are valid signals (e.g., high level). Furthermore, during the signal writing phase T3_k, the ga_k signal is valid (e.g., high level), and the data writing transistor M1 is turned on. Therefore, if the rising edge of ga_k+p corresponding to the sub-pixel in the k+pth row is after the falling edge of re1_k corresponding to the sub-pixel in the kth row, but does not affect the normal operation of other timings, the first reset control signal line REL1 corresponding to the sub-pixel in the kth row to the first reset control signal line REL1 corresponding to the sub-pixel in the k+pth row can be electrically connected to each other; wherein p is an integer greater than or equal to 2.

[0160] Moreover, taking the kth row of sub-pixels as an example, in order to make the threshold compensation stages T2 corresponding to the rows of sub-pixels of the first reset control signal line REL1 electrically connected to each other the same, the falling edge of re1_k-1 can also be adjusted, for example, the falling edge of re1_k-1 can be adjusted to after the falling edge of em1_k.

[0161] Furthermore, the structures shown in FIG13a and FIG13b can also support multiple display sub-areas. In a specific implementation, the multiple first reset shift register units include multiple first reset register groups, each corresponding one-to-one to the multiple display sub-areas, and each coupled to the first reset control signal line REL1 in the corresponding display sub-area. Furthermore, the multiple first reset register groups correspond one-to-one to the multiple first reset trigger signal terminals, and the input signal terminals of the first-stage first reset shift register units in the first reset register groups are coupled to the corresponding first reset trigger signal terminals. Alternatively, the multiple first reset register groups correspond to one first reset trigger signal terminal, the input signal terminal of the first-stage first reset shift register unit in the first reset register group of the multiple first reset register groups is coupled to the first reset register group, and the driving output terminal of the last-stage first reset shift register unit of the previous first reset register group of two adjacent first reset register groups is coupled to the input signal terminal of the first-stage first reset shift register unit of the next first reset register group.

[0162] For example, as shown in Figures 13a and 13b, sub-areas Aa and Ab are displayed. Sub-area Aa corresponds to the scan register group 230a, the first reset register group 221a, the fourth reset register group 224a, the fourth light-emitting register group 214a, and the second light-emitting register group 212a. Sub-area Ab corresponds to the scan register group 230b, the first reset register group 221b, the fourth reset register group 224b, the fourth light-emitting register group 214b, and the second light-emitting register group 212b. The first reset shift register unit GRE1_1 is coupled to the first reset trigger signal terminal RSTV1a, and the first reset shift register unit GRE1_(k+2) / 2 is coupled to the first reset trigger signal terminal RSTV1b. Furthermore, the signal timing diagram corresponding to the structures shown in Figures 13a and 13b is shown in Figure 14. The specific working process thereof can be referred to the description in the above embodiment and will not be repeated here.

[0163] The present disclosure provides some further structural diagrams of display panels, as shown in FIG15a, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0164] In the disclosed embodiment, as shown in Figures 15a and 15b, the pixel control circuit may also include a second reset control circuit 150, and the drive control circuit may include a third reset drive control circuit, the third reset drive control circuit including a plurality of third reset shift register units GRE3_1 to GRE3_H (H is an integer greater than 0). Furthermore, the shift register unit includes a third reset shift register unit. The control signal line includes a second reset control signal line REL2. The second reset control signal lines REL2 corresponding to two adjacent rows of sub-pixels are coupled to each other and then coupled to one of the plurality of third reset shift register units. For example, as shown in Figures 15a to 16, the second reset control signal line REL2_k-1 corresponding to the sub-pixel in the k-1th row and the second reset control signal line REL2_k corresponding to the sub-pixel in the kth row are coupled to each other and then coupled to the driving output end of the third reset shift register unit GRE3_k / 2, and the second reset control signal re2_k-1 is input to the second reset control signal line REL2_k-1 and the second reset control signal line REL2_k through the third reset shift register unit GRE3_k / 2. Furthermore, the second reset control signal line REL2_k+1 corresponding to the sub-pixels in the k+1th row and the second reset control signal line REL2_k+2 corresponding to the sub-pixels in the k+2th row are coupled to each other and then coupled to the driving output terminal of the third reset shift register unit GRE3_(k+2) / 2. The second reset control signal re2_k+1 is input to the second reset control signal line REL2_k+1 and the second reset control signal line REL2_k+2 via the third reset shift register unit GRE3_(k+2) / 2. This configuration can reduce the number of third reset shift register units by half. Of course, in practical applications, the second reset control signal lines REL2 corresponding to three, four, or more adjacent rows of sub-pixels can also be coupled to each other and then coupled to one third reset shift register unit, but this is not limited here.

[0165] It should be noted that, taking the sub-pixels in the k-1th and k-th rows as an example, during the threshold compensation phase T2_k-1 corresponding to the sub-pixels in the k-1th row, both the first emission control transistor M2 and the first reset control transistor M4 are turned on, i.e., the period during which both the em1_k-1 and re1_k-1 signals are valid signals (e.g., high level). Furthermore, during the signal writing phase T3_k-1, the ga_k-1 signal is valid (e.g., high level), and the data writing transistor M1 is turned on. During the threshold compensation phase T2_k corresponding to the sub-pixels in the k-th row, both the first emission control transistor M2 and the first reset control transistor M4 are turned on, i.e., the period during which both the em1_k and re1_k signals are valid signals (e.g., high level). Furthermore, during the signal writing phase T3_k, the ga_k signal is valid (e.g., high level), and the data writing transistor M1 is turned on. Therefore, if the rising edge of ga_k+q corresponding to the sub-pixel in the k+qth row is after the falling edge of re1_k corresponding to the sub-pixel in the kth row, but does not affect the normal operation of other timing sequences, the first reset control signal line REL1 corresponding to the sub-pixel in the kth row to the first reset control signal line REL2 corresponding to the sub-pixel in the k+qth row can be electrically connected to each other; where q is an integer greater than or equal to 2. In addition, if the rising edge of em1_k+w corresponding to the sub-pixel in the k+wth row is before the falling edge of re2_k corresponding to the sub-pixel in the kth row during the initialization phase T1, but does not affect the normal operation of other timing sequences, the second reset control signal line REL2 corresponding to the sub-pixel in the kth row to the second reset control signal line REL3 corresponding to the sub-pixel in the k+wth row can be electrically connected to each other; where w is an integer greater than or equal to 2.

[0166] Moreover, taking the kth row of sub-pixels as an example, in order to make the threshold compensation stages T2 corresponding to the rows of sub-pixels of the first reset control signal line REL1 electrically connected to each other the same, the falling edge of re1_k-1 can also be adjusted, for example, the falling edge of re1_k-1 can be adjusted to after the falling edge of em1_k.

[0167] Furthermore, the structures shown in FIG15a and FIG15b can also support multiple display sub-areas. In a specific implementation, the multiple third reset shift register units include multiple third reset register groups, each corresponding one-to-one to the multiple display sub-areas, and each coupled to the second reset control signal line REL2 in the corresponding display sub-area. Furthermore, the multiple third reset register groups correspond one-to-one to the multiple third reset trigger signal terminals, and the input signal terminal of the first-stage third reset shift register unit in the third reset register group is coupled to the corresponding third reset trigger signal terminal. Alternatively, the multiple third reset register groups correspond to one third reset trigger signal terminal, the input signal terminal of the first-stage third reset shift register unit in the first third reset register group of the multiple third reset register groups is coupled to the third reset register group, and the driving output terminal of the last-stage third reset shift register unit in the previous third reset register group of two adjacent third reset register groups is coupled to the input signal terminal of the first-stage third reset shift register unit in the next third reset register group.

[0168] For example, as shown in Figures 15a and 15b, sub-areas Aa and Ab are displayed. Sub-area Aa corresponds to the scan register group 230a, the first reset register group 221a, the third reset register group 223a, the fourth light-emitting register group 214a, and the second light-emitting register group 212a. Sub-area Ab corresponds to the scan register group 230b, the first reset register group 221b, the third reset register group 223b, the fourth light-emitting register group 214b, and the second light-emitting register group 212b. The third reset shift register unit GRE3_1 is coupled to the third reset trigger signal terminal RSTV3. Furthermore, the signal timing diagram corresponding to the structures shown in Figures 15a and 15b is shown in Figure 16. The specific operation process can be referred to the description in the above embodiment and will not be repeated here.

[0169] The present disclosure provides some further structural diagrams of display panels, as shown in FIG17a, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0170] In the embodiment of the present disclosure, as shown in Figures 17a and 17b , the pixel control circuit may also include a first reset control circuit 140, a second reset control circuit 150, and a second light-emitting control circuit 130. For example, as shown in Figures 17a and 17b , the first reset control signal line REL1_k-1 corresponding to the sub-pixels in the k-1th row and the first reset control signal line REL1_k corresponding to the sub-pixels in the kth row are coupled to each other and then coupled to the driving output terminal of the first reset shift register unit GRE1_k / 2. Furthermore, the first reset control signal line REL1_k+1 corresponding to the sub-pixels in the k+1th row and the first reset control signal line REL1_k+2 corresponding to the sub-pixels in the k+2th row are coupled to each other and then coupled to the driving output terminal of the first reset shift register unit GRE1_(k+2) / 2. The second reset control signal line REL2_k-1 corresponding to the sub-pixels in the k-1th row and the second reset control signal line REL2_k corresponding to the sub-pixels in the kth row are coupled to each other and then to the driving output terminal of the third reset shift register unit GRE3_k / 2. Furthermore, the second reset control signal line REL2_k+1 corresponding to the sub-pixels in the k+1th row and the second reset control signal line REL2_k+2 corresponding to the sub-pixels in the k+2th row are coupled to each other and then to the driving output terminal of the third reset shift register unit GRE3_(k+2) / 2. The second emission control signal line EML2_k-1 corresponding to the sub-pixels in the k-1th row and the second emission control signal line EML2_k corresponding to the sub-pixels in the kth row are coupled to each other and then to the driving output terminal of the third emission shift register unit GEM3_k / 2. Furthermore, the second light-emitting control signal line EML2_k+1 corresponding to the sub-pixels in the k+1th row and the second light-emitting control signal line EML2_k+2 corresponding to the sub-pixels in the k+2th row are coupled to each other and then to the driving output terminal of the third light-emitting shift register unit GEM3_(k+2) / 2. For the remaining details, refer to the description in the above embodiment and are not repeated here.

[0171] The present disclosure provides some further structural diagrams of display panels, as shown in FIG18a, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0172] In the embodiment of the present disclosure, as shown in Figures 18a and 18b, the pixel control circuit may also include a first reset control circuit 140 and a second light emitting control circuit 130. The specific working process can refer to the description in the above embodiment and will not be repeated here.

[0173] The present disclosure provides some further structural diagrams of display panels, as shown in Figure 19a, which are variations of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0174] In the embodiment of the present disclosure, as shown in Figures 19a and 19b, the pixel control circuit may also include a first reset control circuit 140, a first light emitting control circuit 120, and a second light emitting control circuit 130. The specific working process can refer to the description in the above embodiment and will not be repeated here.

[0175] Of course, the pixel control circuit may also include the first reset control circuit 140 , the second reset control circuit 150 , the first light emitting control circuit 120 and the second light emitting control circuit 130 , which is not limited here.

[0176] Based on the same disclosed concept, the present disclosure also provides a display device, including the display panel provided in the present disclosure. The principles of this display device are similar to those of the aforementioned display panel, so the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be repeated here.

[0177] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0178] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0179] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display panel, comprising: Display area and non-display area; The display area includes: a plurality of sub-pixels and a plurality of control signal lines, wherein each of the plurality of sub-pixels includes a pixel circuit, and the pixel circuit includes: a light-emitting device, a driving transistor, a data writing circuit, and a pixel control circuit; the driving transistor is coupled to the data writing circuit and the pixel control circuit respectively, and the data writing circuit is configured to provide a data voltage at a data signal terminal to a gate of the driving transistor in response to a scanning signal at a scanning signal terminal; the pixel control circuit is configured to control the driving transistor to generate a driving current for driving the light-emitting device to emit light; The pixel circuits in at least one row of sub-pixels among the plurality of sub-pixels are coupled to one control signal line among the plurality of control signal lines, and the control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to each other; The non-display area includes: a driving control circuit, the driving control circuit includes a plurality of shift register units, mutually coupled control signal lines are coupled to a shift register unit among the plurality of shift register units, and the shift register unit is configured to transmit a signal to the pixel circuit through the control signal line.

2. The display panel according to claim 1, wherein: The pixel circuit comprises: a first light emitting control circuit, the first light emitting control circuit is coupled to the first electrode of the driving transistor, the first light emitting control signal terminal and the first power supply terminal, the first light emitting control circuit is configured to respond to the first light emitting control signal of the first light emitting control signal terminal and provide the signal of the first power supply terminal to the first electrode of the driving transistor; The display area further includes: a plurality of first light emitting control signal lines, and a first light emitting control signal terminal of a pixel circuit in at least one row of sub-pixels among the plurality of sub-pixels is coupled to a first light emitting control signal line among the plurality of first light emitting control signal lines.

3. The display panel according to claim 2, wherein: The pixel control circuit includes the first light emitting control circuit, the drive control circuit includes: a first light emitting drive control circuit, the first light emitting drive control circuit includes a plurality of first light emitting shift register units, the shift register units include the first light emitting shift register units, and the control signal line includes the first light emitting control signal line; The first light emitting control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to each other and then coupled to one of the first light emitting shift register units among the plurality of first light emitting shift register units.

4. The display panel according to claim 3, wherein: The display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along the column direction of the sub-pixels, the plurality of first light-emitting shift register units include a plurality of first light-emitting register groups, the plurality of first light-emitting register groups correspond to the plurality of display sub-areas one by one, and the plurality of first light-emitting register groups are coupled to the first light-emitting control signal lines in the corresponding display sub-areas; The multiple first light-emitting register groups correspond one-to-one to the multiple first light-emitting trigger signal terminals, and the input signal terminal of the first-level first light-emitting shift register unit in the first light-emitting register group is coupled to the corresponding first light-emitting trigger signal terminal; or, the multiple first light-emitting register groups correspond to one first light-emitting trigger signal terminal, the input signal terminal of the first-level first light-emitting shift register unit in the first first light-emitting register group of the multiple first light-emitting register groups is coupled to the first light-emitting trigger signal terminal, and the driving output terminal of the last-level first light-emitting shift register unit of the previous first light-emitting register group of two adjacent first light-emitting register groups is coupled to the input signal terminal of the first-level first light-emitting shift register unit of the next first light-emitting register group.

5. The display panel according to claim 2, wherein: The non-display area further includes: a second light emitting drive control circuit, wherein the second light emitting drive control circuit includes a plurality of second light emitting shift register units; The first light emitting control signal line corresponding to the pixel circuit in each row of sub-pixels in the plurality of sub-pixels is coupled to one of the first light emitting shift register units among the plurality of second light emitting shift register units.

6. The display panel according to claim 5, wherein: The display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along the column direction of the sub-pixels, the plurality of second light-emitting shift register units include a plurality of second light-emitting register groups, the plurality of second light-emitting register groups correspond to the plurality of display sub-areas one by one, and the plurality of second light-emitting register groups are coupled to the first light-emitting control signal lines in the corresponding display sub-areas; The multiple second light-emitting register groups correspond one-to-one to the multiple second light-emitting trigger signal terminals, and the input signal terminal of the first-level second light-emitting shift register unit in the second light-emitting register group is coupled to the corresponding second light-emitting trigger signal terminal; or, the multiple second light-emitting register groups correspond to one second light-emitting trigger signal terminal, the input signal terminal of the first-level second light-emitting shift register unit in the first second light-emitting register group of the multiple second light-emitting register groups is coupled to the second light-emitting trigger signal terminal, and the driving output terminal of the last-level second light-emitting shift register unit of the upper second light-emitting register group of two adjacent second light-emitting register groups is coupled to the input signal terminal of the first-level second light-emitting shift register unit of the next second light-emitting register group.

7. The display panel according to any one of claims 1 to 6, wherein: The pixel circuit comprises: a second light emitting control circuit, the second light emitting control circuit is coupled to the second electrode of the driving transistor, the light emitting device and a second light emitting control signal terminal, the second light emitting control circuit is configured to conduct the second electrode of the driving transistor and the light emitting device in response to a second light emitting control signal at the second light emitting control signal terminal; The display area further includes: a plurality of second light emitting control signal lines, and the second light emitting control signal terminal of the pixel circuit in at least one row of sub-pixels among the plurality of sub-pixels is coupled to a second light emitting control signal line among the plurality of second light emitting control signal lines.

8. The display panel according to claim 7, wherein: The pixel control circuit includes the second light emitting control circuit, the drive control circuit includes: a third light emitting drive control circuit, the third light emitting drive control circuit includes a plurality of third light emitting shift register units, and the shift register unit includes the third light emitting shift register unit; The control signal line includes the second light emitting control signal line. The second light emitting control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to one of the third light emitting shift register units after being coupled to each other.

9. The display panel according to claim 8, wherein: The display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along a column direction of the sub-pixels, the plurality of third light-emitting shift register units include a plurality of third light-emitting register groups, the plurality of third light-emitting register groups correspond to the plurality of display sub-areas one by one, and the plurality of third light-emitting register groups are coupled to the second light-emitting control signal lines in the corresponding display sub-areas; The multiple third light-emitting register groups correspond one-to-one to multiple third light-emitting trigger signal terminals, and the input signal terminal of the first-level third light-emitting shift register unit in the third light-emitting register group is coupled to the corresponding third light-emitting trigger signal terminal; or, the multiple third light-emitting register groups correspond to a third light-emitting trigger signal terminal, the input signal terminal of the first-level third light-emitting shift register unit in the first third light-emitting register group of the multiple third light-emitting register groups is coupled to the third light-emitting trigger signal terminal, and the driving output terminal of the last-level third light-emitting shift register unit of the upper third light-emitting register group of two adjacent third light-emitting register groups is coupled to the input signal terminal of the first-level third light-emitting shift register unit of the next third light-emitting register group.

10. The display panel according to claim 7, wherein: The non-display area further includes: a fourth light emitting drive control circuit, the fourth light emitting drive control circuit including a plurality of fourth light emitting shift register units; The second light emitting control signal line corresponding to the pixel circuit in each row of sub-pixels in the plurality of sub-pixels is One of the plurality of fourth light emitting shift register units is coupled.

11. The display panel according to claim 10, wherein: The display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along the column direction of the sub-pixels, the plurality of fourth light-emitting shift register units include a plurality of fourth light-emitting register groups, the plurality of fourth light-emitting register groups correspond to the plurality of display sub-areas one by one, and the plurality of fourth light-emitting register groups are coupled to the second light-emitting control signal lines in the corresponding display sub-areas; The multiple fourth light-emitting register groups correspond one-to-one to the multiple fourth light-emitting trigger signal terminals, and the input signal terminal of the first-level fourth light-emitting shift register unit in the fourth light-emitting register group is coupled to the corresponding fourth light-emitting trigger signal terminal; or, the multiple fourth light-emitting register groups correspond to a fourth light-emitting trigger signal terminal, the input signal terminal of the first-level fourth light-emitting shift register unit in the first fourth light-emitting register group of the multiple fourth light-emitting register groups is coupled to the fourth light-emitting trigger signal terminal, and the driving output terminal of the last-level fourth light-emitting shift register unit of the previous fourth light-emitting register group of two adjacent fourth light-emitting register groups is coupled to the input signal terminal of the first-level fourth light-emitting shift register unit of the next fourth light-emitting register group.

12. The display panel according to any one of claims 1 to 11, wherein: The pixel circuit comprises: a first reset control circuit, the first reset control circuit is coupled to the gate of the driving transistor, a first reset control signal terminal and a reference signal terminal, the first reset control circuit is configured to respond to a first reset control signal of the first reset control signal terminal and provide a signal of the reference signal terminal to the gate of the driving transistor; The display area further includes: a plurality of first reset control signal lines, and a first reset control signal terminal of a pixel circuit in at least one row of sub-pixels among the plurality of sub-pixels is coupled to a first reset control signal line among the plurality of first reset control signal lines.

13. The display panel according to claim 12, wherein: The pixel control circuit includes the first reset control circuit, the drive control circuit includes: a first reset drive control circuit, the first reset drive control circuit includes a plurality of first reset shift register units, the shift register units include the first reset shift register unit; The control signal line includes the first reset control signal line. The first reset control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to one of the first reset shift register units after being coupled to each other.

14. The display panel according to claim 13, wherein: The display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along the column direction of the sub-pixels, the plurality of first reset shift register units include a plurality of first reset register groups, the plurality of first reset register groups correspond to the plurality of display sub-areas one by one, and the plurality of first reset register groups are coupled to the first reset control signal lines in the corresponding display sub-areas; The multiple first reset register groups correspond one-to-one to the multiple first reset trigger signal terminals, and the input signal terminal of the first-level first reset shift register unit in the first reset register group is coupled to the corresponding first reset trigger signal terminal; or, the multiple first reset register groups correspond to a first reset trigger signal terminal, the input signal terminal of the first-level first reset shift register unit in the first first reset register group of the multiple first reset register groups is coupled to the first reset register group, and the driving output terminal of the last-level first reset shift register unit of the previous first reset register group of two adjacent first reset register groups is coupled to the input signal terminal of the first-level first reset shift register unit of the next first reset register group.

15. The display panel according to claim 12, wherein: The non-display area further includes: a second reset drive control circuit, the second reset drive control circuit including a plurality of second reset shift register units; The first reset control signal line corresponding to the pixel circuit in each row of sub-pixels in the plurality of sub-pixels is coupled to one of the first reset shift register units among the plurality of second reset shift register units.

16. The display panel according to claim 15, wherein: The display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along the column direction of the sub-pixels, the plurality of second reset shift register units include a plurality of second reset register groups, the plurality of second reset register groups correspond to the plurality of display sub-areas one by one, and the plurality of second reset register groups are coupled to the first reset control signal lines in the corresponding display sub-areas; The multiple second reset register groups correspond one-to-one to the multiple second reset trigger signal terminals, and the input signal terminal of the first-level second reset shift register unit in the second reset register group is coupled to the corresponding second reset trigger signal terminal; or, the multiple second reset register groups correspond to a second reset trigger signal terminal, the input signal terminal of the first-level second reset shift register unit in the first second reset register group of the multiple second reset register groups is coupled to the second reset register group, and the driving output terminal of the last-level second reset shift register unit of the previous second reset register group in two adjacent second reset register groups is coupled to the input signal terminal of the first-level second reset shift register unit of the next second reset register group.

17. The display panel according to any one of claims 1 to 16, wherein: The pixel circuit comprises: a second reset control circuit, the second reset control circuit is coupled to the second electrode of the driving transistor, the second reset control signal terminal and the first initialization signal terminal, the second reset control circuit is configured to respond to the second reset control signal of the second reset control signal terminal and provide the signal of the first initialization signal terminal to the second electrode of the driving transistor; The display area further includes: a plurality of second reset control signal lines, and the second reset control signal terminal of the pixel circuit in at least one row of sub-pixels among the plurality of sub-pixels is coupled to a second reset control signal line among the plurality of second reset control signal lines.

18. The display panel according to claim 17, wherein: The pixel control circuit includes the second reset control circuit, the drive control circuit includes: a third reset drive control circuit, the third reset drive control circuit includes a plurality of third reset shift register units, and the shift register unit includes the third reset shift register unit; The control signal line includes the second reset control signal line. The second reset control signal lines corresponding to at least two adjacent rows of sub-pixels are coupled to one of the third reset shift register units after being coupled to each other.

19. The display panel according to claim 18, wherein: The display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along the column direction of the sub-pixels, the plurality of third reset shift register units include a plurality of third reset register groups, the plurality of third reset register groups correspond to the plurality of display sub-areas one by one, and the plurality of third reset register groups are coupled to the second reset control signal lines in the corresponding display sub-areas; The multiple third reset register groups correspond one-to-one to multiple third reset trigger signal terminals, and the input signal terminal of the first-level third reset shift register unit in the third reset register group is coupled to the corresponding third reset trigger signal terminal; or, the multiple third reset register groups correspond to a third reset trigger signal terminal, the input signal terminal of the first-level third reset shift register unit in the first third reset register group of the multiple third reset register groups is coupled to the third reset register group, and the driving output terminal of the last-level third reset shift register unit of the previous third reset register group of two adjacent third reset register groups is coupled to the input signal terminal of the first-level third reset shift register unit of the next third reset register group.

20. The display panel according to claim 17, wherein: The non-display area further includes: a fourth reset drive control circuit, the fourth reset drive control circuit including a plurality of fourth reset shift register units; The second reset control signal line corresponding to the pixel circuit in each row of sub-pixels in the plurality of sub-pixels is coupled to one of the plurality of fourth reset shift register units.

21. The display panel according to claim 20, wherein: The display area includes a plurality of display sub-areas, the plurality of display sub-areas are arranged along the column direction of the sub-pixels, the plurality of fourth reset shift register units include a plurality of fourth reset register groups, the plurality of fourth reset register groups correspond to the plurality of display sub-areas one by one, and the plurality of fourth reset register groups are coupled to the second reset control signal lines in the corresponding display sub-areas; The multiple fourth reset register groups correspond one-to-one to the multiple fourth reset trigger signal terminals, and the input signal terminal of the first-level fourth reset shift register unit in the fourth reset register group is coupled to the corresponding fourth reset trigger signal terminal; or, the multiple fourth reset register groups correspond to a fourth reset trigger signal terminal, the input signal terminal of the first-level fourth reset shift register unit in the first fourth reset register group of the multiple fourth reset register groups is coupled to the fourth reset register group, and the driving output terminal of the last-level fourth reset shift register unit of the previous fourth reset register group of two adjacent fourth reset register groups is coupled to the input signal terminal of the first-level fourth reset shift register unit of the next fourth reset register group.

22. The display panel according to any one of claims 1 to 21, wherein: The pixel circuit comprises: a third reset control circuit, the third reset control circuit is coupled to the light emitting device, a third reset control signal terminal and a second initialization signal terminal, the third reset control circuit is configured to respond to a third reset control signal of the third reset control signal terminal and provide a signal of the second initialization signal terminal to the light emitting device; The display area further includes: a plurality of third reset control signal lines, and the third reset control signal terminal of the pixel circuit in a row of sub-pixels among the plurality of sub-pixels is coupled to a third reset control signal line among the plurality of third reset control signal lines.

23. The display panel according to claim 22, wherein: The third reset control signal terminal and the second reset control signal terminal are connected to the same signal, and the third reset control signal line and the second reset control signal line are the same signal line.

24. The display panel according to any one of claims 1 to 23, wherein: The pixel circuit further includes: at least one of a first capacitor and a second capacitor; A first end of the first capacitor is coupled to the gate electrode of the driving transistor, and a second end of the first capacitor is coupled to the second electrode of the driving transistor; A first terminal of the second capacitor is coupled to the second electrode of the driving transistor, and a second terminal of the second capacitor is coupled to a fixed voltage terminal.

25. The display panel according to claim 24, wherein: The light emitting device is also coupled to a second power supply terminal; The fixed voltage terminal is connected to the same signal as one of the first power terminal, the reference signal terminal, the first initialization signal terminal, the second initialization signal terminal and the second power terminal.

26. A display device comprising the display panel according to any one of claims 1 to 25.

Images