Topcon battery and preparation method therefor

Abstract

The present application provides a TOPCon battery and a preparation method therefor. The TOPCon battery comprises: a semiconductor substrate layer; a first tunneling oxide layer, which is located on one side of a first surface of the semiconductor substrate layer; a first doped semiconductor layer, which comprises a first doped semiconductor sub-layer and a second doped semiconductor sub-layer, wherein the first doped semiconductor sub-layer is located on the side of the first tunneling oxide layer away from the semiconductor substrate layer, the second doped semiconductor sub-layer is located between the first doped semiconductor sub-layer and the first tunneling oxide layer, the projection area of the first doped semiconductor sub-layer on the semiconductor substrate layer is smaller than the projection area of the second doped semiconductor sub-layer on the semiconductor substrate layer, and the thickness of the second doped semiconductor sub-layer is less than the thickness of the first doped semiconductor sub-layer; and a first electrode, which is located on the side of the first doped semiconductor sub-layer away from the semiconductor substrate layer. The TOPCon battery provided in the present application has strong conductivity and high photoelectric conversion efficiency.

Description

A TOPCon battery and its preparation method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on August 31, 2023, with application number 202311117882.5 and invention name “A TOPCon battery and its preparation method”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of solar energy technology, and in particular to a TOPCon cell and a preparation method thereof. Background Art

[0004] The process for preparing TOPCon cells is one of the promising methods for achieving high efficiency in the production of crystalline silicon solar cells. In TOPCon cells, a tunneling passivation contact structure is formed on the back of the silicon substrate using a stacked structure of a silicon oxide layer and a doped amorphous silicon layer or a doped polycrystalline silicon layer for surface passivation. The tunneling passivation contact structure utilizes the contact between two different semiconductors to form a band bending, which prevents minority carriers from passing through. The majority carriers can tunnel through the ultra-thin oxide layer and undergo short / multi-channel transport in the polycrystalline silicon layer, where they are collected by the electrode, thereby improving the cell's open-circuit voltage, short-circuit current, and photoelectric conversion efficiency. On the front of the silicon substrate, a doped layer is formed by boron diffusion. Because boron diffusion has a low solid solubility in the silicon substrate, it is often necessary to form a good contact area between the doped layer and the metal electrode at high temperature for a long time. This allows for stable contact control. However, the non-contact area provides more recombination centers, which poses a significant bottleneck to further efficiency improvements.

[0005] Currently, the TOPCon cell manufacturing process is limited by equipment configuration, and a full-surface passivation contact structure is primarily formed on the front side of the TOPCon cell. Specifically, a silicon oxide layer and a doped semiconductor layer are stacked. Because the doped semiconductor layer has a relatively high light absorption coefficient, when some light is transmitted to the doped semiconductor layer, it is easily absorbed by the doped semiconductor layer and cannot form carrier collection. Although thinning the doped semiconductor layer can reduce the probability of light absorption, it can also lead to poor contact problems such as burn-through when making ohmic contact with the metal electrode, thereby affecting the conductivity of the TOPCon cell.

[0006] Therefore, there is an urgent need to further optimize the structure of TOPCon batteries.

[0007] Summary of the Invention

[0008] Therefore, the technical problem to be solved by the present application is to overcome the defects of low photoelectric conversion efficiency and poor conductivity of TOPCon cells in the prior art, thereby providing a TOPCon cell and a preparation method thereof.

[0009] The present application provides a TOPCon battery, comprising: a semiconductor substrate layer, the semiconductor substrate layer having a first surface and a second surface arranged opposite to each other; a first tunneling oxide layer, located on one side of the first surface of a portion of the semiconductor substrate layer; a first doped semiconductor layer, the first doped semiconductor layer comprising a first sub-doped semiconductor layer and a second sub-doped semiconductor layer; the first sub-doped semiconductor layer is located on a side of the first tunneling oxide layer away from the semiconductor substrate layer; the second sub-doped semiconductor layer is located between the first sub-doped semiconductor layer and the first tunneling oxide layer; a projected area of ​​the first sub-doped semiconductor layer on the semiconductor substrate layer is smaller than a projected area of ​​the second sub-doped semiconductor layer on the semiconductor substrate layer, and a thickness of the second sub-doped semiconductor layer is smaller than a thickness of the first sub-doped semiconductor layer; and a first electrode, located on a side of the first sub-doped semiconductor layer away from the semiconductor substrate layer.

[0010] Optionally, the width of the first sub-doped semiconductor layer is 45 μm-65 μm, and the width of the second sub-doped semiconductor layer is 70 μm-90 μm.

[0011] Optionally, the thickness of the first doped semiconductor layer is 100 nm-200 nm; the thickness of the first sub-doped semiconductor layer is 80 nm-190 nm; and the thickness of the second sub-doped semiconductor layer is 10 nm-20 nm.

[0012] Optionally, the square resistance of the first sub-doped semiconductor layer is 70Ω-120Ω, and the square resistance of the second sub-doped semiconductor layer is 130Ω-160Ω.

[0013] Optionally, it also includes: an interconnection electrode, located on a side of the first electrode away from the semiconductor substrate layer, used to connect the first electrodes in the same column into one; the interconnection electrode includes a copper electrode; the first electrode includes a tin-bismuth-silver alloy electrode.

[0014] Optionally, the height of the first electrode is 5 μm-10 μm, and the width of the first electrode is 15 μm-25 μm.

[0015] Optionally, it also includes: an intrinsic doped layer, located on the first surface of the semiconductor substrate layer, and located between the first tunneling oxide layer and the semiconductor substrate layer; a passivation layer; located on the surface of a part of the intrinsic doped layer away from the semiconductor substrate layer, and surrounding the first doped semiconductor layer and the first tunneling oxide layer; a first anti-reflection layer; located on the side of the passivation layer away from the semiconductor substrate layer; and further includes: a second tunneling oxide layer, located on the second surface of the semiconductor substrate layer; a second doped semiconductor layer; located on the side of the second tunneling oxide layer away from the semiconductor substrate layer; a second anti-reflection layer; located on the side of the second doped semiconductor layer away from the semiconductor substrate layer; a second electrode; located on the side of the second anti-reflection layer away from the semiconductor substrate layer; wherein the conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer; the passivation layer includes an aluminum oxide layer; and the first anti-reflection layer includes Si x N y layer or SiON y layer; the second anti-reflection layer comprises Si x N y layer or SiON y layer.

[0016] The present application provides a method for preparing a TOPCon battery, comprising: providing a semiconductor substrate layer; the semiconductor substrate layer having a first surface and a second surface arranged opposite to each other; forming a first tunneling oxide layer on one side of the first surface of a portion of the semiconductor substrate layer; forming a first doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer; the first doped semiconductor layer comprising a first sub-doped semiconductor layer and a second sub-doped semiconductor layer; the step of forming the first doped semiconductor layer comprising: forming a first sub-doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer; forming a second sub-doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer, the second sub-doped semiconductor layer being located between the first sub-doped semiconductor layer and the first tunneling oxide layer; a projected area of ​​the first sub-doped semiconductor layer on the semiconductor substrate layer being smaller than a projected area of ​​the second sub-doped semiconductor layer on the semiconductor substrate layer, and a thickness of the second sub-doped semiconductor layer being smaller than a thickness of the first sub-doped semiconductor layer; and forming a first electrode on a side of the first sub-doped semiconductor layer away from the semiconductor substrate layer.

[0017] Optionally, before forming the first tunneling oxide layer on one side of the first surface of a portion of the semiconductor substrate layer, a first initial tunneling oxide layer is formed on one side of the first surface of the semiconductor substrate layer; before forming the first initial tunneling oxide layer, an intrinsic doped layer is formed on the first surface of the semiconductor substrate layer by diffusion treatment; after forming the first initial tunneling oxide layer, before forming the first doped semiconductor layer on the side of the first tunneling oxide layer away from the semiconductor substrate layer, a first intrinsic semiconductor layer is formed on the side of the first initial tunneling oxide layer away from the semiconductor substrate layer; performing boron diffusion treatment on the first intrinsic semiconductor layer to form a first initial doped semiconductor layer; the step of forming a first sub-doped semiconductor layer on the side of the first tunneling oxide layer away from the semiconductor substrate layer includes: providing a first mask, the first mask covering part of the first initial doped semiconductor layer; performing a first cleaning treatment on the area of ​​the first initial doped semiconductor layer not covered by the first mask to obtain a first sub-doped semiconductor layer and a second sub-initial doped semiconductor layer.

[0018] Optionally, the first mask includes an alkali-resistant wax print mask; the first cleaning treatment adopts alkali cleaning, the time of the first cleaning treatment is 250s-380s; the temperature of the first cleaning treatment is 70°C-80°C.

[0019] Optionally, after forming a first sub-doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer, a second sub-doped semiconductor layer is formed on a side of the first tunneling oxide layer away from the semiconductor substrate layer; the step of forming the second sub-doped semiconductor layer includes: providing a second mask, the second mask covering a portion of the second sub-initial doped semiconductor layer; performing a second cleaning treatment on an area of ​​the second sub-initial doped semiconductor layer not covered by the second mask to obtain a second sub-doped semiconductor layer; the second mask includes an alkali-resistant wax printing mask; the second cleaning treatment adopts alkali washing, and the time of the second cleaning treatment is 150s-200s; the temperature of the second cleaning treatment is 60℃-70℃.

[0020] Optionally, after forming the second sub-doped semiconductor layer, the first mask and the second mask are removed; in the process of removing the first mask and the second mask, a portion of the first initial tunneling oxide layer is also removed to expose a portion of the intrinsic doping layer; the first mask and the second mask are removed using an acid solution, the acid solution including an HF solution, and the mass percentage concentration of the acid solution is 2%-6%.

[0021] Optionally, after forming the first doped semiconductor layer, a passivation layer is formed on the surface of a portion of the intrinsic doped layer away from the semiconductor substrate layer, the passivation layer surrounds the first doped semiconductor layer and the first tunneling oxide layer; a first anti-reflection layer is formed on the side of the passivation layer away from the semiconductor substrate layer; after forming the first anti-reflection layer, a first electrode is formed on the side of the first sub-doped semiconductor layer away from the semiconductor substrate layer; further comprising: forming an interconnect electrode on the side of the first electrode away from the semiconductor substrate layer, for connecting the first electrodes in the same column into one; the process for forming the passivation layer includes an atomic layer deposition process; the process for forming the first anti-reflection layer includes a plasma enhanced chemical vapor deposition process.

[0022] Optionally, it also includes: forming a second tunneling oxide layer on the second surface of the semiconductor substrate layer; forming a second doped semiconductor layer on a side of the second tunneling oxide layer away from the semiconductor substrate layer; wherein the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer; before forming the second doped semiconductor layer on the side of the second tunneling oxide layer away from the semiconductor substrate layer, forming a second intrinsic semiconductor layer on a side of the second tunneling oxide layer away from the semiconductor substrate layer; the step of forming the second doped semiconductor layer includes: performing diffusion annealing treatment on the second intrinsic semiconductor layer, and the second intrinsic semiconductor layer is transformed to form a second doped semiconductor layer; it also includes: forming a second anti-reflection layer on a side of the second doped semiconductor layer away from the semiconductor substrate layer; forming a second electrode on a side of the second anti-reflection layer away from the semiconductor substrate layer; the process of forming the second anti-reflection layer includes a plasma enhanced chemical vapor deposition process.

[0023] The technical solution of this application has the following advantages:

[0024] The present application provides a TOPCon battery, in which a first tunneling oxide layer is formed on the first surface of a portion of the semiconductor substrate layer, and the first tunneling oxide layer has the function of selectively passing carriers, which reduces the recombination probability of minority carriers and increases the collection probability of majority carriers, thereby improving the open circuit voltage; the first tunneling oxide layer can also serve as a barrier layer to prevent the doped atoms in the first doped semiconductor layer from diffusing to the semiconductor substrate layer; the first doped semiconductor layer includes a first sub-doped semiconductor layer and a second sub-doped semiconductor layer; wherein the first sub-doped semiconductor layer is located on the side of the first tunneling oxide layer away from the semiconductor substrate layer; and the first electrode is located on the side of the first sub-doped semiconductor layer away from the semiconductor substrate layer, so that the first electrode is in better contact with the first sub-doped semiconductor layer, allowing electrons to be transmitted to the first doped semiconductor layer, increasing the short-circuit current of the TOPCon battery, and at the same time reducing the recombination of the area on the first surface of the semiconductor substrate layer where the first tunneling oxide layer and the first doped semiconductor layer are not set, thereby improving the minority carrier lifetime and the probability of the semiconductor substrate layer absorbing light; in addition, due to the second sub-doping The semiconductor layer is located between the first sub-doped semiconductor layer and the first tunneling oxide layer. The projected area of ​​the first sub-doped semiconductor layer on the semiconductor substrate layer is smaller than the projected area of ​​the second sub-doped semiconductor layer on the semiconductor substrate layer, and the thickness of the second sub-doped semiconductor layer is smaller than the thickness of the first sub-doped semiconductor layer, which is equivalent to the small projected area of ​​the first sub-doped semiconductor layer on the semiconductor substrate layer. The first sub-doped semiconductor layer has a better effect of reducing optical absorption, thereby increasing the probability of light entering the semiconductor substrate layer and improving the photoelectric conversion efficiency of the TOPCon cell. The thickness of the first sub-doped semiconductor layer is large, which avoids poor contact between the first electrode and the first sub-doped semiconductor layer and improves the conductive performance of the TOPCon cell. The projected area of ​​the second sub-doped semiconductor layer on the semiconductor substrate layer is large, which can provide more conductive channels and further increase the conductive performance of the TOPCon cell. The thickness of the second sub-doped semiconductor layer is small, which reduces the light absorption probability of the second sub-doped semiconductor layer and increases the probability of light entering the semiconductor substrate layer, further improving the photoelectric conversion efficiency of the TOPCon cell. In summary, by dividing the first doped semiconductor layer into a first sub-doped semiconductor layer and a second sub-doped semiconductor layer, the light absorption efficiency of the semiconductor substrate layer is significantly increased, the photoelectric conversion efficiency of the TOPCon cell is increased by 0.366%, and the short-circuit current is increased by 0.222A. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] FIG1 is a schematic structural diagram of a TOPCon battery in the prior art;

[0027] FIG2 is a schematic structural diagram of a TOPCon battery provided in an embodiment of the present application;

[0028] FIG3 is a top view of a TOPCon battery provided in an embodiment of the present application;

[0029] FIG4 is a side view of a TOPCon battery provided in an embodiment of the present application;

[0030] FIG5 is a flow chart of a method for preparing a TOPCon battery according to an embodiment of the present application;

[0031] 6 to 15 are schematic structural diagrams of the method for preparing a TOPCon battery provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] Currently, referring to Figure 1, the TOPCon cell includes: a semiconductor substrate layer 1', the semiconductor substrate layer 1' having a first surface and a second surface arranged opposite to each other; a second tunneling oxide layer 9', located on the second surface of the semiconductor substrate layer 1'; a first doped semiconductor layer 4', located on the first surface of the semiconductor substrate layer 1'; a second doped semiconductor layer 11', located on the side of the second tunneling oxide layer 9' away from the semiconductor substrate layer 1'; a passivation layer 5', located on the side of the first doped semiconductor layer 4' away from the semiconductor substrate layer 1'; a first anti-reflection film 6', located on the side of the passivation layer 5' away from the semiconductor substrate layer 1'; a second anti-reflection film 12', located on the side of the second doped semiconductor layer 11' away from the semiconductor substrate layer 1'; a first electrode 7', located on the side of the first anti-reflection film 6' away from the semiconductor substrate layer 1'; and a second electrode 13'; located on the side of the second anti-reflection film 12' away from the semiconductor substrate layer 1'.

[0033] Since the first doped semiconductor layer 4' is provided on the entire surface, the first doped semiconductor layer 4' has a relatively high absorption coefficient for light. When part of the light is transmitted to the first doped semiconductor layer 4', it is easily absorbed by the doped semiconductor layer and cannot form carrier collection. Although thinning the first doped semiconductor layer 4' can reduce the probability of light absorption, it will lead to poor contact problems such as burn-through when making ohmic contact with the first electrode, thereby affecting the conductive performance of the TOPCon battery.

[0034] Therefore, there is an urgent need to further optimize the structure of TOPCon batteries.

[0035] The following will clearly and completely describe the technical solution of this application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0036] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0037] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0038] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0039] This embodiment provides a TOPCon battery, referring to Figure 2, including: a semiconductor substrate layer 1, the semiconductor substrate layer 1 having a first surface and a second surface arranged opposite to each other; a first tunneling oxide layer 2, located on one side of the first surface of a portion of the semiconductor substrate layer 1; a first doped semiconductor layer 4, the first doped semiconductor layer 4 including a first sub-doped semiconductor layer 41 and a second sub-doped semiconductor layer 42; the first sub-doped semiconductor layer 41 is located on a side of the first tunneling oxide layer 2 away from the semiconductor substrate layer 1; the second sub-doped semiconductor layer 42 is located between the first sub-doped semiconductor layer 41 and the first tunneling oxide layer 2; the projected area of ​​the first sub-doped semiconductor layer 41 on the semiconductor substrate layer 1 is smaller than the projected area of ​​the second sub-doped semiconductor layer 42 on the semiconductor substrate layer 1, and the thickness of the second sub-doped semiconductor layer 42 is smaller than the thickness of the first sub-doped semiconductor layer 41; a first electrode 7, located on a side of the first sub-doped semiconductor layer 41 away from the semiconductor substrate layer 1.

[0040] In this embodiment, a first tunneling oxide layer 2 is formed on a portion of the first surface of the semiconductor substrate layer 1. The first tunneling oxide layer 2 has the function of selectively passing carriers, reducing the recombination probability of minority carriers while increasing the collection probability of majority carriers, thereby improving the open circuit voltage; the first tunneling oxide layer 2 can also serve as a barrier layer to prevent the dopant atoms in the first doped semiconductor layer 4 from diffusing into the semiconductor substrate layer 1; the first doped semiconductor layer 4 includes a first sub-doped semiconductor layer 41 and a second sub-doped semiconductor layer 42; wherein the first sub-doped semiconductor layer 41 is located on a side of the first tunneling oxide layer 2 away from the semiconductor substrate layer 1; and the first electrode 7 is located on a side of the first sub-doped semiconductor layer 41 away from the semiconductor substrate layer 1, so that the first electrode 7 is in better contact with the first sub-doped semiconductor layer 41, allowing electrons to be transmitted to the first doped semiconductor layer 4, increasing the short-circuit current of the TOPCon battery, and at the same time reducing the recombination of the region of the first surface of the semiconductor substrate layer 1 where the first tunneling oxide layer 2 and the first doped semiconductor layer 4 are not provided, thereby improving the minority carrier lifetime and the probability of the semiconductor substrate layer absorbing light; in addition, since the second sub-doped semiconductor layer 42 is located on the side of the first doped semiconductor layer 41 away from the semiconductor substrate layer 1, the first electrode 7 is in better contact with the first sub-doped semiconductor layer 41, allowing electrons to be transmitted to the first doped semiconductor layer 4, thereby increasing the short-circuit current of the TOPCon battery, and reducing the recombination of the region of the first surface of the semiconductor substrate layer 1 where the first tunneling oxide layer 2 and the first doped semiconductor layer 4 are not provided, thereby improving the minority carrier lifetime and the probability of the semiconductor substrate layer absorbing light; Between the first sub-doped semiconductor layer 41 and the first tunneling oxide layer 2, the projected area of ​​the first sub-doped semiconductor layer 41 on the semiconductor substrate layer 1 is smaller than the projected area of ​​the second sub-doped semiconductor layer 42 on the semiconductor substrate layer 1, and the thickness of the second sub-doped semiconductor layer 42 is smaller than the thickness of the first sub-doped semiconductor layer 41, which is equivalent to the small projected area of ​​the first sub-doped semiconductor layer 41 on the semiconductor substrate layer 1. The first sub-doped semiconductor layer 41 has a better effect of reducing optical absorption, thereby increasing the probability of light entering the semiconductor substrate layer 1 and improving the photoelectric conversion efficiency of the TOPCon cell. In addition, the thickness of the first sub-doped semiconductor layer 41 is large, which avoids poor contact between the first electrode 7 and the first sub-doped semiconductor layer 41 and improves the conductive performance of the TOPCon cell. The second sub-doped semiconductor layer 42 has a large projected area on the semiconductor substrate layer 1, which can provide more conductive channels and further improve the conductive performance of the TOPCon cell. In addition, the thickness of the second sub-doped semiconductor layer 42 is small, which reduces the probability of light absorption by the second sub-doped semiconductor layer 42, increases the probability of light entering the semiconductor substrate layer 1, and further improves the photoelectric conversion efficiency of the TOPCon cell. In summary, by dividing the first doped semiconductor layer 4 into the first sub-doped semiconductor layer 41 and the second sub-doped semiconductor layer 42, the light absorption efficiency of the semiconductor substrate layer 1 is significantly increased, the photoelectric conversion efficiency of the TOPCon cell is increased by 0.366%, and the short-circuit current is increased by 0.222A.

[0041] It should be noted that, in this embodiment, the first surface is the front surface of the TOPCon battery, that is, the light-facing surface of the TOPCon battery, and the second surface is the back surface of the TOPCon battery, that is, the backlight surface of the TOPCon battery.

[0042] In one embodiment, the width of the first sub-doped semiconductor layer 41 is 45 μm-65 μm, for example, 45 μm, 50 μm, 60 μm or 65 μm; the width of the second sub-doped semiconductor layer 42 is 70 μm-90 μm, for example, 70 μm, 80 μm or 90 μm.

[0043] In one embodiment, the thickness of the first doped semiconductor layer 4 is 100nm-200nm, for example, 100nm, 120nm, 140nm, 160nm, 180nm or 200nm; the thickness of the first sub-doped semiconductor layer 41 is 80nm-190nm, for example, 80nm, 100nm, 120nm, 140nm, 160, 180nm or 190nm; the thickness of the second sub-doped semiconductor layer 42 is 10nm-20nm, for example, 10nm, 15nm or 20nm.

[0044] In one embodiment, the square resistance of the first sub-doped semiconductor layer 41 is 70Ω-120Ω, for example, 70Ω, 80Ω, 90Ω, 100Ω, 110Ω or 120Ω, and the square resistance of the second sub-doped semiconductor layer 42 is 130Ω-160Ω, for example, 130Ω, 140Ω, 150Ω or 160Ω.

[0045] Sheet resistance is positively correlated with doping concentration; the higher the concentration, the greater the sheet resistance.

[0046] The TOPCon cell also includes an interconnecting electrode 8, located on a side of the first electrodes 7 away from the semiconductor substrate layer 1, for connecting the first electrodes 7 in the same column. The interconnecting electrode 8 connects the first electrodes 7 in the same column, facilitating better charge collection. Furthermore, because the first electrodes 7 are made of low-cost materials, the combination of the interconnecting electrode 8 and the first electrodes 7 can reduce production costs.

[0047] In one embodiment, the interconnection electrode 8 comprises a copper electrode.

[0048] In one embodiment, the first electrode 7 comprises a tin-bismuth-silver alloy electrode.

[0049] In one embodiment, the height of the first electrode 7 is 5 μm-10 μm, for example, 5 μm, 7 μm, 9 μm or 10 μm; the width of the first electrode 7 is 15 μm-25 μm, for example, 15 μm, 20 μm or 25 μm.

[0050] It should be noted that the width direction of the first electrode 7 is the same as the width direction of the first sub-doped semiconductor layer 41 and the second sub-doped semiconductor layer 42, and is perpendicular to the column direction of the first electrode 7; the height direction of the first electrode 7 is the same as the thickness direction of the first sub-doped semiconductor layer 41 and the second sub-doped semiconductor layer 42.

[0051] Referring to Figures 3 and 4, Figure 3 is a top view of the TOPCon battery, and Figure 4 is a side view of part of the TOPCon battery. The extension direction of the interconnection electrode 8 in Figure 3 is consistent with the column direction of the first electrode 7. Since the first sub-doped semiconductor layer 41 corresponds to and is connected to the first electrode 7, the first sub-doped semiconductor layer 41 is located in the shielding area of ​​the first electrode 7.

[0052] Continuing with reference to Figure 2, the TOPCon cell also includes: an intrinsic doped layer 3; located on the first surface of the semiconductor substrate layer 1, and located between the first tunneling oxide layer 2 and the semiconductor substrate layer 1; a passivation layer 5; located on a side surface of a portion of the intrinsic doped layer 3 away from the semiconductor substrate layer 1, and surrounding the first doped semiconductor layer 4 and the first tunneling oxide layer 2; a first anti-reflection layer 6; located on a side of the passivation layer 5 away from the semiconductor substrate layer 1; and further includes: a second tunneling oxide layer 9, located on the second surface of the semiconductor substrate layer 1; a second doped semiconductor layer 11; located on a side of the second tunneling oxide layer 9 away from the semiconductor substrate layer 1; a second anti-reflection layer 12; located on a side of the second doped semiconductor layer 11 away from the semiconductor substrate layer 1; a second electrode 13; located on a side of the second anti-reflection layer 12 away from the semiconductor substrate layer 1; wherein the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer.

[0053] In this embodiment, the passivation layer 5 includes an aluminum oxide layer; the first anti-reflection layer 6 includes a Si x N y layer or SiON y The second anti-reflection layer 12 includes Si x N y layer or SiON y layer.

[0054] In this embodiment, the first tunneling oxide layer 2 includes a silicon dioxide layer, the second tunneling oxide layer 9 includes a silicon dioxide layer; the first doped semiconductor layer 4 includes a P-type polysilicon layer, and the second doped semiconductor layer 11 includes an N-type polysilicon layer.

[0055] In this embodiment, the second electrode 13 includes a silver electrode.

[0056] This embodiment also provides a method for preparing a TOPCon battery, referring to FIG5 , comprising:

[0057] S1: providing a semiconductor substrate layer; the semiconductor substrate layer having a first surface and a second surface opposite to each other;

[0058] S2: forming a first tunneling oxide layer on one side of the first surface of a portion of the semiconductor substrate layer;

[0059] S3: forming a first doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer; the first doped semiconductor layer includes a first sub-doped semiconductor layer and a second sub-doped semiconductor layer; the step of forming the first doped semiconductor layer includes: forming the first sub-doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer; forming the second sub-doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer, the second sub-doped semiconductor layer being located between the first sub-doped semiconductor layer and the first tunneling oxide layer; the projected area of ​​the first sub-doped semiconductor layer on the semiconductor substrate layer is smaller than the projected area of ​​the second sub-doped semiconductor layer on the semiconductor substrate layer, and the thickness of the second sub-doped semiconductor layer is smaller than the thickness of the first sub-doped semiconductor layer;

[0060] S4: forming a first electrode on a side of the first sub-doped semiconductor layer away from the semiconductor substrate layer.

[0061] In one embodiment, before forming the first tunneling oxide layer 2 on a portion of the first surface side of the semiconductor substrate layer 1 , a first initial tunneling oxide layer 2 a is formed on the first surface side of the semiconductor substrate layer 1 .

[0062] Before forming the first initial tunneling oxide layer 2a, an intrinsic doped layer 3 is formed on the first surface of the semiconductor substrate layer 1 by diffusion treatment; after forming the first initial tunneling oxide layer 2a, before forming the first doped semiconductor layer 4 on the side of the first tunneling oxide layer away from the semiconductor substrate layer 1, a first intrinsic semiconductor layer is formed on the side of the first initial tunneling oxide layer 2a away from the semiconductor substrate layer 1; the first intrinsic semiconductor layer is subjected to boron diffusion treatment to form a first initial doped semiconductor layer 4a.

[0063] The step of forming a first sub-doped semiconductor layer 41 on the side of the first tunneling oxide layer 2 away from the semiconductor substrate layer 1 includes: providing a first mask A, the first mask A covering a portion of the first initial doped semiconductor layer 4a; performing a first cleaning treatment on the area of ​​the first initial doped semiconductor layer 4a not covered by the first mask A to obtain a first sub-doped semiconductor layer 41 and a second sub-initial doped semiconductor layer 42a.

[0064] After forming the first sub-doped semiconductor layer 41 on the side of the first tunneling oxide layer 2 away from the semiconductor substrate layer 1, forming the second sub-doped semiconductor layer 42 on the side of the first tunneling oxide layer 2 away from the semiconductor substrate layer 1; the step of forming the second sub-doped semiconductor layer 42 includes: providing a second mask B, the second mask B covering a portion of the second sub-initial doped semiconductor layer 42a; performing a second cleaning treatment on the area of ​​the second sub-initial doped semiconductor layer 42a not covered by the second mask to obtain the second sub-doped semiconductor layer 42.

[0065] The first sub-doped semiconductor layer 41 and the second sub-doped semiconductor layer 42 constitute a first doped semiconductor layer 4; after the first doped semiconductor layer 4 is formed, a passivation layer 5 is formed on a first surface of a portion of the intrinsic doped layer 3 away from the semiconductor substrate layer 1, and the passivation layer 5 surrounds the first doped semiconductor layer 4 and the first tunneling oxide layer 2; a first anti-reflection layer 6 is formed on a side of the passivation layer 5 away from the semiconductor substrate layer 1; after the first anti-reflection layer 6 is formed, a first electrode 7 is formed on a side of the first sub-doped semiconductor layer 41 away from the semiconductor substrate layer 1; and further comprising: forming an interconnecting electrode 8 on a side of the first electrode 7 away from the semiconductor substrate layer 1, for connecting the first electrodes 7 in the same column into one.

[0066] The preparation method of TOPCon battery is described in detail below with reference to Figures 6-15.

[0067] 6 , a semiconductor substrate layer 1 is provided.

[0068] The semiconductor substrate layer 1 is made of single crystal silicon and has an N-type conductivity. In other embodiments, the semiconductor substrate layer is made of other semiconductor materials, such as silicon or silicon germanium, and has a P-type conductivity.

[0069] The semiconductor substrate layer 1 has a first surface and a second surface opposite to each other. In this embodiment, the first surface is the front side of the TOPCon cell, that is, the light-facing side of the TOPCon cell, and the second surface is the back side of the TOPCon cell, that is, the backlight side of the TOPCon cell.

[0070] The first and second surfaces of the semiconductor substrate layer 1 are textured to form a pyramid texture structure on the first and second surfaces of the semiconductor substrate layer 1. The texture treatment is a conventional process in the art and will not be described in detail here.

[0071] 7 , an intrinsic doping layer 3 is formed on the first surface of the semiconductor substrate layer 1 by diffusion treatment.

[0072] After the first surface and the second surface of the semiconductor substrate layer 1 are textured, an intrinsic doping layer 3 is formed on the first surface of the semiconductor substrate layer 1 by diffusion.

[0073] In one embodiment, the diffusion process adopts boron diffusion process, and the gas source adopted by the boron diffusion process is a boron-containing gas source; the boron-containing gas source includes BCl3.

[0074] In this embodiment, the intrinsic doping layer 3 includes a P-type doping layer. Referring to FIG8 , a first initial tunneling oxide layer 2 a is formed on a surface of the intrinsic doping layer 3 away from the semiconductor substrate layer 1 .

[0075] After the intrinsic doping layer 3 is formed on the first surface of the semiconductor substrate layer 1 by diffusion treatment, a first initial tunneling oxide layer 2 a is formed on the surface of the intrinsic doping layer 3 on a side away from the semiconductor substrate layer 1 .

[0076] The process of forming the first initial tunneling oxide layer 2 a includes a plasma enhanced chemical vapor deposition process. The first initial tunneling oxide layer 2 a completely covers the first surface of the semiconductor substrate layer 1 .

[0077] In one embodiment, the thickness of the first initial tunneling oxide layer 2 a is 1.5 nm-2 nm, for example, 1.5 nm or 2 nm.

[0078] In this embodiment, the first initial tunneling oxide layer 2 a includes a silicon dioxide layer.

[0079] 9 , a first initial doped semiconductor layer 4 a is formed on a side of the first initial tunneling oxide layer 2 a away from the semiconductor substrate layer 1 .

[0080] After forming the first initial tunneling oxide layer 2 a on the surface of the intrinsic doped layer 3 away from the semiconductor substrate layer 1 , a first initial doped semiconductor layer 4 a is formed on the side of the first initial tunneling oxide layer 2 a away from the semiconductor substrate layer 1 .

[0081] It should be noted that after the first initial tunneling oxide layer 2a is formed on the first surface of the semiconductor substrate layer 1, before the first initial doped semiconductor layer 4a is formed on the side of the first initial tunneling oxide layer 2a away from the semiconductor substrate layer 1, a first intrinsic semiconductor layer (not shown in the figure) is formed on the side of the first initial tunneling oxide layer 2a away from the semiconductor substrate layer 1.

[0082] The process of forming the first intrinsic semiconductor layer includes a low pressure chemical vapor deposition process or a physical vapor deposition process.

[0083] In this embodiment, the first intrinsic semiconductor layer includes a polysilicon layer, that is, the first intrinsic semiconductor layer includes a polysilicon layer.

[0084] After forming a first intrinsic semiconductor layer on a side of the first initial tunneling oxide layer 2a away from the semiconductor substrate layer 1, a boron diffusion process is performed on the first intrinsic semiconductor layer to form a first initial doped semiconductor layer 4a. The boron diffusion process gradually diffuses impurities within the semiconductor substrate layer 1 into the first intrinsic semiconductor layer, enriching the impurities in the first intrinsic semiconductor layer so that the first initial doped semiconductor layer 4a is formed in a portion of the thickness of the first intrinsic semiconductor layer.

[0085] In one embodiment, the gas source used in the boron diffusion process is a boron-containing gas source; the boron-containing gas source includes BCl 3 .

[0086] Before the boron diffusion treatment, the first intrinsic semiconductor layer and the semiconductor substrate layer 1 have the same conductivity type, and the conductivity type of the first intrinsic semiconductor layer and the semiconductor substrate layer 1 are both N-type; after the boron diffusion treatment, the conductivity type of the first initial doped semiconductor layer 4a is P-type, and the first initial doped semiconductor layer 4a includes a P-type polycrystalline silicon layer, that is, the first initial doped semiconductor layer 4a includes a P-type polysilicon layer.

[0087] It should be noted that the boron diffusion treatment is an existing process in this field. The time and temperature of the boron diffusion treatment refer to the existing process parameters and will not be described in detail here.

[0088] 10 and 11 , a first sub-doped semiconductor layer 41 is formed in a portion of the first initially doped semiconductor layer 4 a .

[0089] A first initial doped semiconductor layer 4a is formed on a side of the first initial tunneling oxide layer 2a away from the semiconductor substrate layer 1. Then, a first sub-doped semiconductor layer 41 is formed in a portion of the first initial doped semiconductor layer 4a.

[0090] The step of forming the first sub-doped semiconductor layer 41 includes: providing a first mask A, wherein the first mask A covers a portion of the first initially doped semiconductor layer 4a (see FIG10 ); and performing a first cleaning process on the area of ​​the first initially doped semiconductor layer 4a not covered by the first mask A to obtain the first sub-doped semiconductor layer 41 and the second sub-initial doped semiconductor layer 42a (see FIG11 ). The first sub-doped semiconductor layer 41 is located on a side of the second sub-initial doped semiconductor layer 42a away from the semiconductor substrate layer 1 .

[0091] It should be noted that, in this embodiment, the first cleaning treatment only removes a portion of the thickness of the first initial doped semiconductor layer 4a; wherein, part of the first sub-doped semiconductor layer 41 is the area covered by the first mask A, and part of the second sub-initial doped semiconductor layer 42a is the area not covered by the first mask, and the thickness of the obtained second sub-initial doped semiconductor layer 42a is less than the thickness of the first sub-doped semiconductor layer 41.

[0092] In one embodiment, the first mask A includes an alkali-resistant wax print mask; the first cleaning treatment adopts alkali cleaning, and the time of the first cleaning treatment is 250s-380s, for example, 250s, 300s, 350s or 380s; the temperature of the first cleaning treatment is 70℃-80℃, for example, 70℃, 75℃ or 80℃.

[0093] 12 and 13 , a second sub-doped semiconductor layer 42 is formed.

[0094] After forming the first sub-doped semiconductor layer 41 in a portion of the first initial doped semiconductor layer 4 a , the second sub-doped semiconductor layer 42 is formed. The second sub-doped semiconductor layer 42 is located between the first sub-doped semiconductor layer 41 and the first tunneling oxide layer 2 .

[0095] The steps of forming the second sub-doped semiconductor layer 42 include: providing a second mask B, which covers a portion of the second sub-initial doped semiconductor layer 42a (refer to Figure 12); performing a second cleaning treatment on the area of ​​the second sub-initial doped semiconductor layer 42a not covered by the second mask B to obtain the second sub-doped semiconductor layer 42 (refer to Figure 13).

[0096] In one embodiment, the second mask B includes an alkali-resistant wax print mask; the second cleaning treatment adopts alkali cleaning, and the time of the second cleaning treatment is 150s-200s, for example, 150s, 180s or 200s; the temperature of the second cleaning treatment is 60℃-70℃, for example, 60℃, 65℃ or 70℃.

[0097] In other embodiments, after forming the second sub-doped semiconductor layer in a portion of the first initial doped semiconductor layer, the first sub-doped semiconductor layer may be formed on a side of the second sub-doped semiconductor layer away from the semiconductor substrate layer.

[0098] 14 , the first mask A and the second mask B are removed.

[0099] After the second sub-doped semiconductor layer 42 is formed, the first mask A and the second mask B are removed.

[0100] In this embodiment, during the process of removing the first mask A and the second mask B, a portion of the first initial tunneling oxide layer 2 a is also removed to expose a portion of the intrinsic doping layer 3 .

[0101] In one embodiment, acid solution is used to remove the first mask A and the second mask B. The acid solution includes HF solution. The mass percentage concentration of the acid solution is 2%-6%, for example, 2%, 3%, 4%, 5% or 6%.

[0102] In this embodiment, before removing the first mask A and the second mask B, the second surface of the semiconductor substrate layer 1 is polished to remove the borosilicate glass on the second surface. The polishing is performed using an alkaline solution. The polishing process is conventional in the art, and the process parameters of time and temperature during the polishing process are not specifically described here.

[0103] Referring to Figure 15, after removing the first mask A and the second mask B, a passivation layer 5 is formed on the surface of a portion of the intrinsic doped layer 3 away from the semiconductor substrate layer 1, and the passivation layer 5 surrounds the first doped semiconductor layer 4 and the first tunneling oxide layer 2; a first anti-reflection layer 6 is formed on the side of the passivation layer 5 away from the semiconductor substrate layer 1; after the first anti-reflection layer 6 is formed, a first electrode 7 is formed on the side of the first sub-doped semiconductor layer 41 away from the semiconductor substrate layer.

[0104] In one embodiment, the process of forming the passivation layer 5 includes an atomic layer deposition process; and the process of forming the first anti-reflection layer 6 includes a plasma enhanced chemical vapor deposition process.

[0105] The method further includes forming an interconnection electrode 8 on a side of the first electrode 7 away from the semiconductor substrate layer 1 , so as to connect the first electrodes 7 in the same column into one.

[0106] Continuing with reference to FIG15 , the method for preparing a TOPCon battery further includes: forming a second tunneling oxide layer 9 on the second surface of the semiconductor substrate layer 1; forming a second doped semiconductor layer 11 on a side of the second tunneling oxide layer 9 away from the semiconductor substrate layer 1; wherein the conductivity type of the second doped semiconductor layer 11 is opposite to the conductivity type of the first doped semiconductor layer 4.

[0107] In one embodiment, before forming the second doped semiconductor layer 11 on the side of the second tunneling oxide layer 9 away from the semiconductor substrate layer 1, a second intrinsic semiconductor layer (not shown in the figure) is formed on the side of the second tunneling oxide layer 9 away from the semiconductor substrate layer 10; the step of forming the second doped semiconductor layer 11 includes: performing diffusion annealing treatment on the second intrinsic semiconductor layer, and the second intrinsic semiconductor layer is transformed to form the second doped semiconductor layer 11.

[0108] The diffusion annealing treatment in this embodiment is a conventional process in the art, and its purpose is to partially heavily dope and crystallize the second intrinsic semiconductor layer, which will not be described in detail here.

[0109] In one embodiment, the thickness of the second intrinsic semiconductor layer is 90 nm-130 nm, for example, 90 nm, 100 nm, 120 nm or 130 nm.

[0110] In one embodiment, the conductivity type of the second doped semiconductor layer 11 is opposite to the conductivity type of the first doped semiconductor layer 4 ; in this embodiment, the conductivity type of the first doped semiconductor layer 4 is P type and the conductivity type of the second doped semiconductor layer 11 is N type.

[0111] The process of forming the second tunnel oxide layer 9 includes a plasma enhanced chemical vapor deposition process, and the second tunnel oxide layer 9 completely covers the second surface of the semiconductor substrate layer 1.

[0112] In one embodiment, the thickness of the second tunnel oxide layer 9 is 1.5 nm-2 nm, for example, 1.5 nm or 2 nm.

[0113] In this embodiment, the second tunnel oxide layer 9 includes a silicon dioxide layer.

[0114] The process of forming the second tunneling oxide layer 9 and the second doped semiconductor layer 11 is the same as the process of forming the first tunneling oxide layer 2 and the second doped semiconductor layer 11 , and thus will not be described again.

[0115] After forming the second doped semiconductor layer 11 , a second anti-reflection layer 12 is formed on a side of the second doped semiconductor layer 11 away from the semiconductor substrate layer 1 ; and a second electrode 13 is formed on a side of the second anti-reflection layer 12 away from the semiconductor substrate layer 1 .

[0116] The process of forming the second anti-reflection layer 12 includes a plasma enhanced chemical vapor deposition process.

[0117] The second electrode 13 includes a silver electrode.

[0118] In other embodiments, after removing the first and second masks, a second tunneling oxide layer, a second doped semiconductor layer, a second anti-reflective layer, and a second electrode may be stacked on the second surface of the semiconductor substrate layer, followed by forming a passivation layer on a portion of the first surface of the semiconductor substrate layer. After removing the first and second masks, the first surface side of the TOPCon cell may be prepared first, or the second surface side of the TOPCon cell may be prepared first. The order of preparing the first and second surfaces is not limited.

[0119] Comparative Example

[0120] The comparative example provides a method for preparing a TOPCon battery, comprising:

[0121] Providing a semiconductor substrate layer; the semiconductor substrate layer has a first surface and a second surface disposed opposite to each other;

[0122] Performing texturing on the first surface and the second surface of the semiconductor substrate layer;

[0123] performing a boron diffusion process on the first surface of the semiconductor substrate layer to form a first doped semiconductor layer on the first surface of the semiconductor substrate layer;

[0124] forming a tunneling oxide layer on the second surface of the semiconductor substrate layer;

[0125] forming an intrinsic semiconductor layer on a side of the tunnel oxide layer away from the semiconductor substrate layer; performing a diffusion annealing process on the intrinsic semiconductor layer to form a second doped semiconductor layer in a portion of the intrinsic semiconductor layer;

[0126] forming a passivation layer, a first anti-reflection layer and a first electrode in sequence on a side of the first doped semiconductor layer away from the semiconductor substrate layer;

[0127] A second anti-reflection layer and a second electrode are sequentially formed on a side of the second doped semiconductor layer away from the semiconductor substrate layer.

[0128] The materials and processes for forming the tunneling oxide layer, the passivation layer, the first anti-reflection layer, the first electrode, the second anti-reflection layer and the second electrode in this comparative example are the same as those in the above embodiment and are not described in detail here.

[0129] The sheet resistance of the second doped semiconductor layer is 35Ω-50Ω, for example, 35Ω, 40Ω, 45Ω or 50Ω.

[0130] Table 1

[0131] The TOPCon cell prepared using the TOPCon cell preparation method provided in this application significantly increases the light absorption efficiency of the semiconductor substrate layer by forming a first tunneling oxide layer and a first doped semiconductor layer on one side of the first surface of the semiconductor substrate layer 1, and dividing the first doped semiconductor layer into a first sub-doped semiconductor layer and a second sub-doped semiconductor layer of different thicknesses and widths. The data shown in Table 1 obtained through testing show that compared to existing TOPCon cells, the TOPCon cell provided in this application has a series resistance reduced by 0.7 mΩ, a parallel resistance increased by 108 mΩ, and a reverse current reduced by 0.009 A. At the same time, the open-circuit voltage increased by 4.516 mV, the short-circuit current increased by 0.222 A, the fill factor increased by 0.44%, and the conversion efficiency increased by 0.366%.

[0132] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A TOPCon battery, characterized in that: include: A semiconductor substrate layer, wherein the semiconductor substrate layer has a first surface and a second surface arranged opposite to each other; A first tunneling oxide layer, located on a first surface side of a portion of the semiconductor substrate layer; a first doped semiconductor layer, the first doped semiconductor layer comprising a first sub-doped semiconductor layer and a second sub-doped semiconductor layer; the first sub-doped semiconductor layer is located on a side of the first tunneling oxide layer away from the semiconductor substrate layer; the second sub-doped semiconductor layer is located between the first sub-doped semiconductor layer and the first tunneling oxide layer; The projection area of ​​the first sub-doped semiconductor layer on the semiconductor substrate layer is smaller than the projection area of ​​the second sub-doped semiconductor layer on the semiconductor substrate layer, and the thickness of the second sub-doped semiconductor layer is smaller than the thickness of the first sub-doped semiconductor layer; The first electrode is located at a side of the first sub-doped semiconductor layer away from the semiconductor substrate layer.

2. The TOPCon battery according to claim 1, characterized in that The width of the first sub-doped semiconductor layer is 45 μm-65 μm, and the width of the second sub-doped semiconductor layer is 70 μm-90 μm.

3. The TOPCon battery according to claim 1, characterized in that The thickness of the first doped semiconductor layer is 100nm-200nm; The thickness of the first sub-doped semiconductor layer is 80nm-190nm; the thickness of the second sub-doped semiconductor layer is 10nm-20nm.

4. The TOPCon battery according to claim 1, characterized in that The square resistance of the first sub-doped semiconductor layer is 70Ω-120Ω, and the square resistance of the second sub-doped semiconductor layer is 130Ω-160Ω.

5. The TOPCon battery according to claim 1, characterized in that Also includes: an interconnecting electrode, located at a side of the first electrode away from the semiconductor substrate layer, and used to connect the first electrodes in the same column into one; The interconnection electrode comprises a copper electrode; and the first electrode comprises a tin-bismuth-silver alloy electrode.

6. The TOPCon battery according to claim 1, characterized in that The height of the first electrode is 5 μm-10 μm, and the width of the first electrode is 15 μm-25 μm.

7. The TOPCon battery according to claim 1, characterized in that Also includes: An intrinsic doping layer, located on the first surface of the semiconductor substrate layer and between the first tunneling oxide layer and the semiconductor substrate layer; A passivation layer; located on a surface of a portion of the intrinsic doped layer away from the semiconductor substrate layer, and surrounding the first doped semiconductor layer and the first tunneling oxide layer; a first anti-reflection layer; Located at a side of the passivation layer away from the semiconductor substrate layer; The invention also includes: a second tunneling oxide layer, located on the second surface of the semiconductor substrate layer; a second doped semiconductor layer; located on the side of the second tunneling oxide layer away from the semiconductor substrate layer; a second anti-reflection layer; located on the side of the second doped semiconductor layer away from the semiconductor substrate layer; a second electrode; located on the side of the second anti-reflection layer away from the semiconductor substrate layer; wherein the conductivity type of the second doped semiconductor layer and the conductivity type of the first doped semiconductor layer are on the contrary; The passivation layer includes an aluminum oxide layer; the first anti-reflection layer includes a Si x N y Layer or SiON y layer; the second anti-reflection layer comprises Si x N y Layer or SiON y layer.

8. A method for preparing a TOPCon battery, characterized in that: include: providing a semiconductor substrate layer; The semiconductor substrate layer has a first surface and a second surface arranged opposite to each other; forming a first tunneling oxide layer on one side of the first surface of a portion of the semiconductor substrate layer; forming a first doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer; The first doped semiconductor layer includes a first sub-doped semiconductor layer and a second sub-doped semiconductor layer; The step of forming the first doped semiconductor layer comprises: forming a first sub-doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer; forming a second sub-doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer, wherein the second sub-doped semiconductor layer is located between the first sub-doped semiconductor layer and the first tunneling oxide layer; a projected area of ​​the first sub-doped semiconductor layer on the semiconductor substrate layer is smaller than a projected area of ​​the second sub-doped semiconductor layer on the semiconductor substrate layer, and a thickness of the second sub-doped semiconductor layer is smaller than a thickness of the first sub-doped semiconductor layer; A first electrode is formed on a side of the first sub-doped semiconductor layer away from the semiconductor substrate layer.

9. The method for preparing a TOPCon battery according to claim 8, characterized in that: Before forming the first tunneling oxide layer on the first surface side of the portion of the semiconductor substrate layer, forming a first initial tunneling oxide layer on the first surface side of the semiconductor substrate layer; Before forming the first initial tunneling oxide layer, forming an intrinsic doping layer by diffusion treatment on the first surface of the semiconductor substrate layer; After forming a first initial tunneling oxide layer, before forming a first doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer, forming a first intrinsic semiconductor layer on a side of the first initial tunneling oxide layer away from the semiconductor substrate layer; performing a boron diffusion process on the first intrinsic semiconductor layer to form a first initial doped semiconductor layer; The step of forming a first sub-doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer comprises: providing a first mask, wherein the first mask covers a portion of the first initial doped semiconductor layer; A first cleaning process is performed on the area of ​​the first initial doped semiconductor layer not covered by the first mask to obtain a first sub-doped semiconductor layer and a second sub-initial doped semiconductor layer.

10. The method for preparing a TOPCon battery according to claim 9, characterized in that: The first mask includes an alkali-resistant wax printing mask; the first cleaning treatment adopts alkali cleaning, and the time of the first cleaning treatment is 250s-380s; the temperature of the first cleaning treatment is 70°C-80°C.

11. The method for preparing a TOPCon battery according to claim 9, characterized in that: After forming a first sub-doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer, forming a second sub-doped semiconductor layer on a side of the first tunneling oxide layer away from the semiconductor substrate layer; The step of forming the second sub-doped semiconductor layer comprises: providing a second mask, wherein the second mask covers a portion of the second sub-initial doped semiconductor layer; layer; performing a second cleaning process on the area of ​​the second initial sub-doped semiconductor layer not covered by the second mask to obtain a second sub-doped semiconductor layer; The second mask includes an alkali-resistant wax printing mask; the second cleaning treatment adopts alkali cleaning, and the time of the second cleaning treatment is 150s-200s; the temperature of the second cleaning treatment is 60°C-70°C.

12. The method for preparing a TOPCon battery according to claim 11, characterized in that: After forming the second sub-doped semiconductor layer, removing the first mask and the second mask; In the process of removing the first mask and the second mask, a portion of the first initial tunneling oxide layer is also removed to expose a portion of the intrinsic doping layer; The first mask and the second mask are removed by using an acid solution, wherein the acid solution includes an HF solution, and the mass percentage concentration of the acid solution is 2%-6%.

13. The method for preparing a TOPCon battery according to claim 9, characterized in that: After forming the first doped semiconductor layer, forming a passivation layer on a surface of a part of the intrinsic doped layer away from the semiconductor substrate layer, wherein the passivation layer surrounds the first doped semiconductor layer and the first tunneling oxide layer; forming a first anti-reflection layer on a side of the passivation layer away from the semiconductor substrate layer; After forming the first anti-reflection layer, forming a first electrode on a side of the first sub-doped semiconductor layer away from the semiconductor substrate layer; The invention also includes: forming an interconnecting electrode on a side of the first electrode away from the semiconductor substrate layer, so as to connect the first electrodes in the same column into one; The process of forming the passivation layer includes an atomic layer deposition process; The process of forming the first anti-reflection layer includes a plasma enhanced chemical vapor deposition process.

14. The method for preparing a TOPCon battery according to claim 8, characterized in that: Also includes: forming a second tunneling oxide layer on the second surface of the semiconductor substrate layer; forming a second doped semiconductor layer on a side of the second tunneling oxide layer away from the semiconductor substrate layer; wherein the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer; Before forming the second doped semiconductor layer on the side of the second tunneling oxide layer away from the semiconductor substrate layer, forming a second intrinsic semiconductor layer on the side of the second tunneling oxide layer away from the semiconductor substrate layer; the step of forming the second doped semiconductor layer comprises: performing diffusion annealing treatment on the second intrinsic semiconductor layer, and transforming the second intrinsic semiconductor layer into a second doped semiconductor layer; The invention also includes: forming a second anti-reflection layer on a side of the second doped semiconductor layer away from the semiconductor substrate layer; forming a second electrode on a side of the second anti-reflection layer away from the semiconductor substrate layer; The process of forming the second anti-reflection layer includes a plasma enhanced chemical vapor deposition process.

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