Pin-multiplexed trimming circuit, trimming chip, and trimming method for chip

Abstract

Provided are a pin-multiplexed trimming circuit, a trimming chip, and a trimming method for a chip. The pin-multiplexed trimming circuit comprises a first superposition circuit and a trimming chip; the trimming chip comprises a separation circuit, a control circuit, and an in-chip trimming circuit; the first superposition circuit is electrically connected to the separation circuit by means of a power input pin of the trimming chip; the first superposition circuit receives a power supply signal and superposes the power supply signal with a first data signal sent by a controller to obtain a first fused signal; the separation circuit separates the first fused signal to obtain a second data signal and the power supply signal; the power supply signal supplies power to the in-chip trimming circuit, the separation circuit, and the control circuit; the control circuit decodes the second data signal to obtain a third data signal and sends the third data signal to the in-chip trimming circuit.

Description

A multiplexed pin trimming circuit, trimming chip, and chip trimming method

[0001] Related applications

[0002] This application claims priority to the Chinese invention patent with application number 202311109440.6 filed on August 30, 2023, and patent name “A multiplexed pin trimming circuit and trimming method”. All contents of the patent are incorporated herein in their entirety. Technical Field

[0003] The present invention relates to the technical field of integrated circuits, and in particular to a trimming circuit for multiplexed pins, a trimming chip, and a trimming method for the chip. Background Art

[0004] Analog integrated circuits, such as high-precision references, op amps, and analog analog circuits, require very high circuit parameter accuracy. Therefore, the chip is typically trimmed after packaging, and the trimming results need to be read back. This is typically done using the chip's data pins to write and read fuse trimming data. However, using the data pins for fuse trimming simultaneously connects the data pins to both the functional circuitry and the trimming circuitry within the trimming chip, potentially causing chip instability during operation.

[0005] Summary of the Invention

[0006] In view of the above problems in the prior art, the purpose of this article is to provide a multiplexed pin trimming circuit, a trimming chip and a chip trimming method to solve the problem of chip instability caused by the use of data pins in the prior art.

[0007] In order to solve the above technical problems, the specific technical solutions of this article are as follows:

[0008] In one aspect, a multiplexed pin trimming circuit is provided, comprising: a first superimposed circuit and a trimming chip, wherein the trimming chip comprises a separation circuit, a control circuit, and an on-chip trimming circuit, wherein the first superimposed circuit is electrically connected to the separation circuit via a power input pin of the trimming chip;

[0009] The first superposition circuit is configured to receive and superimpose the power signal and the first data signal sent by the controller to obtain a first fused signal;

[0010] The separation circuit is used to separate the first fused signal to obtain a second data signal and the power signal; the power signal is used to power the on-chip trimming circuit, the separation circuit, and the control circuit;

[0011] The control circuit is configured to decode the second data signal to obtain a third data signal, and send the third data signal to the on-chip trimming circuit in the trimming chip.

[0012] As an embodiment of the present invention, the invention further includes a state detection circuit and a second superposition circuit; the state detection circuit is electrically connected to the separation circuit and the second superposition circuit respectively;

[0013] The state detection circuit is configured to detect a flag bit of the second data signal, and if the flag bit is a first type flag bit, disable the second superposition circuit; if the flag bit is a second type flag bit, enable the second superposition circuit;

[0014] The second superposition circuit is used to receive the readback data of the on-chip trimming circuit, and superimpose the data with the power supply signal to obtain a second fusion signal, which is sent to the controller through the power input pin.

[0015] As an embodiment of this document, the first superposition circuit includes a first inverter, MN1, a resistor R1, and a resistor R2;

[0016] An input end of the first inverter receives the first data signal sent by the controller, and an output end of the first inverter is connected to the gate of the MN1;

[0017] The source of the MN1 is grounded via the resistor R2;

[0018] The drain of the MN1 receives the power signal through the resistor R1 , and the drain of the MN1 is connected to the power input pin.

[0019] As an embodiment of the present invention, the first superposition circuit includes a switch, an oscillation circuit, a resistor R3, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a first operational amplifier, and a third operational amplifier;

[0020] The oscillation circuit receives the power supply signal through the switch, and the switch receives the first data signal to be turned on / off; the oscillation circuit is used to output an oscillation signal when the switch is turned on;

[0021] The oscillation signal is sent to the positive input terminal of the first operational amplifier through the resistor R3;

[0022] The resistor R6 and the resistor R7 are connected in series, and the power signal is grounded through the resistor R6 and the resistor R7;

[0023] The positive input terminal of the third operational amplifier is provided at the connection point between the resistor R6 and the resistor R7, the negative input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier, and the resistor R5 is connected in series between the output terminal of the third operational amplifier and the positive input terminal of the first operational amplifier;

[0024] The output terminal of the first operational amplifier is grounded through the resistor R8 and the resistor R9, and the connection point between the resistor R8 and the resistor R9 is connected to the inverting input terminal of the first operational amplifier;

[0025] The output end of the first operational amplifier is connected to the power input pin.

[0026] As an embodiment of this document, the separation circuit includes a first comparator;

[0027] The positive input terminal of the first comparator receives the first fusion signal, and the negative input terminal of the first comparator receives a reference voltage;

[0028] The first comparator compares the first fusion signal and the reference voltage. When the first fusion signal is greater than the reference voltage, the output end of the first comparator outputs the second data signal of a high level; when the first fusion signal is less than the reference voltage, the output end of the first comparator outputs the second data signal of a low level.

[0029] As an embodiment of this document, the separation circuit includes a second inverter, a second operational amplifier, and a second comparator;

[0030] The positive input terminal of the second operational amplifier receives the first fusion signal;

[0031] An input terminal of the second inverter receives the first fusion signal, and an output terminal of the second inverter is connected to an inverting input terminal of the second operational amplifier;

[0032] The output terminal of the second operational amplifier is connected to the input terminal of the second comparator, and the output terminal of the second comparator outputs the second data signal of different levels.

[0033] On the other hand, this document also provides a trimming chip, comprising: a power input pin, a separation circuit, a control circuit, and an on-chip trimming circuit, wherein the power input pin is electrically connected to the separation circuit, the control circuit is electrically connected to the separation circuit, and the on-chip trimming circuit is electrically connected to the control circuit;

[0034] The power input pin is used to receive a first fusion signal, where the first fusion signal is formed by superimposing a power signal and a first data signal for trimming;

[0035] The separation circuit is used to separate the first fused signal to obtain the power signal and the second data signal; the power signal is used to power the on-chip trimming circuit, the separation circuit and the control circuit;

[0036] The control circuit is used to decode the second data signal to obtain a third data signal, and send the third data signal to the on-chip trimming circuit.

[0037] As an embodiment of the present invention, the trimming chip further includes a state detection circuit and a second superposition circuit; the state detection circuit is electrically connected to the separation circuit and the second superposition circuit respectively, and the second superposition circuit is electrically connected to the power input pin and the control circuit respectively;

[0038] The state detection circuit is configured to detect a flag bit of the second data signal, and if the flag bit is a first type flag bit, disable the second superposition circuit; if the flag bit is a second type flag bit, enable the second superposition circuit;

[0039] The second superposition circuit is used to receive the readback data of the on-chip trimming circuit, and superimpose the data with the power supply signal to obtain a second fusion signal, and output the second fusion signal through the power input pin.

[0040] As an embodiment of this document, the on-chip trimming circuit is a fuse trimming circuit.

[0041] As an embodiment of this invention, the second superposition circuit includes a first inverter, MN1, a resistor R1 and a resistor R2;

[0042] An input end of the first inverter receives the readback data, and an output end of the first inverter is connected to the gate of the MN1;

[0043] The source of the MN1 is grounded via the resistor R2;

[0044] The drain of the MN1 receives the power signal through the resistor R1 , and the drain of the MN1 is connected to the power input pin.

[0045] As an embodiment of this document, the separation circuit includes a first comparator;

[0046] The positive input terminal of the first comparator is electrically connected to the power input pin and is used to receive the first fusion signal. The negative input terminal of the first comparator is used to receive a reference voltage. The output terminal of the first comparator is electrically connected to the control circuit.

[0047] The first comparator compares the first fusion signal and the reference voltage. When the first fusion signal is greater than the reference voltage, the output end of the first comparator outputs the second data signal of a high level; when the first fusion signal is less than the reference voltage, the output end of the first comparator outputs the second data signal of a low level.

[0048] As an embodiment of this document, the separation circuit includes a second inverter, a second operational amplifier, and a second comparator;

[0049] The positive input terminal of the second operational amplifier is electrically connected to the power input pin, and is used to receive the first fusion signal;

[0050] The input end of the second inverter is electrically connected to the power input pin and is used to receive the first fusion signal, and the output end of the second inverter is connected to the inverting input end of the second operational amplifier;

[0051] The output terminal of the second operational amplifier is connected to the input terminal of the second comparator;

[0052] An output terminal of the second comparator is electrically connected to the control circuit and is configured to output the second data signal of different levels.

[0053] As an embodiment of this document, the second comparator includes MP3, MP4, MP5, MP6, MP7, MP8, MP9, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11 and MN12;

[0054] The sources of the MP3, the MP4, the MP5, the MP6, the MP7, the MP8 and the MP9 all receive the power signal;

[0055] The sources of the MN8, the MN9, the MN10, the MN11, and the MN12 are all grounded;

[0056] The gate of the MP3 is short-circuited with its drain, and the gate of the MP3 is connected to the gate of the MP4;

[0057] The drain of MP4 is connected to the drain of MP5, the gate of MP5 is short-circuited with its drain, and the gate of MP5 is connected to the gate of MP6 and the gate of MP9;

[0058] The drain of MP7 and the gate of MP7 are respectively connected to the gate of MP8;

[0059] The drain of MP3 is connected to the drain of MN4 and the drain of MN5 respectively, and the drain of MP5 is connected to the drain of MN6 and the drain of MN7 respectively;

[0060] The drain of MP6 and the drain of MP7 are connected to the drain of MN10, the drain of MP8 is connected to the drain of MN11, and the drain of MP9 is connected to the drain of MN12;

[0061] The gates of the MN4 and the MN7 are both connected to the positive input terminal of the second comparator, and the gates of the MN5 and the MN6 are both connected to the negative input terminal of the second comparator;

[0062] The source of MN4 and the source of MN6 are both connected to the drain of MN8, and the gate of MN8 receives a first bias voltage BIA1;

[0063] The source of the MN5 and the source of the MN7 are both connected to the drain of the MN9, and the gate of the MN9 receives a second bias voltage BIA2;

[0064] The gate of the MN10 receives the second bias voltage BIA2;

[0065] The gate of MN11 is connected to the gate of MN12, and the gate of MN11 is connected to its drain;

[0066] The drain of the MP9 outputs the second data signal.

[0067] As an embodiment of this article, it also includes: a logic control circuit;

[0068] The logic control circuit is configured to adjust the state of the trimming chip according to the first fusion signal, and enable the separation circuit, the control circuit, and the on-chip trimming circuit if the first fusion signal includes the first data signal;

[0069] If the first fusion signal does not include the first data signal, a functional circuit in the trimming chip is enabled.

[0070] As an embodiment of this article, it also includes: a logic control circuit;

[0071] the logic control circuit being configured to adjust the state of the trimming chip according to the first fusion signal, and enable the separation circuit, the second superposition circuit, the state detection circuit, the control circuit, and the on-chip trimming circuit if the first fusion signal includes the first data signal;

[0072] If the first fusion signal does not include the first data signal, a functional circuit in the trimming chip is enabled.

[0073] On the other hand, this article also provides a chip tuning method, including:

[0074] Superimposing the first data signal for trimming and the power supply signal to obtain a first fused signal;

[0075] Inputting the first fusion signal into the chip through the power input pin of the chip;

[0076] Separating the first fused signal to obtain a second data signal and a power signal;

[0077] The second data signal is decoded to obtain a third data signal, and the third data signal is used for trimming the chip.

[0078] As an embodiment of this article, it also includes:

[0079] The readback data signal for instructing the trimming unit of the chip is superimposed on the power supply signal to obtain a second fusion signal,

[0080] The second fusion signal is output to the outside of the chip through the power input pin of the chip.

[0081] By adopting the above-mentioned technical solution, the power supply signal and the first data signal can be superimposed through the first superposition circuit to obtain the first fusion signal, which is then sent to the inside of the trimming chip through the power input pin of the trimming chip, so that the separation circuit in the trimming chip separates the first fusion signal to obtain the second data signal. The control circuit in the trimming chip parses the second data signal to obtain the third data signal, and sends the third data signal to the on-chip trimming circuit so that the on-chip trimming circuit performs trimming.

[0082] In order to make the above and other purposes, features and advantages of this article more obvious and easy to understand, the following specifically cites preferred embodiments and provides detailed descriptions in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] In order to more clearly illustrate the technical solutions in the embodiments of this article or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of this article. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0084] FIG1 shows a schematic diagram of a multiplexed pin trimming circuit according to an embodiment of the present invention;

[0085] FIG2 shows a first schematic diagram of a first superposition circuit according to an embodiment of the present invention;

[0086] FIG3 shows a second schematic diagram of the first superposition circuit according to the embodiment of this invention;

[0087] FIG4 shows a first schematic diagram of an oscillating circuit according to an embodiment of the present invention;

[0088] FIG5 shows a second schematic diagram of the oscillation circuit according to the embodiment of this invention;

[0089] FIG6 shows a first schematic diagram of a separation circuit according to an embodiment of the present invention;

[0090] FIG7 shows a second schematic diagram of the separation circuit according to the embodiment of this invention;

[0091] FIG8 shows a schematic diagram of a second comparator according to an embodiment of the present invention;

[0092] FIG9 shows a schematic diagram of a trimming unit in a fuse trimming circuit according to an embodiment of the present invention;

[0093] FIG10 shows a schematic diagram of a trimming circuit with a second superimposed circuit according to an embodiment of the present invention;

[0094] FIG11 shows a schematic diagram of a trimming circuit with a logic control circuit according to an embodiment of the present invention;

[0095] FIG12 is a schematic diagram showing the steps of a chip trimming method according to an embodiment of the present invention;

[0096] FIG13 shows a second schematic diagram of the first superposition circuit and a timing diagram corresponding to the second schematic diagram of the separation circuit according to the embodiment of this document.

[0097]

Description of the accompanying drawings

[0098] 1. First superposition circuit;

[0099] 11. First inverter;

[0100] 12. Switch;

[0101] 13. Oscillation circuit;

[0102] 14. A first operational amplifier;

[0103] 15. The third operational amplifier;

[0104] 2. Adjust the chip;

[0105] 3. Separation circuit;

[0106] 31. First comparator;

[0107] 32. Second inverter;

[0108] 33. Second operational amplifier;

[0109] 34. Second comparator;

[0110] 4. Control circuit;

[0111] 5. Power input pin;

[0112] 6. On-chip trimming circuit;

[0113] 7. Status detection circuit;

[0114] 8. Second superposition circuit;

[0115] 9. Logic control circuit. DETAILED DESCRIPTION

[0116] The technical solutions in the embodiments of this document will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of this document.

[0117] In this article, MN is an N-type MOS transistor and MP is a P-type MOS transistor.

[0118] As shown in FIG1 , a schematic diagram of a multiplexed pin trimming circuit includes: a first superimposed circuit 1 and a trimming chip 2, wherein the trimming chip 2 includes a separation circuit 3, a control circuit 4, and an on-chip trimming circuit 6, and the first superimposed circuit 1 is electrically connected to the separation circuit 3 via a power input pin 5 of the trimming chip 2;

[0119] The first superposition circuit 1 is configured to receive and superimpose the power signal and the first data signal sent by the controller to obtain a first fused signal;

[0120] In the embodiments herein, the controller may be a FPGA (Field Programmable Gate Array), a DSP, an MCU, etc. In the present invention, FPGA is preferably used as the controller.

[0121] The separation circuit 3 is used to separate the first fused signal to obtain the second data signal and the power signal; the power signal is used to power the separation circuit 3, the control circuit 4, and the on-chip trimming circuit 6;

[0122] The control circuit 4 is configured to decode the second data signal to obtain a third data signal, and send the third data signal to the on-chip trimming circuit 6 in the trimming chip 2 .

[0123] By adopting the above technical solution, the power supply signal and the first data signal can be superimposed through the first superposition circuit 1 to obtain the first fusion signal, which is then sent to the inside of the trimming chip 2 through the power input pin 5 of the trimming chip 2, so that the separation circuit 3 in the trimming chip 2 separates the first fusion signal to obtain the second data signal. The control circuit 4 in the trimming chip 2 receives the second data signal and restores the clock and data according to the agreed protocol to obtain the third data signal, and then controls the on-chip trimming circuit 6 to perform trimming through the third data signal according to the agreed command format.

[0124] Regarding the on-chip trimming circuit 6, a fuse trimming circuit is used in the embodiment of this invention. Those skilled in the art will appreciate that, depending on the number of repeatable trimming cycles, different trimming methods can be categorized as MTP (Multiple-Time Programmable, which can be programmed multiple times), FTP (Few-Time Programmable, which can be programmed a limited number of times), OTP (One-Time Programmable, which allows programming only once and the data is permanently valid once programmed). Common trimming techniques include: digital calibration, hardware register trimming (Trimming with Register Settings), fuse programming or laser trimming, adaptive calibration, multiplexer and resistor array (MRA), iterative learning algorithm (ILA), on-chip self-calibration (OSCAL), and multistage calibration. In the present invention, fuse trimming is mainly used as an example, and fuse trimming itself is a specific implementation example of OTP trimming. The specific on-chip trimming circuit is also taken as an example of a fuse trimming circuit.

[0125] In this article, the first superimposed circuit 1 is disposed outside the trimming chip 2. Because the number of chips to be trimmed is often large during chip production, it is possible to produce a number of first superimposed circuits 1 that does not match the number of trimming chips 2. This reduces trimming costs. For example, if there are ten trimming chips 2, the number of first superimposed circuits 1 can be one, two, or three, etc. This is not a limitation herein.

[0126] In this article, the first data signal is divided into read data and write data. First, this article introduces the data writing process. The first data signal is in the form of a data frame, and its specific format can be 0111xxxxxyyyyyyyyz, where x represents a 5-bit address, y represents 8-bit data, and z is a checksum; 0111 is a specific flag bit. In this article, if the flag bit is 0111, then the flag bit is a first-class flag bit, which corresponds to write data; if the flag bit is 0110, then the flag bit is a second-class flag bit, which corresponds to read data.

[0127] In this article, the power supply signal may be 3.3V, 5V or 12V, etc., which is not limited in this article.

[0128] In this document, the first superposition circuit 1 can superimpose the power signal and the first data signal. For example, in this document, when the first data signal is at a high level, the corresponding level is 3.3V, and when it is at a low level, the corresponding level is 0V. The power signal is 5V. Then, after the first superposition circuit 1 superimposes the high-level first data signal and the power signal, it obtains the first fused signal of 8.3V; after the first superposition circuit 1 superimposes the low-level first data signal and the power signal, it obtains the first fused signal of 5.0V. Of course, those skilled in the art can adjust the amplitudes of the first data signal and the power signal as needed, and this document does not limit this.

[0129] In this article, the separation circuit 3 is connected to the first superposition circuit 1 through the power input pin 5 of the trimming chip 2. In this way, the data pin of the trimming chip 2 is avoided from receiving the first data signal sent by the controller, which can protect the functional circuit in the trimming chip 2 from being affected, and improve the stability of the trimming chip 2. In this article, the functional circuit mainly performs the core function of the trimming chip 2. For example, if the trimming chip 2 is a comparison chip, the functional circuit is a circuit that performs the comparison function. If the trimming chip 2 is an isolation operational amplifier chip, the functional circuit is a circuit that performs the isolation amplification function. In addition, the separation circuit 3 can decompose the first fusion signal inside the trimming chip 2 to obtain the second data signal and the power signal, wherein the power signal can power all non-functional circuits in the trimming chip 2. The content of the second data signal is the same as the first data signal, both describing 8-bit data.

[0130] In this context, the control circuit 4 is primarily configured to decode the second data signal sent by the separation circuit 3 to obtain the third data signal. Specifically, the control circuit 4 receives the pulse of the write data frame and recovers the clock and the second data signal according to the agreed protocol, and then performs fuse trimming according to the agreed command format.

[0131] The control fuses of the control circuit 4 have four states: start, sel, and stop. The start fuse in the control circuit 4 indicates the start of trimming, the sel fuse is used to control whether the readback data is the result of fuse trimming, and the stop fuse indicates the end of trimming and the entry into the trimming function off state.

[0132] Herein, the on-chip trimming circuit 6 mainly performs trimming and status reading.

[0133] As shown in the first schematic diagram of the first superposition circuit in FIG2 , the first superposition circuit 1 includes: a first inverter 11 , MN1 , a resistor R1 and a resistor R2 ;

[0134] An input end of the first inverter 11 receives the first data signal sent by the FPGA, and an output end of the first inverter 11 is connected to the gate of the MN1;

[0135] The source of the MN1 is grounded via the resistor R2;

[0136] The drain of the MN1 receives the power signal through the resistor R1 , and the drain of the MN1 is connected to the power input pin 5 .

[0137] The first data signal generated by the FPGA acts on the gate of MN1 through the first inverter 11. The source of MN1 is grounded through the resistor R2, and the drain of MN1 is connected to the power signal VDD through the resistor R1. The voltage output by the power signal VDD is V1. When the FPGA output data is 1, MN1 is disconnected, and the input voltage of the power input pin 5 is V1. When the FPGA output data is 0, MN1 is closed, and the input voltage of the power input pin 5 is V2. V2 = V1*R2 / (R1+R2), and the amplitude difference between V1 and V2 is x (x can be 1V). Thus, the first data signal and the power signal are superimposed to obtain the first fused signal.

[0138] As shown in the second schematic diagram of the first superposition circuit in FIG3 , the first superposition circuit 1 includes: the first superposition circuit 1 includes a switch 12 , an oscillation circuit 13 , a resistor R3 , a resistor R5 , a resistor R6 , a resistor R7 , a resistor R8 , a resistor R9 , a first operational amplifier 14 , and a third operational amplifier 15 ;

[0139] The oscillation circuit 13 receives the power signal through the switch 12, and the switch 12 receives the first data signal to be turned on / off; the oscillation circuit 13 is configured to output an oscillation signal when the switch 12 is turned on;

[0140] The oscillation signal is sent to the positive input terminal of the first operational amplifier 14 through the resistor R3;

[0141] The resistor R6 and the resistor R7 are connected in series, and the power signal is grounded through the resistor R6 and the resistor R7;

[0142] The positive input terminal of the third operational amplifier 15 is provided at the connection point between the resistor R6 and the resistor R7, the negative input terminal of the third operational amplifier 15 is connected to the output terminal of the third operational amplifier 15, and the resistor R5 is connected in series between the output terminal of the third operational amplifier 15 and the positive input terminal of the first operational amplifier 14;

[0143] The output terminal of the first operational amplifier 14 is grounded through the resistor R8 and the resistor R9, and the connection point between the resistor R8 and the resistor R9 is connected to the inverting input terminal of the first operational amplifier 14;

[0144] The output end of the first operational amplifier 14 is connected to the power input pin 5 .

[0145] This article provides two solutions for oscillator circuit 13. The first data signal generated by the FPGA acts on the oscillator circuit 13 via the switch 12. When the first data signal output by the FPGA is low (data 0), the switch 12 is disconnected, the oscillator circuit 13 does not operate, and the voltage at point C is 0. The voltage output by the power supply signal VDD is V3, and the voltage at point B is V4 = V3*R7 / (R6+R7).

[0146] When the first data signal output by the FPGA is at a high level (data 1), the switch 12 is closed, the oscillator circuit 13 operates, and point C is at an oscillating voltage V5. The voltages at points C and B are superimposed via the first operational amplifier 14. By properly setting the resistance values ​​of R3, R5, R8, and R9, for example, R3 = R5 = R8 = R9, the voltages at points C and B are superimposed via the first operational amplifier 14 to produce an oscillating voltage V6 = V4 + V5. The input voltage to the power input pin 5 is V6. This superimposes the first data signal and the power signal.

[0147] As shown in the first schematic diagram of the oscillation circuit in FIG4 , the oscillation circuit 13 includes: MP1, MP2, MN2, MN3, an inductor L1 and a capacitor C1;

[0148] The sources of the MP1 and the MP2 both receive the power signal through the switch 12;

[0149] The gate of MP1 is connected to the drain of MP2, and the drain of MP1 is connected to the gate of MP2.

[0150] Two ends of the inductor L1 are electrically connected to the drain of MP1 and the drain of MP2 respectively;

[0151] The two ends of the capacitor C1 are electrically connected to the two ends of the inductor L1;

[0152] The drain of the MN2 and the drain of the MN3 are electrically connected to both ends of the capacitor C1 respectively;

[0153] The sources of the MN2 and the MN3 are grounded;

[0154] The gate of MN2 is connected to the drain of MN3, and the gate of MN3 is connected to the drain of MN2;

[0155] The drain of MP2 (ie, point C) outputs the oscillation signal to the resistor R3.

[0156] As shown in the second schematic diagram of the oscillation circuit in FIG5 , the oscillation circuit 13 includes MN4, MN5, capacitor C2, and inductor L2;

[0157] The two ends of the capacitor C2 are electrically connected to the two ends of the inductor L2;

[0158] The center tap of the inductor L2 receives the power signal through the switch 12;

[0159] The drain of the MN4 and the drain of the MN5 are respectively connected to the two ends of the capacitor C2;

[0160] The source of the MN4 and the source of the MN5 are both grounded;

[0161] The gate of MN4 is connected to the drain of MN5 (i.e., point C), and the gate of MN5 is connected to the drain of MN4;

[0162] The drain of MN5 outputs the oscillation signal to the resistor R3.

[0163] As shown in the first schematic diagram of the separation circuit in FIG6 , the separation circuit 3 includes a first comparator 31 ;

[0164] The positive input terminal IN+ of the first comparator 31 receives the first fusion signal, and the negative input terminal IN- receives the reference voltage;

[0165] The first comparator 31 compares the first fusion signal and the reference voltage. When the first fusion signal is greater than the reference voltage, the output end OUT of the first comparator 31 outputs the second data signal of a high level; when the first fusion signal is less than the reference voltage, the output end OUT of the first comparator 31 outputs the second data signal of a low level.

[0166] The first fusion signal received by the power input pin 5 is connected to the positive input terminal IN+ of the first comparator 31, and the negative input terminal IN- of the first comparator 31 is connected to the reference voltage Vref, Vref = V2 + x / 2; when the amplitude of the received first fusion signal is greater than Vref, the first comparator 31 outputs "1"; when the amplitude of the received first fusion signal is less than Vref, the first comparator 31 outputs "0", thereby, the first comparator 31 separates the first data signal from the received first fusion signal, and outputs the second data signal from the output terminal OUT of the first comparator 31.

[0167] Furthermore, it should be understood that the power supply signal can be obtained after the first fusion signal is shaped and filtered.

[0168] As shown in the second schematic diagram of the separation circuit in FIG7 , the separation circuit 3 includes a second inverter 32 , a second operational amplifier 33 and a second comparator 34 ;

[0169] The positive input terminal IN+ of the second operational amplifier 33 receives the first fusion signal;

[0170] The input end of the second inverter 32 receives the first fusion signal, and the output end of the second inverter 32 is connected to the inverting input end IN- of the second operational amplifier 33; after being amplified by the second operational amplifier, the first fusion signal is output through the positive output end OUT+ and the reverse output end OUT- of the second operational amplifier respectively.

[0171] The positive output terminal OUT+ of the second operational amplifier 33 is connected to the positive input terminal IN+ of the second comparator 34, the negative output terminal OUT- of the second operational amplifier 33 is connected to the negative input terminal IN- of the second comparator 34, and the output terminal OUT of the second comparator 34 outputs the second data signal of different levels.

[0172] The first fused signal received by the power input pin 5 is connected to the positive input terminal IN+ of the second operational amplifier 33. The first fused signal received by the power input pin 5 is inverted by the second inverter 32 and then connected to the negative input terminal IN- of the second operational amplifier 33. The low-frequency gain of the second operational amplifier 33 is 0, so only the oscillation voltage is amplified after passing through the second operational amplifier 33. The amplified oscillation voltage is output as "1" at the output terminal OUT of the second comparator 34; the DC voltage is output as "0" at the output terminal OUT of the second comparator 34. In this way, the first data signal is separated from the received first fused signal to obtain the second data signal.

[0173] As shown in the timing diagram corresponding to the second schematic diagram of the first superposition circuit and the second schematic diagram of the separation circuit in Figure 13, the C signal in the figure is the signal at point C in Figure 3, that is, the output signal of the oscillator, the D signal is the first fusion signal, and the "second comparator output" in Figure 13 represents the second data signal, that is, the second data signal finally obtained by the separation circuit 3.

[0174] As shown in the schematic diagram of the second comparator in FIG8 , the second comparator 34 includes MP3, MP4, MP5, MP6, MP7, MP8, MP9, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11 and MN12;

[0175] The ratio of the width to length ratio (w / l) of each MOS tube is as follows:

[0176] MP3:MP4:MP5:MP6:MP7:MP8:MP9=4:1:1:1:2:2:2;

[0177] MN4:MN5:MN6:MN7:MN8:MN9:MN10:MN11:MN12=24:24:4:4:4:4:1:1:4.

[0178] The sources of the MP3, the MP4, the MP5, the MP6, the MP7, the MP8 and the MP9 all receive the power signal;

[0179] The gate of the MP3 is short-circuited with its drain, and the gate of the MP3 is connected to the gate of the MP4;

[0180] The drain of MP4 is connected to the drain of MP5, the gate of MP5 is short-circuited with its drain, and the gate of MP5 is connected to the gate of MP6 and the gate of MP9;

[0181] The drain of MP7 and the gate of MP7 are respectively connected to the gate of MP8;

[0182] The drain of MP3 is connected to the drain of MN4 and the drain of MN5 respectively, and the drain of MP5 is connected to the drain of MN6 and the drain of MN7 respectively;

[0183] The drain of MP6 and the drain of MP7 are connected to the drain of MN10, the drain of MP8 is connected to the drain of MN11, and the drain of MP9 is connected to the drain of MN12;

[0184] The gates of the MN4 and the MN7 are both connected to the positive input terminal of the second comparator, and the gates of the MN5 and the MN6 are both connected to the negative input terminal of the second comparator;

[0185] The source of MN4 and the source of MN6 are both connected to the drain of MN8, and the gate of MN8 receives a first bias voltage BIA1;

[0186] The source of the MN5 and the source of the MN7 are both connected to the drain of the MN9, and the gate of the MN9 receives a second bias voltage BIA2;

[0187] The gate of MN10 receives the second bias voltage BIA2. The first bias voltage BIA1 and the second bias voltage BIA2 may be equal or different. The first bias voltage BIA1 controls the current flowing through MN8 to be I. The second bias voltage BIA2 controls the current flowing through MN9 to be I, and the current flowing through MN10 to be I / 4.

[0188] The gate of MN11 is connected to the gate of MN12, and the gate of MN11 is connected to its drain;

[0189] The drain of the MP9 outputs the second data signal.

[0190] When the first fusion signal is an oscillating voltage, one group of MN4 and MN7 and one group of MN5 and MN6 are cut off, and all currents flow through the other group of NMOS tubes. At this time, the drain current of MP3 is I, the drain current of MN8 is I, the drain current of MN9 is I, and the drain current of MN10 is I / 4. Since MP3:MP4=4:1, the drain current of MP4 is I / 4, the drain current of MP5 is 3I / 4, MP5:MP6=1:1, and the drain current of MP6 is 3I / 4. Since 3I / 4 is greater than I / 4, the current flowing through MP7, MP8, MN11, and MN12 is 0, and MP9 is turned on and outputs "1". When the first fusion signal received is a DC voltage, the MN4, the MN7, the MN5 and the MN6 are all turned on. At this time, the drain current of the MP3 is 6*I / 7, and the sum of the drain currents flowing through the MP4 and the MP5 is I / 7. Since MP3:MP4=4:1, the drain current flowing through the MP4 is 3*I / 14. Since 3I / 14 is greater than I / 7, the MP5 and the MP9 are cut off and the output is "0".

[0191] FIG9 is a schematic diagram of a trimming unit in a fuse trimming circuit, wherein the trimming unit includes MN13, MN14, MN15 and MP10;

[0192] It should be understood that the on-chip trimming circuit 6 may be specifically the fuse trimming circuit, and the on-chip trimming circuit includes N (N≥1) trimming units as shown in FIG. 9 .

[0193] The sources of the MN13, the MN14 and the MN15 are all grounded;

[0194] The gate of the MN13 receives the third data signal Control sent by the control circuit 4, and the drain of the MN13 receives the power signal through the fuse resistor;

[0195] The gate of the MN14 receives a bias voltage signal Vbias, and the drain of the MN14 is connected to the drain of the MN13;

[0196] The gate of the MN15 and the gate of the MP10 are both connected to the drain of the MN14, and the source of the MP10 receives the power signal;

[0197] The drain of the MN15 is connected to the drain of the MP10, and the drain of the MN15 outputs the read-back data.

[0198] The bias voltage signal Vbias controls MN14 to provide a weak pull-down. This means that MN14 is turned on, but the current flowing through the fuse alone, when MN14 is turned on, is insufficient to cause the fuse to blow. For example, the pull-down current can be 1 μA. When the third data signal Control received by the gate of MN13 is 0 (low level), MN13 is turned off, the fuse remains intact, and the gates of MN15 and MP10 are connected to VDD via the fuse. MN15 is turned on, MP10 is turned off, and OUT outputs a low level. When the third data signal Control received by the gate of MN13 is 1 (high level), MN13 is turned on, the fuse blows, and after the fuse blows, the weak pull-down provided by MN14 causes the gates of MN15 and MP10 to be low, thereby ensuring that OUT outputs a stable high level.

[0199] On the other hand, in some cases, it is necessary to read back the fuse status of the trimming chip 2. Therefore, this paper also designs a circuit related to data readback, specifically:

[0200] The schematic diagram of the trimming circuit with the second superposition circuit shown in FIG10 further includes a state detection circuit 7 and a second superposition circuit 8; the state detection circuit 7 is electrically connected to the separation circuit 3 and the second superposition circuit 8 respectively;

[0201] The state detection circuit 7 is used to detect the flag bit of the second data signal, and if the flag bit is a first type flag bit, that is, a write data state, the second superposition circuit 8 is turned off; if the flag bit is a second type flag bit, that is, a read data state, the second superposition circuit 8 is enabled;

[0202] The second superposition circuit 8 is used to receive the readback data of the on-chip trimming circuit 6 and superimpose it with the power supply signal to obtain the second fusion signal, and send the second fusion signal to the controller through the power input pin 5.

[0203] In this document, the second superposition circuit 8 is disposed within the trimming chip 2. The circuit structure of the second superposition circuit 8 is the same as that of the first superposition circuit 1. For example, the second superposition circuit 8 includes a first inverter 11, MN1, resistors R1, and R2. The input of the first inverter 11 receives the readback data, and the output of the first inverter 11 is connected to the gate of MN1. The source of MN1 is grounded via resistor R2. The drain of MN1 receives the power signal via resistor R1, and the drain of MN1 is connected to the power input pin. Those skilled in the art can construct the second superposition circuit 8 using the circuit principles of the first superposition circuit 1 as needed. In this document, the format of the readback data is 0110xxxxx00000000z00000000, where x represents a 5-bit address and z is a checksum. In this way, the state of a specific fuse in the on-chip trimming circuit 6 can be read using a specific address.

[0204] The schematic diagram of the trimming circuit with a logic control circuit shown in FIG11 also includes a logic control circuit 9;

[0205] The logic control circuit 9 is configured to adjust the state of the trimming chip 2 according to the first / second fusion signal. If the first fusion signal includes the first data signal (or the second fusion signal includes the readback data signal), the logic control circuit 9 enables the separation circuit 3, the second superposition circuit 8, the state detection circuit 7, the control circuit 4, and the on-chip trimming circuit 6, and disables the functional circuits in the trimming chip 2.

[0206] If the first fusion signal does not include the first data signal (or the second fusion signal does not include the readback data signal), the functional circuit in the trimming chip 2 is enabled, and all circuits related to the trimming action are turned off, such as the separation circuit 3, the second superposition circuit 8, the state detection circuit 7, the control circuit 4, and the on-chip trimming circuit 6.

[0207] The logic control circuit 9 can ensure that when the trimming circuit is trimmed, it will not be affected by the functional circuit, and when the functional circuit is working, all circuits related to the trimming action can be turned off to prevent all circuits related to the trimming action from affecting the functional circuit.

[0208] Based on the same inventive concept, an embodiment of the present invention further provides a trimming chip, comprising: a power input pin, a separation circuit, a control circuit, and an on-chip trimming circuit, wherein the power input pin is electrically connected to the separation circuit, the control circuit is electrically connected to the separation circuit, and the on-chip trimming circuit is electrically connected to the control circuit;

[0209] The power input pin is used to receive a first fusion signal, and the first fusion signal can be formed by superimposing the power signal and the first data signal for adjustment by the first superposition circuit shown in FIG. 2 or FIG. 3 ;

[0210] The separation circuit is used to separate the first fused signal to obtain the power signal and the second data signal; the power signal is used to power the on-chip trimming circuit, the separation circuit and the control circuit;

[0211] The control circuit is used to decode the second data signal to obtain a third data signal, and send the third data signal to the on-chip trimming circuit.

[0212] The trimming chip further includes a state detection circuit and a second superposition circuit; the state detection circuit is electrically connected to the separation circuit and the second superposition circuit respectively, and the second superposition circuit is electrically connected to the power input pin and the control circuit respectively;

[0213] The state detection circuit is configured to detect a flag bit of the second data signal, and if the flag bit is a first type flag bit, disable the second superposition circuit; if the flag bit is a second type flag bit, enable the second superposition circuit;

[0214] The second superposition circuit is used to receive the readback data of the on-chip trimming circuit, and superimpose the data with the power supply signal to obtain a second fusion signal, and output the second fusion signal through the power input pin.

[0215] The separation circuit can refer to Figures 6 and 7, the second superposition circuit can refer to Figures 2 and 3, and the second comparator can refer to Figure 8. Since the trimming chip of the embodiment of this invention has the same principle as the trimming circuit of the multiplexed pin, the repeated parts will not be repeated.

[0216] Analog integrated circuits, such as high-precision references, op amps, and analog analog circuits, require very high circuit parameter accuracy. Therefore, the chip is typically trimmed after packaging, and the trimming results need to be read back. This is typically done using the chip's data pins to write and read fuse trimming data. However, using the data pins for fuse trimming simultaneously connects the data pins to both the functional circuitry and the trimming circuitry within the trimming chip, potentially causing chip instability during operation.

[0217] In order to solve the above problems, based on the same inventive concept, the embodiments of this document provide a chip trimming method, which can avoid using the data pins of the trimming chip 2 to implement fuse trimming. Figure 12 is a step diagram of a chip trimming method provided in the embodiments of this document. This specification provides method operation steps as described in the embodiments or flow charts, but based on conventional or non-creative labor, more or fewer operation steps may be included. The order of steps listed in the embodiments is only one way of executing the steps among many, and does not represent the only execution order. When the actual system or device product is executed, it can be executed in sequence or in parallel according to the method shown in the embodiments or the accompanying drawings. Specifically, as shown in Figure 12, the method may include:

[0218] Step 1201: Superimpose a first data signal for trimming and a power signal to obtain a first fused signal;

[0219] Step 1202: Input the first fusion signal to the chip through the power input pin of the chip;

[0220] Step 1203: Separate the first fused signal to obtain a second data signal and a power signal;

[0221] Step 1204: Decode the second data signal to obtain a third data signal, where the third data signal is used for trimming the chip.

[0222] As an embodiment of this invention, the method further includes:

[0223] Superimposing a readback data signal for instructing the trimming unit of the chip and the power supply signal to obtain a second fusion signal;

[0224] The second fusion signal is output to the outside of the chip through the power input pin of the chip.

[0225] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Claims

1. A multiplex pin trimming circuit, characterized in that: include: A first superimposed circuit and a trimming chip, wherein the trimming chip includes a separation circuit, a control circuit, and an on-chip trimming circuit, and the first superimposed circuit is electrically connected to the separation circuit via a power input pin of the trimming chip; The first superposition circuit is used to receive and superimpose the power signal with the first data signal sent by the controller to obtain a first fusion signal; The separation circuit is used to separate the first fusion signal to obtain a second data signal and the power signal; the power signal is used to supply power to the on-chip trimming circuit, the separation circuit and the control circuit; The control circuit is used for decoding the second data signal to obtain a third data signal, and sending the third data signal to the on-chip trimming circuit in the trimming chip.

2. The multiplexed pin trimming circuit according to claim 1, characterized in that: It also includes a state detection circuit and a second superposition circuit; the state detection circuit is electrically connected to the separation circuit and the second superposition circuit respectively; The state detection circuit is used to detect the flag bit of the second data signal, and if the flag bit is a first type of flag bit, turn off the second superposition circuit; If the flag bit is a second type of flag bit, enabling the second superposition circuit; The second superposition circuit is used to receive the readback data of the on-chip trimming circuit, and superimpose the data with the power supply signal to obtain a second fusion signal, which is sent to the controller through the power supply input pin.

3. The multiplexed pin trimming circuit according to claim 1 or 2, characterized in that: The first superposition circuit includes a first inverter, MN1, a resistor R1 and a resistor R2; An input end of the first inverter receives the first data signal sent by the controller, and an output end of the first inverter is connected to the gate of the MN1; The source of the MN1 is grounded through the resistor R2; The drain of the MN1 receives the power signal through the resistor R1 , and the drain of the MN1 is connected to the power input pin.

4. The multiplexed pin trimming circuit according to claim 1 or 2, characterized in that: The first superposition circuit includes a switch, an oscillation circuit, a resistor R3, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a first operational amplifier and a third operational amplifier; The oscillation circuit receives the power supply signal through the switch, and the switch receives the first data signal to be turned on / off; the oscillation circuit is used to output an oscillation signal when the switch is turned on; The oscillation signal is sent to the positive input terminal of the first operational amplifier through the resistor R3; The resistor R6 and the resistor R7 are connected in series, and the power signal is grounded through the resistor R6 and the resistor R7; The positive input terminal of the third operational amplifier is arranged at the connection point between the resistor R6 and the resistor R7, the negative input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier, and the resistor R5 is connected in series between the output terminal of the third operational amplifier and the positive input terminal of the first operational amplifier; The output end of the first operational amplifier is grounded through the resistor R8 and the resistor R9, and the connection point between the resistor R8 and the resistor R9 is connected to the inverting input end of the first operational amplifier; The output end of the first operational amplifier is connected to the power input pin.

5. The multiplexed pin trimming circuit according to claim 1 or 2, characterized in that: The separation circuit includes a first comparator; The positive input terminal of the first comparator receives the first fusion signal, and the negative input terminal of the first comparator receives a reference voltage; The first comparator compares the first fusion signal and the reference voltage. When the first fusion signal is greater than the reference voltage, the output end of the first comparator outputs the second data signal of a high level; when the first fusion signal is less than the reference voltage, the output end of the first comparator outputs the second data signal of a low level.

6. The multiplexed pin trimming circuit according to claim 1 or 2, characterized in that: The separation circuit includes a second inverter, a second operational amplifier and a second comparator; The positive input terminal of the second operational amplifier receives the first fusion signal; An input end of the second inverter receives the first fusion signal, and an output end of the second inverter is connected to an inverting input end of the second operational amplifier; The output terminal of the second operational amplifier is connected to the input terminal of the second comparator, and the output terminal of the second comparator outputs the second data signal of different levels.

7. A trimming chip, characterized in that: include: A power input pin, a separation circuit, a control circuit, and an on-chip trimming circuit, wherein the power input pin is electrically connected to the separation circuit, the control circuit is electrically connected to the separation circuit, and the on-chip trimming circuit is electrically connected to the control circuit; The power input pin is used to receive a first fusion signal, where the first fusion signal is formed by superimposing a power signal and a first data signal for adjustment; The separation circuit is used to separate the first fusion signal to obtain the power signal and the second data signal; the power signal is used to supply power to the on-chip trimming circuit, the separation circuit and the control circuit; The control circuit is used for decoding the second data signal to obtain a third data signal, and sending the third data signal to the on-chip trimming circuit.

8. The trimming chip according to claim 7, characterized in that: The trimming chip further includes a state detection circuit and a second superposition circuit; the state detection circuit is electrically connected to the separation circuit and the second superposition circuit respectively, and the second superposition circuit is electrically connected to the power input pin and the control circuit respectively; The state detection circuit is used to detect the flag bit of the second data signal, and if the flag bit is a first type of flag bit, turn off the second superposition circuit; If the flag bit is a second type of flag bit, enabling the second superposition circuit; The second superposition circuit is used to receive the readback data of the on-chip trimming circuit, and superimpose the data with the power supply signal to obtain a second fused signal, and output the second fused signal through the power supply input pin.

9. The trimming chip according to claim 7 or 8, characterized in that: The on-chip trimming circuit is a fuse trimming circuit.

10. The trimming chip according to claim 8, characterized in that: The second superposition circuit includes a first inverter, MN1, a resistor R1 and a resistor R2; An input end of the first inverter receives the read-back data, and an output end of the first inverter is connected to the gate of the MN1; The source of the MN1 is grounded through the resistor R2; The drain of the MN1 receives the power signal through the resistor R1 , and the drain of the MN1 is connected to the power input pin.

11. The trimming chip according to claim 7 or 8, characterized in that: The separation circuit includes a first comparator; The positive input terminal of the first comparator is electrically connected to the power input pin and is used to receive the first fusion signal. The negative input terminal of the first comparator is used to receive a reference voltage. The output terminal of the first comparator is electrically connected to the control circuit. The first comparator compares the first fusion signal with the reference voltage, and when the first fusion signal is greater than the reference voltage, the output terminal of the first comparator outputs the second data signal of a high level; When the When the first fusion signal is less than the reference voltage, the output terminal of the first comparator outputs the second data signal of a low level.

12. The trimming chip according to claim 7 or 8, characterized in that: The separation circuit includes a second inverter, a second operational amplifier and a second comparator; The positive input terminal of the second operational amplifier is electrically connected to the power input pin, and is used to receive the first fusion signal; The input end of the second inverter is electrically connected to the power input pin and is used to receive the first fusion signal, and the output end of the second inverter is connected to the inverting input end of the second operational amplifier; The output terminal of the second operational amplifier is connected to the input terminal of the second comparator; The output terminal of the second comparator is electrically connected to the control circuit and is used to output the second data signal of different levels.

13. The trimming chip according to claim 12, characterized in that: The second comparator includes MP3, MP4, MP5, MP6, MP7, MP8, MP9, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11 and MN12; The sources of the MP3, the MP4, the MP5, the MP6, the MP7, the MP8 and the MP9 all receive the power signal; The sources of the MN8, the MN9, the MN10, the MN11 and the MN12 are all grounded; The gate of the MP3 is short-circuited with its drain, and the gate of the MP3 is connected to the gate of the MP4; The drain of the MP4 is connected to the drain of the MP5, the gate of the MP5 is short-circuited with its drain, and the gate of the MP5 is connected to the gate of the MP6 and the gate of the MP9; The drain of MP7 and the gate of MP7 are connected to the gate of MP8 respectively; The drain of the MP3 is connected to the drain of the MN4 and the drain of the MN5 respectively, and the drain of the MP5 is connected to the drain of the MN6 and the drain of the MN7 respectively; The drain of the MP6 and the drain of the MP7 are connected to the drain of the MN10, the drain of the MP8 is connected to the drain of the MN11, and the drain of the MP9 is connected to the drain of the MN12; The gate of the MN4 and the gate of the MN7 are both connected to the positive input terminal of the second comparator, and the gate of the MN5 and the gate of the MN6 are both connected to the negative input terminal of the second comparator; The source of the MN4 and the source of the MN6 are both connected to the drain of the MN8, and the gate of the MN8 receives a first bias voltage BIA1; The source of the MN5 and the source of the MN7 are both connected to the drain of the MN9, and the gate of the MN9 receives a second bias voltage BIA2; The gate of the MN10 receives the second bias voltage BIA2; The gate of MN11 is connected to the gate of MN12, and the gate of MN11 is connected to its drain; The drain of the MP9 outputs the second data signal.

14. The trimming chip according to claim 7, characterized in that: Also includes: Logic control circuit; The logic control circuit is used to adjust the state of the trimming chip according to the first fusion signal, and enable the separation circuit, the control circuit and the on-chip trimming circuit if the first fusion signal includes the first data signal; If the first fusion signal does not include the first data signal, a functional circuit in the trimming chip is enabled.

15. The trimming chip according to claim 8, characterized in that: Also includes: Logic control circuit; The logic control circuit is used to adjust the state of the trimming chip according to the first fusion signal, and enable the separation circuit, the second superposition circuit, the state detection circuit, the control circuit and the on-chip trimming circuit if the first fusion signal includes the first data signal; If the first fusion signal does not include the first data signal, a functional circuit in the trimming chip is enabled.

16. A chip adjustment method, characterized in that: include: Superimposing the first data signal for trimming and the power supply signal to obtain a first fused signal; Inputting the first fusion signal into the chip through a power input pin of the chip; Separating the first fused signal to obtain a second data signal and a power signal; The second data signal is decoded to obtain a third data signal, and the third data signal is used for trimming the chip.

17. The chip trimming method according to claim 16, characterized in that: Also includes: The readback data signal for indicating the trimming unit of the chip is superimposed on the power supply signal to obtain a second fusion signal, The second fusion signal is output to the outside of the chip through the power input pin of the chip.

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