Circuit communication

Abstract

A circuit system is disclosed that comprises a first circuit portion comprising a clock output portion, a data input portion and a delay portion, and a second circuit portion comprising a clock input connected to the clock output portion and a data output connected to the data input portion. The delay portion comprises a replica of at least part of the clock output portion or the data input portion. The first circuit portion is arranged to transmit a first clock signal via the clock output portion, and to input the first clock signal to the delay circuit portion to generate a second clock signal comprising a delayed version of the first clock signal. The second circuit portion is arranged to receive the first clock signal and to send data to the first circuit portion by transmitting a data signal to the data input portion via the data output according to the first clock signal. The first circuit portion is arranged to receive the data from the second circuit portion by sampling the data signal according to the second clock signal.

Description

[0001] Circuit communication

[0002] BACKGROUND OF THE INVENTION

[0003] The present invention relates to communication between circuit portions.

[0004] Modern electronic devices commonly include several separate integrated circuits that need to communicate with each other. For instance, an embedded computer system may include one or more slave devices (e.g. sensors) that need to communicate with a master microcontroller. A number of different approaches to such communication have been developed.

[0005] One widely-used communication protocol is called Serial Peripheral Interface (SPI). SPI communication uses four communication lines between a master device and a slave device: one carries a clock signal issued by the master device (SCLK), one carries data from the master device to the slave device (MOSI), one carries data from the slave device to the master device (MISO), and one is a slave select signal (SS) which indicates that data is being sent from the master device.

[0006] SPI provides full-duplex communications between devices using four communication lines. There are also variants of SPI that include parallel data lines for increased throughput (e.g. Dual SPI, Quad SPI).

[0007] The data communication rate of SPI is dictated by the speed of the clock signal carried on the SCLK line. Data signals sent from the master device to the slave device, and from the slave device to the master device are both clocked by the clock signal generated by the master device.

[0008] It has been recognised that at high clock speeds (e.g. above 10 MHz), latencies in the propagation of the clock signal from the master device to the slave device, and the return of a data signal from the slave device to the master device can approach the duration of a clock cycle. This can cause errors in receiving the returning data signal. For instance, the data signal from the slave device may become offset from and / or out-of-sync with the clock signal as seen by the master device, e.g. with transitions in the data signal occurring at unexpected times relative to transitions of the master device clock.

[0009] An improved approach may be desired. SUMMARY OF THE INVENTION

[0010] According to a first aspect of the present invention there is provided a first circuit portion for receiving data from a second circuit portion, the first circuit portion comprising: a clock output portion; a data input portion; and a delay portion comprising a replica of at least part of the clock output portion or the data input portion; wherein the first circuit portion is arranged: to transmit a first clock signal via the clock output portion, and to input the first clock signal to the delay circuit portion to generate a second clock signal comprising a delayed version of the first clock signal; and to receive data from the second circuit portion by sampling a data signal input to the data input portion according to the second clock signal.

[0011] According to a second aspect of the present invention there is provided a method of operating a first circuit portion to receive data from a second circuit portion, the method comprising: transmitting a first clock signal via a clock output portion; generating a second clock signal that comprises a delayed version of the first clock signal by inputting the first clock signal to a delay portion comprising a replica of at least part of the clock output portion or a data input portion of the first circuit portion; and the first circuit portion receiving data from the second circuit portion by sampling a data signal input to the data input portion according to the second clock signal.

[0012] According to a third aspect of the present invention there is provided a circuit system comprising: a first circuit portion comprising a clock output portion, a data input portion, and a delay portion, the delay portion comprising a replica of at least part of the clock output portion or the data input portion; and a second circuit portion comprising a clock input connected to the clock output portion, and a data output connected to the data input portion; wherein the first circuit portion is arranged to transmit a first clock signal via the clock output portion, and to input the first clock signal to the delay circuit portion to generate a second clock signal comprising a delayed version of the first clock signal; wherein the second circuit portion is arranged to receive the first clock signal and to send data to the first circuit portion by transmitting a data signal to the data input portion via the data output according to the first clock signal; and wherein the first circuit portion is arranged to receive the data from the second circuit portion by sampling the data signal according to the second clock signal.

[0013] According to a fourth aspect of the present invention there is provided a method of operating a circuit system comprising a first circuit portion and a second circuit portion, the method comprising: the first circuit portion transmitting a first clock signal via a clock output portion; the second circuit portion receiving the first clock signal and sending data to the first circuit portion by transmitting a data signal according to the first clock signal to a data input portion of the first circuit portion; the first circuit portion generating a second clock signal that comprises a delayed version of the first clock signal by inputting the first clock signal to a delay portion, the delay portion comprising a replica of at least part of the clock output portion or the data input portion; and the first circuit portion receiving the data from the second circuit portion by sampling the data signal according to the second clock signal.

[0014] Thus, it will be appreciated by those skilled in the art that by using the second, delayed, clock signal to sample the data signal, latencies associated with the transmission of the first clock signal and the reception of the data signal may be at least partially compensated for and thus the quality of data reception may be improved. In contrast, if the first circuit portion were to sample the data signal according to the first clock signal, the timing of the sampling may not correspond to the timing of the data signal due to the latencies mentioned above, potentially leading to errors and / or the loss of data.

[0015] The inventors have recognised that much of the delay in the timing of the data signal compared to the first clock signal transmitted by the first circuit portion arises in components of the clock output portion and the data input portion. For instance, the clock output portion and / or the data input portion may comprise components such as up or down level shifters and output or input drivers, which can delay the outgoing clock signal and / or the returning data signal. Because the delay portion comprises a replica of at least part of the clock output portion or the data input portion, some or all of these delays can be accurately compensated for in the delay added to the second clock signal by the delay portion.

[0016] Moreover, the delay added by these components may be somewhat unpredictable, e.g. varying with one or more parameters of a manufacturing process, a supply voltage and / or an operating temperature (i.e. PVT variations). However, because the delay portion comprises a replica of at least part of the clock output portion or the data input portion, some or all of these variations are also experienced by the replica. This means that the delay added to the second clock signal by the delay portion may vary in a corresponding way to the delay added by components of the clock output portion and / or the data input portion. Thus, embodiments of the present invention may reliably sample the data signal with more accurate timing than conventional approaches, even when subject to PVT variations. In other words, the delay portion is adapted to dynamically emulate the delay added to the clock signal in the clock output portion and / or the data input portion.

[0017] In some sets of embodiments, the delay portion comprises a replica of part or all of the clock output portion. The clock output portion may comprise one or more components through which the first clock signal passes as it is transmitted, and the delay portion may direct the first clock portion through a matching one or more components. The matching components may be identical components (e.g. identical makes and models), or components with closely matching or identical delay behaviour (e.g. matching behaviour in light of PVT variations). For instance, the clock output portion may comprise a level shifter arranged to shift a voltage of the first clock signal up or down. The delay portion may comprise a matching level shifter. Additionally or alternatively, the clock output portion may comprise an output driver for transmitting the first clock signal. The delay portion may comprise a matching output driver. In some embodiments, one or more matching components in the delay portion may be scaled-down (or scaled-up) versions of the one or more components in the clock output portion.

[0018] In some sets of embodiments, additionally or alternatively, the delay portion comprises a replica of part or all of the data input portion. The data input portion may comprise one or more components through which the data signal passes as it is received, and the delay portion may direct the first clock portion through a matching one or more components. The matching components may be identical components (e.g. identical makes and models), or components with closely matching or identical delay behaviour (e.g. matching behaviour in light of PVT variations). For instance, the data input portion may comprise a level shifter arranged to shift a voltage of the data signal up or down. The delay portion may comprise a matching level shifter. Additionally or alternatively, the data input portion may comprise an input driver arranged to receive the data signal. The delay portion may comprise a matching input driver. In some embodiments, one or more matching components in the delay portion may be scaled-down (or scaled-up) versions of the one or more components in the data input portion.

[0019] As explained above, the delay portion replicating part or all of the clock output portion and / or the data input portion may mean that the second clock signal accurately and reliably compensates for delays in the timing of the incoming data signal. However, in some embodiments one or more additional measures may also be taken to improve the accuracy of the delay compensation.

[0020] In a set of embodiments, the first circuit portion comprises a clock generation portion arranged to generate the first clock signal. In such embodiments, the clock output portion may be arranged to receive the first clock signal from the clock generation portion via one or more routing and / or buffering elements. Similarly, the delay portion may be arranged to receive the first clock signal from the clock generation portion via one or more routing and / or buffering elements. In a set of embodiments, one or more routing and / or buffering elements via which the delay portion receives the first clock signal from the clock generation portion is matched to one or more routing and / or buffering elements via which the delay portion receives the first clock signal from the clock generation portion.

[0021] In other words, the first circuit portion may be arranged to match a path taken by the first clock signal to the output clock portion to a path taken by the first clock signal to the delay portion. This may help to minimise differences in the delays of the second clock signal and the data signal.

[0022] In a set of embodiments, the first circuit portion comprises a sampling portion arranged to sample the data signal according to the second clock signal. For instance, the sampling portion may comprise a flip-flop (e.g. a d-type flip-flop) which is arranged to be clocked by the second clock signal (or an inverted version of the second clock signal) and to receive the data signal as a data input. The sampling portion may be arranged to receive the second clock signal from the delay portion via one or more routing and / or buffering elements. Similarly, the sampling portion may be arranged to receive the data signal from the data input portion via one or more routing and / or buffering elements. In a set of embodiments, one or more routing and / or buffering elements via which the sampling portion receives the second clock signal from the delay portion is matched to one or more routing and / or buffering elements via which the sampling portion receives the data signal from the data input portion.

[0023] In other words, the first circuit portion may be arranged to match a path taken by the data signal from the data input portion to a path taken by the second clock signal from the delay portion. This may also help to minimise differences in the delays of the second clock signal and the data signal.

[0024] The timing of the data signal from the second circuit portion may also be subject to delays caused by other sources (e.g. external to the first circuit portion). For instance, the second circuit portion may have internal latencies which mean that the data signal it outputs is not perfectly synchronised with the first clock signal it receives. There may also be propagation delays associated with the time taken for the clock signal to propagate from the clock output portion to the clock input and / or for the data signal to propagate from the data output to the data input portion.

[0025] In some embodiments, the delay portion comprises one or more additional delay elements (i.e. in addition to one or more elements comprising the replica of at least part of the clock output portion or the data input portion).

[0026] One or more additional delay elements may be arranged to compensate for a delay associated with the second circuit portion. One or more additional delay element may be arranged to compensate for a delay associated with the propagation of the first clock signal and / or the data signal between the first and second circuit portions. One or more additional delay elements may be arranged to add a fixed delay, e.g. designed for a specific implementation. In contrast, one or more further delay elements may be arranged to add delay that is configurable (i.e. the delay portion may comprise one or more configurable delay elements). For instance, the delay portion may comprise an adjustable bias current source for one or more components (e.g. a buffer). The first circuit portion (e.g. a processing portion thereof) may be arranged to configure a delay added by an additional delay element of the delay portion, e.g. based on a measured or expected external delay.

[0027] For instance, because the second clock signal is generated by the delay portion it does not inherently see the output load capacitance that is seen by the output clock portion. In a set of embodiments, the delay portion comprises a configurable capacitance (e.g. an adjustable capacitor) arranged to replicate a load capacitance experienced by the output clock portion.

[0028] At relatively low clock rates, the delay between the first clock signal transmitted by the clock output portion and the timing of the data signal received by the data input portion may be small compared to the length of a clock cycle. In such situations, errors in data reception may be rare. However, at higher rates the latencies may become more significant compared to the clock period and so errors may become more likely. Embodiments of the present invention may be particularly advantageous when used with clock signals having relatively high rates. In a set of embodiments, the first clock signal has a frequency of 1 MHz or more, 10 MHz or more, 25 MHz or more, 50 MH or more, 75 MHz or more or 100 MHz or more. In some embodiments the first clock signal has a frequency of approximately 64 MHz Because the second clock signal is a delayed version of the first clock signal, it will be recognised that it has substantially the same frequency as the first clock signal, but with a phase offset (e.g. of anywhere from 0° to 360°) depending on the delay applied by the delay portion. The second clock signal may in some circumstances be delayed by a time corresponding to an integer number of clock cycles, so that there is no phase offset between the first and second clocks. However, in practice it is likely that the first and second clocks will be out of phase.

[0029] In a set of embodiments, the second clock signal is delayed compared to the first clock signal by 50% of a first clock signal period or more, 75% of a first clock signal period or more, a first clock signal period or more, 150% of a first clock signal period or more, two first clock signal periods or more, or three first clock signal periods or more. The second clock signal may be delayed by 5 ns or more, 10 ns or more, 20 ns or more, or 30 ns or more. For instance, when the first clock signal has a frequency of 96 MHz, a delay corresponding to three first clock signal periods is 31.25 ns.

[0030] In some embodiments, the second circuit portion is arranged to start transmitting the data signal in response to the start of the first clock signal (e.g. in response to a first transition of the first clock signal). However, in some embodiments the second circuit portion is arranged to start transmitting the data signal at another agreed time. For instance, the second circuit portion may be arranged to start to transmit the data signal at a pre-agreed time unrelated to a start time of the first clock signal. Alternatively, the second circuit portion may be arranged to start to transmit the data signal in response to a separate trigger from the first circuit portion.

[0031] The actual start time of the data signal may not be known to the first circuit portion. However, because the first circuit portion initiates or agrees the initiation of the data signal it can know a reference start time which corresponds to the start of the data signal. For instance, when the second circuit portion is arranged to start transmitting the data signal in response to the start of the first clock signal, the reference start time may be the time at which the first clock signal starts. Alternatively, if the second circuit portion is arranged to start to transmit the data signal at a pre-agreed time, this pre-agreed time may be the reference start time.

[0032] The first circuit portion may comprise an integrated circuit device. The second circuit portion may comprise an integrated circuit device. The first and second circuit portions may be part of the same physical product. For instance, the circuit system may comprise an embedded computer system. The first and second circuit portions are preferably connected by wired connections such as PCB traces or vias, or separate conductive wires. The data input portion of the first circuit portion and the data output of the second circuit portion enable communication from the second circuit portion to the first circuit potion. In a set of embodiments, the first circuit portion also comprises a data output for outputting a data signal, e.g. according to the first clock signal. The second circuit portion may comprise a data input for receiving this data signal. The data output of the first circuit portion may be connected to the data input of the second circuit portion, i.e. to enable communication from the first circuit portion to the second circuit portion. The first and second circuit portions may be arranged for duplex communication, and preferably for full duplex communication.

[0033] The first and second circuit portions may be arranged to communicate according to a Serial Peripheral Interface (SPI) protocol. The first circuit portion may comprise an SPI master device. The second circuit portion may comprise an SPI slave device. The first clock signal may comprise a serial clock signal (SCLK). The data signal transmitted from the second circuit portion to the first circuit portion may comprise a Master-ln-Slave-Out (MISO) signal. In relevant embodiments, the data signal transmitted from the first circuit portion to the second circuit portion may comprise a Master-Out-Slave-ln (MOSI) signal. The first circuit portion may additionally comprise a slave select output for outputting a Slave Select (SS) signal. The second circuit portion may comprise a slave select input. The first circuit portion may be arranged to transmit a slave select signal from the slave select output to the slave select input.

[0034] The first and second circuit portions may be arranged to communicate according to a Serial Wire Debug (SWD) protocol. In such embodiments the first circuit portion may comprise a master device, and the second circuit portion may comprise a slave device. The first clock signal may comprise an SWD clock signal. The data signal transmitted from the second circuit portion to the first circuit portion may comprise a SWD data signal.

[0035] The first circuit portion may comprise only one data input portion. In other words, the first circuit portion may be arranged to receive purely serial data. However, the approach disclosed herein may be extended to parallel data reception. In a set of embodiments, the first circuit portion comprises a plurality of data input portions for receiving multiple data signals in parallel. The second circuit portion may comprise a corresponding plurality of data outputs and be arranged to send data to the first circuit portion by transmitting multiple data signals in parallel. The multiple data signals may be transmitted according to the first clock signal. The first circuit portion may be arranged to receive the data from the second circuit portion by sampling the multiple data signals according to the second clock signal. Such embodiments may involve the first and second circuit portions communicating according to a dual SPI protocol or a quad SPI protocol. The approach to circuit communication disclosed herein may, additionally or alternatively, be extended to systems with more than two circuit portions. For instance, the SPI protocol can support multiple slave devices communicating data to a single master device, and the master device may use the techniques disclosed herein to improve the reliability of data reception from multiple or all of these devices. More generally, in a set of embodiments, the circuit system comprises a third circuit portion comprising a clock input connected to the clock output portion, and a data output connected to the data input portion. In such embodiments the third circuit portion may be arranged to receive the first clock signal and to send data to the first circuit portion by transmitting a data signal to the data input portion via the data output according to the first clock signal. In some such embodiments, the first circuit portion is arranged to receive the data from the third circuit portion by sampling the data signal according to the second clock signal.

[0036] The first and / or second clock signals are preferably digital signals (e.g. signals alternating between two digital states at a clock frequency). The data signal may be digital. The second circuit portion may send a sequence of digital states in which data is encoded to the first circuit portion by changing the digital state of the data signal at times corresponding to transitions of the first clock signal (i.e. on rising or falling edges). The first circuit portion may retrieve this sequence by sampling the data signal (i.e. determining a state of the data signal, e.g. by measuring a voltage on the data input) at times corresponding to transitions of the second clock signal. Sampling the data signal according to the second clock signal may comprise storing a state of the data signal at times corresponding to the second clock signal (e.g. at transition times).

[0037] As explained above, sampling the data signal according to the second clock signal can advantageously mitigate data reception errors. However, the inventors have recognised that it may often be necessary to subsequently transfer the samples out of the second clock signal domain for further processing. For instance, the first circuit portion may comprise data input logic or a processing portion arranged to operate according to a core clock signal that is different to the second clock signal (e.g. with a different frequency and / or phase). The first circuit portion may thus require a mechanism for transferring the samples of the data signal from the second clock signal domain into the core clock signal domain.

[0038] The core clock signal may be unrelated to the first clock signal. However, in a set of embodiments the core clock signal is the first clock signal, or is derived from or used to derive the first clock signal. For instance, the first clock signal may comprise an integer division or multiple of the core clock signal, i.e. the first clock signal may be in phase with the core clock signal and have a frequency that is an integer division or multiple of the frequency of the core clock signal.

[0039] In a set of embodiments, the first circuit portion comprises a buffer. In some such embodiments, the first circuit portion is arranged to store samples of the data signal to the buffer. The sampling portion described above may comprise the buffer, i.e. the buffer may be arranged to sample the data signal according to the second clock signal. In other words, sampling the data signal according to the second clock signal may comprise storing a state of the data signal to the buffer at times according to the second clock signal (e.g. at transition times of the second clock signal). Storing the samples in a buffer may facilitate their transfer into a different clock domain.

[0040] In a set of embodiments, the first circuit portion comprises data input logic arranged to read from the buffer according to a core clock signal, e.g. for use by a processing portion operating in the core clock domain. The data input logic may be arranged to read from the buffer according to the first clock signal (e.g. when the first clock signal is derived from the core clock signal).

[0041] As explained above, the delay of the second clock signal may vary, e.g. with PVT variations. As such, the time at which samples begin to be stored in the buffer after the data signal begins may also vary. The first circuit portion may be arranged to decide dynamically on when the data input logic begins reading from the buffer, e.g. based on an estimated or measured delay. In other words, the data input logic may be arranged to start to read from the buffer after a read delay based on an estimated or measured delay of the second clock signal. In a set of embodiments, the first circuit portion is arranged to detect how delayed the second clock signal is (i.e. a delay between the first and second clock signals) and to start to read from the buffer after a read delay corresponding to the detected delay. The first circuit portion may be arranged to detect the delay of the second clock signal by counting a number of clock cycles (e.g. of the first clock signal or a core clock signal) between the first clock signal and the second clock signal (e.g. between first rising or falling edges of the signals). The first circuit portion may comprise a counter for detecting a delay between the first and second clock signals.

[0042] However, in some implementations it may be difficult to accurately estimate or measure the delay of the second clock signal. Therefore, in a set of embodiments, the data input logic is arranged to start to read from the buffer after a fixed read delay corresponding to a maximum expected delay of the second clock signal. Reading from the buffer after a fixed read delay corresponding to a maximum expected delay may mitigate the possibility of the buffer not containing valid data when it is read. The read delay may be measured from a reference start time of the data signal (e.g. the start time of the first clock signal). The maximum expected delay may be based on known performance specifications of components of the clock output portion and the data input portion.

[0043] As explained above, in some embodiments the maximum expected delay of the second clock signal may be equal to several first clock cycles. In some embodiments therefore the fixed read delay may need to be correspondingly long. However, in such embodiments, when the delay is less than the maximum expected delay the fixed read delay may mean that first circuit portion does not start to read from the buffer until several samples have been stored to the buffer. Therefore, in a set of embodiments, the buffer comprises a plurality of memory elements arranged to store successive samples of the data signal. This may allow the data input logic to start reading from the buffer at an appropriate time without losing any data, regardless of the actual delay experienced. The buffer may comprise a First-In-First-Out buffer. In embodiments featuring a plurality of data input portions for receiving multiple data signals in parallel, the first circuit portion may comprise multiple corresponding buffers. Additionally or alternatively, each memory element of one buffer may be arranged to store multiple parallel samples.

[0044] The buffer may be sized to store at least a number of samples corresponding to the read delay. In other words, the buffer may be sized based on the maximum expected delay between the first clock signal and the second clock signal. In a set of embodiments, the buffer comprises four memory elements. This may provide sufficient storage for delays of up to three first clock cycles. More generally, the buffer may comprise at least as many, or more, memory elements as an expected maximum delay of the second clock measured in cycles of the first clock signal.

[0045] The first circuit portion may comprise a write pointer register arranged to control which memory element of the buffer a current sample is stored to. The write pointer register may be incremented or decremented according to the second clock signal.

[0046] The first circuit portion may comprise a read pointer register arranged to control which memory element of the buffer is read by the data input logic at a given time. For instance, the read pointer register may control a multiplexer arranged to connect one of the memory elements to a common output that is connected to the data input logic. The read pointer register may control the multiplexer to connect a memory element to the common output in advance of the data input logic reading the state of the output.

[0047] The read pointer register may be enabled according to the read delay. The read pointer register may be incremented or decremented according to the first clock signal. In some cases, the delay experienced by the first clock signal and the data signal might sometimes drop sufficiently low that the use of the second clock signal is not needed to avoid glitches or errors (e.g. when the round-trip delay, including any internal delay of the second circuit portion is less than one first clock cycle). In such circumstances it may be beneficial to bypass the use of the second clock signal and instead simply sample the data signal according the first clock signal as is conventional, to potentially reduce latency and power use. In a set of embodiments, the first circuit portion is operable in: a first mode in which the first circuit portion is arranged to sample the data signal according the first clock signal; and a second mode in which the first circuit portion is arranged to sample the data signal according to the second clock signal.

[0048] The buffer may be entirely bypassed in the first mode (because the incoming data signal will already be in the first clock signal domain).

[0049] In some embodiments, a user or an external device can configure manually whether the first circuit portion operates in the first mode or the second mode. Alternatively, the first circuit portion may be arranged to determine automatically which mode to operate in based on one or more detections. For instance, if the user knows (or the first circuit portion detects) that the round-trip delay in a particular implementation will be sufficiently low to bypass the use of the second clock signal they can select the first circuit portion to operate in the first mode. Conversely, if the user or knows or suspects (or the first circuit portion detects) that the roundtrip delay in another implementation will be higher, they can select the first circuit portion to operate in the second mode.

[0050] The operation of the first circuit portion in the first or second mode may be based on one or more published performance capabilities of one or more elements of the circuit system (e.g. a maximum specified internal delay of the second circuit portion) and / or the frequency of the first clock signal. For instance, the second mode may be used when a maximum specified internal delay of the second circuit portion exceeds a predetermined threshold based on the frequency of the first clock signal (e.g. 25%, 50% or 75% of the first clock signal period). Conversely, the first mode may be used when a maximum specified internal delay of the second circuit portion is less than the predetermined threshold.

[0051] In some embodiments, the first mode may be used when the frequency of the first clock signal is below a safe threshold (e.g. set based on worst-case delay performance, e.g. a threshold of 50 MHz or less, 25 MHz or less or 10 MHz or less), and the second may be used when the frequency of the first clock signal is above the safe threshold. Features of any aspect or embodiment described herein may, wherever appropriate, be applied to any other aspect or embodiment described herein. Where reference is made to different embodiments, it should be understood that these are not necessarily distinct but may overlap.

[0052] BRIEF DESCRIPTION OF THE DRAWINGS

[0053] One or more non-limiting examples will now be described, by way of example only, and with reference to the accompanying figures in which:

[0054] Figure 1 is a schematic diagram of a circuit system according to an embodiment of the present invention;

[0055] Figure 2 is a schematic diagram of the master device of the circuit system; and Figures 3-5 are timing diagrams illustrating operation of the circuit system.

[0056] DETAILED DESCRIPTION

[0057] Figure 1 shows a circuit system 100 comprising a master device 102 and a slave device 104. The master and slave devices 102, 104 communicate according to an SPI protocol by exchanging four digital signals: a clock signal SCLK, a master-in-slave-out data signal MISO, a master-out-slave-in data signal MOSI, and a slave select signal SS.

[0058] The master device 102 comprises a clock output portion 106, a data input portion 108, a data output 110 and a slave select output 112. The master device 102 also comprises a delay portion 114 and a core portion 118. The slave device 104 comprises a clock input 120, a data output 122, a data input 124, a slave select input 126 and a core portion 128.

[0059] The clock input 120 is connected to the clock output portion 106 via a connection which carries the SCLK signal, the data output 122 of the slave device 104 is connected to the data input portion 108 of the master device 102 via a connection which carries the MISO signal, the data input 124 of the slave device 104 is connected to the data output portion 110 of the master device 102 via a connection which carries the MOSI signal, and the slave select output 112 is connected to the slave select input 126 via a connection which carries the SS signal.

[0060] The clock output portion 106 comprises a up-level shifter 130, an output buffer 132 and a physical pad 134. The data input portion 108 comprises a physical pad 136, an input buffer 138 and a down-level shifter 140. The other inputs and outputs of the master and slave devices 102, 104 may comprise corresponding components. The core portion 118 generates a first clock signal SCLK_CORE and sends this to the clock output portion 106 via routing and buffering elements 105. The clock output portion 106 transmits the first clock signal as the clock signal SCLK of the SPI protocol. The routing and buffering elements 105 and the components of the clock output portion 106 add a small delay to the first clock signal as it is transmitted. For clarity, in Figures 1-5 and in this description, the first clock signal as it is generated by the core portion 118 is given the label SCLK_CORE and the first clock signal as it propagates from the master device 102 to the slave device 104 is labelled SCLK.

[0061] The data input portion 108 receives and forwards the data signal MISO of the SPI protocol to the core portion 118 via routing and buffering elements 109. The components of the data input portion 108 and the routing and buffering elements 109 add a small delay to the data signal. For clarity, in Figures 1-5 and in this description, the data signal as it is received by the core portion 118 is given the label MISO_II\IT and the data signal as it propagates from the slave device 104 to the master device 102 is labelled MISO.

[0062] The delay portion 114 comprises a replica of the clock output portion 106 and the data input portion 108. The delay portion 114 comprises an up-level shifter 131 and an output buffer 133 which are the same as the corresponding components of the clock output portion 106, a physical pad 135, and an input buffer 139 and a down-level shifter 141 which are the same as the corresponding components of the data input portion 108. The delay portion 114 also comprises an adjustable capacitor 143 and an adjustable bias current source 145 for the buffer 133.

[0063] The delay portion 114 receives the first clock signal SCLK_CORE via routing and buffering elements 105 and generates a second, delayed clock signal FBCLK. The second clock signal FBCLK is sent to the core portion 118 via routing and buffering elements 115. The routing and buffering elements 115 at the output of the delay portion 114 are matched (e.g. identical) to the routing and buffering elements 109 at the output of the data input portion 108.

[0064] As will be explained below in more detail, the clock output portion 106, data input portion 108, data output 110, slave select output 112, delay portion 114 and the core portion 118 facilitate the sending and receiving of data to and from the slave device 104. Part of the core portion 118 is shown in more detail in Figure 2. Figure 2 shows part of the core portion 118 that handles receiving data from the slave device 104 (i.e. data sent by the MISO signal). The core portion 118 may also comprise other parts, not shown, for handling data transmission and other functions of the master device 102.

[0065] The part of the core portion 118 shown in Figure 2 comprises a First-In-First-Out (FIFO) buffer 142, a first clock signal generator portion 144 and data input logic 146. The buffer 142 comprises four memory elements 148A, 148B, 148C, 148D. The digital states stored in the memory elements 148A-148D are labelled BUFFER J), BUFFER l, BUFFER_2 and BUFFER_3 respectively. The storage elements 148A-148D are clocked by the second clock signal FBCLK from the delay portion 114, and receive the MISOJNT signal as a data input.

[0066] The buffer 142 also comprises a read multiplexer 150, a two-bit read pointer register 152 and a two-bit write pointer register 154. In other embodiments one-hot shifters may be used in place of two-bit registers. The read multiplexer has four inputs connected to the four memory elements 148A-148D. The output of the read multiplexer 150 is labelled READ_MUX. The value of the read pointer is labelled READ_PTR and the value of the write pointer is labelled WRITE_PTR. The read pointer register 152 controls which input of the read multiplexer 150 is output by the read multiplexer 150. The write pointer register 154 enables one of the memory elements 148A- 148D to store the state of the MISOJNT signal at a time.

[0067] Finally, the buffer 142 comprises a bypass multiplexer 156 controlled by an externally-provided bypass signal BYPASS (e.g. provided by separate control circuitry). The bypass multiplexer 156 has one input connected to the read multiplexer 150 and one input connected to the data signal MISOJNT.

[0068] A user controls the bypass signal BYPASS according to the current implementation of the circuit system 100, to operate the master device 102 in one of two modes. When the frequency of the first clock signal that is below a safe threshold (e.g. when the frequency is low enough such that the maximum expected round-trip delay between the master and slave devices 102, 104 is less than one first clock cycle), the bypass signal BYPASS is controlled such that the bypass multiplexer 156 causes the data signal MISOJNT to bypass the buffer entirely and instead be sent directly to the data input logic 146. This causes the master device 102 to operate in a first mode in which the data signal MISOJNT is sampled according to the first clock signal.

[0069] However, when the frequency of the first clock signal is above the safe threshold, the bypass signal BYPASS is controlled such that the bypass multiplexer 156 connects the read multiplexer 150 to the data input logic 146. In this second mode, the buffer 142 is used and the data signal MISO_II\IT is sampled according to the second clock signal as explained below.

[0070] The first clock signal generator portion 144 receives a core clock signal CCLK and generates the first clock signal SCLK_CORE. The core clock signal CCLK is used by the read pointer register 152 and the data input logic 146. The core clock signal CCLK also clocks other parts of the core portion 118.

[0071] The operation of the circuit system 100 when the buffer 142 is in use will now be described in more detail with reference to the timing diagrams 300, 400, 500 shown in Figures 3, 4 and 5.

[0072] Each of Figures 3-5 shows an operation in which the slave device 104 sends a series of seven bits to the master device 102, but with varying magnitudes of delay of the second clock signal FBCLK. The master device 102 controls the timing of the data transfer by transmitting seven SCLK pulses to the slave device 104. The slave device 104 sends seven MISO bits synchronised with these pulses.

[0073] Figure 3 shows an example where the delay of the second clock signal FBCLK is between 0 and 1 cycles of the first clock signal SCLK_CORE.

[0074] At a first time to, the master device 102 initiates the SCLK pulses. The first clock signal generator portion 144 begins to generate a first clock signal SCLK_CORE using the core clock CCLK. The first clock signal SCLK_CORE is in phase with and half the frequency of the core clock CCLK (In other examples the first clock signal SCLK_CORE may have a different frequency relationship to the core clock CCLK, e.g. being quarter the frequency). The first clock signal SCLK_CORE is transmitted via the clock output portion 106 (as SCLK) and received by the clock input 120 of the slave device 104.

[0075] The slave device 104 sends data to the master device 102 by transmitting a data signal MISO from the data output 122 to the data input portion 108. The data signal MISO is clocked by the first clock signal SCLK according to the SPI protocol. Transitions of the data signal MISO correspond with falling edges of the first clock signal SCLK. The first falling edge of the first clock signal SCLK occurs at ti . In other embodiments, transitions of the data signal MISO may correspond with rising edges of the first clock signal SCLK.

[0076] However, because the clock output portion 106 adds some delay to the first clock signal SCLK and the data input portion 108 adds some delay to the data signal MISO, the timing of the data signal MISOJNT after it has passed through the data input portion 108 is not in sync with the first clock signal SCLK_CORE before it is transmitted by the clock output portion 106. There is also an internal delay in the slave device 104 which adds a delay of less than one first clock cycle. Therefore, to avoid mitigate reception errors, the master device 102 uses the second clock signal FBCLK to sample the received data signal MISOJNT.

[0077] The first falling edge of the second clock signal FBCLK occurs at t2, delayed by dcik compared to the first clock signal SCLK_CORE. The delay dcik is determined by the components of the delay portion 114 and the routing and buffering elements 105, 115. The delay dcik is equal to a noninteger number of cycles of the core clock CCLK. As mentioned above, in the situation shown in Figure 3, the delay dcik is between 0 and 1 cycles of the first clock signal SCLK_CORE.

[0078] Because the delay portion 114 replicates the clock output portion 106 and the data input portion 108, and the routing and buffering elements 105, 115 match the routing and buffering elements 105, 109 associated with the clock output portion 106 and the data input portion 108, the delay dcik added to the second clock signal FBCLK approximates the delay experienced by the first clock signal SCLK as it is transmitted by the clock output portion 106, and the delay experienced by the data signal MISO as it is received by data input portion 108. The adjustable capacitor 143 is also be controlled to imitate the load capacitance experienced by the clock output portion 106. The bias current source 145 may be controlled to fine tune the delay of the delay portion 114.

[0079] Because the delay portion 114 replicates the sources of delay rather than simply attempting to compensate for an estimated delay, the delay dcik in the second clock signal FBCLK varies with PVT variations in the same way as the cumulative delay in the first clock signal and data signal.

[0080] As a result, the timing of the second clock signal FBCLK is suitable for sampling the data signal MISOJNT as it is received by the buffer 142.

[0081] The master device 102 stores incoming samples to the successive memory elements 148A- 148D according to the write pointer register 154. The write pointer register value WRITE_PTR is incremented on the rising edges of the second clock signal FBCLK, and thus causes successive states of the data signal MISOJNT to be stored to different storage elements of the buffer 142. For instance, the first falling edge of the second clock signal FBCLK occurs at t2, and the value of WRITE_PTR is 0. The first state of the data signal MISOJNT (which precedes the first valid data bit) is thus stored to the first memory element 148A. On the next falling edge of the second clock signal FBCLK, at time ts, the value of WRITE_PTR is 1 , and the next state of the data signal MISOJNT (i.e. the first valid data bit) is stored to the second memory element 148B.

[0082] This sampling process repeats for all bits of the incoming data signal MISOJNT, with the write pointer register value WRITE_PTR wrapping from 3 to 0 so that the buffer 142 acts as a circular buffer.

[0083] Thus, by using the second clock signal FBCLK, the buffer 142 can cleanly and reliably sample the incoming data signal MISOJNT, even when the delay experienced by the first clock signal SCLK and the data signal MISO varies with PVT variations. In the illustrated example, the buffer 142 is clocked by an inverted version of the second clock signal FBCLK. However this is not essential and in some embodiments a non-inverted version of the second clock signal FBCLK may be used. The buffer 142 may be controllable to use inverted or non-inverted versions of the second clock signal FBCLK as needed for different implementations.

[0084] Concurrently (albeit with a short delay), the master device 102 uses the buffer 142 to transfer the samples of the data signal MISOJNT from the second clock signal domain into the core clock signal domain in which the rest of the master device 102 operates.

[0085] The data input logic 146 reads the samples from the buffer 142 using the read multiplexer 150 and the read pointer register 152. Because there is an unknown and variable delay between the start of the first SCLKJDORE pulse and the data samples starting to be stored to the buffer 142, the data input logic 146 starts to read the samples only after a fixed read delay dbuffer_read from the start of the first SCLKJDORE pulse, at ts. The read pointer register 152 is enabled one cycle earlier, at t4, to ensure that the sample is there to be read. The data input logic 146 starts reading from the second memory element 148B to account for the non-valid (garbage) first bit.

[0086] The delay dbuffer_read is ten cycles of the core clock signal CCLK. This ensures that valid data will be read from the buffer 142 when reading starts for values of dcik between zero and seven cycles of the core clock signal CCLK (i.e. an expected range of delays). Similarly, the buffer 142 is sized to ensure that valid data is available to read for this range of delays. Figures 4 and 5 illustrate situations in which the circuit system 100 experiences other delays in this range.

[0087] Once enabled, the read pointer register value READ_PTR is incremented on falling edges of the first clock signal SCLKJDORE. This connects successive memory elements 148A-D of the buffer 142 to the output READJVIUX at successive falling edges of the first clock signal SCLK_CORE. The output READ_MUX thus provides the data of the incoming data signal to the data input logic 146 with a timing matching the first clock signal SCLK_CORE. The read times of the data input logic 146 portion are indicated by small circles at the bottom of Figure 3.

[0088] Figure 4 shows an example where the delay dcik of the second clock signal FBCLK is between 1 and 2 cycles of the first clock signal SCLK_CORE.

[0089] At a first time te, the master device 102 initiates the SCLK pulses and the first clock signal SCLK_CORE is transmitted via the clock output portion 106 (as SCLK) and received by the clock input 120 of the slave device 104.

[0090] The slave device 104 transmits the data signal MISO from the data output 122 to the data input portion 108, with transitions of the data signal MISO corresponding with falling edges of the first clock signal SCLK. The first falling edge of the first clock signal SCLK occurs at t?.

[0091] In the example shown in Figure 4, the first falling edge of the second clock signal FBCLK occurs at ts, with a delay dcik of roughly 1 .5 cycles of the first clock signal SCLK_CORE (determined by the components of the delay portion 114 and the routing and buffering elements 105, 115 to approximate the delay experienced by the first clock signal SCLK as it is transmitted by the clock output portion 106, and the delay experienced by the data signal MISO as it is received by data input portion 108.).

[0092] As a result, the timing of the second clock signal FBCLK is suitable for sampling the data signal MIS0_INT as it is received by the buffer 142.

[0093] As with the process described above with reference to Figure 3, the master device 102 stores incoming samples to the successive memory elements 148A-148D according to the write pointer register 154, with write pointer register value WRITE_PTR being incremented on the rising edges of the second clock signal FBCLK

[0094] Concurrently the master device 102 uses the buffer 142 to transfer the samples of the data signal MIS0_INT from the second clock signal domain into the core clock signal domain in which the rest of the master device 102 operates.

[0095] The data input logic 146 reads the samples from the buffer 142 using the read multiplexer 150 and the read pointer register 152, after the fixed read delay dbuffer_read from the start of the first SCLK_CORE pulse, at tg. The fixed read delay dbuffer_read is the same as that used in the situation shown in Figure 3 (i.e. ten cycles of the core clock signal CCLK).

[0096] Figure 5 shows another situation where the delay dcik of the second clock signal FBCLK is between 2 and 3 cycles of the first clock signal SCLK_CORE.

[0097] At a first time t , the master device 102 initiates the SCLK pulses and the first clock signal SCLK_CORE is transmitted via the clock output portion 106 (as SCLK) and received by the clock input 120 of the slave device 104. The first falling edge of the first clock signal SCLK occurs at tn.

[0098] The first falling edge of the second clock signal FBCLK occurs at ti2, with a delay dcik of roughly 2.5 cycles of the first clock signal SCLK_CORE.

[0099] The master device 102 stores incoming samples to the successive memory elements 148A- 148D according to the write pointer register 154, with write pointer register value WRITE_PTR being incremented on the rising edges of the second clock signal FBCLK

[0100] The data input logic 146 reads the samples from the buffer 142 using the read multiplexer 150 and the read pointer register 152, after the fixed read delay dbuffer_read from the start of the first SCLK_CORE pulse, at ti3. The fixed read delay dbuffer_read is the same as that used in the situation shown in Figure 3 and Figure 4 (i.e. ten cycles of the core clock signal CCLK).

[0101] Thus, the master device 102 is able to reliably receive and process an incoming SPI data signal that has an unknown and variable delay (albeit within known limits). The configuration described above (i.e. with four memory elements 148A-148D, and with a fixed read delay dbuffer_read of ten cycles) is operable to reliably receive data with a delay dcik of up to three cycles of the first clock signal SCLK_CORE, independent of the specific value of dcik.

[0102] While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the scope of the invention. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.

Claims

Claims1. A first circuit portion for receiving data from a second circuit portion, the first circuit portion comprising: a clock output portion; a data input portion; and a delay portion comprising a replica of at least part of the clock output portion or the data input portion; wherein the first circuit portion is arranged: to transmit a first clock signal via the clock output portion, and to input the first clock signal to the delay circuit portion to generate a second clock signal comprising a delayed version of the first clock signal; and to receive data from the second circuit portion by sampling a data signal input to the data input portion according to the second clock signal.

2. The circuit portion of claim 1 , wherein the delay portion comprises a replica of part or all of the clock output portion.

3. The circuit portion of claim 1 or 2, wherein the delay portion comprises a replica of part or all of the data input portion.

4. The circuit portion of any preceding claim, arranged to match a path taken by the first clock signal to the output clock portion to a path taken by the first clock signal to the delay portion.

5. The circuit portion of any preceding claim, arranged to match a path taken by the data signal from the data input portion to a path taken by the second clock signal from the delay portion.

6. The circuit portion of any preceding claim, wherein the delay portion comprises one or more additional delay elements arranged to compensate for a delay associated with the second circuit portion or a delay associated with the propagation of the first clock signal and / or the data signal between the first and second circuit portions.

7. The circuit portion of any preceding claim, wherein the delay portion comprises one or more configurable delay elements.

8. The circuit portion of any preceding claim, wherein the first clock signal has a frequency of 1 MHz or more.

9. The circuit portion of any preceding claim, wherein the second clock signal is delayed compared to the first clock signal by a first clock signal period or more.

10. The circuit portion of any preceding claim, comprising a Serial Peripheral Interface master device.

11. The circuit portion of any preceding claim, comprising a plurality of data input portions for receiving multiple data signals in parallel, wherein the first circuit portion is arranged to receive the data from the second circuit portion by sampling the multiple data signals according to the second clock signal.

12. The circuit portion of any preceding claim, comprising a buffer and arranged to sample the data signal according to the second clock signal by storing a state of the data signal to the buffer at times according to the second clock signal.

13. The circuit portion of claim 12, comprising data input logic arranged to operate according to a core clock signal that is different to the second clock signal, and the data input logic is arranged to read from the buffer according to the core clock signal.

14. The circuit portion of claim 13, wherein the data input logic is arranged to start to read from the buffer after a read delay based on an estimated or measured delay of the second clock signal.

15. The circuit portion of claim 13, wherein the data input logic is arranged to start to read from the buffer after a fixed read delay corresponding to a maximum expected delay of the second clock signal.

16. The circuit portion of any of claims 12-15, wherein the buffer comprises a plurality of memory elements arranged to store successive samples of the data signal.

17. The circuit portion of any preceding claim, operable in: a first mode in which the first circuit portion is arranged to sample the data signal according the first clock signal; and a second mode in which the first circuit portion is arranged to sample the data signal according to the second clock signal.

18. A method of operating a first circuit portion to receive data from a second circuit portion, the method comprising: transmitting a first clock signal via a clock output portion; generating a second clock signal that comprises a delayed version of the first clock signal by inputting the first clock signal to a delay portion comprising a replica of at least part of the clock output portion or a data input portion of the first circuit portion; and the first circuit portion receiving data from the second circuit portion by sampling a data signal input to the data input portion according to the second clock signal.

19. A circuit system comprising: a first circuit portion comprising a clock output portion, a data input portion, and a delay portion, the delay portion comprising a replica of at least part of the clock output portion or the data input portion; and a second circuit portion comprising a clock input connected to the clock output portion, and a data output connected to the data input portion; wherein the first circuit portion is arranged to transmit a first clock signal via the clock output portion, and to input the first clock signal to the delay circuit portion to generate a second clock signal comprising a delayed version of the first clock signal; wherein the second circuit portion is arranged to receive the first clock signal and to send data to the first circuit portion by transmitting a data signal to the data input portion via the data output according to the first clock signal; and wherein the first circuit portion is arranged to receive the data from the second circuit portion by sampling the data signal according to the second clock signal.

20. A method of operating a circuit system comprising a first circuit portion and a second circuit portion, the method comprising: the first circuit portion transmitting a first clock signal via a clock output portion; the second circuit portion receiving the first clock signal and sending data to the first circuit portion by transmitting a data signal according to the first clock signal to a data input portion of the first circuit portion; the first circuit portion generating a second clock signal that comprises a delayed version of the first clock signal by inputting the first clock signal to a delay portion, the delay portion comprising a replica of at least part of the clock output portion or the data input portion; and the first circuit portion receiving the data from the second circuit portion by sampling the data signal according to the second clock signal.

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