Computational task processing method and apparatus

Abstract

Provided in the present invention are a computational task processing method and apparatus. The method comprises: receiving a computational task, wherein the computational task comprises an original-version field, and then executing the following processing steps: modifying the original-version field to obtain a plurality of modified-version fields; and on the basis of the plurality of modified-version fields, executing a hash operation on the computational task to generate a plurality of intermediate state values, wherein the plurality of intermediate state values are used for proof-of-work computations. By using the method, computational space for a hash operation is increased, and the frequency of receiving tasks is reduced, thereby achieving the aim of improving the efficiency of computation; and the area of computing hardware can be reduced, thereby achieving the aim of reducing power consumption.

Description

Computational task processing method and device

[0001] This application claims priority to Chinese patent application number CN202311161624.7, filed on September 8, 2023, entitled “Computational Task Processing Method and Device,” and the disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention belongs to the field of computing processing technology, and in particular relates to a computing task processing method and device. Background Art

[0003] This section is intended to provide a background or context to embodiments of the invention that are recited in the claims. No statement herein is admitted to be prior art by inclusion in this section.

[0004] Proof of Work (POW) is a consensus mechanism used in some cryptographic calculations. Its fundamental characteristic is that it requires a large number of hash operations to find a hash value that meets certain requirements under a specific difficulty value, also known as block calculation. Essentially, it involves performing a large number of SHA-256 operations on a given block header to determine a set of hash values ​​that meet the desired difficulty. As shown in Figure 1, a block header used by a cryptographic algorithm consists of a 4-byte version field; a 32-byte previous block hash; a 32-byte hash Merkle root field; a 4-byte timestamp; a 4-byte target value; and a 4-byte random number. The block header is divided into two parts. The first part includes a 4-byte version field; a 32-byte previous block hash and the first 28-byte hash Merkle root field (the first section of the hash Merkle root); the second part includes a 4-byte hash Merkle root field (the second section of the hash Merkle root); a 4-byte timestamp; a 4-byte difficulty target value; and a 4-byte random number. This encryption algorithm stipulates that the first part needs to be calculated by SHA-256 first, and the result is the intermediate state value. The SHA-256 calculation is performed based on the intermediate state value and the second part, and finally the SHA-256 calculation is performed again based on the result to obtain a calculation result.

[0005] In traditional block calculation, the version field, the hash value of the previous block, and the difficulty target value are all fixed, so it is necessary to constantly modify the random number to calculate. However, the random number is only 4 bytes and can only do 2 32Therefore, the Merkle root is typically modified to find a larger computational space. As can be seen from the block header structure in Figure 1, the hash Merkle root is split into two parts. Existing techniques typically use a large number of hash collisions to find block headers with the same last 4 bytes of multiple hash Merkle roots, thereby maximizing computational efficiency and reducing power consumption. However, performing hash collisions to find the same last 4 bytes of the hash Merkle root is costly and may not be supported.

[0006] Therefore, how to implement proof-of-work calculations in a less costly and power-efficient manner is an urgent problem to be solved.

[0007] Summary of the Invention

[0008] In response to the problems existing in the above-mentioned prior art, a computing task processing method and device are proposed to maximize computing efficiency savings and solve the problems of high computational cost and high power consumption of the above-mentioned proof of work.

[0009] The present invention provides the following solutions.

[0010] In a first aspect, a computing task processing method is provided, comprising:

[0011] Receive a computing task including an original version field, and perform the following processing steps:

[0012] Modifying the original version field to obtain multiple modified version fields;

[0013] Based on the multiple modified version fields, a hash operation is performed on the computing task to generate multiple intermediate state values, and the multiple intermediate state values ​​are used for workload proof calculation.

[0014] In some embodiments, the processing steps are performed iteratively, and the modified version field in the (n+1)th round of processing steps is inconsistent with the modified version fields in the 1st to nth rounds of processing steps.

[0015] In some embodiments, it further includes:

[0016] Another computing task is received, and the processing step is performed based on the original version field of the another computing task.

[0017] In some embodiments, the original version field includes a fixed field, a soft fork voting field, and a remaining field, and the remaining field is used to modify the original version field to obtain multiple modified version fields.

[0018] In some embodiments, the bits of the remaining fields are modified randomly or in a fixed order to modify the original version field to obtain a plurality of modified version fields.

[0019] In some embodiments, the original version field is 32 bits and the remaining field is 16 bits.

[0020] In some embodiments, the computing task further includes a message field, wherein the message field includes a previous block hash and a first region of a hash Merkle root.

[0021] In some embodiments, it further includes:

[0022] Based on the intermediate state value, obtaining a plurality of sub-intermediate state values;

[0023] The serial data stream composed of the plurality of sub-intermediate state values ​​is outputted for use in workload proof calculation.

[0024] In some embodiments, based on the intermediate state value, it is split to obtain multiple sub-intermediate state values.

[0025] In some embodiments, the intermediate state value is 256 bits, and the sub-intermediate state value is 32 bits.

[0026] In some embodiments, the computing task further includes a message field, and performing a hash operation on the computing task based on the plurality of modified version fields to generate a plurality of intermediate state values ​​includes:

[0027] The plurality of modified version fields are respectively combined with the message field to obtain a plurality of first block fields, and a hash operation is performed based on the plurality of first block fields to generate a plurality of the intermediate state values.

[0028] In some embodiments, each first block field is split into multiple sub-first block fields, and a hash operation is performed based on a serial data stream formed by the multiple sub-first block fields of each first block field to generate the intermediate state value.

[0029] In some embodiments, based on the sequence values ​​of the plurality of modified version fields, each modified version field is combined with the message field to obtain a corresponding first block field.

[0030] In some embodiments, a pulse level corresponding to the sequence value is output, and in response to the pulse level, the modified version field corresponding to the sequence value and the message field are latched as the first block field.

[0031] In some embodiments, after performing a hash operation on the mth first block field to generate the intermediate state value, the m+1th modified version field and the message field are combined to obtain the m+1th first block field.

[0032] In some embodiments, it further includes:

[0033] A hash operation is performed based on the plurality of intermediate state values ​​and a second block field of the computing task to obtain proof of work; the second block field includes a second area of ​​the hash Merkle root, a timestamp, a target value, and a random number.

[0034] In some embodiments, performing a hash operation based on the plurality of intermediate state values ​​and the second block field of the computing task includes:

[0035] performing a first extension operation on the second block field to obtain first extended data;

[0036] performing a plurality of first compression operations based on the plurality of intermediate state values ​​and the first expansion operation result to obtain a plurality of first compressed data;

[0037] performing a plurality of second expansion operations based on the plurality of first compressed data to obtain a plurality of second expanded data;

[0038] A plurality of second compression operations are performed based on the plurality of second extended data to obtain the proof of work.

[0039] In some embodiments, the intermediate state value is generated in a high voltage region. After generating a plurality of the intermediate state values, the plurality of the intermediate state values ​​are converted from the high voltage region to a low voltage region for use in proof-of-work calculations.

[0040] In some embodiments, the intermediate state value is generated in a top region of the chip.

[0041] In some embodiments, the hash operation is a SHA-256 operation.

[0042] In a second aspect, a computing task processing device is provided, comprising:

[0043] A receiving module, configured to receive a computing task, wherein the computing task includes an original version field;

[0044] A modification module, which modifies the original version field to obtain multiple modified version fields;

[0045] A computing module is configured to perform a hash operation on the computing task based on the plurality of modified version fields to generate a plurality of the intermediate state values, wherein the plurality of the intermediate state values ​​are used for workload proof calculation.

[0046] In some embodiments, the modification module is further configured to iteratively modify a plurality of the modified version fields.

[0047] In some embodiments, the receiving module is further used to receive a new computing task, and the modifying module is further used to modify the original version field of the new computing task to obtain multiple modified version fields.

[0048] In some embodiments, the original version field includes a fixed field, a soft fork voting field, and a remaining field, and the remaining field is used to modify the original version field to obtain multiple modified version fields.

[0049] In some embodiments, the computing task further includes a message field, wherein the message field includes a previous block hash and a first region of a hash Merkle root.

[0050] In some embodiments, a bit width conversion module is further included, which is used to split the intermediate state value of the first bit width generated by the calculation module into multiple sub-intermediate state values ​​of the second bit width; the serial data stream composed of the multiple sub-intermediate state values ​​is used for proof of work calculation.

[0051] In some embodiments, the computing task also includes a message field, the computing module includes a first latch, the first latch is used to store a first block field composed of a single modified version field and the message field, and the computing module performs a hash operation based on multiple first block fields to generate multiple intermediate state values.

[0052] In some embodiments, the calculation module includes a shift register, which is used to split the first block field into multiple sub-first block fields, and the serial data stream composed of the multiple sub-first block fields is used to perform a hash operation to generate the intermediate state value.

[0053] In some embodiments, the calculation module includes a counter, which is used to generate a count value. The calculation module combines the modified version field corresponding to the count value and the message field based on the sequence values ​​of multiple modified version fields to obtain the corresponding first block field according to the count value.

[0054] In some embodiments, the calculation module includes a level generation module, which generates a corresponding pulse level according to the count value, and the calculation module latches the modified version field corresponding to the count value and the message field as the first block field in response to the pulse level.

[0055] In some embodiments, the calculation module generates a completion signal when generating a single intermediate state value, the counter updates the count value in response to the completion signal, and restores the count value to an initial value after all the first block fields perform hash operations.

[0056] In some embodiments, a proof-of-work calculation module is further included, which is used to perform a hash operation based on multiple intermediate state values ​​and the second block field of the computing task to obtain a proof of work; the second block field includes the second area of ​​the hash Merkle root, a timestamp, a target value, and a random number.

[0057] In some embodiments, it also includes multiple second latches for receiving multiple intermediate state values; a first expander for performing a first expansion operation on the second block field to obtain first expanded data; multiple first compressors for performing multiple first compression operations based on the multiple intermediate state values ​​and the first expansion operation results to obtain multiple first compressed data; multiple second expanders for performing multiple second expansion operations based on the multiple first compressed data to obtain multiple second expanded data; and multiple second compressors for performing multiple second compression operations based on the multiple second expanded data to obtain the proof of work.

[0058] In some embodiments, the computing module is disposed in a top layer area of ​​the chip.

[0059] In some embodiments, a level converter is further included for converting the plurality of intermediate state values ​​from a high voltage region to a low voltage region.

[0060] In some embodiments, the hash operation is a SHA-256 operation.

[0061] At least one of the above-mentioned technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: In this embodiment, by adding modifications to the version field, the computational space for hash operations is increased, the frequency of receiving tasks is reduced, and computational efficiency is improved. Furthermore, in this application, no additional storage space is required to store block headers with the same 4 bytes after the hash Merkle root generated by hash collision operations, nor is additional storage space required to store calculated intermediate state values. Multiple intermediate state values ​​generated based on multiple modified version fields are pipelined and input to the next stage for proof-of-work calculations, thereby reducing the computing hardware area and achieving the purpose of reducing power consumption.

[0062] It should be understood that the above description is only an overview of the technical solution of the present invention, so that the technical means of the present invention can be more clearly understood and implemented in accordance with the contents of the description. In order to make the above and other objects, features and advantages of the present invention more clearly understood, the following examples are given to illustrate specific embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The advantages and benefits described herein, as well as other advantages and benefits, will become apparent to those skilled in the art upon reading the detailed description of the exemplary embodiments below. The accompanying drawings are provided for illustration purposes only and are not to be construed as limiting the present invention. The same reference numerals are used throughout the accompanying drawings to denote the same components. In the accompanying drawings:

[0064] FIG1 is a schematic diagram of a block header structure in the prior art;

[0065] FIG2 is a flow chart of a method for calculating proof of work according to an embodiment of the present invention;

[0066] FIG3 is a schematic diagram of the structure of a computing chip according to an embodiment of the present invention;

[0067] FIG4 is a schematic diagram of a transmission state of an intermediate state value according to an embodiment of the present invention;

[0068] FIG5 is a schematic flow chart of a method for calculating proof of work according to another embodiment of the present invention;

[0069] FIG6 is a schematic diagram of the structure of a computing device for proof of work according to an embodiment of the present invention;

[0070] FIG7 is a schematic diagram of the structure of a computing module of a computing device for proof of work according to an embodiment of the present invention;

[0071] FIG8 is a schematic diagram of the structure of a next-level computing core according to an embodiment of the present invention.

[0072] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts. DETAILED DESCRIPTION

[0073] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0074] In the description of the embodiments of the present application, it should be understood that terms such as "including" or "having" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or a combination thereof disclosed in this specification, and are not intended to exclude the possibility of the presence of one or more other features, numbers, steps, actions, components, parts, or a combination thereof.

[0075] Unless otherwise specified, “ / ” means or. For example, A / B can mean A or B. “and / or” in this article is only a way to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0076] The terms "first," "second," etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0077] All codes in this application are exemplary, and those skilled in the art may think of various modifications based on the programming language used, specific needs, personal habits and other factors without departing from the ideas of this application.

[0078] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0079] Referring to Figure 1, the block header structure shows that the hash Merkle root is split into two parts: the first 28-byte Head (the first area of ​​the hash Merkle root) and the last 4-byte Tail (the second area of ​​the hash Merkle root). The calculation of the intermediate state value relies only on the first 512 bits of the block header. The traditional method uses hash collision to find multiple candidate Merkle root values ​​with a modified Head portion and an unchanged Tail portion. The Mid value is then calculated based on these values ​​for subsequent calculations. This can increase the computational space of SHA-256, but changing the Head portion of the Merkle root will increase the computational complexity. Therefore, if other fields in the first part can be changed to traverse the values ​​within it, more computational space may be available.

[0080] The first part of the block header includes the version field, the previous block hash, and the first 28 bytes of the Merkle root. The 4-byte version field has a total of 32 bits, of which the first 3 bits are fixed, and the remaining bits are used for voting during technology upgrades or soft forks. However, in actual applications, there will not be so many soft fork votes at the same time. Therefore, some of these bits can be ignored by modifying the node software, so that these bits can be used for general use without issuing error warnings during soft forks. Referring to the BIP320 protocol, it stipulates that the 13-28 bits of the version field can be occupied, that is, 0x1fffe000. If this 16-bit space can be used, then there will be 2 more16 When receiving the same task, you can perform 2 16 Rounds of operation, and each round of operation can be 2 32 The operation of traversing random numbers, that is, a total of 2 16 ×2 32 Based on this, this application uses the version field in the first part of the block header as a modification item.

[0081] FIG2 is a flow chart of a method for processing a computing task according to an embodiment of the present application. As shown in FIG2 , the method provided in this embodiment may include the following steps:

[0082] Step 210: Receive a computing task, which includes an original version field; then, perform the following processing steps:

[0083] Step 220: Modify the original version field to obtain multiple modified version fields;

[0084] Step 230: Based on the multiple modified version fields, perform a hash operation on the computing task to generate multiple intermediate state values, and the multiple intermediate state values ​​are used for workload proof calculation.

[0085] In the above scheme, after the front end of the computing device receives the computing task, it can use software to modify the configuration of the original version field to obtain multiple modified version fields. The back end of the computing device, that is, the computing chip, can receive multiple modified version fields through the APB bus. The computing task also includes a message field. The multiple modified version fields and the message field are combined to obtain multiple first blocks. The computing chip performs a hash operation on them to obtain an intermediate state value. The intermediate state value is output to the next level for subsequent hash operation to finally obtain the proof of work.

[0086] The hash operation includes a pre-hash operation, which includes an expansion operation and a compression operation. The expansion operation uses the first 512 bits of the block header, including the modified version field and the message field. The message field includes the previous block hash and the first area of ​​the hash Merkle root. The compression operation uses the 256-bit constant field and the output of the expansion operation, ultimately outputting the intermediate state value.

[0087] Referring to Figure 3, the generation of the intermediate state value can be done in the top area of ​​the computing chip. The top area can also be understood as the main control area of ​​the computing chip. The top area works in the high voltage area and can issue computing instructions to the computing area. The computing chip also includes multiple computing areas, each of which can be understood as the computing core of the computing chip. The computing core uses the intermediate state value and the second part of the block header, that is, the last 4 bytes of the hash Merkle root field (the second area of ​​the hash Merkle root), a 4-byte timestamp, a 4-byte difficulty target value, and a 4-byte random number to complete the proof of work calculation. The top area works in the high voltage area, can issue computing instructions to the computing area, and receive data from the computing area; the computing area works in the low voltage area, and the high frequency operation of the computing area is used to calculate the 2 32 times the operation space.

[0088] In this embodiment, by adding modifications to the version field, the computational space for hash operations is increased, the frequency of receiving tasks is reduced, and computational efficiency is improved. Furthermore, this application does not require additional storage space to store block headers with the same 4 bytes after the hash Merkle root generated by hash collision operations, nor does it require additional storage space to store calculated intermediate state values. Multiple intermediate state values ​​generated based on multiple modified version fields are pipelined into the next stage for proof-of-work calculations, thereby reducing the area of ​​computing hardware and achieving the goal of reducing power consumption.

[0089] In some embodiments, the processing steps are iteratively performed, and the modified version field in the (n+1)th round of processing steps is inconsistent with the modified version fields in the 1st to nth rounds of processing steps.

[0090] In the above scheme, after receiving a computing task, the modification space of the original version field is 16 bits, which can be 2 16 In each round of operation, multiple modified version fields are generated, correspondingly multiple intermediate state values ​​are generated, and then the original version fields are modified in the next round to obtain new modified version fields.

[0091] In some embodiments, the method further includes: receiving another computing task, and executing a processing step based on an original version field of the another computing task.

[0092] In the above scheme, in the computation space of the computation task, i.e. 2 16 ×2 32 After the calculation is completed, or after the calculation task generates the target result, or after the previous round of calculation task is stopped, the front end of the computing device receives a new calculation task, and then modifies the original version field of the new calculation task to obtain multiple modified version fields, and then generates an intermediate state value based on the modified version field, and finally performs proof of work calculation based on the intermediate state value.

[0093] In some embodiments, the original version field includes a fixed field, a soft fork voting field, and a remaining field, and the remaining field is used to modify the original version field to obtain multiple modified version fields.

[0094] In the above scheme, the 4-byte version field has a total of 32 bits. The first 3 bits are fixed, i.e., the fixed field. The remaining bits are used for voting during technology upgrades or soft forks, i.e., the soft fork voting field. However, in practice, there will not be so many soft fork votes at the same time. Therefore, it is possible to modify the node software to ignore some of these bits. This allows these bits, i.e., the remaining field, to be used for general use without generating error warnings during soft forks. Referring to the BIP320 protocol, it stipulates that bits 13-28 of the version field can be occupied, i.e., 0x1fffe000.

[0095] In some embodiments, the bits of the remaining fields are modified randomly or in a fixed order to modify the original version field to obtain multiple modified version fields.

[0096] In the above scheme, the bits of the remaining field occupy 13-28 bits of the version field. Each bit can be modified to 0 or 1 randomly or in a fixed order, thereby modifying the original version field to obtain multiple modified version fields.

[0097] In some embodiments, the original version field is 32 bits and the remaining field is 16 bits.

[0098] In the above scheme, the original version field is the first 4 sections of the block header, that is, 32 bits, and the bits of the remaining fields occupy 13-28 bits of the version field, which can be used for 2 16 Modifications.

[0099] In some embodiments, the computation task further includes a message field including a previous block hash and a first region of the hash Merkle root.

[0100] In the above scheme, the calculation task is the block header, which includes the first part, which includes: a 4-byte version field; a 32-byte previous block hash and the first 28-byte hash Merkle root field (the first area of ​​the hash Merkle root). The modified version field and the message field are combined to form the first block field, which is used to perform the pre-hash operation to obtain the intermediate state value.

[0101] In some embodiments, it further includes:

[0102] Based on the intermediate state value, obtaining multiple sub-intermediate state values;

[0103] The serial data stream consisting of multiple sub-intermediate state values ​​is output for proof-of-work calculation.

[0104] In the above scheme, the pre-hash operation occurs in the high-voltage area, and the subsequent hash operation occurs in the low-voltage area. The data bit width of the generated intermediate state value can be 256 bits. In order to reduce the routing bit width requirements from the high-voltage area to the low-voltage area, a bit width conversion operation can be used.

[0105] In some embodiments, based on the intermediate state value, it is split to obtain multiple sub-intermediate state values.

[0106] In the above solution, the intermediate state value is evenly split from the lowest bit to the highest bit, and finally multiple sub-intermediate state values ​​with the same length are obtained.

[0107] In some embodiments, the intermediate state value is 256 bits, and the sub-intermediate state value is 64 bits.

[0108] In the above scheme, each intermediate state value of 256 bits can be divided into 64-bit sub-intermediate state values, which are defined as {mid <n>_3,mid <n>_2,mid <n>_1,mid <n>_0}(n=0,1,2,3), where n is the identifier of the intermediate state value. Each intermediate state value is serially transmitted in 4 cycles according to the 64-bit data bit width. If there are 4 intermediate state values, a serial data stream similar to the sequence shown in Figure 4 is formed according to the order of the intermediate state value identifiers and is passed to the next level for use.

[0109] In some embodiments, the computing task further includes a message field, and based on the multiple modified version fields, a hash operation is performed on the computing task to generate multiple intermediate state values, including:

[0110] The multiple modified version fields are respectively combined with the message field to obtain multiple first block fields, and a hash operation is performed based on the multiple first block fields to generate multiple intermediate state values.

[0111] In the above scheme, the first block field is the first part of the block header, which includes: a 4-byte version field; a 32-byte previous block hash; and the first 28 bytes of the hash Merkle root field (the first area of ​​the hash Merkle root). The first block field is 512 bits. Each time multiple modified version fields are received, each modified version field is combined with the message field to form the first block field, and then a pre-hash operation is performed to generate an intermediate state value.

[0112] In some embodiments, each first block field is split into multiple sub-first block fields, and a hash operation is performed based on a serial data stream formed by the multiple sub-first block fields of each first block field to generate an intermediate state value.

[0113] In the above scheme, the first block field can be 512 bits. To meet the routing width requirements and facilitate the pre-hash operation in the top-level area of ​​the computing chip, the data is split into fine-grained 32-bit sub-block fields for SHA-256 pipeline calculation. After 64 rounds of expansion and compression operations, the intermediate state value is finally generated.

[0114] In some embodiments, based on the sequential values ​​of the plurality of modification version fields, each modification version field is combined with the message field to obtain the corresponding first block field.

[0115] In the above scheme, multiple modified version fields have an identifier, i.e., a sequence value, when generated. Each modified version field is combined with the message field according to the sequence value to form the first block field, and then a pre-hash operation is performed to generate an intermediate state value.

[0116] In some embodiments, a pulse level corresponding to the sequence value is output, and in response to the pulse level, the modified version field and the message field corresponding to the sequence value are latched as the first block field.

[0117] In the above scheme, a pulse level corresponding to the sequence value is output, and then the corresponding modified version field and message field are latched to form a first block field for performing a pre-hash operation.

[0118] In some embodiments, after performing a hash operation on the mth first block field to generate an intermediate state value, the m+1th modified version field and the message field are combined to obtain the m+1th first block field.

[0119] In the above scheme, to conserve the hardware circuit area of ​​the computing chip, only one pre-hash operation unit is provided to perform a single expansion and compression operation. Therefore, only a single first block field can be calculated at a time. After generating a single intermediate state value, the next first block field is latched and the next pre-hash operation is performed. The multiple intermediate state values ​​generated in sequence form a serial pipeline data that can be directly passed to the next stage for proof-of-work calculation without storage, thus reducing the computing hardware area and achieving the goal of lowering power consumption.

[0120] In some embodiments, it further includes:

[0121] A hash operation is performed based on multiple intermediate state values ​​and the second block field of the computing task to obtain the proof of work; the second block field includes the second area of ​​the hash Merkle root, a timestamp, a target value, and a random number.

[0122] In the above scheme, the second part of the block header, or the second block field, includes: the last 4 bytes of the hash Merkle root field (the second area of ​​the hash Merkle root); a 4-byte timestamp; a 4-byte difficulty target value; and a 4-byte random number. The final generation of the proof of work occurs in multiple computing areas of the computing chip, and each computing area performs two hash operations, including the first hash operation and the second hash operation.

[0123] In some embodiments, referring to FIG. 5 , performing a hash operation based on a plurality of intermediate state values ​​and a second block field of a computing task includes:

[0124] Step 510: Perform a first extension operation on the second block field to obtain first extended data;

[0125] Step 520: Perform multiple first compression operations based on the multiple intermediate state values, the first expansion operation result, and the second block field to obtain multiple first compressed data.

[0126] Step 530: Perform multiple second expansion operations based on the multiple first compressed data to obtain multiple second expanded data;

[0127] Step 540: Perform multiple second compression operations based on the multiple second extended data to obtain proof of work.

[0128] In the above solution, the first hash operation includes a first expansion operation and multiple first compression operations, and the second hash operation includes multiple second expansion operations and multiple second compression operations.

[0129] When performing the first hash operation, a single operation area, i.e., the operation core, includes a single first expander and multiple first compressors. The first expander uses the second block field to perform the first expansion operation to obtain first expanded data. Multiple first compressors can share the first expanded data of the single expander. The multiple first compressors perform multiple first compression operations corresponding to multiple intermediate state values ​​and the second block field to obtain multiple first compressed data. Because multiple first expanders do not need to be arranged in multiples and do not need to correspond one-to-one with multiple first compressors, the layout area of ​​the operation core is saved, further reducing power consumption.

[0130] When performing the second hash operation, a single operation area, i.e., an operation core, includes multiple second expanders and multiple second compressors. The multiple second expanders perform multiple second expansion operations based on the multiple first compressed data to obtain multiple second expanded data. The multiple second compressors perform multiple second compression operations based on the multiple second expanded data and a 256-bit constant field to obtain proof of work.

[0131] Each time a round of the first and second hash operations is completed, the random number in the second block field in the next round of hash operations must be within 2 32 The operation space is switched again, thereby traversing the operation space of the block header to complete the proof of work calculation.

[0132] In some embodiments, the intermediate state value is generated in the top area of ​​the chip, and the intermediate state value is generated in the high voltage area. After generating multiple intermediate state values, the multiple intermediate state values ​​are converted from the high voltage area to the low voltage area for proof of work calculation.

[0133] In the above scheme, the generation of the intermediate state value can be done in the top area of ​​the computing chip. The top area can also be understood as the main control area of ​​the computing chip. The top area works in the high voltage area and can issue computing instructions to the computing area. The computing chip also includes multiple computing areas, each of which can be understood as the computing core of the computing chip. The top area works in the high voltage area and can issue computing instructions to the computing area and receive data from the computing area; the computing area works in the low voltage area, and the high frequency operation of the computing area is used to calculate the 2 32 The top-level area performs the pre-hash operation to generate the intermediate state value to multiple operation areas. The operation area needs to be in 2 32 The first hash operation and the second hash operation are traversed in the operation space for the second time, so the operation area works in a low voltage and high frequency environment to speed up the calculation efficiency. During the time of traversing the operation area, the top area does not have to calculate and generate the intermediate state value all the time, but waits until the operation area is traversed before adding the value in the version field 2. 16 The next round of intermediate state values ​​is generated within the modifiable range. Therefore, the top-level area operates in a high-voltage, low-frequency environment to complete the pre-hash operation. Converting the intermediate state values ​​from the high-voltage area to the low-voltage area facilitates high-speed calculations in the operation area, improving computing efficiency.

[0134] In some embodiments, the hash operation is a SHA-256 operation.

[0135] In the above scheme, the hash operation is a SHA operation, specifically a SHA-256 operation. This scheme can also be applied to the SHA-1, SHA-2, and RIPEMD families, which all use schemes similar to SHA-256. Therefore, if a variable domain can be added, the number of input acceptance tasks will be reduced, which can also improve computational efficiency.

[0136] Based on the same technical concept, an embodiment of the present invention further provides a computing task processing device for executing the computing task processing method provided by any of the above embodiments. FIG6 is a schematic diagram of the structure of a computing task processing device provided by an embodiment of the present invention.

[0137] The computing task processing device comprises:

[0138] A receiving module 610 is configured to receive a computing task, where the computing task includes an original version field;

[0139] A modification module 620 modifies the original version field to obtain multiple modified version fields;

[0140] The computing module 630 is used to perform a hash operation on the computing task based on the multiple modified version fields to generate multiple intermediate state values, and the multiple intermediate state values ​​are used for workload proof calculation.

[0141] In the above scheme, the receiving module 610 and the modifying module 620 can be set at the front end of the computing device, and the original version field can be modified and configured using software to obtain multiple modified version fields. The computing module 630 can be set at the back end of the computing device, specifically the top area of ​​the computing chip. The top area can also be understood as the main control area of ​​the computing chip. The computing module 630 is used to complete the pre-hash operation to generate an intermediate state value. The generated intermediate state value is pipelined to multiple computing areas of the computing chip for workload proof calculation. Of course, the receiving module 610 and the modifying module 620 can also be set in the computing chip, and the computing module 630 can also be set at the front end of the computing device. This application does not make specific restrictions on this. The receiving module 610 and the modifying module 620 can be set at the front end of the computing device, and the computing module 630 can be set at the back end of the computing device, just as one of the preferred embodiments.

[0142] In this embodiment, by adding modifications to the version field, the computational space for hash operations is increased, the frequency of receiving tasks is reduced, and computational efficiency is improved. Furthermore, this application does not require additional storage space to store block headers with the same 4 bytes after the hash Merkle root generated by hash collision operations, nor does it require additional storage space to store calculated intermediate state values. Multiple intermediate state values ​​generated based on multiple modified version fields are pipelined into the next stage for proof-of-work calculations, thereby reducing the area of ​​computing hardware and achieving the goal of reducing power consumption.

[0143] In some embodiments, the modification module 630 is further configured to iteratively modify multiple modified version fields.

[0144] In the above scheme, in a computing chip, the top area of ​​the computing chip receives multiple modified version fields in each round, and generates multiple intermediate state values ​​accordingly. The generated intermediate state values ​​are pipelined to all or part of the computing areas of the computing chip for workload proof calculation. The computing area traverses 2 32 The random number in the second block field is then received by the top area of ​​the computing chip, which then receives multiple modified version fields of the next round. This cycle continues, continuously generating intermediate state values ​​and transmitting them to the computing area of ​​the computing chip until the computing task is completed or stopped.

[0145] In some embodiments, the receiving module 620 is further configured to receive a new computing task, and the modifying module 620 is further configured to modify the original version field of the new computing task to obtain multiple modified version fields.

[0146] In the above scheme, in the computation space of the computation task, i.e. 2 16 ×2 32 After the calculation is completed, or after the calculation task generates the target result, or after the previous round of calculation task is stopped, the receiving module 610 receives a new calculation task, the modification module 620 modifies the original version field of the new calculation task to obtain multiple modified version fields, and the calculation module 630 generates an intermediate state value based on the modified version field, and finally performs proof of work calculation based on the intermediate state value.

[0147] In some embodiments, the original version field includes a fixed field, a soft fork voting field, and a remaining field, and the remaining field is used to modify the original version field to obtain multiple modified version fields.

[0148] In the above scheme, the 4-byte version field has a total of 32 bits. The first 3 bits are fixed, i.e., the fixed field. The remaining bits are used for voting during technology upgrades or soft forks, i.e., the soft fork voting field. However, in practice, there will not be so many soft fork votes simultaneously. Therefore, it is possible to modify the node software to ignore some of these bits. This allows these bits, i.e., the remaining field, to be used for general use without generating error warnings during soft forks. Referring to the BIP320 protocol, it stipulates that bits 13-28 of the version field can be occupied, i.e., 0x1fffe000. The remaining field bits occupy bits 13-28 of the version field. Each bit can be modified to 0 or 1 in a random or fixed order, thereby modifying the original version field to generate multiple modified version fields.

[0149] In some embodiments, the computation task further includes a message field including a previous block hash and a first region of the hash Merkle root.

[0150] In the above scheme, the calculation task is the block header, which includes the first part, which includes: a 4-byte version field; a 32-byte previous block hash and the first 28-byte hash Merkle root field (the first area of ​​the hash Merkle root). The modified version field and the message field are combined to form the first block field. The first block field is used by the calculation module to perform a pre-hash operation to obtain an intermediate state value.

[0151] In some embodiments, a bit width conversion module is also included, which is used to split the intermediate state value of the first bit width generated by the calculation module into multiple sub-intermediate state values ​​of the second bit width; the serial data stream composed of the multiple sub-intermediate state values ​​is used for proof of work calculation.

[0152] In the above scheme, the pre-hashing operation occurs in the high voltage area, and the subsequent hashing operation occurs in the low voltage area. The data width of the generated intermediate state value can be 256 bits. In order to reduce the wiring width requirement from the high voltage area to the low voltage area, a bit width conversion operation can be used. The bit width conversion module can be used to split each intermediate state value of the output 256 bits into 64-bit sub-intermediate state values, which are defined as {mid <n>_3,mid <n>_2,mid <n>_1,mid <n>_0}(n=0,1,2,3), where n is the identifier of the intermediate state value. Each intermediate state value is serially transmitted in 4 cycles according to the 64-bit data bit width. If there are 4 intermediate state values, a serial data stream similar to the sequence shown in Figure 4 is formed according to the order of the intermediate state value identifiers and is passed to the next level for use.

[0153] In some embodiments, the computing task also includes a message field. Referring to Figure 7, the computing module 630 includes a first latch 631, which is used to store a first block field composed of a single modified version field and a message field. The computing module 630 performs a hash operation based on multiple first block fields to generate multiple intermediate state values.

[0154] In the above scheme, the first block field is the first part of the block header, which includes: a 4-byte version field; a 32-byte previous block hash; and the first 28 bytes of the hash Merkle root field (the first area of ​​the hash Merkle root). The first block field is 512 bits. Each time multiple modified version fields are received, the first latch 631 needs to combine each modified version field with the message field to form the first block field, and then perform a pre-hash operation to generate an intermediate state value.

[0155] In some embodiments, still referring to Figure 7, the calculation module 630 includes a shift register 632, which is used to split the first block field into multiple sub-first block fields, and the serial data stream composed of the multiple sub-first block fields is used to perform a hash operation to generate an intermediate state value.

[0156] In the above scheme, the first block field can be 512 bits. To meet the required routing width and facilitate pre-hashing operations in the top-level area of ​​the computing chip, the data is split into fine-grained 32-bit sub-block fields using shift registers for SHA-256 pipeline calculations. After 64 rounds of expansion and compression operations, the intermediate state value is finally generated.

[0157] In some embodiments, still referring to Figure 7, the calculation module 630 includes a counter 633, which is used to generate a count value, so that the calculation module 630 combines the modified version field and the message field corresponding to the count value based on the sequence values ​​of multiple modified version fields to obtain the corresponding first block field.

[0158] In the above scheme, multiple modified version fields have an identifier, i.e., a sequence value, when generated. The first latch 631 responds to the count value, and the corresponding sequence value combines each modified version field with the message field to form a first block field, and then performs a pre-hash operation to generate an intermediate state value.

[0159] In some embodiments, still referring to Figure 7, the calculation module 630 includes a level generation module 634, which generates a corresponding pulse level according to the count value. The calculation module latches the modified version field and the message field corresponding to the count value as the first block field in response to the pulse level.

[0160] In the above scheme, the level generation module 634 outputs a pulse level corresponding to the count value according to the count value output by the counter 633. The pulse level corresponds to the sequence value. Then the first latch 631 latches the corresponding modified version field and the message field to form the first block field for performing the pre-hash operation.

[0161] It can be understood that a latch is a storage unit circuit that is sensitive to pulse levels and can change state under the influence of a specific input pulse level. Latching is to temporarily store a signal to maintain a certain level state. In this embodiment, multiple count values ​​of counter 633 are associated with multiple pulse levels, and the count value itself and the sequence value of the version field also have a one-to-one correspondence. Then, the generated pulse level can be used to latch the version field and message field corresponding to the current count value as the first block field. By setting the coordinated operation of the latch and the counter, this embodiment can generate the first block field corresponding to multiple version fields in an orderly and pipelined manner.

[0162] In some embodiments, the calculation module 630 generates a completion signal when generating a single intermediate state value, the counter 633 updates the count value in response to the completion signal, and restores the count value to the initial value after all the first block fields perform the hash operation.

[0163] In the above scheme, to conserve hardware circuit area on the computing chip, the computing module only includes a single pre-hash operation unit to perform a single expansion and compression operation, so it can only perform calculations on a single first-block field at a time. After generating a single intermediate state value, it begins latching the next first-block field to perform the next pre-hash operation. After the computing module receives multiple modified version fields and message fields, the value of counter 633 is 0. At this time, the first latch 631 latches the modified version field and message field with a sequence value of 0. After the pre-hash operation unit generates the 0th intermediate state value, it generates a completion signal, and the counter 633 updates its count value to 1. The first latch 631 then begins latching the modified version field and message field with a sequence value of 1. After all the first-block fields have been hashed, the count value of counter 633 returns to its initial value, and the computing module waits to receive the next round of multiple modified version fields and message fields. The multiple intermediate state values ​​generated sequentially form a serial pipeline of data that can be directly passed to the next stage for proof-of-work calculations without storage, thereby reducing computing hardware area and power consumption.

[0164] In some embodiments, a proof-of-work calculation module is further included, which is used to perform a hash operation based on multiple intermediate state values ​​and the second block field of the computing task to obtain a proof of work; the second block field includes the second area of ​​the hash Merkle root, a timestamp, a target value, and a random number.

[0165] In the above scheme, the second part of the block header, or the second block field, includes: the last 4 bytes of the hash Merkle root field (the second area of ​​the hash Merkle root); a 4-byte timestamp; a 4-byte difficulty target value; and a 4-byte random number. The final generation of the proof of work occurs in multiple computing areas of the computing chip, namely the proof-of-work computing modules, also known as computing cores. Each computing core performs two hash operations: the first hash operation and the second hash operation.

[0166] In some embodiments, it also includes multiple second latches for receiving multiple intermediate state values; a first expander for performing a first expansion operation on the second block field to obtain first expanded data; multiple first compressors for performing multiple first compression operations based on the multiple intermediate state values ​​and the first expansion operation results and the second block field to obtain multiple first compressed data; multiple second expanders for performing multiple second expansion operations based on the multiple first compressed data to obtain multiple second expanded data; and multiple second compressors for performing multiple second compression operations based on the multiple second expanded data to obtain proof of work.

[0167] Referring to Figure 8, the proof-of-work calculation module, i.e., the operation core, includes: multiple second latches arranged in parallel, such as the second latch _0, the second latch _1, the second latch _2, and the second latch _3; multiple first compressors arranged in parallel, such as the first compressor _0, the first compressor _1, the first compressor _2, and the first compressor _3, and the multiple first compressors are electrically connected to the multiple second latches in a one-to-one correspondence; a first expander, and the multiple first compressors are electrically connected to the first expander in common; multiple second expanders arranged in parallel, such as the second expander _0, the second expander _1, the second expander _2, and the second expander _3, which are electrically connected to the multiple first compressors in a one-to-one correspondence; multiple second compressors, such as the second compressor _0, the second compressor _1, the second compressor _2, and the second compressor _3, which are electrically connected to the multiple second expanders in a one-to-one correspondence.

[0168] The first latch and the second latch in this embodiment refer to electronic devices with a latching function, and are not limited to dedicated latches. Therefore, other devices with a latching function can also be used as the above-mentioned first latch or second latch, such as a register.

[0169] In the above solution, the first hash operation includes a first expansion operation and multiple first compression operations, and the second hash operation includes multiple second expansion operations and multiple second compression operations.

[0170] When performing the first hash operation, a single operation area, i.e., the operation core, includes a single first expander and multiple first compressors. The first expander performs a first expansion operation using the second block field to obtain first expanded data. Multiple first compressors can share the first expanded data of the single expander. The multiple first compressors perform multiple first compression operations corresponding to multiple intermediate state values ​​and the second block field to obtain multiple first compressed data. Because multiple first expanders do not need to be arranged in a one-to-one correspondence with multiple first compressors, the layout area of ​​the operation core is saved, further reducing power consumption.

[0171] When performing the second hash operation, a single operation area, i.e., an operation core, includes multiple second expanders and multiple second compressors. The multiple second expanders perform multiple second expansion operations based on the multiple first compressed data to obtain multiple second expanded data. The multiple second compressors perform multiple second compression operations based on the multiple second expanded data and a 256-bit constant field to obtain proof of work.

[0172] Each time a round of the first and second hash operations is completed, the random number in the second block field in the next round of hash operations must be within 2 32 The operation space is switched again, thereby traversing the operation space of the block header to complete the proof of work calculation.

[0173] In some embodiments, the computing module is disposed in a top region of the chip, and further includes a level converter for converting a plurality of intermediate state values ​​from a high voltage region to a low voltage region.

[0174] In the above scheme, the generation of the intermediate state value can be done in the top area of ​​the computing chip. The top area can also be understood as the main control area of ​​the computing chip. The top area works in the high voltage area and can issue computing instructions to the computing area. The computing chip also includes multiple computing areas, each of which can be understood as the computing core of the computing chip. The top area works in the high voltage area and can issue computing instructions to the computing area and receive data from the computing area; the computing area works in the low voltage area, and the high frequency operation of the computing area is used to calculate the 2 32 The top-level area performs the pre-hash operation to generate the intermediate state value to multiple operation areas. The operation area needs to be in 2 32 The first hash operation and the second hash operation are traversed in the operation space for the second time, so the operation area works in a low voltage and high frequency environment to speed up the calculation efficiency. During the time of traversing the operation area, the top area does not have to calculate and generate the intermediate state value all the time, but waits until the operation area is traversed before adding the value in the version field 2. 16 The next round of intermediate state values ​​is generated within the modifiable range. Therefore, the top-level area operates in a high-voltage, low-frequency environment to complete the pre-hash operation. The use of a level converter to convert the intermediate state values ​​from the high-voltage area to the low-voltage area facilitates high-speed calculations in the operation area and improves computing efficiency.

[0175] In some embodiments, the hash operation is a SHA-256 operation.

[0176] The following is one specific embodiment of this application:

[0177] The receiving module and the modification module can be set at the front end of the computing device, and the software can be used to modify the configuration of the original version field to obtain multiple modified version fields. The computing module can be set at the back end of the computing device, specifically the top-level area of ​​the computing chip. The top-level area can also be understood as the main control area of ​​the computing chip.

[0178] The computation module receives multiple revision fields and message fields configured by software via the APB bus. For example, four revision fields are included in the message field, which includes the previous block hash value and the first 28 bytes of the hash Merkle root. Because there are four revision fields, a set of 2-bit counters can be maintained. Each 2-bit counter has four count values ​​{0, 1, 2, 3}, where the four count values ​​{0, 1, 2, 3} of the counter correspond one-to-one to the sequential values ​​of the four revision fields.

[0179] Furthermore, according to the current count value of the counter, the modified version field and the message field corresponding to the current count value can be spliced ​​and latched using the first latch, thereby obtaining the first block field {modified version field, message field} corresponding to the current count value, that is, the first 512 bits of the block header shown in Figure 1.

[0180] After obtaining the first block field, the latched first block field can be used for pre-hashing. To meet the routing width requirements and facilitate the pre-hashing operation in the top area of ​​the computing chip, the data is split into 32-bit fine-grained sub-block fields using a shift register for use in SHA-256 pipeline calculations. Of course, the sub-block field is not limited to 32 bits and can also be any other bit.

[0181] Specifically, multiple iterative expansion and compression operations can be performed on the first block field to obtain a 256-bit intermediate state value Mid and generate a completion signal. The 256-bit intermediate state value Mid will be immediately output to the next-level operation core for subsequent hash operations. The 256-bit intermediate state value can be placed on the intermediate state value bus and output to the next-level operation core through the intermediate state value bus.

[0182] This completion signal is output to the counter, which, in response to the completion signal, increments the current count by 1. Subsequently, based on the updated current count value of the counter, the first block field corresponding to the next modified version field is latched and hashed using the pre-hash operation unit. This loop iteratively calculates multiple intermediate state values ​​until the counter overflows, indicating that the calculation of the first block fields corresponding to all four modified version fields has been completed.

[0183] As shown in Figure 4, the 256-bit intermediate state values ​​corresponding to the four version fields can be sequentially generated during the iteration process, such as Mid(0)[255:0], Mid(1)[255:0], Mid(2)[255:0], and Mid(3)[255:0]. The counter is cleared after the calculation of the multiple intermediate state values ​​in the previous round is completed. Alternatively, the counter can be cleared when a new calculation task arrives, so that the new task can be recalculated.

[0184] The pre-hashing operation occurs in the high voltage region, and the subsequent hashing operation occurs in the low voltage region. The data width of the generated intermediate state value can be 256 bits. In order to reduce the wiring width requirement from the high voltage region to the low voltage region, a bit width conversion operation can be used. Each intermediate state value of the output 256 bits can be divided into 64-bit sub-intermediate state values, which are defined as {mid <n>_3,mid <n>_2,mid <n>_1,mid <n>_0} (n = 0, 1, 2, 3), where n is the identifier of the intermediate state value. Each intermediate state value is serially transmitted in 4 cycles with a 64-bit data bit width. If there are four intermediate state values, they are arranged in the order of the intermediate state value identifiers to form a serial data stream similar to the sequence shown in Figure 4 and passed to the next-level computing core for use. Of course, the intermediate state value is not limited to 64 bits and can also be any other bit width.

[0185] The generation of intermediate state values ​​can be done in the top area of ​​the computing chip. The top area can also be understood as the main control area of ​​the computing chip. The top area works in the high voltage area and can issue computing instructions to the computing area. The computing chip also includes multiple computing areas, each of which can be understood as the computing core of the computing chip. The top area works in the high voltage area and can issue computing instructions to the computing area and receive data from the computing area; the computing area works in the low voltage area and the high frequency operation of the computing area is used to calculate the 2 32 The use of a level converter to convert the intermediate state value from the high voltage area to the low voltage area is conducive to high-speed calculation in the operation area and improves calculation efficiency.

[0186] The next-level operation core receives the transmitted serial data stream, for example, the serial data stream is a 64-bit serial data stream shown in Figure 4, and uses multiple second latches to restore the serial data stream with the second bit width to multiple intermediate state values ​​of the first bit width, and inputs them into multiple first compressors respectively. For example, Mid(0)_0, ..., Mid(0)_3 in Figure 4 are sequentially input into the second latch _0, restored to the 256-bit intermediate state value Mid(0), and input it into the corresponding first compressor _0, Mid(1)_0, ..., Mid(1)_3 in Figure 4 are sequentially input into the second latch _1, restored to the 256-bit intermediate state value Mid(1), and input it into the corresponding first compressor _1, and so on.

[0187] The next-level computing core also receives a second block field, wherein the second block field includes the second area of ​​the hash Merkle root, a timestamp, a target value, and a random number, totaling 128 bits. The next-level computing core also receives pre-calculated data from the computing module, wherein the pre-calculated data can be 1408 bits, consisting of 4 groups of 352-bit data. The pre-calculated data is not limited to this and can also be any other bit. The pre-calculated data is obtained by calculating the first block field and / or the intermediate state value by the pre-calculation module in the top-level area of ​​the computing chip. The 4 groups of 352-bit data can be used by the first expander and / or the 4 first compressors and / or the 4 second expanders and / or the 4 second compressors. While generating the intermediate state value, using the pre-calculation module to calculate the pre-calculated data first can reduce the amount of calculation of the computing core, improve computing efficiency, reduce the computing layout area of ​​the computing core, and reduce power consumption. When the second block field and pre-calculated data are transmitted from the top area of ​​the computing chip to the computing core, they can also be transmitted through the bit width conversion module and the level converter. The computing core is provided with a latch for recovering the serial data stream of the second block field and the pre-calculated data.

[0188] A first expander is used to perform a first expansion operation on the second block field, and the result of the first expansion operation is shared with multiple first compressors, so that only one expansion operation needs to be performed; the multiple first compressors each perform a first compression operation based on the input intermediate state value and the expansion operation result, and input the first compression operation results into multiple second expanders respectively; the multiple second expanders each perform a second expansion operation based on the first compression operation result, and output the second expansion operation results to each electrically connected second compressor; the second compressors perform a second compression operation based on the second expansion result to obtain proof of work.

[0189] In the description of this specification, reference to the terms "some possible implementations," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification, as well as features of different embodiments or examples, unless they are mutually inconsistent.

[0190] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0191] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0192] About the method flow chart of the embodiment of the present application, some operations are described as the different steps performed in a certain order.Such flow chart belongs to illustrative and non-restrictive.Some steps described in this article can be grouped together and performed in a single operation, some steps can be divided into multiple sub-steps and can be performed in a different order than shown in this article.The various steps shown in the flow chart can be realized in any way by any circuit structure and / or tangible mechanism (for example, by the software, hardware (for example, the logical function realized by processor or chip) etc. running on computer equipment and / or its any combination).

[0193] It should be noted that the device in the embodiment of the present application can implement the various processes of the embodiment of the aforementioned method and achieve the same effects and functions, which will not be repeated here.

[0194] The various embodiments in this application are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the descriptions of the apparatus, device, and computer-readable storage medium embodiments are simplified because they are generally similar to the method embodiments. For relevant parts, please refer to the descriptions of the method embodiments.

[0195] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0196] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0197] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0198] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0199] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0200] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0201] Computer-readable media include permanent and non-permanent, removable and non-removable media that can be used to store information using any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. In addition, although the operations of the present method are described in a particular order in the accompanying drawings, this does not require or imply that the operations must be performed in this particular order or that all illustrated operations must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into a single step, and / or a single step may be broken down into multiple steps.

[0202] Although the spirit and principles of the present invention have been described with reference to several specific embodiments, it should be understood that the present invention is not limited to the specific embodiments disclosed, and the division into various aspects does not mean that the features of these aspects cannot be combined to benefit. Such division is only for the convenience of expression. The present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A computing task processing method, characterized in that: include: A computing task is received, the computing task including an original version field, and the following processing steps are performed: Modifying the original version field to obtain multiple modified version fields; Based on the multiple modified version fields, a hash operation is performed on the computing task to generate multiple intermediate state values, and the multiple intermediate state values ​​are used for workload proof calculation.

2. The method according to claim 1, characterized in that The processing steps are iteratively executed, and the modified version field in the (n+1)th round of processing steps is inconsistent with the modified version field in the 1st to nth rounds of processing steps.

3. The method according to claim 1 or 2, characterized in that: Also includes: Another computing task is received, and the processing step is performed based on the original version field of the another computing task.

4. The method according to any one of claims 1 to 3, characterized in that: The original version field includes a fixed field, a soft fork voting field and a remaining field, and the remaining field is used to modify the original version field to obtain a plurality of modified version fields.

5. The method according to claim 4, characterized in that The bits of the remaining fields are modified randomly or in a fixed order to modify the original version field to obtain a plurality of modified version fields.

6. The method according to claim 4 or 5, characterized in that: The original version field is 32 bits, and the remaining field is 16 bits.

7. The method according to any one of claims 1 to 6, characterized in that: The computation task also includes a message field, wherein the message field includes a previous block hash and a first area of ​​a hash Merkle root.

8. The method according to any one of claims 1 to 7, characterized in that: Also includes: Based on the intermediate state value, obtaining a plurality of sub-intermediate state values; The serial data stream composed of the plurality of sub-intermediate state values ​​is output for workload proof calculation.

9. The method according to claim 8, characterized in that Based on the intermediate state value, it is split to obtain a plurality of sub-intermediate state values.

10. The method according to claim 8 or 9, characterized in that: The intermediate state value is 256 bits, and the sub-intermediate state value is 32 bits.

11. The method according to any one of claims 1 to 10, characterized in that: The computing task further includes a message field, and performing a hash operation on the computing task based on the plurality of modified version fields to generate a plurality of intermediate state values ​​includes: The plurality of modified version fields are respectively combined with the message field to obtain a plurality of first block fields, and based on the plurality of the first block fields, a hash operation is performed to generate a plurality of the intermediate state values.

12. The method according to claim 11, characterized in that Each first block field is split into a plurality of sub-first block fields, and a hash operation is performed based on a serial data stream formed by the plurality of sub-first block fields of each first block field to generate the intermediate state value.

13. The method according to claim 11 or 12, characterized in that: Based on the sequence values ​​of the plurality of modified version fields, each modified version field is combined with the message field to obtain a corresponding first block field.

14. The method according to claim 13, characterized in that A pulse level corresponding to the sequence value is outputted, and in response to the pulse level, a modified version field corresponding to the sequence value and the message field are latched as the first block field.

15. The method according to claim 13 or 14, characterized in that After performing a hash operation on the mth first block field to generate the intermediate state value, the m+1th modified version field and the message field are combined to obtain the m+1th first block field.

16. The method according to claim 1, characterized in that Also includes: A hash operation is performed based on the plurality of intermediate state values ​​and the second block field of the computing task to obtain proof of work; the second block field includes the second area of ​​the hash Merkle root, a timestamp, a target value, and a random number.

17. The method according to claim 16, characterized in that The performing a hash operation based on the plurality of intermediate state values ​​and the second block field of the computing task comprises: Performing a first extension operation on the second block field to obtain first extended data; Perform multiple first compression operations based on the multiple intermediate state values ​​and the first expansion operation result to obtain multiple first compressed data; Performing a plurality of second expansion operations based on a plurality of the first compressed data to obtain a plurality of the second expanded data; A plurality of second compression operations are performed based on the plurality of second extended data to obtain the proof of work.

18. The method according to claim 1, characterized in that The intermediate state value is generated in the high voltage area. After generating multiple intermediate state values, the multiple intermediate state values ​​are converted from the high voltage area to the low voltage area for proof of work calculation.

19. The method according to any one of claims 1 to 18, characterized in that: The intermediate state values ​​are generated in a top layer region of the chip.

20. The method according to any one of claims 1 to 19, characterized in that: The hash operation is a SHA-256 operation.

21. A computing task processing device, characterized in that: include: A receiving module, configured to receive a computing task, wherein the computing task includes an original version field; A modification module, which modifies the original version field to obtain multiple modified version fields; A computing module is used to perform a hash operation on the computing task based on the multiple modified version fields to generate multiple intermediate state values, and the multiple intermediate state values ​​are used for proof of work calculation.

22. The device according to claim 21, characterized in that The modification module is further configured to iteratively modify a plurality of the modified version fields.

23. The device according to claim 21 or 22, characterized in that The receiving module is further used to receive a new computing task, and the modifying module is further used to modify the original version field of the new computing task to obtain a plurality of modified version fields.

24. The device according to any one of claims 21 to 23, characterized in that The original version field includes a fixed field, a soft fork voting field and a remaining field, and the remaining field is used to modify the original version field to obtain a plurality of modified version fields.

25. The device according to any one of claims 21 to 24, characterized in that The computation task also includes a message field, wherein the message field includes a previous block hash and a first area of ​​a hash Merkle root.

26. The device according to any one of claims 21 to 25, characterized in that It also includes a bit width conversion module, which is used to split the intermediate state value of the first bit width generated by the calculation module into multiple sub-intermediate state values ​​of the second bit width; the serial data stream composed of the multiple sub-intermediate state values ​​is used for proof of work calculation.

27. The device according to any one of claims 21 to 26, characterized in that The computing task also includes a message field, and the computing module includes a first latch, which is used to store a first block field composed of a single modified version field and the message field. The computing module performs a hash operation based on multiple first block fields to generate multiple intermediate state values.

28. The device according to claim 27, characterized in that The calculation module includes a shift register, which is used to split the first block field into multiple sub-first block fields, and the serial data stream composed of the multiple sub-first block fields is used to perform a hash operation to generate the intermediate state value.

29. The device according to claim 27 or 28, characterized in that The calculation module includes a counter, which is used to generate a count value. The calculation module combines the modified version field corresponding to the count value and the message field based on the count value and the sequence values ​​of the multiple modified version fields to obtain the corresponding first block field.

30. The device according to claim 29, characterized in that The calculation module includes a level generation module, which generates a corresponding pulse level according to the count value. The calculation module latches the modified version field corresponding to the count value and the message field as the first block field in response to the pulse level.

31. The device according to claim 29 or 30, characterized in that The calculation module generates a completion signal when generating a single intermediate state value, the counter updates the count value in response to the completion signal, and restores the count value to an initial value after all the hash operations are performed on the plurality of first block fields.

32. The device according to any one of claims 21 to 31, characterized in that It also includes a proof-of-work calculation module, which is used to perform a hash operation based on a plurality of the intermediate state values ​​and a second block field of the computing task to obtain a proof of work; the second block field includes a second area of ​​the hash Merkle root, a timestamp, a target value, and a random number.

33. The device according to claim 32, characterized in that It also includes a plurality of second latches for receiving a plurality of the intermediate state values; a first expander for performing a first expansion operation on the second block field to obtain first expansion data; A plurality of first compressors, configured to perform a plurality of first compression operations based on the plurality of intermediate state values ​​and the first expansion operation results to obtain a plurality of first compressed data; A plurality of second expanders, configured to perform a plurality of second expansion operations based on a plurality of the first compressed data to obtain a plurality of the second expanded data; A plurality of second compressors are used to perform a plurality of second compression operations based on a plurality of the second extended data to obtain the proof of work.

34. The device according to any one of claims 21 to 33, characterized in that The computing module is arranged in the top layer area of ​​the chip.

35. The device according to any one of claims 21 to 34, characterized in that A level converter is also included, which is used to convert the plurality of intermediate state values ​​from a high voltage region to a low voltage region.

36. The device according to any one of claims 21 to 35, characterized in that The hash operation is a SHA-256 operation.

Images