Apparatus and method for parent-child relationship-based memory allocation for memory reuse

Abstract

The present disclosure relates to an apparatus and a method for parent-child relationship-based memory allocation for memory reuse. According to an aspect of the present disclosure, a memory allocation method is provided, the method comprising: an allocation request reception procedure of receiving a plurality of memory allocation requests defined as an allocation request occurrence time, a required memory size, and a required memory use period; and a memory allocation procedure of, when the plurality of memory allocation requests include information on a parent-child relationship, allocating respective memory areas corresponding to the plurality of memory allocation requests by using an ILP solver on the basis of the information on the parent-child relationship, wherein the information on the parent-child relationship includes information on a location to be reused by a child memory allocation request from among memory addresses corresponding to one or more parent memory allocation requests included in the plurality of memory allocation requests.

Description

Memory allocation device and method for memory reuse based on parent-child relationship

[0001] The present disclosure relates to a memory allocation device and method for memory reuse based on a parent-child relationship.

[0002] The content described below merely provides background information related to the present embodiment and does not constitute prior art.

[0003] In deep learning models that perform multi-layered operation layers, memory allocation methods are generally performed statically, and the system in which the deep learning model operates typically uses physically contiguous on-chip memory addresses.

[0004] In an environment where a memory management unit (MMU) is not used, if memory fragmentation occurs during the operation of a deep learning model, the problem arises that memory space cannot be utilized efficiently.

[0005] Traditional approaches to address this issue involve using heuristics to allocate memory. These methods only consider the current context at the time of allocation, which can lead to inefficient memory allocation in certain situations.

[0006] Furthermore, existing heuristic memory allocation methods present a challenge in efficiently utilizing reusable memory blocks in subsequent layers of a deep learning model after one layer has been operated. This is because memory is allocated without considering the reuse relationship between memory blocks.

[0007] The main purpose of the present disclosure is to provide a memory allocation device and method for memory reuse based on a parent-child relationship.

[0008] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0009] According to one aspect of the present disclosure, a memory allocation method is provided, comprising: an allocation request receiving process for receiving a plurality of memory allocation requests defined by an allocation request occurrence time, a required memory size, and a required memory usage period; and a memory allocation process for allocating each memory area corresponding to the plurality of memory allocation requests using an integer linear programming solver (ILP Solver) based on information about the parent-child relationship when the plurality of memory allocation requests include information about a parent-child relationship, wherein the information about the parent-child relationship includes information about a location to be reused by a child memory allocation request among memory addresses corresponding to at least one parent memory allocation request included in the plurality of memory allocation requests.

[0010] According to another aspect of the present disclosure, a computer program stored in a computer-readable recording medium is provided to execute each process included in the memory allocation method according to any one of claims 1 to 9.

[0011] According to another aspect of the present disclosure, a memory allocation device is provided, comprising: an allocation request receiving unit that receives a plurality of memory allocation requests defined by an allocation request occurrence time, a required memory size, and a required memory usage period; and a memory allocation unit that allocates each memory area corresponding to the plurality of memory allocation requests using an ILP solver based on information about the parent-child relationship when the plurality of memory allocation requests include information about a parent-child relationship, wherein the information about the parent-child relationship includes information about a location to be reused by a child memory allocation request among memory addresses corresponding to at least one parent memory allocation request included in the plurality of memory allocation requests.

[0012] According to an embodiment of the present disclosure, by allocating memory by considering the relationship between parent and child memory blocks in a deep learning model, there is an effect of optimizing memory reuse and increasing the efficiency of memory allocation.

[0013] Additionally, it has the effect of reducing the execution time of deep learning models and minimizing memory usage.

[0014] Additionally, it reduces the overhead of memory management by reducing the complexity of memory management, thereby contributing to improving the overall performance of deep learning models.

[0015] In addition, the present invention significantly contributes to minimizing memory fragmentation, thereby improving the overall performance and efficiency of a machine learning accelerator, and is highly versatile as it can be applied to various deep learning models and platforms.

[0016] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0017] FIG. 1 is a block diagram illustrating the configuration of a memory allocation device (100) according to one embodiment of the present disclosure.

[0018] Figure 2 is a diagram illustrating the result of allocating multiple memory allocation requests using a heuristic method.

[0019] FIG. 3a is a diagram illustrating a case where there is one parent memory allocation request and three child memory allocation requests, and FIG. 3b is a diagram illustrating a case where three child memory allocation requests are integrated to create an integrated child memory allocation request.

[0020] FIG. 4a is a diagram illustrating a case where there is one parent memory allocation request and three child memory allocation requests where the required memory usage periods are different from each other, and FIG. 4b is a diagram illustrating a case where the three child memory allocation requests of FIG. 4a are integrated to create an integrated child memory allocation request.

[0021] Figure 5 is a diagram illustrating the result of reallocating each reallocated memory area corresponding to multiple memory allocation requests using an ILP solver.

[0022] FIG. 6 is a flowchart illustrating a memory allocation method according to one embodiment of the present disclosure.

[0023] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When assigning identification numbers to components in each drawing, it should be noted that, where possible, identical components are assigned the same numbers, even if they appear in different drawings. Furthermore, when describing the present invention, detailed descriptions of known related components or functions will be omitted if they are deemed to obscure the gist of the present invention.

[0024] In describing components of embodiments according to the present disclosure, symbols such as first, second, i), ii), a), b) may be used. These symbols are only for distinguishing the components from other components, and the nature, order, or sequence of the components are not limited by the symbols. When a part in the specification is said to "include" or "have" a component, this does not mean that other components are excluded, but rather that other components may be included, unless explicitly stated otherwise.

[0025] The detailed description set forth below, together with the accompanying drawings, is intended to explain exemplary embodiments of the present disclosure and is not intended to represent the only embodiments in which the present disclosure may be practiced.

[0026] FIG. 1 is a block diagram illustrating the configuration of a memory allocation device (100) according to one embodiment of the present disclosure.

[0027] As illustrated in FIG. 1, a memory allocation device (100) according to the present embodiment may be implemented by including an allocation request receiving unit (110) and a memory allocating unit (120). The memory allocation device (100) according to the present embodiment may be implemented by omitting some of the components illustrated in FIG. 1 or by adding other components not illustrated in FIG. 1.

[0028] The allocation request receiving unit (110) receives multiple memory allocation requests defining the required memory size and required memory usage period.

[0029] The memory allocation unit (120) allocates each memory area corresponding to multiple memory allocation requests using an ILP solver. Here, the memory area refers to an area defined by the time of allocation request occurrence, the start address of the allocated memory, the last address of the allocated memory, and the usage period of the allocated memory.

[0030] The memory allocation unit (120) allocates memory areas corresponding to multiple memory allocation requests using a preset heuristic algorithm, and then reallocates each memory area corresponding to the multiple memory allocation requests using an ILP solver.

[0031] Figure 2 is a diagram illustrating the result of allocating multiple memory allocation requests using a heuristic method.

[0032] As illustrated in FIG. 2, the plurality of memory allocation requests include memory allocation request a, memory allocation request b, memory allocation request c, memory allocation request d, memory allocation request e, memory allocation request f, memory allocation request g, memory allocation request h, memory allocation request i, memory allocation request j, memory allocation request k, memory allocation request l, memory allocation request m, and memory allocation request n.

[0033] The horizontal and vertical axes of Figure 2 represent time and memory addresses, respectively. The time on the horizontal axis represents the preset unit of time for which the corresponding memory is used in response to a memory allocation request. In the following description, the numbers representing time will be explained without specifying the unit. Furthermore, the memory address on the vertical axis is explained assuming the main memory address range is 0 to 100.

[0034] In this embodiment, each memory allocation request can be defined by the allocation request occurrence time, required memory size, and required memory usage period, respectively, and can be expressed as (allocation request identifier)[allocation request occurrence time, required memory size, required memory usage period]. For example, memory allocation request a is a memory allocation request defined as the allocation request occurrence time is 1, the required memory size is 5, and the required memory usage period is 6, and is conveniently expressed as a[1, 5, 6] for explanation.

[0035] The allocation request receiving unit (110) sequentially receives a[1,5,6], b[1,20,4], c[2,10,4], d[2,5,2], e[2,20,1], f[3,15,1], g[4,50,4], h[4,3,3], i[5,5,3], j[5,15,3], k[5,10,5], l[6,3,3], m[6,5,2], n[9,10,1] as multiple memory allocation requests in the order of allocation request occurrence.

[0036] The allocation request receiving unit (110) can receive information about the parent-child relationship between memory allocation requests in addition to multiple memory allocation requests.

[0037] This is information about the parent-child relationship, which represents the relationship in which at least part of the memory block corresponding to the parent memory allocation request is reused by the memory block related to the child memory allocation request.

[0038] For example, when the allocation request receiving unit (110) receives child memory allocation requests such as h[4,3,3], k[5,10,5], and l[6,3,3], it can receive [information about the parent memory allocation request, information about the location to be reused among the memory addresses corresponding to the parent memory allocation request] as parent-child relationship information related to the child memory allocation request. For example, the allocation request receiving unit (110) receives, together with the child memory allocation request k[5,10,5], information indicating that the parent memory allocation request is b as [information about the parent memory allocation request, information about the location to be used among the memory addresses corresponding to the parent memory allocation request], and information about the required memory start address 10 that k[5,10,5] wants to reuse among the required memory addresses of the memory allocation request of b, and the required memory end address 20 that k[5,10,5] wants to use.

[0039] The memory allocation unit (120) can generate memory allocation results, such as those shown in FIG. 2, for multiple memory allocation requests using, for example, a first fit algorithm as a heuristic algorithm. Here, the first fit algorithm is described as being used as a heuristic algorithm, but the present invention is not limited thereto.

[0040] The heuristic algorithm can be performed sequentially for multiple memory allocation requests, each in the order of their occurrence time.

[0041] When applying the heuristic algorithm, the memory allocation unit (120) allocates a memory area by referring to information about the parent-child relationship. For example, in the case of child memory allocation requests h[4,3,3], k[5,10,5], and l[6,3,3] that have more information about the parent-child relationship, they are excluded from the application target of the heuristic algorithm, and are allocated to a memory address area corresponding to a reuse location among the memory addresses of the parent memory allocation requests based on the information about the parent-child relationship corresponding to each of the child memory allocation requests.

[0042] Multiple memory allocation requests may include one or more parent memory allocation requests. Each parent memory allocation request may have one or more corresponding child memory allocation requests.

[0043] When there are multiple child memory allocation requests for each parent memory allocation request, if the gap between the memory address areas corresponding to the multiple child memory allocation requests is less than or equal to a preset size, the memory allocation unit (120) integrates the multiple child memory allocation requests into one and creates an integrated memory allocation request as one component of the multiple memory allocation requests, and deletes the multiple corresponding child memory allocation requests so that they are not included in the multiple memory allocation requests. At this time, the integrated memory allocation request is determined as a child memory allocation request for the corresponding parent memory allocation request.

[0044] FIG. 3a is a diagram illustrating a case where there is one parent memory allocation request and three child memory allocation requests, and FIG. 3b is a diagram illustrating a case where three child memory allocation requests are integrated to create an integrated child memory allocation request.

[0045] When two or more child memory allocation requests exist for a single parent memory allocation request, the memory allocation operation performed by the ILP solver can become complex. Therefore, to reduce the computational complexity of the ILP solver in such cases, multiple child memory allocation requests related to each parent memory allocation request can be treated and processed as a single, unified child memory allocation request.

[0046] As shown in Figure 3a, one parent memory allocation request P i When there are three child memory allocation requests C1, C2, and C3, respectively, the memory allocation unit (120) sets the gap offset between the area corresponding to the adjacent child memory allocation request C1 and the memory address area corresponding to C2. i,2 If the size is less than the preset size, a unified memory allocation request is created with a required memory size that combines the areas of adjacent child memory allocation requests C1 and C2.

[0047] Also, the gap offset between the area corresponding to C1 and the memory address area corresponding to C2 i,2 Wow, the gap offset between the area corresponding to C2 and the memory address area corresponding to C3 i,3 If each of the child memory allocation requests C1, C2, and C3 is smaller than or equal to the preset size, the memory allocation unit (120) generates a unified memory allocation request Cm having a required memory size that combines the areas of adjacent child memory allocation requests C1, C2, and C3 as one component of the plurality of memory allocation requests. In this case, the three child memory allocation requests C1, C2, and C3 are deleted from the plurality of memory allocation requests.

[0048] At this time, the allocation request occurrence time and required memory usage period of the integrated memory allocation request can be implemented to be the same as any one of the child memory allocation requests C1, C2, and C3, respectively.

[0049] As illustrated in FIG. 3b, the memory allocation unit (120) generates a unified memory allocation request Cm that combines the areas of all child memory allocation requests of one parent memory allocation request Pi.

[0050] The memory allocation unit (120) defines the required memory size corresponding to the unified memory allocation request as the memory address between the smallest address and the largest address among the memory addresses corresponding to multiple child memory allocation requests. That is, as shown in Fig. 3b, the unified memory allocation request C m The required memory size corresponding to start(P) is the smallest memory address among the memory addresses corresponding to multiple child memory allocation requests. i )+offset i,1 The largest address among the memory addresses corresponding to the location corresponding to the multiple child memory allocation requests is end(P i )-offset i,4 It can be defined as the size between the corresponding positions.

[0051] FIG. 4a is a diagram illustrating a case where there is one parent memory allocation request and three child memory allocation requests where the required memory usage periods are different from each other, and FIG. 4b is a diagram illustrating a case where the three child memory allocation requests of FIG. 4a are integrated to create an integrated child memory allocation request.

[0052] As illustrated in FIG. 4b, the memory allocation unit (120) defines the required memory usage period corresponding to the integrated memory allocation request as 2, which is equal to the largest required memory usage period among the required memory usage periods corresponding to multiple child memory allocation requests.

[0053] Although not illustrated in FIGS. 3A and 4A, there may be cases where the allocation request occurrence times corresponding to multiple child memory allocation requests are different from each other. In this case, the memory allocation unit (120) defines the allocation request occurrence time corresponding to the integrated memory allocation request as the smallest allocation request occurrence time among the allocation request occurrence times corresponding to multiple child memory allocation requests.

[0054] Meanwhile, when allocating memory for multiple memory allocation requests by the first fit algorithm, there may be cases where memory allocation request g[4,50,4] cannot be allocated within the main memory address area 100 as shown in Fig. 2 and must be allocated to an area exceeding memory address 100. Here, allocation to an area exceeding memory address 100 means allocation to virtual memory, and when allocated to virtual memory, it means that input / output to the main memory for the disk swap area corresponding to the virtual memory is required to access the memory data.

[0055] Accordingly, the memory allocation unit (120) operates the ILP solver so that multiple memory allocation requests are allocated to an area within the entire main memory address 100 as much as possible.

[0056] The memory allocation unit (120) determines the start address of each memory area when allocating memory areas corresponding to multiple memory allocation requests, and sets the minimization of the total sum of the start addresses of each allocated memory area for multiple memory allocation requests as the objective of the ILP solver.

[0057] Additionally, the memory allocation unit (120) can set at least one constraint. The at least one constraint can be composed of, for example, a first constraint, a second constraint, etc.

[0058] The memory allocation unit (120) sets a first constraint to maintain a preset relative position between the memory area corresponding to the parent memory allocation request and the memory area corresponding to the child memory allocation request based on information about the parent-child relationship.

[0059] The first constraint can be expressed using a formula as follows.

[0060] ∀i, start(C i,1 )= start(P i )+offset i,1

[0061] ∀i, start(C i,j )= end(C i,(j-1) )+ offset i,j (provided j > 1)

[0062] Here, start(P i ) is the required memory start address of the i-th parent memory allocation request, and start(C i,1 ) is the required memory starting address of the 1st child memory allocation request (i.e., the i1th child memory allocation request) for the i-th parent memory allocation request, and offset i,1 means the set interval from the required memory start address of the ith parent memory allocation request to the required memory start address of the i1th child memory allocation request, and start(C i,j ) is the required memory starting address of the jth child memory allocation request for the ith parent memory allocation request (i.e., the ijth child memory allocation request), and end(C i,(j-1) ) is the last address of the required memory of the (j-1)th child memory allocation request for the i-th parent memory allocation request (i.e., the i(j-1)th child memory allocation request), and offset i,j means the set interval from the last address of the required memory of the i(j-1)th child memory allocation request to the start address of the required memory of the ijth child memory allocation request.

[0063] [∀i, start(C i,1 )= start(P i )+offset i,1 ] means that for every parent memory allocation request, the required memory starting address of the i1th child memory allocation request is the value obtained by adding the required memory starting address of the i-th parent memory allocation request and the set interval from the required memory starting address of the i-th parent memory allocation request to the required memory starting address of the i1th child memory allocation request.

[0064] [∀i, start(C i,j )= end(C i,(j-1) )+ offset i,j (where j > 1)] means that for all parent memory allocation requests, the required memory start address of the jth child memory allocation request is the sum of the required memory last address of the ith (j-1)th child memory allocation request and the set interval from the required memory last address of the ith (j-1)th child memory allocation request to the required memory start address of the jth child memory allocation request.

[0065] Meanwhile, memory reuse in deep learning models is often the case where the end address of the parent memory block matches the end address of the child memory block, so depending on the embodiment, [∀i, end(C i,ni )= end(P i )] can be implemented to add an additional constraint. That is, this constraint is the last address of required memory of the last nth child memory allocation request for the i-th parent memory allocation request (end(C i,ni )) is the last address of the required memory of the i-th parent memory allocation request (end(P i )) means the same as .

[0066] In addition, the memory allocation unit (120) sets as a second constraint that no overlap occurs between each allocated memory area corresponding to multiple memory allocation requests.

[0067] The memory allocation unit (120) sets the objective and constraints as a polynomial, and optimizes the allocation of each memory area corresponding to multiple memory allocation requests by using the polynomial as an ILP solver.

[0068] The details of how to allocate each reallocated memory area corresponding to multiple memory allocation requests using an ILP solver are beyond the scope of the present invention, and thus further description thereof is omitted.

[0069] Figure 5 is a diagram illustrating the result of reallocating each reallocated memory area corresponding to multiple memory allocation requests using an ILP solver.

[0070] As shown in Fig. 5, it can be seen that the allocation of memory areas for multiple memory allocation requests was performed within memory address 100 for all memory allocation requests.

[0071] FIG. 6 is a flowchart illustrating a memory allocation method according to one embodiment of the present disclosure.

[0072] A memory allocation method according to one embodiment of the present disclosure is performed by a memory allocation device (100).

[0073] The allocation request receiving unit (110) performs an allocation request receiving process of receiving multiple memory allocation requests defined by the allocation request occurrence time, required memory size, and required memory usage period (S610).

[0074] When there are multiple child memory allocation requests for each parent memory allocation request, if the gap between memory address areas corresponding to the multiple child memory allocation requests is smaller than a preset size, the memory allocation unit (120) generates an integrated memory allocation request that integrates the required memory sizes of the multiple child memory allocation requests into one as a component of the multiple memory allocation requests, and deletes the multiple child memory allocation requests within the multiple memory allocation requests (S620).

[0075] The memory allocation unit (120) defines the required memory size corresponding to the integrated memory allocation request as the smallest address and the largest address among the memory addresses corresponding to multiple child memory allocation requests (S630).

[0076] The memory allocation unit (120) defines the largest required memory usage period among the required memory usage periods corresponding to multiple child memory allocation requests as the required memory usage period corresponding to the integrated memory allocation request (S640).

[0077] The memory allocation unit (120) allocates memory areas corresponding to multiple memory allocation requests using a preset heuristic algorithm (S650). Depending on the embodiment, the memory allocation unit (120) may omit step S650.

[0078] The memory allocation unit (120) performs a memory allocation process of reallocating each memory area corresponding to multiple memory allocation requests using an ILP solver based on information about the parent-child relationship (S660).

[0079] Each component of the device or method according to the present invention may be implemented in hardware, software, or a combination of hardware and software. Furthermore, the functions of each component may be implemented in software, with a microprocessor executing the software functions corresponding to each component.

[0080] Various implementations of the systems and techniques described herein may be implemented as digital electronic circuits, integrated circuits, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations of one or more computer programs executable on a programmable system. The programmable system includes at least one programmable processor (which may be a special purpose processor or a general purpose processor) coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device. Computer programs (also known as programs, software, software applications, or code) include instructions for the programmable processor and are stored on a "computer-readable recording medium."

[0081] A computer-readable recording medium includes any type of recording device that stores data that can be read by a computer system. Such a computer-readable recording medium may be a non-volatile or non-transitory medium such as a ROM, CD-ROM, magnetic tape, floppy disk, memory card, hard disk, magneto-optical disk, storage device, and may further include a transitory medium such as a data transmission medium. Furthermore, the computer-readable recording medium may be distributed across network-connected computer systems, so that computer-readable code can be stored and executed in a distributed manner.

[0082] Although the flowchart / timing diagram of this specification describes each process as being executed sequentially, this is merely an illustrative description of the technical idea of ​​one embodiment of the present disclosure. In other words, a person of ordinary skill in the art to which one embodiment of the present disclosure belongs may modify and apply various modifications and variations by changing the order described in the flowchart / timing diagram without departing from the essential characteristics of one embodiment of the present disclosure, or by executing one or more of the processes in parallel. Therefore, the flowchart / timing diagram is not limited to a chronological order.

[0083] The above description is merely an example of the technical idea of ​​the present embodiment, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of ​​the present embodiment, but rather to explain it, and the scope of the technical idea of ​​the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted by the claims below, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of rights of the present embodiment.

[0084] [Explanation of symbols]

[0085] 100: Memory allocation device 110: Allocation request receiver

[0086] 120: Memory allocation section

[0087]

[0088] (Statement regarding sponsored research or development)

[0089] The present invention is the result of a research project (Project Unique Number: 1711153007, Subproject Number: 2021-0-00310-002, Project Management (Specialized) Organization Name: Information and Communications Technology Planning and Evaluation Institute, Research Project Name: SW Computing Industry Core Technology Development, Research Project Name: Development of Server SW Framework for Improving Artificial Intelligence Learning / Inference Efficiency, Contribution Rate: 1 / 1, Project Performing Organization Name: Sapion Korea Co., Ltd., Research Period: 2021-04-01~2024-12-31).

[0090]

[0091] (CROSS-REFERENCE TO RELATED APPLICATION)

[0092] This patent application claims priority to Korean Patent Application No. 10-2023-0117823, filed September 5, 2023, which is incorporated herein by reference in its entirety.

Claims

1. An allocation request receiving process that receives multiple memory allocation requests defined by the allocation request occurrence time, required memory size, and required memory usage period; and If the plurality of memory allocation requests include information about a parent-child relationship, a memory allocation process for allocating each memory area corresponding to the plurality of memory allocation requests using an ILP solver based on the information about the parent-child relationship. Including, A memory allocation method characterized in that the information on the parent-child relationship includes information on a location to be reused by a child memory allocation request among memory addresses corresponding to at least one parent memory allocation request included in the plurality of memory allocation requests.

2. In paragraph 1, The above memory allocation process is, A memory allocation method characterized in that, when there are multiple child memory allocation requests for each parent memory allocation request, if the gap between memory address areas corresponding to the multiple child memory allocation requests is smaller than a preset size, a unified memory allocation request that unifies the required memory sizes of the multiple child memory allocation requests into one is generated as a component of the multiple memory allocation requests, and the multiple child memory allocation requests are deleted from the components of the multiple memory allocation requests.

3. In paragraph 2, The above memory allocation process is, A memory allocation method characterized in that the memory address between the smallest address and the largest address among the memory addresses corresponding to the plurality of child memory allocation requests is defined as the required memory size corresponding to the integrated memory allocation request.

4. In paragraph 2, The above memory allocation process is, A memory allocation method characterized in that the largest required memory usage period among the required memory usage periods corresponding to the plurality of child memory allocation requests is defined as the required memory usage period corresponding to the integrated memory allocation request.

5. In paragraph 2, The above memory allocation process is, A memory allocation method characterized in that the smallest allocation request occurrence time among the allocation request occurrence times corresponding to the above multiple child memory allocation requests is defined as the allocation request occurrence time corresponding to the integrated memory allocation request.

6. In paragraph 1, The above memory allocation process is, A memory allocation method characterized in that memory areas corresponding to the plurality of memory allocation requests are allocated using a preset heuristic algorithm, and then each memory area corresponding to the plurality of memory allocation requests is reallocated using the ILP solver.

7. In paragraph 6, A memory allocation method characterized in that the child memory allocation request is excluded from the application target of the heuristic algorithm, and a memory area corresponding to the child memory allocation request is allocated based on information about the location to be reused.

8. In paragraph 6, The above heuristic algorithm is, A memory allocation method characterized in that the above multiple memory allocation requests are sequentially performed in the order of their occurrence times.

9. In paragraph 1, The above memory allocation process is, Determine the starting address of each memory area corresponding to the above multiple memory allocation requests, and set the minimization of the sum of the starting addresses of the memory areas as the objective of the ILP solver, According to the information about the parent-child relationship, a first constraint is set on the relative position between the memory area corresponding to the parent memory allocation request and the memory area corresponding to the child memory allocation request, and a second constraint is set on the fact that no overlap occurs between the respective reallocation memory areas corresponding to the plurality of memory allocation requests. A memory allocation method characterized in that the ILP solver is operated to satisfy the above purpose, the first constraint, and the second constraint, thereby reallocating each memory area corresponding to the plurality of memory allocation requests.

10. A computer program stored on a computer-readable recording medium for executing each process included in the memory allocation method according to any one of claims 1 to 9.

11. An allocation request receiving unit that receives multiple memory allocation requests defined by the allocation request occurrence time, required memory size, and required memory usage period; and When the plurality of memory allocation requests include information about a parent-child relationship, a memory allocation unit that allocates each memory area corresponding to the plurality of memory allocation requests using an ILP solver based on the information about the parent-child relationship. Including, A memory allocation device characterized in that the information on the parent-child relationship includes information on a location to be reused by a child memory allocation request among memory addresses corresponding to at least one parent memory allocation request included in the plurality of memory allocation requests.

12. In paragraph 11, The above memory allocation part is, A memory allocation device characterized in that, when there are multiple child memory allocation requests for each parent memory allocation request, if the gap between memory address areas corresponding to the multiple child memory allocation requests is smaller than a preset size, an integrated memory allocation request that integrates the required memory sizes of the multiple child memory allocation requests into one is generated as a component of the multiple memory allocation requests, and the multiple child memory allocation requests are deleted within the multiple memory allocation requests.

13. In paragraph 11, The above memory allocation part is, A memory allocation device characterized in that it allocates memory areas corresponding to the plurality of memory allocation requests using a preset heuristic algorithm, and then reallocates each memory area corresponding to the plurality of memory allocation requests using the ILP solver.

14. In paragraph 11, The above memory allocation part is, Determine the starting address of each memory area corresponding to the above multiple memory allocation requests, and set the minimization of the sum of the starting addresses of the memory areas as the objective of the ILP solver, According to the information about the parent-child relationship, a first constraint is set on the relative position between the memory area corresponding to the parent memory allocation request and the memory area corresponding to the child memory allocation request, and a second constraint is set on the fact that no overlap occurs between the respective reallocation memory areas corresponding to the plurality of memory allocation requests. A memory allocation device characterized in that it operates the ILP solver to reallocate each memory area corresponding to the plurality of memory allocation requests so as to satisfy the above purpose, the first constraint, and the second constraint.

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