Network interface card circuit and network interface card circuit control method

Abstract

Provided in the embodiments of the present application are a network interface card circuit and a network interface card circuit control method. The network interface card circuit comprises a microcontroller, a switch chip, a clock chip and at least two network interface cards, wherein the microcontroller is connected to the switch chip; the switch chip is further connected to both the clock chip and the at least two network interface cards; and the microcontroller is used for controlling, after receiving a power-on instruction, the clock chip, the switch chip and the at least two network interface cards to be powered on, and controlling the switch chip to be in an off state, and controlling, after the at least two network interface cards are successfully powered on, the switch chip to be in an on state, so as to make the clock chip provide a clock signal to one of the at least two network interface cards by means of the switch chip. By means of the network interface card circuit, the reliability of network interface card can be improved.

Description

Network card circuit and network card circuit control method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 15, 2023, with application number 202311206038.X and application name “Network Card Circuit, and Network Card Circuit Control Method”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of computing devices, and in particular to a network card circuit and a network card circuit control method. Background Art

[0003] With the launch of the Open Compute Project (OCP) Network Interface Card (NIC) specification, OPC NICs are widely used in servers. In servers, OCP NICs can communicate with clock chips through switch chips to obtain clock signals from the clock chips.

[0004] Currently, within a specific period of time after the server is powered on, the clock signal of the clock chip is transmitted to the OCP NIC through the switch chip. This causes the clock chip to leak electricity into the OCP NIC and damage the OCP NIC, making the OCP NIC less reliable.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a network card circuit and a network card circuit control method, wherein the network card circuit can improve the reliability of the network card.

[0007] In a first aspect, an embodiment of the present application provides a network card circuit, including a microcontroller, a switching chip, a clock chip, and at least two network cards, wherein:

[0008] The microcontroller is connected to the switching chip; the switching chip is also connected to the clock chip and the at least two network cards respectively;

[0009] The microcontroller is used to control the clock chip, the switching chip and the at least two network cards to power on after receiving a power-on instruction, and control the switching chip to be in an unpowered state; after the at least two network cards are successfully powered on, control the switching chip to be in an powered-on state, so that the clock chip provides a clock signal to one of the at least two network cards through the switching chip.

[0010] In the above scheme, the microcontroller can control the power-up of the switching chip, the clock chip, and at least two network cards, and can control the switching chip to be in the enabled state after the at least two network cards are successfully powered on. Through the above circuit, the switching chip can be kept in the disabled state during the power-up phase of the clock chip, the switching chip, and at least two network cards. This prevents the clock chip's clock signal from being transmitted to the network cards during the power-up phase of the clock chip, the switching chip, and at least two network cards. This prevents leakage of electricity from the clock chip into the network cards, thereby improving the reliability of the network cards.

[0011] In one possible implementation, the switching chip includes an enabling interface, and the microcontroller is connected to the enabling interface, wherein the microcontroller is specifically configured to:

[0012] After receiving the power-on instruction, sending a power-on signal to the clock chip, the switching chip and the at least two network cards, and outputting a first level to the enable interface to control the switching chip to be in an inactive state;

[0013] After the at least two network cards are powered on successfully, outputting a second electrical level to the enable interface to control the switch chip to be in an on state;

[0014] The first level and the second level are opposite to each other.

[0015] In the above solution, the microcontroller can output a first level to the enable interface during the network card power-on phase, and can output a second level to the enable interface after the network card is successfully powered on, so as to achieve the purpose of controlling the clock chip to be in a disabled state during the network card power-on phase.

[0016] In one possible implementation, the microcontroller is specifically configured to:

[0017] After a preset time, a second level is output to the enable interface; the preset time is a preset time after the microcontroller sends a power-on signal to the clock chip, the switching chip and the at least two network cards.

[0018] In the above solution, the microcontroller can determine whether the network card is powered on successfully by timing, thereby achieving the purpose of determining whether the network card is powered on successfully.

[0019] In a possible implementation, the switching chip further includes at least two first clock interfaces and at least two second clock interfaces, and the clock chip includes at least two third clock interfaces, wherein:

[0020] The at least two first clock interfaces are respectively connected to corresponding network cards;

[0021] The at least two second clock interfaces are respectively connected to corresponding third clock interfaces.

[0022] In the above solution, the switching chip can be connected to the clock chip and the network card respectively through different clock interfaces, so as to achieve the purpose of connecting the clock chip and the network card through the switching chip.

[0023] In a possible implementation, the switching chip further includes a selection interface, and the microcontroller is connected to the selection interface, wherein:

[0024] The microcontroller is further configured to output a selection signal to the selection interface;

[0025] The switching chip is further configured to control one of the first clock interfaces to communicate with a corresponding one of the second clock interfaces according to the selection signal.

[0026] In the above solution, the switching chip can control different first clock interfaces to communicate with corresponding second clock interfaces according to the selection signal, thereby achieving the purpose of controlling the clock chip to connect with different network cards according to the selection signal.

[0027] In a possible implementation, the circuit further includes an out-of-band controller, and the out-of-band controller is connected to the switching chip, wherein:

[0028] The out-of-band controller is used to perform data communication with the at least two network cards through the switching chip.

[0029] In the above solution, the out-of-band controller can be connected to at least two network cards through the switching chip, thereby achieving the purpose of data communication between the out-of-band controller and the network cards.

[0030] In a possible implementation, the switching chip further includes a first data interface and at least two second data interfaces, wherein:

[0031] The out-of-band controller is connected to the first data interface, and the at least two network cards are respectively connected to corresponding second data interfaces of the at least two second data interfaces;

[0032] The switching chip is further used to control the first data interface to be connected to a target data interface among the at least two second data interfaces according to a selection signal output by the microcontroller, so that the out-of-band controller can perform data communication with the network card corresponding to the target data interface.

[0033] In the above solution, the switching chip can also control the out-of-band controller to connect to different network cards according to different selection signals, thereby achieving the purpose of controlling the out-of-band controller to communicate data with the network card according to the selection signal.

[0034] In a second aspect, an embodiment of the present application provides a network card circuit control method, which is applied to a network card circuit, wherein the network card circuit includes a microcontroller, a switching chip, a clock chip, and at least two network cards; the method further includes:

[0035] The microcontroller receives a power-on instruction;

[0036] The microcontroller controls the at least two network cards to be powered on according to the power-on instruction, and controls the switching chip to be in an unpowered state; after the at least two network cards are successfully powered on, the microcontroller controls the switching chip to be in an powered-on state, so that the clock chip provides a clock signal to one of the at least two network cards.

[0037] In the above scheme, the microcontroller can control the power-up of at least two network cards and, after the at least two network cards are successfully powered on, control the clock chip to provide a clock signal to one of the at least two network cards. This circuit can disable the switching chip during the power-up phase of the clock chip, the switching chip, and the at least two network cards. This prevents the clock chip's clock signal from being transmitted to the network card during the power-up phase of the clock chip, the switching chip, and the at least two network cards. This prevents leakage of electricity from the clock chip into the network card, thereby improving the reliability of the network card.

[0038] In one possible implementation, the switching chip includes an enable interface, and the microcontroller is connected to the enable interface; the microcontroller controls the at least two network cards to be powered on according to the power-on instruction, and controls the switching chip to be in an inactive state; and after the at least two network cards are successfully powered on, controls the switching chip to be in an active state so that the clock chip provides a clock signal to one of the at least two network cards, including:

[0039] The microcontroller sends a power-on signal to the at least two network cards according to the power-on instruction, and outputs a first electrical level to the enable interface;

[0040] After determining that the at least two network cards are powered on successfully, outputting the second level to the enabling interface; or, after a preset time period, outputting the second level to the enabling interface.

[0041] In the above solution, the microcontroller can output a first level to the enable interface during the network card power-on phase, and can output a second level to the enable interface after the network card is successfully powered on, so as to achieve the purpose of keeping the switching chip in an inactive state during the network card power-on phase.

[0042] In a third aspect, an embodiment of the present application provides a computing device, which includes the network card circuit described in any one of the first aspects.

[0043] In the above scheme, the switching chip can be kept in an inactive state during the power-on phase of the clock chip, the switching chip, and at least two network cards; the clock signal of the clock chip can be prevented from being transmitted to the network card during the power-on phase of the clock chip, the switching chip, and at least two network cards, thereby preventing the clock chip from leaking electricity into the network card, thereby improving the reliability of the network card.

[0044] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the method as described in any one of the second aspects.

[0045] In the above scheme, the switching chip can be kept in an inactive state during the power-on phase of the clock chip, the switching chip, and at least two network cards; the clock signal of the clock chip can be prevented from being transmitted to the network card during the power-on phase of the clock chip, the switching chip, and at least two network cards, thereby preventing the clock chip from leaking electricity into the network card, thereby improving the reliability of the network card.

[0046] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which implements the method described in any one of the second aspects when executed by a computer.

[0047] In the above scheme, the switching chip can be kept in an inactive state during the power-on phase of the clock chip, the switching chip, and at least two network cards; the clock signal of the clock chip can be prevented from being transmitted to the network card during the power-on phase of the clock chip, the switching chip, and at least two network cards, thereby preventing the clock chip from leaking electricity into the network card, thereby improving the reliability of the network card. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0049] FIG1 is a schematic diagram of a network card circuit provided in an embodiment of the present application;

[0050] FIG2 is a schematic diagram of a network card circuit in a related art provided by an embodiment of the present application;

[0051] FIG3 is a schematic diagram of the architecture of a network card circuit provided in an embodiment of the present application;

[0052] FIG4 is a schematic diagram showing the connection between a switching chip, a clock chip, and a network card according to an embodiment of the present application;

[0053] FIG5 is a schematic diagram of the architecture of another network card circuit provided in an embodiment of the present application;

[0054] FIG6 is a schematic diagram showing the connection between a switching chip and an out-of-band controller, a clock chip, and a network card according to an embodiment of the present application;

[0055] FIG7 is a flow chart of a network card circuit control method provided in an embodiment of the present application;

[0056] FIG8 is a schematic diagram of the architecture of another network card circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numbers in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0058] The embodiment of the present application relates to a network card circuit. For ease of understanding, the network card circuit involved in the embodiment of the present application is first described with reference to FIG1 .

[0059] Figure 1 is a schematic diagram of a network card circuit provided by an embodiment of the present application. Referring to Figure 1 , as shown in Figure 1 , the network card circuit may include N network cards (N is an integer greater than or equal to 2), a switch chip, a clock chip, a microcontroller, and an out-of-band controller. When N is 2, as shown in Figure 1 , Figure 1 illustrates a network card circuit including two network cards, namely OCP NIC1 and OCP NIC2.

[0060] The switching chip may include a data interface, a clock interface, an enable interface ( / EN in FIG1 ), and a select interface (S in FIG1 ).

[0061] The data interface may be an interface for connecting an out-of-band controller and a network card so that the out-of-band controller and the network card can communicate with each other. For example, the out-of-band controller and the network card can communicate based on the Network Controller Sideband Interface (NCSI) protocol. As shown in Figure 1, the data interface of the switching chip may include an A1 interface, an A2 interface, an A3 interface, an A4 interface, an A5 interface, and an A6 interface (the A1-A6 interfaces in Figure 1), may include a B1 interface, a B2 interface, a B3 interface, a B4 interface, a B5 interface, and a B6 interface (the B1-B6 interfaces in Figure 1), and may also include a C1 interface, a C2 interface, a C3 interface, a C4 interface, a C5 interface, and a C6 interface (the C1-C6 interfaces in Figure 1). Among them, the A1-A6 interfaces can be connected to the out-of-band controller, the B1-B6 interfaces can be connected to the OCP NIC1, and the C1-C6 interfaces can be connected to the OCP NIC2. If interfaces A1-A6 are connected to interfaces B1-B6 respectively, the out-of-band controller can communicate with OCP NIC1 through the switch chip. If interfaces A1-A6 are connected to interfaces C1-C6 respectively, the out-of-band controller can communicate with OCP NIC2 through the switch chip.

[0062] The clock interface may be an interface for connecting a clock chip and a network card so that the network card can obtain the clock signal (CLK) output by the clock chip. As shown in Figure 1, the clock interface of the switching chip may include an A7 interface, an A8 interface, a B7 interface, and a C8 interface. Among them, the A7 interface can be connected to OCP NIC1, the A8 interface can be connected to OCP NIC2, the B7 interface can be connected to one clock interface of the clock chip, and the C8 interface can be connected to another clock interface of the clock chip. Among them, the frequencies of the clock signals output by different clock interfaces on the clock chip can be the same, or the frequencies of the clock signals output by different clock interfaces on the clock chip can also be different, which is not limited in this embodiment of the present application. If the A7 interface is connected to the B7 interface, the clock chip can input the clock signal CLK1 to the OCP NIC1 through the switching chip; if the A8 interface is connected to the C8 interface, the clock chip can input the clock signal CLK2 to the OCP NIC2 through the switching chip.

[0063] It should be noted that FIG1 is only an example of illustrating the network card circuit and does not constitute a limitation on the network card circuit. In other embodiments, the network card circuit may further include other components or interfaces. For example, the switching chip may further include other clock interfaces.

[0064] The enable interface can be a low-level active interface or a high-level active interface. As shown in Figure 1, the enable interface / EN of the switch chip is low-level active. Therefore, in order to keep the switch chip in the enabled state at all times, the enable interface is usually grounded.

[0065] The selection interface can be used, based on instructions from the microcontroller, to select a network card to connect to the out-of-band controller and clock chip via the switch chip. As shown in Figure 1, the selection interface of the switch chip can be connected to the microcontroller. If the microcontroller inputs a first selection signal to the selection interface, interfaces A1-A6 of the switch chip connect to interfaces B1-B6, respectively, and interface A7 connects to interface B7. That is, if the microcontroller inputs a first selection signal to the selection interface, the out-of-band controller can connect to OCP NIC1 via the switch chip, and the clock chip can input clock signal CLK1 to OCP NIC1 via the switch chip. If the microcontroller inputs a second selection signal to the selection interface, interfaces A1-A6 of the switch chip connect to interfaces C1-C6, respectively, and interface A8 connects to interface C8. That is, if the microcontroller inputs a second selection signal to the selection interface, the out-of-band controller can connect to OCP NIC2 via the switch chip, and the clock chip can input clock signal CLK2 to OCP NIC2 via the switch chip. The first selection signal and the second selection signal can be signals of different voltage levels.

[0066] In the network card circuit described above, the microcontroller can be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), or a microcontroller unit (MCU). The embodiments of the present application do not limit the specific form of the microcontroller; the above description is merely illustrative. In the following embodiments, the microcontroller is described as a CPLD.

[0067] The out-of-band controller can be a management unit that is independent of the server's operating system and is not a business module. For example, the out-of-band controller can perform out-of-band management of the OPC NIC. The out-of-band controller can be a baseboard management controller (BMC), a monitoring management device, or a system management module (SMM). The embodiments of the present application do not limit the specific form of the out-of-band controller; the above is merely an example. In the following embodiments, the out-of-band controller is described as a BMC.

[0068] It should be noted that different servers have different names for BMC. For example, some servers call it BMC, some servers call it iLO (Integrated Lights-Out), and others call it Integrated Dell Remote Access Controller (iDRAC). Regardless of whether it is called BMC, iLO, or iDRAC, it can be understood as the BMC in the embodiments of the present invention.

[0069] The inventors discovered in actual testing that during the business power-on phase of the network card circuit, for example, within a specific period of time after the network card is powered on (for example, 500ms after the network card circuit is powered on), the clock signal output by the clock chip will be transmitted to OCP NIC1 or OCP NIC2, causing the clock chip to leak electricity into the interior of OCP NIC1 or OCP NIC2 and damage the corresponding OCP NIC, making the reliability of the OCP NIC low. It should be noted that business power refers to the power supply of the network card circuit, not the standby power supply, but the power that can be provided to the network card for normal operation and business processing. To simplify the expression, the power-on mentioned below refers to business power supply.

[0070] Currently, to prevent the clock chip from leaking electricity into the OCP NIC, related technologies can provide a switch chip for each OCP NIC. In other words, each OCP NIC can be connected to the clock chip, out-of-band controller, and microcontroller through the corresponding switch chip.

[0071] Next, the network card circuit in the related art will be described with reference to FIG2 .

[0072] Figure 2 is a schematic diagram of a network card circuit in a related technology provided by an embodiment of the present application. Referring to Figure 2, the network card circuit may include an OCP NIC, a switch chip, a clock chip, an out-of-band controller, and a microcontroller.

[0073] As shown in Figure 2, the switch chip's clock interfaces include A7, A8, B7, and C8. The A7 interface can be connected to an OCP NIC, the B7 interface can be connected to a clock chip, and the C8 interface is not connected to either the clock chip or the OCP NIC. If the A7 interface is connected to the B7 interface, the clock chip can input clock signals to the OCP NIC through the switch chip. If the A8 interface is connected to the C8 interface, the clock chip does not input clock signals to the OCP NIC.

[0074] It should be noted that other descriptions of the clock chip, out-of-band controller, microcontroller and switch chip in the network card circuit shown in FIG2 can be found in FIG1 and will not be repeated here.

[0075] In the aforementioned network card circuit, during the power-up phase of the network card circuit, the microcontroller can control the connection between the A4 interface and the C4 interface to prevent the clock signal output by the clock chip from being transmitted to the OCP NIC during the power-up phase of the network card circuit. This prevents the clock chip from leaking electricity into the OCP NIC.

[0076] However, in the above circuit, a corresponding switch chip needs to be configured for each OCP NIC, so that the number of switch chips required for the network card circuit is large, resulting in a high cost of the network card circuit.

[0077] In view of this, embodiments of the present application provide a network card circuit and a network card circuit control method to solve the problem of low reliability of the network card without increasing the cost of the network card circuit.

[0078] In the network card circuit provided in the embodiment of the present application, during the power-on phase of the network card circuit, the switching chip can be controlled to be in a disabled state to prevent the clock chip from inputting a clock signal to the network card through the switching chip during the power-on phase of the network card circuit; and after a specific period of time after the network card circuit is powered on, the switching chip can be controlled to be in an enabled state to allow the clock chip to provide a clock signal to the network card through the switching chip. In this way, the clock signal of the clock chip can be prevented from being transmitted to the network card during the power-on phase of the network card circuit, thereby preventing the clock chip from leaking electricity into the network card, thereby improving the reliability of the network card. In addition, the above-mentioned network card circuit does not require additional components such as a switching chip, which makes the cost of the network card circuit low.

[0079] It should be noted that in the embodiments of the present application, the switch chip is in the on state, that is, the switch chip is in the enabled state; the switch chip is in the off state, that is, the switch chip is in the off state. In other words, the on state recorded in this application document is the enabled state, and the off state is the off state.

[0080] The following specific embodiments are used to describe the technical solutions of the embodiments of the present application in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0081] FIG3 is a schematic diagram of the architecture of a network card circuit provided by an embodiment of the present application. Referring to FIG3 , the network card circuit includes a microcontroller, a switching chip, a clock chip, and at least two network cards, wherein the two network cards are network card 1 and network card 2.

[0082] In this embodiment, the network card may be an OCP NIC.

[0083] The microcontroller is connected to the switching chip.

[0084] The switching chip is also connected to the clock chip and at least two network cards respectively. That is, each network card can be connected to the clock circuit through the switching chip.

[0085] In this embodiment, the number of network cards may be greater than or equal to 2. FIG3 only uses 2 network cards as an example for illustration, which does not constitute a limitation on the embodiments of the present application.

[0086] Optionally, the switching chip also includes at least two first clock interfaces and at least two second clock interfaces, and the clock circuit includes at least two third clock interfaces, wherein at least two first clock interfaces are respectively connected to corresponding network cards; and at least two second clock interfaces are respectively connected to corresponding third clock interfaces.

[0087] Below, taking the number of network cards as 2 as an example, in combination with Figure 4, the connection method between the switching chip, the clock circuit and the network card is described. Figure 4 is a schematic diagram of the connection between a switching chip, a clock circuit and a network card provided in an embodiment of the present application. Referring to Figure 4, the switching chip may include a first clock interface 1, a first clock interface 2, a second clock interface 1, and a second clock interface 2. The clock circuit may include a third clock interface 1 and a third clock interface 2. As shown in Figure 4, the first clock interface 1 can be connected to the network card 1, the first clock interface 2 can be connected to the network card 2, the third clock interface 1 can be connected to the second clock interface 1, and the third clock interface 2 can be connected to the second clock interface 2.

[0088] It should be noted that the number of first clock interfaces, the number of second clock interfaces, the number of third clock interfaces, and the number of network cards can all be increased. FIG4 is merely an example of the connection between the switching chip, the clock circuit, and the network card, and does not constitute a limitation on the embodiments of the present application.

[0089] The microcontroller is configured to, upon receiving a power-on instruction, control the clock chip, the switching chip, and at least two network cards to power on, and to control the switching chip to be in an inactive state. After the at least two network cards are successfully powered on, the microcontroller controls the switching chip to be in an active state, so that the clock chip provides a clock signal to one of the at least two network cards via the switching chip. For example, the power-on instruction may be a power-on instruction for an electronic device to which the network card circuitry belongs. After receiving the power-on instruction, the network card circuitry may obtain power from a mainboard of the electronic device (e.g., a server).

[0090] In this embodiment, the microcontroller can control the switch chip to be in an enabled state or an disabled state. If the switch chip is in the enabled state, the clock chip can send a clock signal to a network card through the switch chip. If the switch chip is in the disabled state, the clock chip cannot send a clock signal to any network card.

[0091] During the specific implementation process, the microcontroller can first control the clock chip, the switching chip and at least two network cards to power on, and after the two network cards are successfully powered on, control the switching chip to be in the on state so that the clock chip can provide a clock signal to one of the at least two network cards through the switching chip.

[0092] Optionally, the switching chip includes an enabling interface, and the microcontroller is connected to the enabling interface.

[0093] It should be noted that if the enable interface receives a low level (ie, the enable interface is in a grounded state), the switching chip is in an on state; if the enable interface receives a high level (ie, the enable interface is in an ungrounded state), the switching chip is in an off state.

[0094] In this embodiment, after receiving a power-on command, the microcontroller sends a power-on signal to the clock chip, the switch chip, and at least two network cards, and outputs a first voltage level to the enable interface. After the at least two network cards are successfully powered on, the microcontroller outputs a second voltage level to the enable interface. The first voltage level and the second voltage level are opposite.

[0095] Specifically, the microcontroller can control the power-on of at least two network cards according to a power-on instruction, and can also simultaneously control the switching chip to be in an inactive state. After the at least two network cards are successfully powered on, the microcontroller can control the switching chip to be in an active state. This method can prevent the clock chip from sending clock signals to any of the network cards during the power-on phase of the network card circuit, thereby preventing the clock chip from leaking electricity into the network card during the power-on phase.

[0096] In this embodiment, the microcontroller can determine that at least two network cards are powered on successfully through detection; the microcontroller can also determine that at least two network cards are powered on successfully after a preset time period. The preset time period can be the time required for at least two network cards to be powered on successfully, as determined through multiple historical detections. For example, the preset time period can be 500ms.

[0097] The network card is powered on successfully, which means that the microcontroller can detect the presence signals of all network cards and is in a normal business power-on state.

[0098] Optionally, the microcontroller may include a timer. Upon receiving the power-on command, the microcontroller may start the timer and output the second level to the enable interface after the timer reaches a preset duration. With this method, the microcontroller does not need to detect whether at least two network cards have been successfully powered on, thereby reducing microcontroller overhead.

[0099] Optionally, the switching chip also includes a selection interface, and the microcontroller is connected to the selection interface, wherein the microcontroller is also used to output a selection signal to the selection interface; the switching chip is also used to control a first clock interface to be connected to a corresponding second clock interface according to the selection signal.

[0100] In this embodiment, the selection signal can be a first selection signal or a second selection signal. When the selection signals are different, the switching chip can control different first clock interfaces to connect to corresponding second clock interfaces, so that the clock chip can send a clock signal to the network card corresponding to the first clock interface. The first selection signal and the second selection signal can have different level signals. For example, the first selection signal can be a low level signal, and the second selection signal can be a high level signal.

[0101] For example, using FIG4 as an example, assuming that the first selection signal can indicate that the first clock interface 1 is connected to the second clock interface 1, and the second selection signal can indicate that the first clock interface 2 is connected to the second clock interface 2. Then, when the switching chip receives the first selection signal, it can control the first clock interface 1 to connect to the second clock interface 1, so that the clock chip is connected to the network card 1; when the switching chip receives the second selection signal, it can control the first clock interface 2 to connect to the second clock interface 2, so that the clock chip can send a clock signal to the network card 2.

[0102] It should be noted that Figure 4 only illustrates an example in which the switching chip includes two first clock interfaces and two second clock interfaces. In a specific implementation, the switching chip may also include more first clock interfaces and second clock interfaces, which is not limited in this embodiment of the present application.

[0103] The network card circuit provided in this embodiment may include a microcontroller, a switch chip, a clock chip, and at least two network cards. The microcontroller can control the power-on of the at least two network cards and, after the at least two network cards are successfully powered on, control the switch chip to be in an enabled state. This circuit can keep the switch chip in an inactive state during the power-on phase of the clock chip, the switch chip, and the at least two network cards. This prevents clock signals from the clock chip from being transmitted to the network cards during the power-on phase of the clock chip, the switch chip, and the at least two network cards. This prevents leakage of electricity from the clock chip into the network card, thereby improving the reliability of the network card.

[0104] Based on the embodiment of Figure 3, the network card circuit may further include an out-of-band controller.

[0105] Figure 5 is a schematic diagram of the architecture of another network card circuit provided by an embodiment of the present application. Referring to Figure 5 , based on Figure 3 , the network card circuit may further include an out-of-band controller. The out-of-band controller is connected to a switching chip, wherein the out-of-band controller is used to communicate data with at least two network cards through the switching chip.

[0106] It should be noted that FIG5 further illustrates the network card circuit based on FIG3. The description of the clock chip, microcontroller, switching chip, network card 1 and network card 2 in FIG5 can be found in the embodiment of FIG3 and will not be repeated here.

[0107] Optionally, the switching chip also includes a first data interface and at least two second data interfaces, wherein the out-of-band controller is connected to the first data interface, and at least two network cards are respectively connected to corresponding second data interfaces of the at least two second data interfaces; the switching chip is also used to control the first data interface to be connected to a target data interface of the at least two second data interfaces according to a selection signal output by the microcontroller, so that the out-of-band controller and the network card corresponding to the target data interface can communicate data.

[0108] Below, taking the number of network cards as 2 as an example, in conjunction with Figure 6, the connection method of the out-of-band controller, switching chip, clock chip, and network card is described. Figure 6 is a schematic diagram of the connection between a switching chip and an out-of-band controller, a clock chip, and a network card provided in an embodiment of the present application. Referring to Figure 6, the switching chip may include a data interface and a clock interface. The data interface may include a first data interface, a second data interface 1, and a second data interface 2. The clock interface may include a first clock interface 1, a first clock interface 2, a second clock interface 1, and a second clock interface 2.

[0109] As shown in Figure 6, the out-of-band controller can be connected to the first data interface, and the network card 1 can be connected to the second data interface 1 and the first clock interface 1. The network card 2 can be connected to the second data interface 2 and the first clock interface 2. The clock chip can be connected to the second clock interface 1 and the second clock interface 2.

[0110] When the switching chip receives different selection signals, it can control the first data interface to be connected to different second data interfaces, so that the out-of-band controller can perform data communication with the corresponding network card.

[0111] For example, assuming that the selection signal includes a first selection signal and a second selection signal, the first selection signal may indicate that the first data interface is connected to the second data interface 1, and the second selection signal may indicate that the first data interface is connected to the second data interface 2. Then, when the switching chip receives the first selection signal, it may control the first data interface to connect to the second data interface 1, so that the out-of-band controller and the network card 1 can communicate data; when the switching chip receives the second selection signal, it may control the first data interface to connect to the second data interface 2, so that the out-of-band controller and the network card 2 can communicate data.

[0112] The network card circuit provided in this embodiment may include an out-of-band controller connected to a switch chip. The circuit allows the out-of-band controller to connect to at least two network cards via the switch chip, thereby enabling data communication between the out-of-band controller and the at least two network cards via the switch chip.

[0113] Based on any of the above embodiments, the present invention also provides a network card circuit control method.

[0114] FIG7 is a flow chart of a network card circuit control method provided by an embodiment of the present application. Referring to FIG7 , the method may include:

[0115] S701: The microcontroller receives a power-on instruction.

[0116] This embodiment is applied to a network card circuit, which includes a microcontroller, a switching chip, a clock chip, and at least two network cards.

[0117] The power-on instruction can be used to instruct and control the microcontroller, the switch chip, the clock chip, and the at least two network cards to power on. For example, the power-on instruction can be a power-on instruction for the electronic device to which the network card circuit belongs.

[0118] S702: The microcontroller controls at least two network cards to power on according to the power-on instruction.

[0119] In this embodiment, the switching chip includes an enabling interface, and the microcontroller is connected to the enabling interface.

[0120] After receiving the power-on instruction, the microcontroller can send a power-on signal to at least two network cards according to the power-on instruction, and output a first level signal to the enable interface. The first level signal is used to put the switching chip into an unpowered state; for example, the first level signal can be a high level.

[0121] The power-on signal may be used to instruct at least two network cards to power on.

[0122] Optionally, the power-on signal may also be used to instruct the clock chip and the switching circuit to power on.

[0123] It should be noted that the microcontroller outputs a high level to the enable interface to control the switch chip to be in the disabled state. In other words, after receiving the power-on command, the microcontroller can control the clock chip, the switch chip, and at least one network card to power on, and can also control the switch chip to be in the disabled state at the same time.

[0124] S703: After the at least two network cards are powered on successfully, the microcontroller controls the switch chip to be in an on state, so that the clock chip provides a clock signal to one of the at least two network cards through the switch chip.

[0125] In this embodiment, after determining that at least two network cards are powered on successfully, the microcontroller may output a second level to the enable interface; or, after a preset time, output the second level to the enable interface. For example, the second level may be a low level.

[0126] The preset time length may be a preset time length after the microcontroller sends a power-on signal to the clock chip, the switch chip, and the at least two network cards.

[0127] In this embodiment, the time required for at least two network cards to be powered on successfully can be determined as the preset time through multiple detections. For example, the preset time can be 500ms.

[0128] It should be noted that the microcontroller outputs the second level to the enable interface, which can control the switch chip to be in an on state, so that the clock chip can provide a clock signal to one of the at least two network cards.

[0129] In one example, the microcontroller can directly determine whether the at least two network cards are powered on successfully, and output a low level to the enable interface after determining that the at least two network cards are powered on successfully. In this example, the timing function of the microcontroller does not need to be used, thereby saving microcontroller resources.

[0130] In another example, the microcontroller may, after a preset time period, assume that at least two network cards are powered on successfully and output a low level to the enable interface.

[0131] In the network card circuit control method provided in this embodiment, a microcontroller can receive a power-on command; based on the power-on command, the microcontroller can control the clock chip, the switching chip, and at least two network cards to power on; after the at least two network cards are successfully powered on, the microcontroller can control the switching chip to be in an on state, so that the clock chip provides a clock signal to one of the at least two network cards via the switching chip. This method prevents the clock chip's clock signal from being transmitted to the network card during the power-on phase of the clock chip, the switching chip, and the at least two network cards, thereby preventing leakage of electricity from the clock chip into the network card and improving the reliability of the network card.

[0132] Below, in conjunction with Figure 8, the network card circuit provided in the embodiment of the present application is described in detail through a specific example.

[0133] FIG8 is a schematic diagram of the architecture of another network card circuit provided by an embodiment of the present application. Referring to FIG8 , the network card circuit includes a microcontroller, an out-of-band controller, a switch chip, a clock chip, an OCP NIC1, and an OCP NIC2.

[0134] The switching chip may include an A1 interface, an A2 interface, an A3 interface, an A4 interface, an A5 interface, and an A6 interface (the A1-A6 interfaces in FIG8 ), may include a B1 interface, a B2 interface, a B3 interface, a B4 interface, a B5 interface, and a B6 interface (the B1-B6 interfaces in FIG8 ), and may further include a C1 interface, a C2 interface, a C3 interface, a C4 interface, a C5 interface, and a C6 interface (the C1-C6 interfaces in FIG8 ). The A1-A6 interfaces may be connected to an out-of-band controller, the B1-B6 interfaces may be connected to OCP NIC1, and the C1-C6 interfaces may be connected to OCP NIC2. If the A1-A6 interfaces are connected to the B1-B6 interfaces, respectively, the out-of-band controller may communicate with OCP NIC1 through the switching chip; if the A1-A6 interfaces are connected to the C1-C6 interfaces, respectively, the out-of-band controller may communicate with OCP NIC2 through the switching chip.

[0135] The switch chip may also include an A7 interface, an A8 interface, a B7 interface, and a C8 interface. The A7 interface may be connected to OCP NIC1, the A8 interface may be connected to OCP NIC2, and the B7 interface and C8 interface may each be connected to a clock chip. If the A7 interface is connected to the B7 interface, the clock chip may input clock signal CLK1 to OCP NIC1 through the switch chip. If the A8 interface is connected to the C8 interface, the clock chip may input clock signal CLK2 to OCP NIC2 through the switch chip.

[0136] The switch chip may further include an enable interface ( / EN interface in FIG8 ) and a select interface (S interface in FIG8 ). The / EN interface and the S interface may be connected to the microcontroller respectively.

[0137] If the microcontroller inputs a first selection signal to the S interface, the A1-A6 interfaces of the switch chip connect to the B1-B6 interfaces, respectively, and the A7 interface connects to the B7 interface. That is, if the microcontroller inputs a first selection signal to the S interface, the out-of-band controller can communicate data with OCP NIC1 through the switch chip, and the clock chip can input clock signal CLK1 to OCP NIC1 through the switch chip. If the microcontroller inputs a second selection signal to the S interface, the A1-A6 interfaces of the switch chip connect to the C1-C6 interfaces, respectively, and the A8 interface connects to the C8 interface. That is, if the microcontroller inputs a second selection signal to the S interface, the out-of-band controller can communicate data with OCP NIC2 through the switch chip, and the clock chip can input clock signal CLK2 to OCP NIC2 through the switch chip.

[0138] If the microcontroller inputs a high-level signal to the / EN interface, the switch chip is in the disabled state. If the microcontroller inputs a low-level signal to the EN interface, the switch chip is in the enabled state.

[0139] In this embodiment, during the power-on phase of the network card circuit, the microcontroller can control the power-on of the out-of-band controller, the switch chip, the clock chip, OCP NIC1, and OCP NIC2, and simultaneously input a high-level signal to the / EN interface to disable the switch chip. After OCP NIC1 and OCP NIC2 are successfully powered on, the microcontroller can input a low-level signal to the / EN interface to enable the switch chip. This circuit prevents the clock chip's clock signal from being transmitted to OCP NIC1 or OCP NIC2 during the power-on phase of the clock chip, the switch chip, OCP NIC1, and OCP NIC2. This prevents the clock chip from leaking electricity into OCP NIC1 or OCP NIC2, thereby improving the reliability of OCP NIC1 and OCP NIC2.

[0140] An embodiment of the present application provides a computing device, which may include the network card circuit provided by any of the above embodiments.

[0141] An embodiment of the present application provides a computer-readable storage medium having computer-executable instructions stored thereon; the computer-executable instructions are used to implement the network card circuit control method as described in any of the above embodiments.

[0142] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed, the computer executes the above-mentioned network card circuit control method.

[0143] All or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, it performs the steps of the above-mentioned method embodiments; and the aforementioned memory (storage medium) includes: read-only memory (ROM), RAM, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disc, and any combination thereof.

[0144] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, device (system), and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processing unit of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable terminal device to produce a machine, so that the instruction executed by the processing unit of the computer or other programmable terminal device produces a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0145] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0146] These computer program instructions can also be loaded onto a computer or other programmable terminal device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0147] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the embodiments of the present application are intended to include such modifications and variations.

[0148] In the embodiments of the present application, the terms "include", "comprise" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. The term "or" and its variations may refer to "and / or". In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In the embodiments of the present application, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0149] Those skilled in the art will readily conceive of other embodiments of the present application after considering the invention disclosed in the specification and practice. The embodiments of the present application are intended to cover any variations, uses, or adaptations of the embodiments of the present application, which follow the general principles of the embodiments of the present application and include common knowledge or customary technical means in the art that are not disclosed in the embodiments of the present application.

Claims

1. A network card circuit, characterized in that: It includes a microcontroller, a switching chip, a clock chip and at least two network cards, wherein: The microcontroller is connected to the switching chip; the switching chip is also connected to the clock chip and the at least two network cards respectively; The microcontroller is used to control the clock chip, the switching chip and the at least two network cards to power on after receiving a power-on instruction, and control the switching chip to be in an unpowered state; after the at least two network cards are successfully powered on, control the switching chip to be in an powered-on state, so that the clock chip provides a clock signal to one of the at least two network cards through the switching chip.

2. The circuit according to claim 1, characterized in that The switching chip includes an enabling interface, and the microcontroller is connected to the enabling interface, wherein the microcontroller is specifically used for: After receiving the power-on instruction, sending a power-on signal to the clock chip, the switching chip and the at least two network cards, and outputting a first level to the enabling interface to control the switching chip to be in an unenabled state; After the at least two network cards are powered on successfully, outputting a second level to the enabling interface to control the switching chip to be in an on state; The first level and the second level are opposite.

3. The circuit according to claim 2, characterized in that The microcontroller is specifically used for: After a preset time, a second level is output to the enable interface; the preset time is a preset time after the microcontroller sends a power-on signal to the clock chip, the switching chip and the at least two network cards.

4. The circuit according to claim 2 or 3, characterized in that The switching chip further includes at least two first clock interfaces and at least two second clock interfaces, and the clock chip includes at least two third clock interfaces, wherein: The at least two first clock interfaces are respectively connected to corresponding network cards; The at least two second clock interfaces are respectively connected to corresponding third clock interfaces.

5. The circuit according to claim 4, characterized in that The switching chip further includes a selection interface, and the microcontroller is connected to the selection interface, wherein: The microcontroller is also used to output a selection signal to the selection interface; The switching chip is further used to control one of the first clock interfaces to be connected to a corresponding one of the second clock interfaces according to the selection signal.

6. The circuit according to any one of claims 1 to 5, characterized in that: The circuit further includes an out-of-band controller, which is connected to the switching chip, wherein: The out-of-band controller is used to perform data communication with the at least two network cards through the switching chip.

7. The circuit according to claim 6, characterized in that The switching chip also includes a first data interface and at least two second data interfaces, wherein: The out-of-band controller is connected to the first data interface, and the at least two network cards are respectively connected to corresponding second data interfaces of the at least two second data interfaces; The switching chip is also used to control the first data interface to be connected to a target data interface among the at least two second data interfaces according to a selection signal output by the microcontroller, so that the out-of-band controller can perform data communication with the network card corresponding to the target data interface.

8. A network card circuit control method, characterized in that: Applied to a network card circuit, the network card circuit includes a microcontroller, a switching chip, a clock chip and at least two network cards; the method also includes: The microcontroller receives a power-on instruction; The microcontroller controls the at least two network cards to be powered on according to the power-on instruction, and controls the switching chip to be in an unpowered state; after the at least two network cards are powered on successfully, the switching chip is controlled to be in an powered-on state, so that the clock chip provides a clock signal to one of the at least two network cards.

9. The method according to claim 8, characterized in that The switching chip includes an enabling interface, and the microcontroller is connected to the enabling interface; the microcontroller controls the at least two network cards to be powered on according to the power-on instruction, and controls the switching chip to be in an unpowered state; After the at least two network cards are powered on successfully, controlling the switch chip to be in an on state so that the clock chip provides a clock signal to one of the at least two network cards, includes: The microcontroller sends a power-on signal to the at least two network cards according to the power-on instruction, and outputs a first level to the enable interface; After determining that the at least two network cards are powered on successfully, outputting the second level to the enabling interface; or, after a preset time period, outputting the second level to the enabling interface.

10. A computing device, characterized in that The computing device comprises the network card circuit according to any one of claims 1-7.

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