Instruction-resource conflict detection method and apparatus, and chip, device and storage medium

Abstract

An instruction-resource conflict detection method and apparatus, and a chip, a device and a storage medium, which relate to the technical field of chips. The method comprises: creating a first resource recording space (310); when hardware resource information associated with an ith compiling instruction indicates that a plurality of groups of hardware resources meet a resource occupation condition, writing, into the first resource recording space, resource occupation information respectively corresponding to the plurality of groups of hardware resources, so as to obtain second resource recording spaces respectively corresponding to the plurality of groups of hardware resources (320); and with regard to a process during which an (i+k)th compiling instruction is written into a plurality of second resource recording spaces, when there is a conflict recording space among the plurality of second resource recording spaces, deleting the conflict recording space from the plurality of second resource recording spaces, wherein the conflict recording space refers to a second resource recording space which has a resource conflict with the (i+k)th compiling instruction (330).

Description

Instruction resource conflict detection method, device, chip, equipment and storage medium

[0001] This application claims priority to Chinese patent application number 202311166405.8, filed on September 11, 2023, entitled “Conflict detection method, device, equipment and storage medium for instruction resources”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip technology, and in particular to a method, apparatus, chip, device and storage medium for detecting conflict of instruction resources. Background Art

[0003] Artificial Intelligence (AI) chips often use the Very Long Instruction Word (VLIW) architecture as their infrastructure. In the VLIW architecture, the compiler not only needs to convert high-level language code into machine code but also needs to perform complex optimization work. Instruction scheduling is a key optimization stage, where the compiler can reorder the issuance order of instructions to improve the parallelism of instruction execution.

[0004] In related technologies, compilers usually use a reservation table (RT) to record the hardware resources occupied when instructions are executed during the instruction scheduling process. Before calling a new instruction, resource conflict detection will be performed through the reservation table. When it is detected that the hardware resources required by the new instruction are occupied, the execution interval between instructions will be increased until the required hardware resources are no longer occupied. Then, the new instruction will be called and the occupation of the hardware resources of the new instruction will be written into the reservation table.

[0005] However, the instruction resources maintained by the reservation table in the related art are relatively fixed, and the scheduling decision is relatively rigid. When the instruction to be called encounters a resource conflict, the execution time of the instruction will be increased, reducing the scheduling efficiency of the instruction scheduling.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a method, apparatus, chip, device, and storage medium for detecting conflict in instruction resources, which can improve the scheduling efficiency of instruction scheduling. The technical solution is as follows.

[0008] In one aspect, a method for detecting conflict of instruction resources is provided, which is performed by a first device, and the method includes:

[0009] Creating a first resource recording space, the first resource recording space being used to record hardware resource usage of a plurality of compilation instructions, the plurality of compilation instructions being respectively associated with hardware resource information, the hardware resource information indicating at least one set of hardware resources used to complete the compilation instructions;

[0010] If the hardware resource information associated with the i-th compilation instruction indicates that multiple groups of hardware resources meet the resource occupation condition, writing the resource occupation information corresponding to the multiple groups of hardware resources into the first resource recording space to obtain second resource recording spaces corresponding to the multiple groups of hardware resources, where i is a positive integer and the resource occupation condition indicates that the hardware resources required to complete the compilation instruction are not occupied;

[0011] In a process of writing a plurality of second resource recording spaces for an i+k-th compilation instruction, if a conflicting recording space exists among the plurality of second resource recording spaces, deleting the conflicting recording space from the plurality of second resource recording spaces, wherein the conflicting recording space refers to the second resource recording space that has a resource conflict with the i+k-th compilation instruction, and the resource conflict refers to resource occupancy information written in the second resource recording space indicating that hardware resources required to complete the i+k-th compilation instruction are already occupied, where k is a positive integer.

[0012] In another aspect, a device for detecting conflict of instruction resources is provided, the device comprising:

[0013] a processing module, configured to create a first resource recording space, wherein the first resource recording space is configured to record hardware resource usage of a plurality of compilation instructions, wherein the plurality of compilation instructions are respectively associated with hardware resource information, wherein the hardware resource information indicates at least one set of hardware resources used to complete the compilation instructions;

[0014] The processing module is further configured to, when the hardware resource information associated with the i-th compilation instruction indicates that the multiple groups of hardware resources meet the resource occupation condition, write the resource occupation information corresponding to the multiple groups of hardware resources into the first resource recording space to obtain second resource recording spaces corresponding to the multiple groups of hardware resources, where i is a positive integer and the resource occupation condition indicates that the hardware resources required to complete the compilation instruction are not occupied;

[0015] The processing module is further configured to write into a plurality of second resource recording spaces respectively for the (i+k)th compilation instruction, and, if a conflicting recording space exists among the plurality of second resource recording spaces, delete the conflicting recording space from the plurality of second resource recording spaces, wherein the conflicting recording space refers to the second resource recording space that has a resource conflict with the (i+k)th compilation instruction, and the resource conflict refers to resource occupancy information written in the second resource recording space indicating that hardware resources required to complete the (i+k)th compilation instruction are already occupied, where k is a positive integer.

[0016] On the other hand, a chip is provided, comprising a processor and a memory, wherein the memory stores a computer program, and the computer program is loaded and executed by the processor to implement any of the instruction resource conflict detection methods described above.

[0017] On the other hand, a computer device is provided, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set, or an instruction set, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement any of the instruction resource conflict detection methods described above.

[0018] On the other hand, a computer-readable storage medium is provided, wherein the storage medium stores at least one instruction, at least one program, code set or instruction set, and the at least one instruction, the at least one program, the code set or instruction set is loaded and executed by a processor to implement the instruction resource conflict detection method as described in any of the above.

[0019] In another aspect, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the aforementioned instruction resource conflict detection methods.

[0020] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0021] When conflict detection is performed on compilation instructions through resource record space, if a compilation instruction has multiple sets of hardware resources available and these multiple sets of hardware resources are not occupied, a resource record space is maintained for each of these multiple sets of hardware resources. When conflict detection is performed on new compilation instructions later, the resource record space that has a resource conflict with the new instruction can be deleted, thereby providing more selection opportunities for the instruction scheduling process. For example: if the hardware resources required by the currently called compilation instruction have a resource conflict with resource record space 1, but not with resource record space 2, then resource record space 1 can be deleted and resource record space 2 can be maintained, thereby reducing the situation where instruction resource conflicts are avoided by increasing the execution interval between instructions, thereby improving the scheduling efficiency of instruction scheduling. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic diagram of instruction resource conflict detection based on record space provided by an exemplary embodiment of the present application;

[0023] FIG2 is a schematic diagram of an implementation environment provided by an exemplary embodiment of the present application;

[0024] FIG3 is a flow chart of a method for detecting conflict of instruction resources provided by an exemplary embodiment of the present application;

[0025] FIG4 is a schematic diagram of a resource description space provided by an exemplary embodiment of the present application;

[0026] FIG5 is a schematic diagram of a writing process provided by an exemplary embodiment of the present application;

[0027] FIG6 is a schematic diagram of a multi-recording space writing process provided by an exemplary embodiment of the present application;

[0028] FIG7 is a schematic diagram of conflicting record space deletion provided by an exemplary embodiment of the present application;

[0029] FIG8 is a flowchart of a method for generating a second resource recording space provided by an exemplary embodiment of the present application;

[0030] FIG9 is a flow chart of a method for deleting conflicting record spaces provided by an exemplary embodiment of the present application;

[0031] FIG10 is a schematic diagram of instruction execution cycle adjustment provided by an exemplary embodiment of the present application;

[0032] FIG11 is a flow chart of a resource description space parsing method provided by an exemplary embodiment of the present application;

[0033] FIG12 is a schematic diagram of a resource description space provided by another exemplary embodiment of the present application;

[0034] FIG13 is a schematic diagram of a timing occupancy diagram provided by an exemplary embodiment of the present application;

[0035] FIG14 is a schematic diagram of instruction resource conflict detection provided by an exemplary embodiment of the present application;

[0036] FIG15 is a schematic diagram showing a performance comparison provided by an exemplary embodiment of the present application;

[0037] FIG16 is a schematic diagram of a parsing process of a resource description space provided by an exemplary embodiment of the present application;

[0038] FIG17 is a schematic diagram of a parsing process of a resource description space provided by another exemplary embodiment of the present application;

[0039] FIG18 is a schematic diagram of a timing occupancy summary diagram provided by an exemplary embodiment of the present application;

[0040] FIG19 is a schematic diagram of a resource conflict detection process provided by an exemplary embodiment of the present application;

[0041] FIG20 is a structural block diagram of an instruction resource conflict detection device provided by an exemplary embodiment of the present application;

[0042] FIG21 is a structural block diagram of a module of a conflict detection device for instruction resources provided by an exemplary embodiment of the present application;

[0043] FIG22 is a structural block diagram of a terminal provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0044] Artificial Intelligence (AI) chips often use the Very Long Instruction Word (VLIW) architecture as their infrastructure. In the VLIW architecture, the compiler not only needs to convert high-level language code into machine code but also needs to perform complex optimization work. Instruction scheduling is a key optimization stage, where the compiler can reorder the issuance order of instructions to improve the parallelism of instruction execution.

[0045] In some embodiments, instruction scheduling can reorder the order in which instructions are emitted. During the actual instruction scheduling process, the device constructs a directed acyclic graph (DAG) based on the input instruction sequence. The DAG is used to represent the dependency relationship between instructions, and priority topological sorting is performed according to the DAG; the instructions that can be emitted in the current instruction execution cycle are determined and conflict detection of instruction resources is performed. The instructions that meet the emission conditions are placed in a first list. The first list includes all instructions that can actually be emitted at present. If there are no instructions that meet the emission conditions, the current instruction execution cycle is continuously adjusted until an instruction that can be used is determined. The above-mentioned emission condition means that there is no resource conflict between the emittable instruction and the emitted instruction; according to the instructions in the first list, the order is adjusted, that is, the instruction determined to be emitted in the current instruction execution cycle is moved to the back of the last scheduled instruction until all instructions are adjusted and the instruction scheduling process is completed. Among them, the instruction resource conflict detection process is used to determine the resource usage of multiple compiled instructions during execution. For example, a hardware device is identified that supports issuing multiple instructions in the same cycle. Instruction A, instruction B, and instruction C, three instructions, and the corresponding six hardware resources are used as an example. The instruction resource usage is shown in Table 1 below:

[0046] Table 1 Instruction resource occupancy table

[0047] As shown in Table 1, resource groups indicate how many hardware resource combinations are available for each instruction. For example, instruction A corresponds to two sets of hardware resources. If instruction A uses resource group 1, then during the execution of instruction A, hardware resource 0a is required in cycle 0, hardware resource 0b is required in cycle 1, and hardware resource 0c is required in cycle 2. A cycle indicates the unit of time during instruction execution. For example, cycle 0 indicates the first instruction execution cycle during instruction execution. It is worth noting that resource groups are independent of each other. For example, instruction A can be executed using resource group 1 or resource group 2, but resource groups 1 and 2 cannot be used interchangeably. If instruction A occupies 0a in cycle 0, it cannot occupy 1b in cycle 1. Please refer to Table 2 for the binary representation of the corresponding six hardware resources.

[0048] Table 2 Resource binary representation

[0049] Since resource conflict detection is based on instruction resource description, the instruction resource description format is first introduced. Taking the Low Level Virtual Machine (LLVM) as an example, LLVM generates an instruction resource description table based on the resource occupancy indicated in Table 1 above. For each compilation instruction, the resources occupied by the compilation instruction at each stage, the occupied time, and the time interval to the next resource are analyzed. When a compilation instruction corresponds to multiple resource groups, different hardware resources occupied at the same stage are connected with "|". The instruction resource description is shown in the structure of Table 3 below:

[0050] Table 3 Instruction resource description table

[0051] As shown in Table 3, the hardware resource usage during the completion of an instruction is described by combining the instruction resources, the occupancy time of each resource, and the interval time to the next instruction. The stage refers to the execution stage of the instruction. For example, instruction A uses resource 0a for 1 cycle in stage 0, and the interval from resource 0a to the next resource is 1 cycle. That is, during the execution process, instruction A occupies 0a in the first cycle, cycle 0, and occupies 0b in the second cycle, cycle 1. Cycle 0 corresponds to stage 0 and is used to indicate the time occupied by the first execution stage, and so on. However, the resource description format shown in Table 3 cannot describe the multiple sets of hardware resources required by an instruction. When an instruction has multiple sets of hardware resources, this description format cannot accurately describe the instruction resources. For example, as shown in Table 3, instruction A needs to occupy hardware resources 0a or 1a in cycle 0, and 0b or 1b in cycle 1. Based on this description format, instruction A can generate four resource occupancy situations in cycle 0 and cycle 1: 0a+1b, 0a+0b, 1a+1b, and 1a+0b. However, according to Table 1, only 0a+0b or 1a+1b conforms to the actual resource occupancy situation.

[0052] Based on the instruction resource description table provided in Table 3, instruction resource conflicts are detected. Assuming that during the instruction scheduling process, instruction C, instruction B, instruction A, instruction A, and instruction C need to be scheduled in order of priority from high to low, please refer to Figure 1. Figure 1 is a schematic diagram of instruction resource conflict detection based on a reservation table provided by an exemplary embodiment of the present application. As shown in Figure 1, the solid rectangular box in the figure is a reservation table, and the dotted rectangular box is used to indicate the instruction execution cycle. The number before the colon in the reservation table is used to identify the instruction execution cycle, and the binary number after the colon is used to indicate the occupied hardware resources, wherein the number marked in underline form before the colon is used to identify the current instruction execution cycle, the number marked in italics after the colon is used to identify the resources occupied by the inserted instruction, and the number marked in bold after the colon is used to identify the conflicting resources. As shown in Figure 1, the resource conflict detection process for scheduling instructions C, instruction B, instruction A, instruction A, and instruction C using the reservation table includes the following steps:

[0053] 1) Create a reservation table 101 and initialize the reservation table data to 0:000000. Insert the hardware resources required by instruction C from the current instruction execution cycle cycle 0, which are hardware resources 0b (000010) occupied in cycle 0, hardware resources 0c (000100) occupied in cycle 1, and hardware resources 0c (000100) occupied in cycle 2, to obtain an updated reservation table;

[0054] 2) Insert the hardware resources occupied by instruction B from the current instruction execution cycle cycle0. Since the hardware resources 0c occupied by instruction B in cycle1 and cycle2 conflict with the hardware resources occupied by cycle1 and cycle2 in the reserved table, adjust the current instruction execution cycle to cycle1; insert the hardware resources occupied by instruction B from the current instruction execution cycle cycle1. Since the hardware resources 0c occupied by instruction B in cycle2 still conflict with the hardware resources occupied by cycle2 in the reserved table, adjust the current instruction execution cycle to cycle2; insert the hardware resources occupied by instruction B from the current instruction execution cycle cycle2, occupying hardware resources 0a (000001) in cycle2, hardware resources 0c (000100) in cycle3, and hardware resources 0c (000100) in cycle4 respectively;

[0055] 3) Insert the hardware resources required for instruction A from the current instruction execution cycle cycle2. Instruction A exists in resource group 1 and resource group 2. Resource conflict detection is performed in the order of resource group 1 and resource group 2 in descending order of priority. Since the hardware resource 0a required by instruction A conflicts with the resource 0a occupied by cycle2 in the reservation table, hardware resource 1a (001000) is selected to be occupied in cycle2. Since the hardware resource 0b required by instruction A does not conflict with the resource 0c occupied by cycle3 in the reservation table, hardware resource 0b (000010) is selected to be occupied in cycle3. Since the hardware resource 0c required by instruction A conflicts with the resource 0c occupied by cycle4 in the reservation table, hardware resource 1c (100000) is selected to be occupied in cycle4.

[0056] 4) Insert the hardware resources required for instruction A from the current instruction execution cycle cycle 2. Since resource 1 and resource group 2 corresponding to instruction A have resource conflicts with the hardware resources in the reservation table starting from cycle 2, adjust the current instruction execution cycle to cycle 3; reinsert the hardware resources required for instruction A from the current instruction execution cycle cycle 3. Resource group 1 and resource group 2 corresponding to instruction A have no resource conflicts with the hardware resources in the reservation table. Since only one reservation table is maintained, resource group 1 is selected according to the resource group priority, and hardware resource 0a (000001) is occupied in cycle 3, hardware resource 0b (000010) is occupied in cycle 4, and hardware resource 0c (000100) is occupied in cycle 5, thereby obtaining the updated reservation table.

[0057] 5) Insert the hardware resources required for instruction C from the current instruction execution cycle cycle3. Since the resource group 1 corresponding to instruction C has a resource conflict with the hardware resources in the reservation table from cycle3 onwards, the current instruction execution cycle is adjusted to cycle4; reinsert the hardware resources required for instruction C from the current instruction execution cycle cycle4. Since the resource group 1 corresponding to instruction C still has a resource conflict with the hardware resources in the reservation table from cycle4 onwards, the current instruction execution cycle is adjusted to cycle5; reinsert the hardware resources required for instruction C from the current instruction execution cycle cycle5, occupying hardware resources 0b (000010) in cycle5, occupying hardware resources 0c (000100) in cycle6, and occupying hardware resources 0c (000100) in cycle7, to obtain an updated reservation table 102.

[0058] In the conflict detection process of the above-mentioned instruction resources, when reinserting the hardware resources required for instruction A from the current instruction execution cycle cycle 3 in step 4, although the resource occupancy information corresponding to resource group 1 and resource group 2 of instruction A can be inserted into the reservation table, since only one reservation table is maintained, the instruction scheduler misses the plan to complete instruction A with resource group 2 when analyzing the available instructions. Based on this, when inserting the hardware resources required for instruction C in step 5, there is a resource conflict in the detection of two consecutive cycles, resulting in a pause of two cycles, which makes the instruction scheduling plan determined based on the above-mentioned conflict detection plan prone to miss more instruction scheduling opportunities and easily cause more cycle pauses, thereby increasing the execution time of the instruction and making the scheduling efficiency of the instruction scheduling low.

[0059] Based on this, an embodiment of the present application provides a method for detecting conflict of instruction resources. First, the computer system provided by the embodiment of the present application is introduced. Please refer to Figure 2, which shows a schematic diagram of a computer system provided by an exemplary embodiment of the present application, and the computer system includes: a terminal 210.

[0060] In some embodiments, an AI chip is used in the terminal 210 to execute the target program. A machine learning model 211 and an AI compiler 212 are deployed in the terminal 210. The AI ​​compiler 212 adopts a classic front-end and back-end structure. The AI ​​compiler 212 is used to connect the machine learning model 211 with the AI ​​chip.

[0061] In some embodiments, the machine learning model 211 is read by the AI ​​compiler 212, and the model is first parsed at the front end to obtain a high-level intermediate representation (IR), and then optimizations unrelated to the target hardware are performed, such as arithmetic simplification, operator fusion, etc., and the optimized high-level IR is output; then the target-related optimizations of the back end are entered, such as dedicated instruction mapping, memory allocation, memory access delay hiding, etc., and the related low-level IR is output; finally, the code generation stage of the back end is entered, and finally a target program that can run on the AI ​​chip is generated.

[0062] In some embodiments, AI chips often use a VLIW architecture as the infrastructure. In this type of architecture, in order to achieve large-scale computing units and power consumption control, many functions that are the responsibility of hardware in traditional chips will be simplified or directly transferred to the compiler for implementation. As the AI ​​compiler 212 becomes more complex, there will be more opportunities to optimize the code more deeply at the software level. Among them, instruction scheduling is an important optimization stage, which can reorder the order of instruction issuance, improve the parallelism of instruction execution, and reduce the total time required for operator execution. Instruction resource conflict detection is required during the instruction scheduling process. In some embodiments, the terminal 210 is used to execute the above-mentioned instruction resource conflict detection method. The above-mentioned terminal is optional. The terminal can be a desktop computer, a laptop computer, a mobile phone, a tablet computer, an e-book reader, a Moving Picture Experts Group Audio Layer III (MP3) player, a Moving Picture Experts Group Audio Layer IV (MP4) player, a smart TV, a smart car, and other terminal devices in various forms. The embodiments of the present application are not limited to this. In some embodiments, the above-mentioned terminal can also be a server. It is worth noting that the above-mentioned server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, a cloud server providing cloud computing services, or a node in a blockchain system.

[0063] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, storage, display, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant region. For example, the compilation instructions and hardware resource information involved in this application are obtained with full authorization.

[0064] Schematically, please refer to FIG3 , which shows a flow chart of a method for detecting conflict of instruction resources provided by an exemplary embodiment of the present application. The method is performed by a first device, which may be a terminal, a server, or both a terminal and a server. As shown in FIG3 , the method includes the following steps:

[0065] Step 310: Create a first resource recording space.

[0066] The first resource recording space is used to record the hardware resource occupancy of multiple compilation instructions. Schematically, the hardware resource occupancy recorded in the first resource recording space refers to the actual resource occupancy during the execution of the compilation instructions.

[0067] Optionally, the record space can be implemented in various forms such as a table, a log file, a key-value storage structure, etc., which is not limited in the present embodiment. The following mainly describes the record space in a table form as an example.

[0068] Optionally, the first resource recording space may be implemented as a first resource reservation table.

[0069] Illustratively, the first resource reservation table is stored in the memory of the first device. The first resource reservation table can be stored in the memory of the first device in the form of an array, a heap, a stack, a queue, a linked list, etc., which is not limited in this application. The first resource reservation table is stored in the memory of the first device in the form of an array as an example for explanation.

[0070] Optionally, creating the first resource reservation table is implemented by creating an array for storing the first resource reservation table.

[0071] Illustratively, in response to the creation of the first resource reservation table, a first array for storing the first resource reservation table is created in the memory of the first device. In response to new hardware resource occupancy information being written to the first resource reservation table, the data corresponding to the updated hardware resource occupancy information is updated in the first array, thereby storing the latest first resource reservation table in real time in the form of an array in the memory of the first device. Optionally, an array can be used to store a single resource reservation table or multiple resource reservation tables.

[0072] The plurality of compilation instructions are respectively associated with hardware resource information, and the hardware resource information indicates at least one set of hardware resources for completing the compilation instructions.

[0073] Wherein, a compilation instruction is a basic unit in a computer program, which tells the computer what operation to perform. Illustratively, in an embodiment of the present application, a compilation instruction can be scheduled by a compiler, and a processor reads and executes the compilation instruction. The hardware resource information associated with the compilation instruction refers to the physical devices directly or indirectly used by the compilation instruction when executing the compilation instruction, including but not limited to processors, memory, registers, input and output devices, caches, interrupt controllers, timers, etc.

[0074] Optionally, the hardware resource information associated with the compilation instruction includes an instruction identifier, a phase identifier, at least one group of hardware resource identifiers, an occupied time, and a time interval to the next resource. The instruction identifier is used to identify the compilation instruction, and the instruction identifier can be implemented as an instruction name, an instruction unique identifier, etc. The phase identifier is used to indicate the instruction execution phase corresponding to the compilation instruction (e.g., the compilation instruction includes three instruction execution phases), and the hardware resources required for different instruction execution phases can be the same or different; at least one group of hardware resource identifiers is used to identify at least one group of hardware resources, and at least one group of hardware resources can be implemented as a hardware name, a hardware unique identifier, etc. The occupied time is used to indicate the number of instruction execution cycles occupied by the hardware resources required in the corresponding instruction execution phase; the time interval to the next resource is used to indicate the number of instruction execution cycles required between the current instruction execution phase and the next instruction execution phase, and the instruction execution cycle is used to indicate the unit time during the instruction execution process.

[0075] Optionally, a single compilation instruction is associated with hardware resource information corresponding to a single set of hardware resources or multiple sets of hardware resources. When a single compilation instruction is associated with hardware resource information corresponding to multiple sets of hardware resources, any of the multiple sets of hardware resources can be used to complete the single compilation instruction. For example, if instruction A is associated with resource group 1 and resource group 2, either resource group 1 or resource group 2 can complete the execution of instruction A.

[0076] In some embodiments, hardware resource information associated with multiple compilation instructions is stored in a resource description space. Optionally, before creating the first resource record space, the method further includes: obtaining a resource description space. Illustratively, the resource description space is used to describe the possible occupancy of instruction resources, and the occupancy of instruction resources is used to indicate at least one set of hardware resources that can be used to complete the compilation instruction.

[0077] Optionally, the hardware resource information stored in the resource description space includes an instruction identifier, a stage identifier, at least one set of hardware resource identifiers, an occupied time, and a time interval to the next resource. Schematically, the instruction resource occupancy shown in Table 1 above is used as an example for illustration. Please refer to FIG4 . FIG4 is a schematic diagram of a resource description provided by an exemplary embodiment of the present application. As shown in FIG4 , the resource description table 400 includes instruction A and resource groups 410 and 420 corresponding to instruction A, instruction B and resource group 430 corresponding to instruction B, instruction C and resource group 440 corresponding to instruction C. Resource group 410 includes hardware resources 0a, 0b, and 0c required for instruction A, resource group 420 includes hardware resources 1a, 1b, and 1c required for instruction A, resource group 430 includes hardware resources 0a, 0c, and 0c required for instruction B, and resource group 440 includes hardware resources 0b, 0c, and 0c required for instruction C. The segmentation word is used to distinguish different resource groups when a single compilation instruction corresponds to multiple groups of hardware resources. For example, instruction A using resource group 1 will occupy hardware resource 0a during instruction execution phase 0, which takes one cycle. The time interval between instruction execution phase 0 and instruction execution phase 1 is one cycle. Hardware resource 0b will be occupied during instruction execution phase 1, which takes one cycle. The time interval between instruction execution phase 1 and instruction execution phase 2 is one cycle. Hardware resource 0c will be occupied during instruction execution phase 2, which takes one cycle. The time interval between instruction execution phase 2 and instruction execution phase 0 of the next instruction is one cycle. That is, during the execution of instruction A, hardware resource 0a will be occupied during the first cycle, hardware resource 0b will be occupied during the second cycle, and hardware resource 0c will be occupied during the third cycle.

[0078] It is worth noting that the above-mentioned resource description table is only an illustrative example. This application does not limit the implementation form of the resource description table. The resource description table used in the embodiment of this application is different from the mixed description method of the two groups of hardware resources for instruction A in Table 3. The resource description table used in the embodiment of this application can independently and clearly describe multiple groups of hardware resources corresponding to a single compilation instruction. For example, segmentation words are used to distinguish resource group 1 and resource group 2. This application does not limit the method of distinguishing between different resource groups.

[0079] In some embodiments, the created first resource recording space is a blank space, that is, no data is recorded. Schematically, the created first resource reservation table is an empty table.

[0080] In some embodiments, a compilation instruction corresponds to multiple instruction execution phases, and the compilation instruction occupies corresponding hardware resources in the order corresponding to the multiple instruction execution phases. Optionally, during the instruction resource conflict detection process, resource occupancy information corresponding to the hardware resources occupied by the compilation instruction in the multiple instruction execution phases is written into the first resource record space based on the resource description table.

[0081] In some embodiments, when there is one first resource recording space, the process of writing hardware resource information corresponding to multiple compilation instructions into the first resource recording space includes the following two cases:

[0082] The first method is to write resource occupancy information corresponding to at least one set of hardware resources from the current instruction execution cycle into the first resource recording space when at least one set of hardware resources capable of completing the compilation instruction meets the resource occupancy condition corresponding to the current instruction execution cycle to obtain a fourth resource recording space.

[0083] The second method is to update the next instruction execution cycle of the current instruction execution cycle to the current instruction execution cycle when at least one group of hardware resources capable of completing the compilation instruction does not meet the resource occupancy conditions corresponding to the current instruction execution cycle, until at least one group of hardware resources capable of completing the compilation instruction meets the resource occupancy conditions corresponding to the current instruction execution cycle, and write the resource occupancy information corresponding to the at least one group of hardware resources from the current instruction execution cycle into the first resource recording space to obtain the fifth resource recording space.

[0084] The resource occupancy condition refers to the at least one set of hardware resources used to complete the compiled instruction, which, from the start of the instruction execution cycle in which the compiled instruction is executed, does not conflict with the first resource recording space. The resource occupancy information indicates the occupancy of the at least one set of hardware resources used to complete the compiled instruction during the instruction execution cycle. The resource occupancy information is used to determine the hardware resource occupancy recorded in the first resource recording space.

[0085] The following description will be made by taking the implementation of the first resource recording space as the first resource reservation table as an example.

[0086] For example, assume that the hardware resource occupancy recorded in the first resource reservation table is "the hardware resources occupied by cycle0 are 0a, the hardware resources occupied by cycle1 are 0b, and the hardware resources occupied by cycle2 are 0c"; if the instruction execution cycle for starting to execute instruction A is cycle0, and the resource occupancy information of instruction A is "the hardware resources required to occupy cycle0, cycle1, and cycle2 are 0a, 0b, and 0c respectively", then there is a resource conflict between the hardware resources corresponding to instruction A and the first resource reservation table.

[0087] Schematically, the writing process of the hardware resource information of the compilation instruction in the resource description table shown in Figure 4 is used as an example for explanation. Assuming that resource conflict detection is performed in the execution order of instruction C and instruction B, please refer to Figure 5. Figure 5 is a schematic diagram of the writing process provided by an exemplary embodiment of the present application. As shown in Figure 5, a first resource reservation table 510 is created as an empty table, and the data of the first resource reservation table 510 is initialized to 0:000000, which is used to indicate that the current instruction execution cycle is cycle0 and no hardware resources are occupied; in response to the hardware resources for the compilation instruction C meeting the resource occupancy conditions corresponding to the current instruction execution cycle cycle0, the resource occupancy information corresponding to the hardware resources is written from the current instruction execution cycle to the first resource reservation table 510 to obtain a fourth resource reservation table 520. The fourth resource reservation table 520 is used to indicate that hardware resources 0b (000010) are occupied in cycle0, hardware resources 0c (000100) are occupied in cycle1, and hardware resources 0 are occupied in cycle2. c(000100); in response to the fact that there is a resource conflict between the hardware resources for the compilation instruction B in the current instruction execution cycle cycle0 and the fourth resource reservation table 520, the next instruction execution cycle cycle1 of the current instruction execution cycle cycle0 is updated to the current instruction execution cycle, until the hardware resources for the compilation instruction B meet the resource occupancy condition corresponding to the current instruction execution cycle cycle2, and the resource occupancy information corresponding to the hardware resources from the current instruction execution cycle cycle2 is written into the first resource reservation table to obtain the fifth resource reservation table 530, which is used to indicate that the hardware resource 0b(000010) is occupied in cycle0, the hardware resource 0c(000100) is occupied in cycle1, the hardware resource 0c(000100) and the hardware resource 0a(000001) are occupied in cycle2, the hardware resource 0c(000100) is occupied in cycle3, and the hardware resource 0c(000100) is occupied in cycle4.

[0088] In the above embodiment, the occupancy of hardware resources is recorded through the resource recording space to ensure that the corresponding resource occupancy information is written into the resource recording space only when the resources meet the resource occupancy conditions corresponding to the current instruction execution cycle, thereby avoiding invalid occupation of hardware resources; and allowing the current instruction execution cycle to be automatically updated to the next cycle when the hardware resources do not meet the resource occupancy conditions of the current instruction execution cycle until the resources meet the conditions, so that the compilation process can dynamically adjust the instruction execution cycle according to the actual occupancy of the hardware resources, ensuring that the compilation instructions are executed immediately when the hardware resources are available, reducing the compilation delay caused by resource waiting.

[0089] Step 320 , when the hardware resource information associated with the i-th compilation instruction indicates that multiple hardware resource groups meet the resource occupancy condition, write the resource occupancy information corresponding to the multiple hardware resource groups into the first resource recording space to obtain the second resource recording space corresponding to the multiple hardware resource groups.

[0090] Wherein, i is a positive integer, and the resource occupation condition is used to indicate that the hardware resources required to complete the compilation instruction are not occupied.

[0091] In some embodiments, the resource occupancy condition includes hardware resources corresponding to the compiled instruction, and no resource conflict with the first resource recording space from the start of the instruction execution cycle in which the compiled instruction is executed. Optionally, the resource occupancy information is used to indicate the occupancy of at least one set of hardware resources used to complete the compiled instruction during the instruction execution cycle, and the resource occupancy information is used to determine the hardware resource occupancy recorded in the first resource recording space.

[0092] For example, assume that the hardware resource occupancy recorded in the first resource reservation table is "the hardware resources occupied by cycle0 are 0a, the hardware resources occupied by cycle1 are 0b, and the hardware resources occupied by cycle2 are 0c"; if the instruction execution cycle for starting to execute instruction A is cycle0, and the resource occupancy information of instruction A is "the hardware resources required to occupy cycle0, cycle1, and cycle2 are 0a, 0b, and 0c respectively", then there is a resource conflict between the hardware resources corresponding to instruction A and the first resource reservation table.

[0093] In some embodiments, a single compilation instruction corresponds to a single set of hardware resources or multiple sets of hardware resources. When a single compilation instruction corresponds to multiple sets of hardware resources, there may be multiple sets of hardware resources that meet the resource occupation condition.

[0094] Schematically, the writing process of the hardware resource information of the compilation instruction in the resource description table shown in FIG4 is used as an example for explanation. Instruction A corresponds to resource group 410 and resource group 420. Please refer to FIG6 , which is a schematic diagram of the writing process of multiple reservation tables provided by an exemplary embodiment of the present application. As shown in FIG6 , the current first resource reservation table 610 is obtained. The resource occupancy status in the first resource reservation table is used to indicate that resources 0b (000010) are occupied in cycle 0, resources 0c (000100) are occupied in cycle 1, resources 1a (001000), 0c (000100), and 0a (000001) are occupied in cycle 2, and resources 0c (000100), 0b (000010) are occupied in cycle 3. ), occupying resources 1c (100000) and 0c (000100) in cycle4; in response to the existence of two groups of hardware resources for instruction A that meet the resource occupation conditions, wherein resource group 410 is used to indicate that instruction A occupies resource 0a from the current instruction execution cycle cycle3, occupies resource 0b in cycle4, and occupies resource 0c in cycle5, and resource group 420 is used to indicate that instruction A occupies 1a from the current instruction execution cycle, occupies resource 1b in cycle4, and occupies resource 1c in cycle5, and the resource occupancy information corresponding to the two groups of resource hardware are written into the first resource reservation table 610, and a second resource reservation table 621 corresponding to resource group 410 and a second resource reservation table 622 corresponding to resource group 420 are obtained.

[0095] Step 330 is a process of writing the (i+k)th compilation instruction into multiple second resource recording spaces. If a conflicting recording space exists among the multiple second resource recording spaces, the conflicting recording space is deleted from the multiple second resource recording spaces. The conflicting recording space refers to the second resource recording space that has a resource conflict with the (i+k)th compilation instruction.

[0096] Among them, resource conflict means that the resource occupancy information written in the second resource recording space indicates that the hardware resources required to complete the i+kth compilation instruction have been occupied, and k is a positive integer. There is a resource conflict between the i+kth compilation instruction and the second resource recording space, that is, the i+kth compilation instruction has a hardware resource group that does not meet the resource occupancy conditions of the second resource recording space. For example, the resource recording space records the resource occupancy of cycle0 to cycle5, and instruction A needs to occupy resource 0a in cycle3. If cycle3 recorded in the resource recording space has occupied 0a, then there is a resource conflict, and the resource recording space can be determined as a conflict recording space.

[0097] In some embodiments, if and only if there are multiple second resource recording spaces, in response to the presence of a conflicting recording space in the multiple second resource recording spaces, the conflicting recording space is deleted from the multiple second resource tables. Optionally, the number of conflicting recording spaces is less than the number of second resource recording spaces.

[0098] Schematically, the writing process of the hardware resource information of the compilation instruction in the resource description table shown in Figure 4 is used as an example for explanation. Please refer to Figure 7. Figure 7 is a schematic diagram of deleting the conflict reservation table provided by an exemplary embodiment of the present application. As shown in Figure 7, for the writing process of the hardware resource information of instruction C in the second resource reservation table 711 and the second resource reservation table 712, in response to the second resource reservation table 711 being a conflict reservation table in the second resource reservation table 711 and the second resource reservation table 712, the second resource reservation table 711 is deleted, and the hardware resource information of instruction C is written into the second resource reservation table 712 to obtain a resource reservation table 720, wherein instruction C needs to occupy resource 0b (000010) in cycle 4, resource 0c (000100) in cycle 5, and resource 0c (000100) in cycle 6, which has a resource conflict with the resources occupied by cycle 4 and cycle 5 in the second resource reservation table 711.

[0099] In some embodiments, if the number of conflict recording spaces is equal to the number of second resource recording spaces, the conflict recording space is not deleted, the current instruction execution cycle is adjusted, the next instruction execution cycle is updated to the current instruction execution cycle, and instruction resource conflict detection is performed again from the current instruction execution cycle.

[0100] It should be noted that the record space is usually used to record the compilation instructions to be called. According to the instruction resource conflict detection method provided in the embodiment of the present application, there may be multiple record spaces finally determined. The first device can randomly select a record space from the multiple record spaces as the record space used for the actual call instruction; or, manually select a record space from the multiple record spaces as the record space used for the actual call instruction; or, load test the multiple record spaces, consider the current system load, and select a record space that can maximize resource utilization and minimize the impact on system performance as the record space used for the actual call instruction; or, input the multiple record spaces into the machine learning model, and extract the feature representations corresponding to the multiple record spaces. The feature representations corresponding to the record spaces should be able to reflect the system status, resource requirements and applicability of the record space, such as the resource type, quantity, historical utilization, current system load, instruction execution time and other features of the record space. Then, the feature representations corresponding to the multiple record spaces are analyzed by the machine learning model to obtain the scores corresponding to the multiple record spaces, and the record space with the highest score is selected as the record space used for the actual call instruction.

[0101] To sum up, the method provided in the embodiment of the present application, when conflict detection is performed on compilation instructions through resource recording space, if a compilation instruction has multiple sets of hardware resources available and these multiple sets of hardware resources are not occupied, then a resource recording space is maintained for each of these multiple sets of hardware resources. When conflict detection is performed on new compilation instructions subsequently, the resource recording space that has a resource conflict with the new instruction can be deleted, thereby providing more selection opportunities for the instruction scheduling process. For example: if the hardware resources required by the currently called compilation instruction have a resource conflict with resource recording space 1, but not with resource recording space 2, then resource recording space 1 can be deleted and resource recording space 2 can be maintained, thereby reducing the situation where instruction resource conflicts are avoided by increasing the execution interval between instructions, thereby improving the scheduling efficiency of instruction scheduling.

[0102] Please refer to FIG8 , which is a flowchart of a method for generating a second resource recording space provided by an exemplary embodiment of the present application. The method is described by taking the first device as an example. As shown in FIG8 , step 320 includes the following steps:

[0103] Step 321 , when the hardware resource information associated with the i-th compilation instruction indicates that the m-th group of hardware resources meets the resource occupancy condition, write the resource occupancy information corresponding to the m-th group of hardware resources into the first resource recording space to obtain the second resource recording space corresponding to the m-th group of hardware resources.

[0104] Wherein, m is a positive integer.

[0105] In some embodiments, if and only if the i-th compilation instruction corresponds to multiple sets of hardware resources and at least two sets of hardware resources among the multiple sets of hardware resources meet the resource occupation condition, the second resource recording space corresponding to the at least two sets of hardware resources is obtained.

[0106] Schematically, the process of writing the hardware resource information of the compilation instruction in the resource description table shown in Figure 4 is used as an example for explanation. Instruction A corresponds to resource group 410 and resource group 420. Please refer to Figure 6. In response to the first group of hardware resources for instruction A, that is, resource group 410, meeting the resource occupancy condition, the resource occupancy information corresponding to the first group of hardware resources is written into the first resource reservation table 610, and the first second resource reservation table 621 corresponding to the first group of hardware resources is obtained; in response to the second group of hardware resources for instruction A, that is, resource group 420, meeting the resource occupancy condition, the resource occupancy information corresponding to the second group of hardware resources is written into the first resource reservation table 610, and the second second resource reservation table 622 corresponding to the second group of hardware resources is obtained.

[0107] In some embodiments, the i-th compiled instruction is executed starting from the j-th instruction execution cycle, where j is a positive integer. For example, after the first resource record space is created, instruction C is executed as the first compiled instruction starting from the first instruction execution cycle, i.e., cycle 0.

[0108] Optionally, the above step 321 can also be implemented as: when the mth group of hardware resources of the i-th compilation instruction meets the resource occupancy conditions corresponding to the j-th instruction execution cycle, the resource occupancy information corresponding to the m-th group of hardware resources is written into the first resource recording space from the j-th instruction execution cycle to obtain the second resource recording space corresponding to the m-th group of hardware resources.

[0109] Schematically, please refer to Figure 6. After writing the hardware resource information of the third compilation instruction, the writing process of the hardware resource information of the fourth compilation instruction, i.e., instruction A, is as follows: in response to the first group of hardware resources for instruction A meeting the resource occupancy condition corresponding to the fourth instruction execution cycle, i.e., cycle3, the resource occupancy information corresponding to the first group of hardware resources is written from the fourth instruction execution cycle, cycle3, into the first resource reservation table 610, and the first second resource reservation table 621 is obtained; in response to the second group of hardware resources for instruction A meeting the resource occupancy condition corresponding to the fourth instruction execution cycle, i.e., cycle3, the resource occupancy information corresponding to the second group of hardware resources is written from the fourth instruction execution cycle, cycle3, into the first resource reservation table 610, and the second second resource reservation table 622 is obtained.

[0110] In the above embodiment, by writing the mth group of hardware resources required for the i-th compilation instruction into the first resource recording space immediately when the resource occupancy condition is met in the j-th instruction execution cycle, it can be ensured that the hardware resources are allocated to the compilation instruction at the most appropriate time point. This precise resource allocation timing reduces the idle time of hardware resources and improves the scheduling efficiency of instruction scheduling.

[0111] Step 322: When the i-th compilation instruction is written, r second resource recording spaces are obtained.

[0112] Here, r is used to indicate the number of multiple groups of hardware resources that meet the resource occupation conditions.

[0113] In some embodiments, assuming that d is the number of resource groups of the multiple groups of hardware resources corresponding to the i-th compilation instruction, then r≤d.

[0114] 6 , in response to the completion of writing the two sets of hardware resource information for instruction A, two second resource reservation tables are obtained, namely, a second resource reservation table 621 and a second resource reservation table 622 .

[0115] To sum up, the method provided in the embodiment of the present application, when the compilation instruction has multiple groups of available hardware resources, will judge the resource occupancy conditions of these multiple groups of available hardware resources in turn. When the compilation instruction has multiple groups of hardware resources that meet the resource occupancy conditions, the multiple groups of hardware resources that meet the resource occupancy conditions will be written into the first resource record space respectively, so as to maintain multiple second resource record spaces in the subsequent process. Maintaining multiple second resource record spaces can adapt to different scheduling requirements, provide more choices and possibilities for the instruction scheduling process, and improve the scheduling efficiency of instruction scheduling.

[0116] Based on the above-mentioned second resource record space generation method, please refer to FIG. 9 , which is a flow chart of a conflict record space deletion method provided by an exemplary embodiment of the present application. The method is described by taking the first device as an example. As shown in FIG. 9 , step 330 includes the following steps:

[0117] Step 331: When there is a resource conflict between the (i+k)th compilation instruction and the pth second resource recording space, the pth second resource recording space is determined as the conflict recording space. After traversing multiple second resource recording spaces, q conflict recording spaces are obtained.

[0118] Where p and q are positive integers, and p≤q <r。

[0119] 7 , in response to a resource conflict between the compilation instruction C and the first second resource reservation table 711 , the first second resource reservation table 711 is determined as a conflicting reservation table, thereby obtaining one conflicting reservation table.

[0120] In some embodiments, the i-th compilation instruction is executed starting from the j-th instruction execution cycle, the i+k-th compilation instruction is executed starting from the j+l-th instruction execution cycle, and the j-th instruction execution cycle to the j+l-th instruction execution cycle are used to execute the i-th compilation instruction to the i+k-1-th compilation instruction, where l is a positive integer.

[0121] Illustratively, assuming that the third compiled instruction is executed starting from the first instruction execution cycle and the fifth compiled instruction is executed starting from the eighth instruction execution cycle, the first instruction execution cycle to the eighth instruction execution cycle are used to execute the third to fourth compiled instructions.

[0122] Optionally, the above step 331 can also be implemented as follows: when there is a resource conflict between the i+kth compilation instruction and the pth second resource record space starting from the j+lth instruction execution cycle, the pth second resource record space is determined as the conflict record space, and when the traversal of multiple second resource record spaces is completed, q conflict record spaces are obtained.

[0123] 7 , in response to instruction C having a resource conflict with the first second resource reservation table 711 starting from the fifth instruction execution cycle cycle 4 , the first second resource reservation table 711 is determined as the conflict reservation table, and one conflict reservation table is obtained.

[0124] The method provided in the embodiment of the present application determines the pth second resource recording space as the conflict recording space when there is a resource conflict between the i+kth compilation instruction and the pth second resource recording space starting from the j+lth instruction execution cycle. Through conflict detection accurate to the instruction execution cycle, once a resource conflict is discovered, the system can immediately mark the relevant resource recording space as a conflict recording space, thereby avoiding further conflict detection based on the conflict recording space in subsequent processes, thereby reducing unnecessary resource waste.

[0125] Step 332: Delete q conflicting record spaces from the r second resource record spaces.

[0126] Schematically, please refer to FIG. 7 , where one conflicting reservation table is deleted from two second resource reservation tables, that is, the second resource reservation table 711 is deleted.

[0127] In some embodiments, all of the multiple second resource record spaces are implemented as conflict record spaces, that is, r=q. Then, the process of writing the r second resource record spaces for the i+kth compilation instruction further includes:

[0128] In the case that there are r conflicting record spaces in the r second resource record spaces, the i+kth compilation instruction is adjusted to start execution from the j+l+tth instruction execution cycle, where t is a positive integer.

[0129] For illustration, please refer to Figure 10, which is a schematic diagram of instruction execution cycle adjustment provided by an exemplary embodiment of the present application. As shown in Figure 10, instruction B starts execution from cycle 3. In response to the existence of two conflicting reservation tables in the two second resource reservation tables, instruction B is adjusted to start execution from cycle 4, wherein the resource 0a (000001) required for instruction B in cycle 3 and the resource 0c (000100) required for instruction B in cycle 4 have a resource conflict with the second resource reservation table 1011, and the resource 0c (000100) required for instruction B in cycle 4 has a resource conflict with the second resource reservation table 1012.

[0130] In some embodiments, after adjusting the i+kth compilation instruction to start execution from the j+l+tth instruction execution cycle, it also includes: when the hardware resource information associated with the i+kth compilation instruction indicates that the target hardware resource meets the resource occupancy conditions corresponding to the r second resource record spaces, the resource occupancy information corresponding to the target hardware resource is written into the r second resource record spaces respectively to obtain r third resource record spaces.

[0131] The resource occupancy condition refers to the resource occupancy condition corresponding to the j+l+tth instruction execution cycle, and the resource occupancy information corresponding to the target hardware resource is written into the second resource recording space from the j+l+tth instruction execution cycle.

[0132] Indicatively, after the protection adjustment instruction execution cycle, there is no resource conflict between the hardware resources of the j+l+tth instruction and all second resource recording spaces, then the resource occupancy information of the hardware resources of the j+l+tth instruction is recorded in each second resource recording space starting from the adjusted instruction execution cycle.

[0133] Please refer to Figure 10. In response to the hardware resources for instruction B meeting the resource occupancy conditions corresponding to cycle4, the resource occupancy information corresponding to the hardware resources is written into the second resource reservation table 1011 and the second reservation table 1012 to obtain the third resource reservation table 1021 and the third resource reservation table 1022.

[0134] To sum up, the method provided in the embodiment of the present application, when there is a resource conflict between the i+kth compilation instruction and the pth second resource recording space, determines the pth second resource recording space as the conflict recording space, and deletes q conflict recording spaces from r second resource recording spaces after obtaining q conflict recording spaces, clarifies the deletion method of the resource recording space, and ensures that the instruction scheduler has more opportunities to choose when analyzing available instructions, while avoiding additional resource expenditure caused by maintaining too many recording spaces at the same time, thereby improving the efficiency of conflict detection.

[0135] In addition, the method provided in the embodiment of the present application, when there are r conflict recording spaces in r second resource recording spaces, adjusts the i+kth compilation instruction to be executed from the j+l+tth instruction execution cycle, and when the hardware resources of the i+kth compilation instruction meet the resource occupancy conditions corresponding to the j+l+tth instruction execution cycle, writes the resource occupancy information corresponding to the hardware resources into the r second resource recording spaces to obtain r third resource recording spaces, clarifies the processing method when multiple second resource recording spaces are all implemented as conflict recording spaces, and makes the hardware resources that were originally unusable due to the conflict become available in the new execution cycle by adjusting the execution cycle, thereby ensuring that the instruction obtains the required hardware resources and ensuring the smooth execution of the instruction.

[0136] In some embodiments, before creating the first resource record space, it is necessary to obtain a resource description table and parse the resource description table. Please refer to Figure 11, which is a flow chart of a method for obtaining and parsing a resource description table provided by an exemplary embodiment of the present application. The method is described as being performed by the first device. As shown in Figure 11, the following steps are included before the above step 310:

[0137] Step 1110: Obtain resource description space.

[0138] The resource description space is used to store hardware resource information associated with multiple compilation instructions.

[0139] Optionally, the description space can be implemented in various forms such as a table, a log file, a key-value storage structure, etc., which is not limited in the present embodiment. The following mainly describes the description space in a table form as an example.

[0140] Optionally, the resource description table is stored in the memory of the first device. This description will be described using the example of a resource description table stored in the memory of the first device in the form of a structure. The hardware resource information in the resource description table can be stored as a whole in a single structure, or can be stored separately in structures corresponding to multiple compilation instructions.

[0141] Taking the example of hardware resource information in a resource description table being dispersedly stored in structures corresponding to a plurality of compilation instructions, obtaining the resource description table can be implemented by respectively reading the hardware resource information corresponding to the compilation instructions from the plurality of structures. Schematically, each group of hardware resources of each compilation instruction corresponds to a structure, and the structure stores the hardware resource information corresponding to the group of hardware resources. Assuming that the resource description table includes hardware resource information corresponding to compilation instructions A, compilation instructions B, and compilation instructions C, respectively, compilation instruction A corresponds to structure a for storing hardware resource information corresponding to resource group 1, and structure b for storing hardware resource information corresponding to resource group 2, compilation instruction B corresponds to structure c for storing hardware resource information, and compilation instruction C corresponds to structure d for storing hardware resource information, obtaining the resource description table is implemented by reading structures a, b, c, and d from the terminal memory, and reading the hardware resource information corresponding to compilation instructions A, B, and C, respectively, from them.

[0142] In some embodiments, the resource description space includes hardware resource information of the first compilation instruction, and the hardware resource information of the first compilation instruction includes information corresponding to multiple independent groups of hardware resources.

[0143] Optionally, the resource description space is implemented as a resource description table for illustration, and the resource description table may be implemented in at least one of the following ways:

[0144] 1. The resource description table also includes a first segmentation word, which is used to distinguish multiple groups of hardware resources corresponding to the compilation instructions.

[0145] Schematically, the resource description table shown in Figure 4 uses separators to distinguish between resource group 1 (0a, 0b, 0c) and resource group 2 (1a, 1b, 1c) corresponding to instruction A, thereby providing independent and clear descriptions of multiple groups of hardware resources corresponding to a single compilation instruction. The first separator includes, but is not limited to, a comma, semicolon, tab, or a custom string.

[0146] 2. Use a nested data structure to store the resource description table. The resource description table corresponds to multiple storage spaces, and each storage space is used to store a single set of hardware resources corresponding to the compilation instructions.

[0147] Schematically, in this way, the resource description table itself can be a top-level space, which contains multiple subspaces representing different hardware resource groups, and each subspace contains information about the hardware resources of the group. Schematically, please refer to FIG12, which shows another form of a resource description table (the subspace can be understood as the structure described in step 310 above, that is, each group of hardware resources of each compilation instruction corresponds to a structure, and the structure stores the hardware resource information corresponding to the group of hardware resources). As shown in FIG12, in the resource description table 1200, For instruction A, instruction B, and instruction C, instruction A corresponds to subspace 1201 and subspace 1202, subspace 1201 contains information about resource group 1 (0a, 0b, 0c) and subspace 1202 contains information about resource group 2 (1a, 1b, 1c), subspace 1203 corresponding to instruction B contains information about resource group 3 (0a, 0c, 0c), and subspace 1204 corresponding to instruction C contains information about resource group 4 (0b, 0c, 0c), thereby independently and clearly describing multiple groups of hardware resources corresponding to a single compilation instruction. The nested data structure includes, but is not limited to, JSON (JavaScript Object Notation), XML (Extensible Markup Language), and the like.

[0148] It should be noted that the above examples of implementation methods of the resource description table are only illustrative and are not limited to this embodiment of the present application.

[0149] Step 1120: parse the resource description space to obtain multiple time sequence occupancy tables.

[0150] The timing occupancy table is used to indicate the occupancy of the instruction execution cycle by at least one group of hardware resources required to complete the compilation of the instruction.

[0151] Optionally, the timing occupancy table is used to determine the hardware resource occupancy recorded in the first resource recording space. Illustratively, after parsing the resource description space to obtain the timing occupancy table, the occupancy of at least one set of hardware resources used to complete the compilation instruction during the instruction execution cycle in the timing occupancy table is written into the first resource reservation table, thereby obtaining the written first resource reservation table. The written first resource reservation table records the hardware resource occupancy corresponding to the compilation instruction.

[0152] In some embodiments, the compilation instruction corresponds to multiple execution stages, and each set of hardware resources includes hardware resources required by the multiple execution stages. Optionally, taking the compilation instruction including the first compilation instruction as an example for explanation, the above step 1120 also includes the following steps:

[0153] The first step is to create a first timing occupancy table corresponding to the first compilation instruction based on the resource description space.

[0154] The hardware resource information associated with the first compilation instruction is used to indicate multiple groups of hardware resources, and any one of the multiple groups of hardware resources can complete the first compilation instruction.

[0155] In some embodiments, the first timing occupancy table is created as an empty table, and there is a correspondence between the first timing occupancy table and the first compilation instruction.

[0156] Optionally, a single first compilation instruction may correspond to one or more first timing occupancy tables, wherein a single first timing occupancy table includes a group of hardware resources corresponding to the first compilation instruction. Illustratively, the first compilation instruction is read from the resource description space and a first timing occupancy table corresponding to the nth group of hardware resources of the first compilation instruction is created.

[0157] The second step is to read and parse the hardware resource information corresponding to the a-th hardware resource from the resource description space to obtain the resource occupancy information of the a-th hardware resource.

[0158] The ath hardware resource refers to the ath hardware resource in the nth group of hardware resources that can complete the first compilation instruction. The resource occupancy information of the ath hardware resource is used to indicate the occupancy of the instruction execution cycle by the ath hardware resource in the ath execution stage. a and n are positive integers.

[0159] Schematically, the resource occupancy information corresponding to the first hardware resource 0a of the resource group 1 (0a, 0b, 0c) of the first compilation instruction, i.e., instruction A, is read from the resource description table shown in FIG4 and the resource occupancy information is parsed to obtain the occupancy of the instruction execution cycle by the first hardware resource 0a corresponding to instruction A in the first execution stage, i.e., stage 0, where resource 0a occupies 1 cycle and the time interval to the next resource is 1 cycle.

[0160] In the third step, the resource occupancy information of the ath hardware resource is updated into the first timing occupancy table.

[0161] Illustratively, the occupancy status of resource group 1 of instruction A is updated to the timing occupancy table, and the timing occupancy table includes the occupancy status of resources 0a, 0b, and 0c required by instruction A in the instruction execution cycle in multiple execution stages.

[0162] For illustration, please refer to Figure 13, which is a schematic diagram of the timing occupancy table provided by an exemplary embodiment of the present application. As shown in Figure 13, the timing occupancy table 1310 indicates the timing occupancy of resource group 1 corresponding to instruction A during the execution process. Resource 0a occupies the first cycle during the execution process, and the time interval to resource 0b is 1 cycle. Resource 0b occupies the second cycle during the execution process, and the time interval to resource 0c is 1 cycle. Resource 0c occupies the third cycle during the execution process.

[0163] In the fourth step, when the hardware resource information associated with the first compilation instruction is parsed, a timing occupancy table corresponding to the plurality of hardware resource groups of the first compilation instruction is obtained.

[0164] In some embodiments, the resource description space further includes a first segmentation word, and the first segmentation word is used to distinguish the nth group of hardware resources and the (n+1)th group of hardware resources of the first compilation instruction.

[0165] Optionally, when the first segmented word is read and the first compilation instruction corresponds to unparsed hardware resource information, a second timing occupancy table corresponding to the n+1th group of hardware resources is newly created and the second timing occupancy table is updated based on the resource description space until the hardware resource information associated with the first compilation instruction is parsed, and the timing occupancy tables corresponding to multiple groups of hardware resources of the first compilation instruction are obtained.

[0166] Schematically, during the resource parsing process of instruction A, in response to reading the segmented words shown in Figure 4, and instruction A corresponds to an unparsed resource group 2, a new timing occupancy table corresponding to resource group 2 is created and the occupancy status in the timing occupancy table corresponding to resource group 2 is updated based on the resource description table, until the hardware resource parsing of the first compilation instruction is completed, and multiple timing occupancy tables corresponding to the first compilation instruction are obtained.

[0167] In the above embodiment, when the first segmentation word is read and the first compilation instruction corresponds to unparsed hardware resources, a new timing occupancy table is created and the timing occupancy table is updated based on the resource description space until the hardware resource parsing of the first compilation instruction is completed, and multiple timing occupancy tables corresponding to the first compilation instruction are obtained. The first segmentation word helps the first device clearly identify the boundaries between each hardware resource group, ensuring the relative independence and accuracy of each hardware resource group during processing.

[0168] In some embodiments, the resource description space also includes a second segmentation word, and the second segmentation word is used to distinguish the first compilation instruction from the second compilation instruction. The resource parsing process for the compilation instruction also includes: when the second segmentation word is read and the hardware resource information corresponding to the first compilation instruction is parsed, a new third timing occupancy table corresponding to the second compilation instruction is created and the third timing occupancy table is updated based on the resource description space until the multiple compilation instructions in the resource description space are parsed and the timing occupancy tables corresponding to the multiple compilation instructions are obtained.

[0169] The first segmentation word and the second segmentation word may be the same or different.

[0170] It should be noted that the process of updating the second time sequence occupancy table based on the resource description space and the process of updating the first time sequence occupancy table based on the resource description space can refer to the process of updating the first time sequence occupancy table based on the resource description space, which will not be repeated here.

[0171] Schematically, the resource description table shown in FIG4 is used as an example for explanation. Assuming that the resource description table 400 further uses segmentation words to distinguish the hardware resource information of instructions A, B, and C, there is a segmentation word between instructions A and B, and a segmentation word between instructions B and C in the resource description table 400. In response to reading the segmentation word and completing the parsing of the hardware resources corresponding to instruction A, a new timing occupancy table corresponding to instruction B is created, and the occupancy status in the timing occupancy table corresponding to instruction B is updated based on the resource description table. In response to reading the segmentation word and completing the parsing of the hardware resources corresponding to instruction B, a new timing occupancy table corresponding to instruction C is created, and the occupancy status in the timing occupancy table corresponding to instruction C is updated based on the resource description table, until the parsing of instructions A, B, and C in the resource description table 400 is completed, and the timing occupancy tables corresponding to instructions A, B, and C, respectively, are obtained.

[0172] In the above embodiment, when the second segmentation word is read and the hardware resource corresponding to the first compilation instruction is parsed, a third timing occupancy table corresponding to the second compilation instruction is newly created and updated based on the resource description space until the multiple compilation instructions in the resource description space are parsed, thereby obtaining timing occupancy tables corresponding to the multiple compilation instructions. The second segmentation word helps the first device clearly identify the boundaries between the various compilation instructions, ensuring the relative independence and accuracy of each compilation instruction during processing. In addition, the use of segmentation words to distinguish multiple hardware resource groups makes the data structure corresponding to the resource description space relatively simple, which helps reduce storage overhead.

[0173] In other embodiments, the resource description space includes multiple subspaces, each subspace is used to store hardware resource information corresponding to a single group of hardware resources capable of completing the compilation instruction.

[0174] Optionally, the first device parses each hardware resource group sequentially, and the fourth step may also be implemented as follows:

[0175] When the hardware resource information in the subspace corresponding to the nth group of hardware resources is parsed and there is unparsed hardware resource information corresponding to the first compilation instruction, a second timing occupancy table corresponding to the (n+1)th group of hardware resources is created and updated based on the resource description space until the multiple subspaces corresponding to the first compilation instruction are all parsed, thereby obtaining the timing occupancy tables corresponding to the multiple groups of hardware resources of the first compilation instruction.

[0176] Schematically, during the resource parsing process of instruction A, after the parsing of the third hardware resource 0c of resource group 1 (0a, 0b, 0c) of instruction A is completed, a new timing occupancy table corresponding to resource group 2 is created and the occupancy status is updated based on the resource description table, until the multiple resource groups corresponding to the first compilation instruction are parsed, and multiple timing occupancy tables corresponding to the first compilation instruction are obtained.

[0177] When the hardware resource groups respectively corresponding to the plurality of compilation instructions are parsed, the timing occupancy tables respectively corresponding to the plurality of compilation instructions are obtained.

[0178] Schematically, during the resource parsing process for instruction A, instruction B, and instruction C, different resource groups for different instructions are parsed independently. When multiple resource groups corresponding to multiple compilation instructions are parsed, the timing occupancy tables corresponding to instruction A, instruction B, and instruction C can be obtained.

[0179] It should be noted that the first device can also parse each hardware resource group in parallel, which will not be described in detail here.

[0180] In the above embodiment, since each storage space corresponding to the resource description space independently stores a single group of hardware resources, the first device can parse each group of hardware resources sequentially according to the storage space, ensuring the relative independence and accuracy of each hardware resource group during processing. Furthermore, if an error occurs during the parsing process, since each group of hardware resources is stored independently, the problem can be more easily identified, which facilitates rapid error diagnosis and repair, reducing downtime.

[0181] To sum up, the method provided in the embodiment of the present application obtains and parses the resource description space to obtain multiple timing occupancy tables. The timing occupancy tables are used to indicate the occupancy of the instruction execution cycle during the execution process of the compiled instructions, so that the machine can quickly perform conflict detection based on the occupancy status, thereby improving the efficiency of conflict detection.

[0182] Among them, for compilation instructions that include multiple execution stages, the embodiment of the present application can clearly indicate the hardware resources required for each stage of the compilation instruction and their occupancy through the timing occupancy table obtained by parsing. The first device can perform instruction scheduling more accurately, which helps to reduce resource conflicts and waiting time and improve the efficiency of instruction scheduling.

[0183] Schematically, please refer to Figure 14. Figure 14 is a schematic diagram of instruction resource conflict detection provided by an exemplary embodiment of the present application. As shown in Figure 14, instruction resource conflict detection is performed based on the resource description table 400 shown in Figure 4. Assuming that during the instruction scheduling process, instruction C, instruction B, instruction A, instruction A, and instruction C need to be scheduled in order of priority from high to low. The solid rectangular box in the figure is a reservation table, and the dotted rectangular box is used to indicate the instruction execution cycle. The number before the colon in the reservation table is used to identify the instruction execution cycle, and the binary number after the colon is used to indicate the occupied hardware resources, wherein the number marked in underline form before the colon is used to identify the current instruction execution cycle, the number marked in italics after the colon is used to identify the resources occupied by the inserted instruction, and the number marked in bold after the colon is used to identify the conflicting resources. As shown in Figure 14, the resource conflict detection process for scheduling instructions C, instruction B, instruction A, instruction A, and instruction C using the reservation table includes the following steps:

[0184] 1) Create a first resource reservation table 1401 and initialize the reservation table data to 0:000000. Insert the hardware resources required by instruction C from the current instruction execution cycle cycle 0, and occupy hardware resources 0b (000010) in cycle 0, hardware resources 0c (000100) in cycle 1, and hardware resources 0c (000100) in cycle 2, respectively, to obtain an updated first resource reservation table;

[0185] 2) Insert the hardware resources occupied by instruction B from the current instruction execution cycle cycle0. Since the hardware resources 0c occupied by instruction B in cycle1 and cycle2 conflict with the hardware resources occupied by cycle1 and cycle2 in the reservation table, adjust the current instruction execution cycle to cycle1; insert the hardware resources occupied by instruction B from the current instruction execution cycle cycle1. Since the hardware resources 0c occupied by instruction B in cycle2 still conflict with the hardware resources occupied by cycle2 in the first resource reservation table, adjust the current instruction execution cycle to cycle2; insert the hardware resources occupied by instruction B from the current instruction execution cycle cycle2, occupying hardware resources 0a (000001) in cycle2, hardware resources 0c (000100) in cycle3, and hardware resources 0c (000100) in cycle4 respectively;

[0186] 3) Insert the hardware resources required for instruction A from the current instruction execution cycle, cycle 2. Instruction A exists in resource group 1 and resource group 2. Resource conflict detection is performed in descending order of priority, with resource group 1 and resource group 2 as the priority. Since resource 1 corresponding to instruction A conflicts with the first resource reservation table, resource group 2 is used. Hardware resource 1a (001000) is occupied in cycle 2, hardware resource 1b (010000) is occupied in cycle 3, and hardware resource 1c (100000) is occupied in cycle 4.

[0187] 4) Insert the hardware resources required for instruction A from the current instruction execution cycle cycle 2. Since resource 1 and resource group 2 corresponding to instruction A have resource conflicts with the hardware resources in the first resource reservation table from cycle 2 onwards, adjust the current instruction execution cycle to cycle 3; reinsert the hardware resources required for instruction A from the current instruction execution cycle cycle 3. Since resource group 1 and resource group 2 corresponding to instruction A have no resource conflicts with the hardware resources in the first resource reservation table, write the resource occupancy information corresponding to resource group 1 into the first resource reservation table. Cycle 3 occupies hardware resource 0a (000001), cycle 4 occupies hardware resource 0b (000010), cycle 5 occupies hardware resource 0c (000100), and the first second resource reservation table is obtained; the resource occupancy information corresponding to resource group 2 is written into the first resource reservation table, and the hardware resource 1a (001000) is occupied in cycle 3, the hardware resource 1b (010000) is occupied in cycle 4, and the hardware resource 1c (100000) is occupied in cycle 5, and the second second resource reservation table is obtained;

[0188] 5) Insert the hardware resources required for instruction C from the current instruction execution cycle cycle3. Since the resource group 1 corresponding to instruction C has resource conflicts with the hardware resources in the two second resource reservation tables starting from cycle3, the current instruction execution cycle is adjusted to cycle4; reinsert the hardware resources required for instruction C from the current instruction execution cycle cycle4. Since the resource group 1 corresponding to instruction C still has resource conflicts with the hardware resources in the first second resource reservation table starting from cycle4, but does not have resource conflicts with the second second resource reservation table, the first second resource reservation table is determined as the conflicting reservation table and deleted; insert the hardware resources required for instruction C from the current instruction execution cycle cycle4 into the two second resource reservation tables, occupying hardware resources 0b (000010) in cycle5, occupying hardware resources 0c (000100) in cycle6, and occupying hardware resources 0c (000100) in cycle7, to obtain the updated reservation table 1402.

[0189] In the above-mentioned instruction resource conflict detection process, since the mechanism of multiple reservation tables can be introduced for inserting instruction A in step 4, all possible resource occupation schemes are retained. Based on this, when inserting the hardware resources required for instruction C in step 5, since the scheme of completing instruction A with resource group 2 is retained, the pause of one cycle can be reduced. Compared with the resource conflict detection method of a single reservation table shown in Figure 1, it can reduce cycle pauses and improve instruction scheduling efficiency.

[0190] For illustration, please refer to Figure 15, which is a performance comparison table provided by an exemplary embodiment of the present application. As shown in Figure 15, some commonly used operators such as operators 1 to 9 are used, and a single reserved table conflict detection method is used in the instruction scheduling enabled by the AI ​​compiler. The performance brought about by this is different from the conflict detection method of instruction resources provided in the embodiment of the present application. It can be seen from the performance comparison table 1500 that the conflict detection method of instruction resources provided in the embodiment of the present application can reduce the instruction execution cycles consumed in actual application and improve the instruction scheduling efficiency.

[0191] In some embodiments, the conflict detection of instruction resources provided in the embodiments of the present application includes a parsing process of the resource description table. By parsing the resource description table, a timing occupancy table recording the resource occupancy status is obtained. The parsing process is also the above-mentioned steps 1110 and 1120. For the machine, it is necessary to parse each piece of hardware resource information for each compilation instruction in the resource description table until the parsing is completed.

[0192] Schematically, please refer to FIG. 16 , which is a schematic diagram of a parsing process of a resource description table based on segmented words provided by an exemplary embodiment of the present application. Taking the method executed by a terminal as an example, as shown in FIG. 16 , the parsing process for the resource description table includes the following steps:

[0193] Step 1610: Read hardware resource information.

[0194] In some embodiments, for the i-th compilation instruction, hardware description information corresponding to the i-th compilation instruction is obtained from the resource description table. For example, hardware resource information corresponding to instruction A, instruction B, and instruction C is obtained, where the hardware resource information of instruction A includes information about the hardware resources corresponding to resource group 1 and resource group 2, respectively.

[0195] Step 1620: Create a new timing occupancy table corresponding to the instruction.

[0196] Indicatively, a new empty table is created for instruction A as the timing occupancy table corresponding to instruction A.

[0197] Step 1630: Determine whether the hardware resource parsing of the compilation instruction is complete.

[0198] Optionally, in response to the hardware resources in the hardware resource information obtained in step 1610 being parsed completely, the parsing process is ended; or, in response to the hardware resources in the hardware resource information obtained in step 1610 being not parsed completely, step 1640 is executed.

[0199] Step 1640: parse resource occupancy information.

[0200] In some embodiments, parsing the resource occupancy information includes analyzing the binary identifier corresponding to the hardware resource occupied by the instruction, the instruction execution cycle occupied by the hardware resource, the time interval between the hardware resource and the next hardware resource, etc.

[0201] Step 1650: Update the occupancy status to the time series occupancy table.

[0202] Schematically, the resource occupancy information is parsed to obtain the hardware resource occupancy, and the hardware resource occupancy is updated to the timing occupancy table. Please refer to Figure 13. The timing occupancy table 1310 includes the occupancy of the instruction execution cycle by each hardware resource in resource group 1 corresponding to instruction A.

[0203] Step 1660: Determine whether there is a segmented word.

[0204] Optionally, in response to the presence of a segmentation word in the hardware resource information obtained in step 1610, step 1620 is executed; or, in response to the absence of a segmentation word in the hardware resource information obtained in step 1610, step 1630 is executed until the hardware resources in the hardware resource information obtained in step 1610 are parsed and the process is terminated, wherein the segmentation word includes a word used to distinguish multiple hardware resource groups corresponding to the same instruction, for example: resource group 1 and resource group 2 corresponding to instruction A, and is also used to distinguish different instructions, such as instruction A and instruction B.

[0205] Schematically, please refer to FIG. 17 , which is a schematic diagram of a parsing process of a resource description table based on independently stored hardware resource groups provided by an exemplary embodiment of the present application. This method is described by taking the execution of the method by a terminal as an example. As shown in FIG. 17 , the parsing process for the resource description table includes the following steps:

[0206] Step 1710: Read the hardware resource information of the hardware resource group of the compilation instruction.

[0207] In some embodiments, for the i-th compilation instruction, hardware resource information of the hardware resource group corresponding to the i-th compilation instruction is obtained from the resource description table, for example, hardware resource information of resource group 1 of instruction A is obtained.

[0208] Step 1720: Create a new timing occupancy table of the hardware resource group corresponding to the instruction.

[0209] Illustratively, a new empty table is created for resource group 1 of instruction A as the timing occupancy table corresponding to resource group 1 of instruction A.

[0210] Step 1730: Determine whether the hardware resources of the hardware resource group of the compilation instruction have been parsed.

[0211] Optionally, in response to the hardware resource information of the hardware resource group of the compilation instruction obtained in step 1710 not being fully parsed, step 1740 is executed; or, in response to the hardware resource information of the hardware resource group of the compilation instruction obtained in step 1710 being fully parsed, step 1760 is executed.

[0212] Step 1740: parse resource occupancy information.

[0213] Illustratively, the resource occupancy information of the unparsed hardware resources in resource group 1 of instruction A is parsed.

[0214] In some embodiments, parsing the resource occupancy information includes analyzing the binary identifier corresponding to the hardware resource occupied by the instruction, the instruction execution cycle occupied by the hardware resource, the time interval between the hardware resource and the next hardware resource, etc.

[0215] Step 1750: Update the occupancy status to the time series occupancy table.

[0216] Illustratively, after the analysis is completed, the occupancy status is updated to the timing occupancy table. Please refer to FIG. 13 . The timing occupancy table 1310 includes the occupancy status of the resource group 1 corresponding to the instruction A for the instruction execution cycle.

[0217] After executing step 1750 , the process returns to step 1730 to determine whether the hardware resources of the hardware resource group of the compilation instruction have been parsed.

[0218] Step 1760: Determine whether the hardware resources of the compilation instruction have been parsed.

[0219] Optionally, in response to the hardware resources of multiple compilation instructions being parsed, the process ends; in response to the existence of unparsed hardware resource groups, return to step 1710, read the unparsed hardware resource groups, and then repeat steps 1720 to 1750 until the hardware resources of multiple compilation instructions are parsed, and the process ends.

[0220] Schematically, the resource parsing of the resource description table 400 shown in Figure 4 or the resource description table 1200 shown in Figure 12 is used as an example for explanation. Please refer to Figure 18. Figure 18 is a schematic diagram of the timing occupancy table provided by an exemplary embodiment of the present application. As shown in Figure 18, in response to the completion of the parsing of the resource description table, a timing occupancy table 1810 corresponding to instruction A resource group 1, a timing occupancy table 1820 corresponding to instruction A resource group 2, a timing occupancy table 1830 corresponding to instruction B, and a timing occupancy table 1840 corresponding to instruction C are obtained.

[0221] In some embodiments, the resource reservation table is stored in the form of an array. Schematically, the resource reservation table is stored in the form of an array as an example for explanation. In the conflict detection process of the instruction resources provided in the embodiment of the present application, it is necessary to update the array storing the resource reservation table based on the resource conflict situation to update the resource reservation table, so that after the conflict detection is completed, a resource reservation table for recording the hardware resource occupancy of multiple compilation instructions is obtained. The above-mentioned multiple compilation instructions are executed according to the resource reservation table and the corresponding hardware resources are occupied. There will be no resource conflict. Please refer to Figure 19. Figure 19 is a schematic diagram of the resource conflict detection process provided by an exemplary embodiment of the present application. The method can be executed by the terminal, or by the server, or by the terminal and the server together. The embodiment of the present application takes the method executed by the terminal as an example for explanation. As shown in Figure 19, the conflict detection process of the instruction resources includes the following steps:

[0222] Step 1901, initialize the first array storing the resource reservation table, and assign a value of 1 to the current instruction execution cycle.

[0223] In some embodiments, a first array is created for storing a resource reservation table and is initialized to an empty array, and the current instruction execution cycle is initialized to the first cycle.

[0224] Step 1902: Determine whether the target instruction exists.

[0225] In some embodiments, the target instruction refers to a compiled instruction that requires conflict detection.

[0226] Optionally, in response to the existence of the target instruction, step 1903 is executed; or, in response to the absence of the target instruction, the instruction resource conflict detection process is ended.

[0227] Step 1903: Obtain hardware resource information corresponding to the compilation instruction and create a corresponding second array.

[0228] In some embodiments, the second array is used to store the resource reservation table updated during the conflict detection process.

[0229] In some embodiments, the hardware resource information corresponding to the compilation instruction is obtained from the resource description table shown in FIG. 4 .

[0230] Step 1904: determine whether there is a resource reservation table that does not conflict with the resource group of the compilation instruction.

[0231] In some embodiments, the existence of a resource reservation table that does not conflict with the resource group of the compiled instruction means that the existence of the resource reservation table enables the resource group of the compiled instruction to meet the resource occupation condition.

[0232] 7 , regarding the writing process of the hardware resource information of instruction C into the second resource reservation table 711 and the second resource reservation table 712 , the existence of the second resource reservation table 712 ensures that the hardware resources corresponding to instruction C meet the resource occupancy conditions.

[0233] Optionally, in response to the existence of a resource reservation table that does not conflict with the resource group of the compilation instruction, step 1906 is executed; or in response to the absence of a resource reservation table that does not conflict with the resource group of the compilation instruction, step 1905 is executed.

[0234] Step 1905, the current instruction execution cycle is assigned a value plus 1.

[0235] In some embodiments, the current instruction execution cycle is assigned a value plus 1 to indicate that the current instruction execution cycle is adjusted, and the next instruction execution cycle is determined as the current instruction execution cycle.

[0236] Step 1906: Determine whether there is a resource reservation table that has not been conflict-checked.

[0237] In some embodiments, there are multiple resource reservation tables, and each resource group of each compilation instruction needs to be conflict-checked one by one with the multiple resource reservation tables.

[0238] Optionally, in response to the existence of a resource reservation table that has not performed conflict detection, step 1908 is executed; or, in response to the absence of a resource reservation table that has not performed conflict detection, step 1907 is executed.

[0239] Step 1907: Overwrite the first array with the second array.

[0240] In some embodiments, overwriting the first array with the second array refers to updating the storage information of the resource reservation table.

[0241] Step 1908: Determine whether there is a resource group for which conflict detection has not been performed.

[0242] In some embodiments, the compilation instruction corresponds to multiple resource groups, and each resource group needs to be conflict detected.

[0243] Optionally, in response to the existence of a resource group for which conflict detection has not been performed, step 1909 is executed; or, in response to the absence of a resource group for which conflict detection has not been performed, step 1906 is executed.

[0244] Step 1909: Create a resource reservation table* based on the original resource reservation table.

[0245] In some embodiments, the resource occupancy status in the resource reservation table* is consistent with that in the original resource reservation table.

[0246] Step 1910: Determine whether there is a resource conflict between the resource reservation table* and the resource group.

[0247] Optionally, in response to a resource conflict between the resource reservation table* and the resource group, step 1911 is executed; or, in response to a resource conflict between the resource reservation table* and the resource group, step 1912 is executed.

[0248] Step 1911: Abandon the resource reservation table*.

[0249] In some embodiments, discarding the resource reservation table* refers to deleting the resource reservation table*.

[0250] Step 1912: retain the resource reservation table* and update the resource occupancy information corresponding to the resource group into the resource reservation table*.

[0251] 7 , in response to the fact that the hardware resource information of instruction C does not conflict with the second resource reservation table 712 , the hardware resource information of instruction C is written into the second reservation table 712 to obtain a resource reservation table 720 .

[0252] Step 1913: Store the resource reservation table* into the second array.

[0253] In some embodiments, the second array is used to store data contents corresponding to a plurality of resource reservation tables. After executing step 1913, the process returns to step 1908 until there are no more compilation instructions requiring conflict detection, and the process ends.

[0254] FIG20 is a structural block diagram of an instruction resource conflict detection device provided by an exemplary embodiment of the present application. As shown in FIG20 , the device includes the following parts:

[0255] Processing module 2010 is configured to create a first resource recording space, the first resource recording space being configured to record hardware resource usage of a plurality of compilation instructions, the plurality of compilation instructions being respectively associated with hardware resource information, the hardware resource information indicating at least one set of hardware resources used to complete the compilation instructions;

[0256] The processing module 210 is further configured to, if the hardware resource information associated with the i-th compilation instruction indicates that multiple groups of hardware resources meet a resource occupation condition, write the resource occupation information corresponding to the multiple groups of hardware resources into the first resource recording space to obtain second resource recording spaces corresponding to the multiple groups of hardware resources, where i is a positive integer and the resource occupation condition indicates that the hardware resources required to complete the compilation instruction are not occupied.

[0257] The processing module 2010 is further configured to write into a plurality of second resource recording spaces respectively for the (i+k)th compilation instruction, and, if a conflicting recording space exists among the plurality of second resource recording spaces, delete the conflicting recording space from the plurality of second resource recording spaces, wherein the conflicting recording space refers to the second resource recording space that has a resource conflict with the (i+k)th compilation instruction, and the resource conflict refers to resource occupancy information written in the second resource recording space indicating that hardware resources required to complete the (i+k)th compilation instruction have been occupied, where k is a positive integer.

[0258] Please refer to Figure 21. In some embodiments, the processing module 2010 includes: a first processing unit 2011, which is used to write the resource occupancy information corresponding to the mth group of hardware resources into the first resource recording space when the mth group of hardware resources indicated by the hardware resource information associated with the i-th compilation instruction meets the resource occupancy condition, and obtain a second resource recording space corresponding to the mth group of hardware resources, where m is a positive integer; and a second processing unit 2012, which is used to obtain r second resource recording spaces when the i-th compilation instruction is written, where r is used to indicate the number of multiple groups of hardware resources that meet the resource occupancy condition.

[0259] In some embodiments, the i-th compilation instruction starts to execute from the j-th instruction execution cycle, where j is a positive integer; the first processing unit 2011 is further configured to, when the m-th group of hardware resources indicated by the hardware resource information associated with the i-th compilation instruction meets the resource occupancy condition corresponding to the j-th instruction execution cycle, write the resource occupancy information corresponding to the m-th group of hardware resources into the first resource record space from the j-th instruction execution cycle.

[0260] In some embodiments, the processing module 2010 includes: a third processing unit 2013, configured to determine the p-th second resource record space as the conflict record space when there is a resource conflict between the (i + k)-th compilation instruction and the p-th second resource record space; the third processing unit 2013 is configured to obtain q conflict record spaces when traversing through all the second resource record spaces, where p and q are positive integers, and p ≤ q < r; a fourth processing unit 2014, configured to delete the q conflict record spaces from the r second resource record spaces.

[0261] In some embodiments, the i-th compilation instruction starts to execute from the j-th instruction execution cycle, and the (i + k)-th compilation instruction starts to execute from the (j + l)-th instruction execution cycle. The j-th instruction execution cycle to the (j + l)-th instruction execution cycle are used to execute the i-th compilation instruction to the (i + k - 1)-th compilation instruction, where l is a positive integer; the third processing unit 2013 is configured to determine the p-th second resource record space as the conflict record space when there is a resource conflict between the (i + k)-th compilation instruction and the p-th second resource record space starting from the (j + l)-th instruction execution cycle.

[0262] In some embodiments, the processing module 2010 is further configured to, for the process of writing the (i + k)-th compilation instruction into the r second resource record spaces respectively, when there are r conflict record spaces in the r second resource record spaces, adjust the (i + k)-th compilation instruction to start executing from the (j + l + t)-th instruction execution cycle, where t is a positive integer; wherein, the j-th instruction execution cycle to the (j + l + t)-th instruction execution cycle are used to execute the i-th compilation instruction to the (i + k - 1)-th compilation instruction.

[0263] In some embodiments, the processing module 2010 is also used for the process of writing the r second resource recording spaces respectively for the i+kth compilation instruction. When the hardware resource information associated with the i+kth compilation instruction indicates that the target hardware resource meets the resource occupancy conditions corresponding to the r second resource recording spaces respectively, the resource occupancy information corresponding to the target hardware resource is written into the r second resource recording spaces respectively to obtain r third resource recording spaces; wherein the resource occupancy condition refers to the resource occupancy condition corresponding to the j+l+tth instruction execution cycle, and the resource occupancy information corresponding to the target hardware resource is written into the second resource recording space from the j+l+tth instruction execution cycle.

[0264] In some embodiments, the apparatus further comprises:

[0265] The acquisition module 2020 is used to obtain a resource description space, which is used to store the hardware resource information associated with the multiple compilation instructions respectively; the processing module 2010 is also used to parse the resource description space to obtain multiple timing occupancy tables, which are used to indicate the occupancy of the instruction execution cycle by at least one group of hardware resources required to complete the compilation instructions.

[0266] In some embodiments, the compilation instruction corresponds to multiple execution stages, and each group of hardware resources includes the hardware resources required by the multiple execution stages. The processing module 2010 is further used to: create a first timing occupancy table corresponding to the first compilation instruction based on the resource description space, where the hardware resource information associated with the first compilation instruction is used to indicate multiple groups of hardware resources, and any one of the multiple groups of hardware resources can complete the first compilation instruction; read and parse the hardware resource information corresponding to the a-th hardware resource from the resource description space to obtain resource occupancy information of the a-th hardware resource, where the a-th hardware resource refers to the a-th hardware resource in the n-th group of hardware resources that can complete the first compilation instruction, and the resource occupancy information of the a-th hardware resource is used to indicate the occupancy of the instruction execution cycle by the a-th hardware resource in the a-th execution stage, where a and n are positive integers; update the resource occupancy information of the a-th hardware resource into the first timing occupancy table; and when the hardware resource information associated with the first compilation instruction is parsed, obtain the timing occupancy tables corresponding to the multiple groups of hardware resources of the first compilation instruction.

[0267] In some embodiments, the resource description space also includes a first segmentation word, which is used to distinguish the nth group of hardware resources and the n+1th group of hardware resources of the first compilation instruction; the processing module 2010 is also used to create a second timing occupancy table corresponding to the n+1th group of hardware resources when the first segmentation word is read and the first compilation instruction corresponds to unparsed hardware resource information, and update the second timing occupancy table based on the resource description space until the hardware resource information associated with the first compilation instruction is parsed, and the timing occupancy tables corresponding to multiple groups of hardware resources of the first compilation instruction are obtained.

[0268] In some embodiments, the resource description space also includes a second segmentation word, which is used to distinguish the first compilation instruction from the second compilation instruction; the processing module 2010 is further used to create a third timing occupancy table corresponding to the second compilation instruction and update the third timing occupancy table based on the resource description space when the second segmentation word is read and the hardware resource information corresponding to the first compilation instruction is parsed, until the multiple compilation instructions in the resource description space are parsed and the timing occupancy tables corresponding to the multiple compilation instructions are obtained.

[0269] In some embodiments, the resource description space includes multiple subspaces, each subspace is used to store hardware resource information corresponding to a single group of hardware resources that can complete the compilation instruction; the processing module 2010 is also used to create a second timing occupancy table corresponding to the n+1th group of hardware resources and update the second timing occupancy table based on the resource description space when the hardware resource information in the subspace corresponding to the nth group of hardware resources is parsed and there is unparsed hardware resource information corresponding to the first compilation instruction, until the multiple subspaces corresponding to the first compilation instruction are all parsed, and the timing occupancy tables corresponding to the multiple groups of hardware resources of the first compilation instruction are obtained.

[0270] In some embodiments, the processing module 2010 is further used to: when at least one group of hardware resources capable of completing the compilation instruction meets the resource occupancy condition corresponding to the current instruction execution cycle, write the resource occupancy information corresponding to the at least one group of hardware resources from the current instruction execution cycle into the first resource recording space to obtain a fourth resource recording space; when at least one group of hardware resources capable of completing the compilation instruction does not meet the resource occupancy condition corresponding to the current instruction execution cycle, update the next instruction execution cycle of the current instruction execution cycle to the current instruction execution cycle, until at least one group of hardware resources capable of completing the compilation instruction meets the resource occupancy condition corresponding to the current instruction execution cycle, write the resource occupancy information corresponding to the at least one group of hardware resources from the current instruction execution cycle into the first resource recording space to obtain a fifth resource recording space.

[0271] It should be noted that the conflict detection device for instruction resources provided in the above embodiment is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0272] Figure 22 shows a block diagram of a terminal 2200 according to an exemplary embodiment of the present application. Terminal 2200 may be a smartphone, tablet computer, MP3 player, MP4 player, laptop computer, or desktop computer. Terminal 2200 may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other similar names.

[0273] Typically, the terminal 2200 includes: a processor 2201 and a memory 2202. The processor 2201 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. The processor 2201 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 2201 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 2201 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 2201 may also include an artificial intelligence (AI) processor, which is used to handle computing operations related to machine learning. The memory 2202 may include one or more computer-readable storage media, which may be non-transitory. The memory 2202 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 2202 is used to store at least one instruction, which is used to be executed by the processor 2201 to implement the instruction resource conflict detection method provided in the method embodiment of the present application.

[0274] In some embodiments, the terminal 2200 further includes other components 2203, and the type and quantity of the other components 2203 can be selected based on the functional requirements of the terminal 2200. It will be understood by those skilled in the art that the structure shown in FIG22 does not constitute a limitation on the terminal 2200, and may include more or fewer components than shown, or combine certain components, or adopt a different component arrangement. An embodiment of the present application also provides a computer device, which can be implemented as a terminal or server as shown in FIG1. ​​The computer device includes a processor and a memory, and the memory stores at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by the processor to implement the instruction resource conflict detection method provided by the above-mentioned method embodiments. An embodiment of the present application also provides a computer-readable storage medium, on which is stored at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by the processor to implement the instruction resource conflict detection method provided by the above-mentioned method embodiments. The embodiments of the present application also provide a computer program product or computer program, which includes computer instructions, which are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions so that the computer device executes the conflict detection method for instruction resources provided by the above-mentioned method embodiments. Optionally, the computer-readable storage medium may include: read-only memory (ROM), random access memory (RAM), solid-state drive (SSD) or optical disk, etc. Among them, random access memory may include resistance random access memory (ReRAM) and dynamic random access memory (DRAM). The above-mentioned serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments. Those of ordinary skill in the art will understand that all or part of the steps of implementing the above-mentioned embodiments can be completed by hardware, or can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a disk or an optical disk, etc. The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for detecting conflict of instruction resources, executed by a first device, the method comprising: Creating a first resource recording space, the first resource recording space is used to record the hardware resource occupation of a plurality of compilation instructions, the plurality of compilation instructions are respectively associated with hardware resource information, the hardware resource information indicates at least one group of hardware resources used to complete the compilation instructions; When the hardware resource information associated with the i-th compilation instruction indicates that multiple groups of hardware resources meet the resource occupation condition, the resource occupation information corresponding to the multiple groups of hardware resources are written into the first resource recording space to obtain the second resource recording space corresponding to the multiple groups of hardware resources, i is a positive integer, and the resource occupation condition is used to indicate that the hardware resources required to complete the compilation instruction are not occupied; A process of writing a plurality of second resource record spaces respectively for an i+k-th compilation instruction, wherein, when a conflicting record space exists in the plurality of second resource record spaces, the conflicting record space is deleted from the plurality of second resource record spaces, wherein the conflicting record space refers to the second resource record space having a resource conflict with the i+k-th compilation instruction, wherein the resource conflict refers to resource occupancy information written in the second resource record space indicating that the hardware resources required to complete the i+k-th compilation instruction have been occupied, and k is a positive integer.

2. The method according to claim 1, wherein: When the hardware resource information associated with the i-th compilation instruction indicates that the multiple groups of hardware resources meet the resource occupation condition, the resource occupation information corresponding to the multiple groups of hardware resources are written into the first resource recording space to obtain the second resource recording space corresponding to the multiple groups of hardware resources, including: When the mth group of hardware resources indicated by the hardware resource information associated with the i-th compilation instruction meets the resource occupation condition, writing the resource occupation information corresponding to the mth group of hardware resources into the first resource recording space to obtain a second resource recording space corresponding to the mth group of hardware resources, where m is a positive integer; When the writing of the i-th compilation instruction is completed, r second resource recording spaces are obtained, where r is used to indicate the number of multiple groups of hardware resources that meet the resource occupation condition.

3. The method according to claim 1 or 2, wherein: The i-th compilation instruction is executed starting from the j-th instruction execution cycle, where j is a positive integer; when the m-th group of hardware resources indicated by the hardware resource information associated with the i-th compilation instruction meets the resource occupancy condition, the resource occupancy information corresponding to the m-th group of hardware resources is written into the first resource recording space, including: when the m-th group of hardware resources indicated by the hardware resource information associated with the i-th compilation instruction meets the resource occupancy condition corresponding to the j-th instruction execution cycle, the resource occupancy information corresponding to the m-th group of hardware resources is written into the first resource recording space from the j-th instruction execution cycle.

4. The method according to any one of claims 1 to 3, wherein: In the case where there is a conflicting record space in the plurality of second resource record spaces, deleting the conflicting record space from the plurality of second resource record spaces comprises: In the case where the resource conflict exists between the i+kth compilation instruction and the pth second resource record space, the pth second resource record space is determined as the conflict record space; when the traversal of the plurality of second resource record spaces is completed, q conflict record spaces are obtained, where p and q are positive integers and p≤q <r; The q conflicting record spaces are deleted from the r second resource record spaces.

5. The method according to any one of claims 1 to 4, wherein: The i-th compilation instruction is executed from the j-th instruction execution cycle, the i+k-th compilation instruction is executed from the j+l-th instruction execution cycle, and the j-th instruction execution cycle to the j+l-th instruction execution cycle are used to execute the i-th compilation instruction to the i+k-1-th compilation instruction, where l is a positive integer; in the case where the i+k-th compilation instruction has the resource conflict with the p-th second resource record space, determining the p-th second resource record space as the conflict record space, comprising: In the case that the i+kth compilation instruction has the resource conflict with the pth second resource recording space since the j+lth instruction execution cycle, the pth second resource recording space is determined as the conflict recording space.

6. The method according to any one of claims 1 to 5, wherein: The method further comprises: In the process of writing the i+kth compilation instruction into the r second resource recording spaces respectively, when there are r conflicting recording spaces in the r second resource recording spaces, adjusting the i+kth compilation instruction from the j+l+tth instruction Let the execution cycle start execution, t is a positive integer; wherein the jth instruction execution cycle to the j+l+tth instruction execution cycle are used to execute the ith compiled instruction to the i+k-1th compiled instruction.

7. The method according to any one of claims 1 to 6, wherein: The method also includes: for the process of writing the i+kth compilation instruction into the r second resource recording spaces respectively, when the hardware resource information associated with the i+kth compilation instruction indicates that the target hardware resource meets the resource occupancy conditions corresponding to the r second resource recording spaces respectively, the resource occupancy information corresponding to the target hardware resource is written into the r second resource recording spaces respectively to obtain r third resource recording spaces; wherein the resource occupancy condition refers to the resource occupancy condition corresponding to the j+l+tth instruction execution cycle, and the resource occupancy information corresponding to the target hardware resource is written into the second resource recording space from the j+l+tth instruction execution cycle.

8. The method according to any one of claims 1 to 7, wherein: Before creating the first resource record space, the method further includes: Acquire a resource description space, wherein the resource description space is used to store hardware resource information respectively associated with the multiple compilation instructions; parse the resource description space to obtain multiple timing occupancy tables, wherein the timing occupancy tables are used to indicate the occupancy of the instruction execution cycle by at least one group of hardware resources required to complete the compilation instructions.

9. The method according to any one of claims 1 to 8, wherein: The compilation instruction corresponds to a plurality of execution stages, and each set of hardware resources includes the hardware resources required by each of the plurality of execution stages; The resource description space is parsed to obtain a plurality of time sequence occupancy tables, including: Based on the resource description space, creating a first timing occupancy table corresponding to a first compilation instruction, wherein the hardware resource information associated with the first compilation instruction is used to indicate a plurality of groups of hardware resources, and any one group of hardware resources among the plurality of groups of hardware resources can complete the first compilation instruction; Read and parse the hardware resource information corresponding to the ath hardware resource from the resource description space to obtain resource occupancy information of the ath hardware resource, wherein the ath hardware resource refers to the ath hardware resource in the nth group of hardware resources that can complete the first compiled instruction, and the resource occupancy information of the ath hardware resource is used to indicate the occupancy of the ath hardware resource for the instruction execution cycle in the ath execution stage, where a and n are positive integers; Updating the resource occupancy information of the ath hardware resource into the first timing occupancy table; When the hardware resource information associated with the first compilation instruction is parsed, a timing occupancy table corresponding to the plurality of groups of hardware resources of the first compilation instruction is obtained.

10. The method according to any one of claims 1 to 9, wherein: The resource description space also includes a first segmentation word, and the first segmentation word is used to distinguish the nth group of hardware resources and the n+1th group of hardware resources of the first compilation instruction; The method of obtaining, when the hardware resource information associated with the first compilation instruction is parsed, timing occupancy tables respectively corresponding to the multiple groups of hardware resources of the first compilation instruction comprises: when the first segmentation word is read and the first compilation instruction corresponds to unparsed hardware resource information, creating a second timing occupancy table corresponding to the n+1th group of hardware resources and updating the second timing occupancy table based on the resource description space, until the hardware resource information associated with the first compilation instruction is parsed, and obtaining timing occupancy tables respectively corresponding to the multiple groups of hardware resources of the first compilation instruction.

11. The method according to any one of claims 1 to 10, wherein: The resource description space also includes a second segmentation word, and the second segmentation word is used to distinguish the first compilation instruction from the second compilation instruction; the method also includes: When the second segmented word is read and the hardware resource information corresponding to the first compilation instruction is parsed, a third timing occupancy table corresponding to the second compilation instruction is newly created and the third timing occupancy table is updated based on the resource description space until the multiple compilation instructions in the resource description space are parsed and the timing occupancy tables corresponding to the multiple compilation instructions are obtained.

12. The method according to any one of claims 1 to 11, wherein: The resource description space includes a plurality of subspaces, each subspace being used to store hardware resource information corresponding to a single set of hardware resources capable of completing the compilation instruction; When the hardware resource information associated with the first compilation instruction is parsed, obtaining a timing occupancy table corresponding to a plurality of groups of hardware resources of the first compilation instruction respectively includes: When the hardware resource information in the subspace corresponding to the nth group of hardware resources is parsed and the first compilation instruction corresponds to unparsed hardware resource information, a second timing occupancy table corresponding to the n+1th group of hardware resources is newly created. The second timing occupancy table is updated based on the resource description space until the multiple subspaces corresponding to the first compilation instruction are parsed, thereby obtaining the timing occupancy tables corresponding to the multiple groups of hardware resources of the first compilation instruction.

13. The method according to any one of claims 1 to 12, wherein: The method also includes: when at least one group of hardware resources capable of completing the compilation instruction meets the resource occupancy condition corresponding to the current instruction execution cycle, writing the resource occupancy information corresponding to the at least one group of hardware resources from the current instruction execution cycle into the first resource recording space to obtain a fourth resource recording space; when at least one group of hardware resources capable of completing the compilation instruction does not meet the resource occupancy condition corresponding to the current instruction execution cycle, updating the next instruction execution cycle of the current instruction execution cycle to the current instruction execution cycle, until at least one group of hardware resources capable of completing the compilation instruction meets the resource occupancy condition corresponding to the current instruction execution cycle, writing the resource occupancy information corresponding to the at least one group of hardware resources from the current instruction execution cycle into the first resource recording space to obtain a fifth resource recording space.

14. A conflict detection device for instruction resources, the device comprising: A processing module, configured to create a first resource recording space, wherein the first resource recording space is used to record hardware resource occupancy of a plurality of compilation instructions, wherein the plurality of compilation instructions are respectively associated with hardware resource information, and the hardware resource information indicates at least one group of hardware resources used to complete the compilation instructions; The processing module is further configured to, when the hardware resource information associated with the i-th compilation instruction indicates that the multiple groups of hardware resources meet the resource occupation condition, write the resource occupation information corresponding to the multiple groups of hardware resources respectively into the first resource recording space to obtain the second resource recording spaces corresponding to the multiple groups of hardware resources respectively, i is a positive integer, and the resource occupation condition is used to indicate that the hardware resources required to complete the compilation instruction are not occupied; The processing module is further used for a process of writing a plurality of second resource record spaces respectively for the i+kth compilation instruction, and in the case where a conflicting record space exists in the plurality of second resource record spaces, deleting the conflicting record space from the plurality of second resource record spaces, wherein the conflicting record space refers to the second resource record space having a resource conflict with the i+kth compilation instruction, and the resource conflict refers to resource occupancy information written in the second resource record space indicating that the hardware resources required to complete the i+kth compilation instruction have been occupied, and k is a positive integer.

15. The device according to claim 14, wherein: The processing module comprises: a first processing unit, configured to, if the mth group of hardware resources indicated by the hardware resource information associated with the i-th compilation instruction meets the resource occupation condition, write the resource occupation information corresponding to the mth group of hardware resources into the first resource recording space, and obtain a second resource recording space corresponding to the mth group of hardware resources, where m is a positive integer; The second processing unit is used to obtain r second resource recording spaces when the i-th compilation instruction is written, where r is used to indicate the number of multiple groups of hardware resources that meet the resource occupation condition.

16. The device according to claim 14 or 15, wherein: The i-th compilation instruction is executed from the j-th instruction execution cycle, where j is a positive integer; The first processing unit is also used to write the resource occupancy information corresponding to the mth group of hardware resources from the jth instruction execution cycle into the first resource recording space when the mth group of hardware resources indicated by the hardware resource information associated with the i-th compilation instruction meets the resource occupancy condition corresponding to the j-th instruction execution cycle.

17. A chip, comprising a processor and a memory, wherein the memory stores a computer program, and the computer program is loaded and executed by the processor to implement the instruction resource conflict detection method according to any one of claims 1 to 13.

18. A computer device, comprising a processor and a memory, wherein the memory stores at least one program, and the at least one program is loaded and executed by the processor to implement the instruction resource conflict detection method according to any one of claims 1 to 13.

19. A computer-readable storage medium, wherein at least one program is stored in the storage medium, and the at least one program is loaded and executed by a processor to implement the instruction resource conflict detection method according to any one of claims 1 to 13.

20. A computer program product, comprising a computer program, wherein the computer program is stored in a computer-readable storage medium, and a processor obtains the computer program from the computer-readable storage medium, so that the processor loads and executes the computer program to implement the instruction resource conflict detection method as described in any one of claims 1 to 13.

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