Train-signal processing method, system and device

Abstract

A train-signal processing method, system and device, which are applied to the technical field of rail transit. A master processor is in communication connection with a slave processor, and a first hardware device sends a time-synchronization hard wire signal to the master processor and the slave processor at the same time. When applied to the master processor, the train-signal processing method comprises: determining whether first collected data received by means of a first input channel is consistent with second collected data sent by a slave processor; if not, entering a fail-safe state; and if so, executing a data processing operation, so as to obtain a first processing result and execute same, wherein the first collected data and the second collected data are respectively data of a target position which is collected by the master processor at a first moment and data of the target position which is collected by the slave processor at the first moment. By means of applying the solution of the present application, the reliability of a train-signal processing process is guaranteed by means of providing a master processor and a slave processor, and time synchronization of the master processor and the slave processor is realized by means of a time-synchronization hard wire signal, thereby saving on a response time in the train-signal processing process.

Description

Train signal processing method, system and device

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on September 15, 2023, with application number 2023112001856 and invention name “A method, system and device for processing train signals”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of rail transit technology, and in particular to a method, system and device for processing train signals. Background Art

[0003] As rail transit becomes increasingly intelligent, some critical safety hardware components, such as safety relays, are being replaced by LCUs (Logical Control Units) that offer a wider range of functions and possess a high level of functional safety. However, in some scenarios, higher system safety requirements are imposed. Therefore, to maintain the original hardware characteristics, these LCUs also place very high demands on real-time performance. Specifically, the response time of the control input and output signals of these LCUs must be less than or equal to the opening and closing time of the safety relays.

[0004] In summary, how to shorten the response time of train signal processing and enable the equipment to replace the train's key safety hard-wired signals while ensuring system safety is a technical problem that technical personnel in this field urgently need to solve.

[0005] Summary of the Invention

[0006] The purpose of the present invention is to provide a train signal processing method, system and equipment to shorten the response time of train signal processing and enable the equipment to replace the train's key safety hard-wired signals while ensuring system safety.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] A train signal processing method is applied to a master processor, wherein the master processor is communicatively connected to a slave processor, and a first hardware device is used to simultaneously send a time synchronization hardwire signal to the master processor and the slave processor to synchronize the time of the master processor and the slave processor. The train signal processing method includes:

[0009] receiving first collected data through its own first input channel;

[0010] sending the first collected data to the slave processor, and receiving second collected data sent by the slave processor;

[0011] Determining whether the first collected data is consistent with the second collected data;

[0012] If not, entering a safety-oriented state so that each output channel of the main processor outputs a preset safety level;

[0013] If yes, performing a preset data processing operation on the first collected data to obtain a first processing result corresponding to the first collected data;

[0014] executing the first processing result;

[0015] The first collected data is the data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is the data of the target position collected by the slave processor through the second collection circuit at the first moment.

[0016] In one embodiment, it further includes:

[0017] Whenever a time synchronization hard-wire signal sent by the first hardware device is received, verifying whether a period of the time synchronization hard-wire signal is equal to a set acquisition period by a first timer set in the main processor;

[0018] If not, the system enters a safety-oriented state so that each output channel of the main processor outputs a preset safety level.

[0019] In one embodiment, sending the first collected data to the slave processor and receiving the second collected data sent by the slave processor includes:

[0020] sending a first request command carrying the first collected data and attribute information of the first collected data to the slave processor;

[0021] A first response command carrying the second collected data and attribute information of the second collected data is received, which is sent by the slave processor.

[0022] In one implementation, the first hardware device is specifically a CPLD.

[0023] In one embodiment, the master processor and the slave processor are communicatively connected using wired communication and / or wireless communication.

[0024] In one embodiment, it further includes:

[0025] After power-on, obtaining a value of its own acquisition period, and receiving a value of the acquisition period of the slave processor sent by the slave processor;

[0026] Determine whether the value of its own acquisition period is consistent with the value of the acquisition period of the slave processor;

[0027] If not, entering a safety-oriented state so that each output channel of the main processor outputs a preset safety level;

[0028] If yes, the first hardware device is enabled and commanded to send a time synchronization hard-wire signal to the master processor and the slave processor simultaneously according to the acquisition cycle.

[0029] In one embodiment, after obtaining the first processing result corresponding to the first collected data, the method further includes:

[0030] receiving a second processing result sent by the slave processor;

[0031] Determining whether the first processing result is consistent with the second processing result;

[0032] If not, entering a safety-oriented state so that each output channel of the main processor outputs a preset safety level;

[0033] If yes, execute the first processing result;

[0034] The second processing result is a second processing result corresponding to the second collected data obtained after the slave processor performs a preset data processing operation on the second collected data.

[0035] In one embodiment, executing the first processing result includes:

[0036] Based on the first processing result, controlling the level state of the first output channel thereof;

[0037] Among them, the first output channel of the master processor is connected to the first input end of the first AND gate circuit, and the first output channel of the slave processor is connected to the second input end of the first AND gate circuit; the level state of the first output channel of the slave processor is the level state determined by the slave processor based on the second processing result.

[0038] A train signal processing method is applied to a slave processor, wherein a master processor is communicatively connected to the slave processor, and a first hardware device is used to simultaneously send a time synchronization hardwire signal to the master processor and the slave processor to synchronize the time of the master processor and the slave processor. The train signal processing method includes:

[0039] receiving the second collected data through its own first input channel;

[0040] receiving the first collected data sent by the main processor, and sending the second collected data to the main processor;

[0041] Determining whether the first collected data is consistent with the second collected data;

[0042] If not, entering a safety-oriented state so that each output channel of the slave processor outputs a preset safety level;

[0043] If yes, performing a preset data processing operation on the second collected data to obtain a second processing result corresponding to the second collected data;

[0044] executing the second processing result;

[0045] The first collected data is the data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is the data of the target position collected by the slave processor through the second collection circuit at the first moment.

[0046] In one embodiment, it further includes:

[0047] Whenever a time synchronization hard-wire signal sent by the first hardware device is received, verifying whether a period of the time synchronization hard-wire signal is equal to a set acquisition period by a second timer set in the slave processor;

[0048] If not, the system enters a safety-oriented state so that each output channel of the slave processor outputs a preset safety level.

[0049] In one embodiment, receiving the first collected data sent by the main processor and sending the second collected data to the main processor includes:

[0050] receiving a first request command sent by the main processor and carrying the first collected data and attribute information of the first collected data;

[0051] A first response command carrying the second collected data and attribute information of the second collected data is sent to the main processor.

[0052] In one embodiment, it further includes:

[0053] After power-on, obtaining the value of its own acquisition period and sending it to the main processor, and receiving the value of the acquisition period of the main processor sent by the main processor;

[0054] Determine whether the value of its own acquisition period is consistent with the value of the acquisition period of the main processor;

[0055] If not, the system enters a safety-oriented state so that each output channel of the slave processor outputs a preset safety level.

[0056] In one embodiment, after obtaining the second processing result corresponding to the second collected data, the method further includes:

[0057] receiving a first processing result sent by the main processor;

[0058] Determining whether the first processing result is consistent with the second processing result;

[0059] If not, entering a safety-oriented state so that each output channel of the slave processor outputs a preset safety level;

[0060] If yes, execute the second processing result;

[0061] The first processing result is a first processing result corresponding to the first collected data obtained after the slave processor performs a preset data processing operation on the first collected data.

[0062] In one embodiment, executing the second processing result includes:

[0063] Based on the second processing result, controlling the level state of the first output channel thereof;

[0064] Among them, the first output channel of the main processor is connected to the first input end of the first AND gate circuit, and the first output channel of the slave processor is connected to the second input end of the first AND gate circuit; the level state of the first output channel of the main processor is the level state determined by the main processor based on the first processing result.

[0065] A train signal processing system is applied to a master processor, wherein the master processor is communicatively connected to a slave processor, and a first hardware device is used to simultaneously send a time synchronization hardwire signal to the master processor and the slave processor to synchronize the time of the master processor and the slave processor. The train signal processing system includes:

[0066] A first collected data receiving module is used to receive first collected data through its own first input channel;

[0067] a first synchronization module, configured to send the first collected data to the slave processor and receive second collected data sent by the slave processor;

[0068] A first judging module, configured to judge whether the first collected data is consistent with the second collected data;

[0069] If not, triggering a first guidance safety module, wherein the first guidance safety module is configured to: enter a guidance safety state so that each output channel of the main processor outputs a preset safety level;

[0070] If yes, triggering a first processing result determination module, the first processing result determination module is configured to: perform a preset data processing operation on the first collected data to obtain a first processing result corresponding to the first collected data;

[0071] A first processing result execution module, configured to execute the first processing result;

[0072] The first collected data is the data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is the data of the target position collected by the slave processor through the second collection circuit at the first moment.

[0073] A train signal processing system is applied to a slave processor, wherein a master processor is communicatively connected to the slave processor, and a first hardware device is used to simultaneously send a time synchronization hard-wire signal to the master processor and the slave processor to synchronize the time of the master processor and the slave processor. The train signal processing method includes:

[0074] A second collected data receiving module is used to receive the second collected data through its own first input channel;

[0075] a second synchronization module, configured to receive the first collected data sent by the main processor, and send the second collected data to the main processor;

[0076] A second judgment module is used to judge whether the first collected data is consistent with the second collected data;

[0077] If not, triggering a second guidance safety module, the second guidance safety module is used to: enter a guidance safety state so that each output channel of the slave processor outputs a preset safety level;

[0078] If yes, triggering a second processing result determination module, the second processing result determination module is configured to: perform a preset data processing operation on the second collected data to obtain a second processing result corresponding to the second collected data;

[0079] A second processing result execution module, configured to execute the second processing result;

[0080] The first collected data is the data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is the data of the target position collected by the slave processor through the second collection circuit at the first moment.

[0081] A train signal processing device, comprising:

[0082] memory for storing computer programs;

[0083] A processor is used to execute the computer program to implement the steps of the train signal processing method as described above.

[0084] By applying the technical solution provided in the embodiment of the present invention, the LCU is implemented based on the master processor and the slave processor. Data processing is performed only when the collected data of the two are consistent, thereby ensuring system security. In addition, in order to reduce response time, in the solution of the present application, time synchronization between the master processor and the slave processor is not achieved directly through communication between the two. Instead, a first hardware device is specially set up. The first hardware device can simultaneously send a time synchronization hard-wire signal to the master processor and the slave processor, thereby performing time synchronization between the master processor and the slave processor. Since the time synchronization between the master processor and the slave processor is achieved based on the time synchronization hard-wire signal, the time synchronization between the master processor and the slave processor can be achieved quickly, which saves the response time of the master processor in the train signal processing process.

[0085] When processing train signals, the main processor can receive first collected data through its own first input channel, then send the first collected data to the slave processor and receive second collected data sent by the slave processor. The first collected data is the data of the target position collected by the main processor through the first acquisition circuit at the first moment, and the second collected data is the data of the target position collected by the slave processor through the second acquisition circuit at the first moment. Therefore, under normal circumstances, the main processor will determine that the first collected data is consistent with the second collected data, and then perform a preset data processing operation on the first collected data to obtain a first processing result corresponding to the first collected data, and then execute the first processing result. If the first collected data is inconsistent with the second collected data, it means that an abnormal situation has occurred. In order to ensure system safety, the main processor can enter a safety-oriented state so that each output channel of the main processor outputs a preset safety level.

[0086] To sum up, the solution of the present application ensures the security and reliability of the train signal processing process through the setting of the main processor and the slave processor, and since the time synchronization of the main processor and the slave processor is achieved through the time synchronization hard-wired signal sent by the first hardware device, the time synchronization process can be implemented quickly, which saves the response time of the main processor in the train signal processing process. That is, under the premise of ensuring the safety of the system, the device composed of the main processor and the slave processor of the present application has the ability to replace the original key safety hard-wired signal of the train. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0088] FIG1 is a flow chart of an implementation method for processing train signals in the present invention, which is applied in a main processor;

[0089] FIG2 is a schematic diagram showing a structure in which a first hardware device simultaneously sends a time synchronization hard-wire signal to a master processor and a slave processor in a specific embodiment of the present invention;

[0090] FIG3 is a schematic diagram of data interaction between a master processor and a slave processor when processing train signals in a specific embodiment of the present invention;

[0091] FIG4 is a flow chart of an implementation method for processing train signals in the present invention, which is applied to a slave processor;

[0092] FIG5 is a schematic diagram of the structure of a train signal processing system according to the present invention, which is applied to a main processor;

[0093] FIG6 is a schematic diagram of the structure of a train signal processing system in the present invention, which is applied to a slave processor. DETAILED DESCRIPTION

[0094] The core of the present invention is to provide a method for processing train signals. Through the setting of the main processor and the slave processor, the security and reliability of the train signal processing process are guaranteed. Moreover, since the time synchronization of the main processor and the slave processor is achieved through the time synchronization hard-wire signal sent by the first hardware device, the time synchronization process can be implemented quickly, which saves the response time of the main processor in the train signal processing process. That is, under the premise of ensuring the safety of the system, the device composed of the main processor and the slave processor of this application has the ability to replace the original key safety hard-wire signal of the train.

[0095] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0096] Please refer to FIG1 , which is a flowchart of an implementation of a train signal processing method according to the present invention. The train signal processing method can be applied to a master processor, wherein the master processor is communicatively connected to a slave processor, and a first hardware device is used to simultaneously send a time synchronization hardwire signal to the master processor and the slave processor to synchronize the time of the master processor and the slave processor. The train signal processing method can include the following steps:

[0097] Step S101: receiving first collected data through its own first input channel.

[0098] Specifically, in the solution of the present application, the LCU is implemented based on the master processor and the slave processor, which can ensure the reliability of the system. That is, when processing train signals, the master processor and the slave processor can verify data consistency in multiple links to ensure reliability. Please see the detailed description in the implementation method below.

[0099] In practical applications, a MCU (Micro Controller Unit) can usually be used as a processor. For example, in FIG2 , MCUA represents the master processor of the present application, and MCUB represents the slave processor of the present application.

[0100] The solution of the present application is also specially provided with a first hardware device, which is used to send a time synchronization hard-wire signal to the master processor and the slave processor at the same time, thereby achieving time synchronization between the master processor and the slave processor based on the time synchronization hard-wire signal. It can be seen that in the solution of the present application, since the first hardware device is introduced between the two processors and the time synchronization hard-wire signal is sent by the first hardware device, compared with the two processors achieving time synchronization through communication, the time synchronization of the present application will take a very short time, which will save the response time of the master processor when performing train signal processing, and similarly, it will also save the response time of the slave processor when performing train signal processing.

[0101] The specific type of the first hardware device can be of various types, as long as it can meet the requirements of the present application, that is, it can send time synchronization hard-wired signals to the master processor and the slave processor at the same time. For example, in a specific embodiment of the present invention, the first hardware device can be specifically a CPLD (Complex Programmable Logic Device). CPLD has the advantages of high reliability, strong flexibility, and the ability to easily respond to different circuit requirements. The use of CPLD can effectively achieve the functional requirements of the present application for the first hardware device and can send time synchronization hard-wired signals. In the embodiment of Figure 2, the first hardware device is specifically selected as a CPLD.

[0102] The main processor can receive the first collected data through its own first input channel. Typically, the main processor can periodically receive the collected data through the first input channel. In addition, it is understandable that in actual applications, the main processor can have multiple input channels, and the first input channel described in this application can be any one of the multiple input channels of the main processor. Different input channels of the main processor can be used to receive data from different collection locations. In other words, this application uses the first input channel as an example for explanation. The data sent to the main processor by other input channels can also be processed according to the principles of the solution of this application, and will not be repeated here.

[0103] Step S102: sending the first collected data to the slave processor, and receiving the second collected data sent by the slave processor.

[0104] After receiving the first collected data, the main processor will send the first collected data to the slave processor, and the slave processor will send the received second collected data to the main processor.

[0105] In the solution of the present application, the first collected data is the data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is the data of the target position collected by the slave processor through the second collection circuit at the first moment.

[0106] That is, the first collected data and the second collected data are both from the same collection position and at the same collection time, so under normal circumstances, the first collected data and the second collected data should be consistent.

[0107] For example, in one scenario, it is necessary to collect voltage data at a certain location. Then, the first acquisition circuit and the second acquisition circuit will both collect the voltage value at that location and send it to the master processor and the slave processor respectively. At the same time, the voltage values ​​of the same location collected by the first acquisition circuit and the second acquisition circuit should be consistent, that is, the first acquisition data and the second acquisition data should be consistent.

[0108] When the slave processor receives the first collected data sent by the master processor, it will perform feedback, that is, the slave processor sends the second collected data collected at the same time to the master processor.

[0109] In a specific embodiment of the present invention, step S102 may specifically include:

[0110] Step 1: sending a first request command carrying first collected data and attribute information of the first collected data to the slave processor;

[0111] Step 2: Receive a first response command sent from the processor and carrying the second collected data and attribute information of the second collected data.

[0112] This implementation method takes into account that after the first collected data is sent to the slave processor, the slave processor needs to know when and from where the collected data was collected, so that it can determine the second collected data collected at the same time and location, and then feed it back to the main processor.

[0113] In this regard, this implementation method will send a first request command to the slave processor. The first request command carries not only the first collected data, but also the attribute information of the first collected data. It can be understood that the attribute information of the first collected data is information used to reflect the collection time and collection location of the first collected data. Similarly, the attribute information of the second collected data is information used to reflect the collection time and collection location of the second collected data. It can be understood that under normal circumstances, the collection time and collection location reflected by the attribute information of the first collected data should be consistent with the collection time and collection location reflected by the attribute information of the second collected data.

[0114] For example, in a specific scenario, the attribute information of the first collected data includes an application execution cycle number and a channel number. The application execution cycle number described here represents the current cycle number when the main processor periodically receives the first collected data through the first input channel. It can be understood that, under normal circumstances, the application execution cycle number included in the attribute information of the second collected data is consistent with the application execution cycle number included in the attribute information of the first collected data, which means that the first collected data and the second collected data are collected at the same time.

[0115] The channel number in the attribute information of the first collected data can indicate which input channel the master processor used to receive the first collected data, thus reflecting the collection location of the first collected data. Similarly, the channel number in the attribute information of the second collected data can indicate which input channel the slave processor used to receive the second collected data, thus reflecting the collection location of the second collected data. In actual applications, for ease of comparison, the master and slave processors typically use the same numbered channels for the same collection location. For example, for the collected voltage value in the above example, the master processor receives the first collected data through its own input channel numbered 01, while the slave processor receives the second collected data through its own input channel numbered 01.

[0116] Step S103: Determine whether the first collected data is consistent with the second collected data. If not, execute the operation of step S104; if yes, execute the operation of step S105.

[0117] After receiving the first collected data and the second collected data, the main processor can determine whether the first collected data is consistent with the second collected data.

[0118] Step S104: Entering a safety-oriented state so that each output channel of the main processor outputs a preset safety level.

[0119] When the first collected data is inconsistent with the second collected data, the main processor will enter the guided safety state. The main processor entering the guided safety state means that each output channel of the main processor outputs a preset safety level. For example, generally speaking, the preset safety level is a low level, that is, generally speaking, after the main processor enters the guided safety state, each output channel of the main processor outputs 0.

[0120] Step S105: performing a preset data processing operation on the first collected data to obtain a first processing result corresponding to the first collected data;

[0121] When the first collected data is consistent with the second collected data, it can usually be said that the first collected data is correct collected data. Therefore, the preset data processing operation can be performed on the first collected data. For example, in one scenario, the first collected data is specifically the voltage data of a certain position. For example, the preset data processing operation is specifically to determine whether the voltage is overvoltage or undervoltage. If so, the first processing result is that the voltage is abnormal and a high-level signal needs to be output. Otherwise, the first processing result is that the voltage is normal and a low-level signal needs to be output.

[0122] Furthermore, it is understood that in the solution of the present application, the master processor determines whether the first collected data and the second collected data are consistent, thereby determining whether to enter the guidance safety state. Similarly, after receiving the first collected data, the slave processor, in addition to feeding back the second collected data to the master processor, may also determine whether the first collected data and the second collected data are consistent, thereby determining whether the slave processor needs to enter the guidance safety state.

[0123] Similarly, if the slave processor determines that the first and second collected data are inconsistent, the slave processor may enter a safety-oriented state so that each output channel of the slave processor outputs a preset safety level. If the slave processor determines that the first and second collected data are consistent, the slave processor may perform a preset data processing operation on the second collected data to obtain a second processing result corresponding to the second collected data. It is understood that the data processing operation performed by the slave processor on the second collected data may be consistent with the data processing operation performed by the master processor on the first collected data, i.e., the related applications used to implement data processing by the two processors may be consistent.

[0124] Please refer to Figure 3, which is a schematic diagram of data interaction between the master processor and the slave processor when processing train signals in a specific embodiment of the present invention. In Figure 3, the CPLD sends a time synchronization hard-wire signal to the master processor and the slave processor at the same time. DI in Figure 3 represents the first collected data received by the master processor and the second collected data received by the slave processor, which are data collected at the same time and at the same location. The master processor in Figure 3 can send a first request command carrying the first collected data to the slave processor, and receive a first response command carrying the second collected data fed back by the slave processor. Afterwards, the voting of the master processor and the slave processor in Figure 3, that is, the master processor and the slave processor will both determine whether the first collected data is consistent with the second collected data. When each of them determines that the first collected data is consistent with the second collected data, the master processor and the slave processor will both perform the preset data processing operation, that is, each of them will execute the application program shown in Figure 3.

[0125] Step S106: Execute the first processing result.

[0126] After obtaining the first processing result corresponding to the first collected data, the first processing result can be executed. For example, in one of the above scenarios, the first processing result is that the voltage is normal and a low-level signal needs to be output. The main processor can, for example, control the first output channel to output a low level.

[0127] In a specific embodiment of the present invention, after obtaining the first processing result corresponding to the first collected data, the following steps may also be included:

[0128] receiving a second processing result sent from the processor;

[0129] Determining whether the first processing result is consistent with the second processing result;

[0130] If not, then enter the safety-oriented state so that each output channel of the main processor outputs a preset safety level;

[0131] If yes, execute the first processing result;

[0132] The second processing result is a second processing result corresponding to the second collected data obtained after the processor performs a preset data processing operation on the second collected data.

[0133] In the above embodiment, the consistency of the first collected data and the second collected data is judged. In this embodiment, the consistency of the result obtained after the data processing operation is performed on the collected data will also be judged, thereby further ensuring the reliability of the output.

[0134] It can also be understood that since it is necessary to perform consistency judgment on the results obtained after performing data processing operations on the collected data, in addition to performing the preset data processing operation on the first collected data to obtain the first processing result corresponding to the first collected data, the slave processor also needs to perform the preset data processing operation on the second collected data to obtain the second processing result corresponding to the second collected data, and then send the second processing result to the main processor, so that after receiving the first processing result sent by the slave processor, the main processor can judge whether the first processing result is consistent with the second processing result.

[0135] If the main processor determines that the first processing result is consistent with the second processing result, it can be determined that the first processing result is correct and the first processing result can be executed. On the contrary, if the main processor determines that the first processing result is inconsistent with the second processing result, it means that there may be an abnormality in the calculation process of the main processor or the slave processor. In order to ensure system safety, the main processor can enter a safety-oriented state so that each output channel of the main processor outputs a preset safety level.

[0136] Similarly, for the slave processor, it can also determine whether the first processing result is consistent with the second processing result. If they are consistent, the slave processor can execute the second processing result. If they are consistent, the slave processor can enter a safety-oriented state so that each output channel of the slave processor outputs a preset safety level.

[0137] In the scenario of Figure 3, after the master processor receives the second processing result, the respective votes of the master processor and the slave processor shown in Figure 3 refer to the master processor and the slave processor, both of which will determine whether the first processing result is consistent with the second processing result to decide whether they need to enter the guided safety state.

[0138] In a specific embodiment of the present invention, step S106 may specifically include:

[0139] Based on the first processing result, controlling the level state of the first output channel thereof;

[0140] Among them, the first output channel of the main processor is connected to the first input end of the first AND gate circuit, and the first output channel of the slave processor is connected to the second input end of the first AND gate circuit; the level state of the first output channel of the slave processor is the level state determined by the slave processor based on the second processing result.

[0141] This implementation takes into account that, under normal circumstances, the first processing result and the second processing result should be consistent. Therefore, an AND gate circuit can be provided, which neither affects the output channel signal under normal circumstances nor can further ensure the reliability of the output.

[0142] Specifically, in this embodiment, when the main processor executes the first processing result, it controls the level state of its own first output channel based on the first processing result, and the first output channel of the main processor itself is not the final output, because the first output channel of the main processor is connected to the first input end of the first AND gate circuit, and the first output channel of the slave processor is connected to the second input end of the first AND gate circuit, and the slave processor can control the level state of its own first output channel based on the second processing result.

[0143] For example, under normal circumstances, if the master processor needs to control its first output channel to 1 based on the first processing result, and since the second processing result is the same as the first processing result, the slave processor will also control its first output channel to 1 based on the second processing result, so the output of the first AND gate circuit is also 1. Correspondingly, when the first output channel of the master processor and the first output channel of the slave processor are both 0, the output of the first AND gate circuit is also 0. It can be seen that the setting of the first AND gate circuit does not change the system output under normal circumstances.

[0144] For example, in one scenario, the first processing result and the second processing result are consistent. However, an error occurs in the process of executing the first processing result or the second processing result. According to the principle of the AND gate, as long as the two input terminals of the AND gate circuit are not 1 at the same time, its output terminal will be 0, that is, the output is a safe level, thereby avoiding abnormalities and further ensuring reliability.

[0145] In FIG3 , the master processor and the slave processor execute the first processing result and the second processing result through the same DO, which means that the final output is determined based on the first AND gate circuit.

[0146] In a specific embodiment of the present invention, it may further include:

[0147] Whenever a time synchronization hard-wire signal sent by the first hardware device is received, verifying whether the period of the time synchronization hard-wire signal is equal to the set acquisition period through a first timer set in the main processor;

[0148] If not, the system enters a safety-oriented state so that each output channel of the main processor outputs a preset safety level.

[0149] This embodiment takes into account that the solution of the present application is to achieve time synchronization between the master processor and the slave processor through a time synchronization hard-wired signal sent by a first hardware device. In order to ensure the reliability of time synchronization, in this embodiment, whenever the master processor receives a time synchronization hard-wired signal sent by the first hardware device, it can verify through the first timer set in the master processor whether the period of the time synchronization hard-wired signal is equal to the set acquisition period. If not, it indicates that an abnormality has occurred. In order to ensure reliability, the master processor can enter a guided safety state.

[0150] For example, in one scenario, the accuracy of a first timer in a main processor is 1ms, meaning the first timer's count value increments by 1 every 1ms. This is typically accomplished through an interrupt. The time synchronization hardwire signal is typically a clock signal. Based on the count value of the first timer, the interval between two adjacent clock pulses in the time synchronization hardwire signal can be determined, thereby determining the period of the time synchronization hardwire signal. The process then determines whether the period of the time synchronization hardwire signal is consistent with a pre-set acquisition period.

[0151] Similarly, in actual applications, the slave processor can also verify whether the period of the time synchronization hard-wired signal is equal to the set acquisition period through the second timer set in the slave processor whenever it receives the time synchronization hard-wired signal sent by the first hardware device. If not, it indicates that an abnormality has occurred. In order to ensure reliability, the slave processor can enter a guided safety state.

[0152] Furthermore, it should be understood that the acquisition period set by the slave processor must be consistent with the acquisition period set by the master processor. This value is also the period used by the slave processor when receiving the second acquisition data. The synchronization signal detection shown in Figure 3 indicates that both the master and slave processors verify whether the period of the time synchronization hardwire signal is equal to the set acquisition period.

[0153] In the solution of the present application, data exchange is required between the master processor and the slave processor. For example, in a specific embodiment of the present invention, the master processor and the slave processor can be connected to each other by wired communication and / or wireless communication to ensure the flexibility of the solution. In addition, in some cases, the communication connection between the two can be achieved with the help of other devices. For example, in the scenario of Figure 2, the master processor and the slave processor are connected to each other through a switching chip, that is, both can send communication data of the set protocol to each other through the switching chip.

[0154] In a specific embodiment of the present invention, it may further include:

[0155] After power-on, obtain the value of its own acquisition cycle and receive the value of the acquisition cycle of the slave processor sent by the slave processor;

[0156] Determine whether the value of its own acquisition cycle is consistent with the value of the acquisition cycle of the slave processor;

[0157] If not, then enter the safety-oriented state so that each output channel of the main processor outputs a preset safety level;

[0158] If yes, the first hardware device is enabled and instructed to send a time synchronization hard-wire signal to the master processor and the slave processor simultaneously according to the acquisition cycle.

[0159] This implementation takes into account that the specific value of the acquisition period can be pre-set, and the acquisition periods saved between the master processor and the slave processor should be consistent. Therefore, after power-on, the master processor can obtain the value of its own acquisition period and receive the value of the acquisition period of the slave processor sent by the slave processor. If the two values ​​are inconsistent, the master processor can enter a safety-oriented state so that each output channel of the master processor outputs a preset safety level to ensure system safety.

[0160] Correspondingly, if the two values ​​are consistent, it generally indicates that both the master processor and the slave processor have correctly saved the same acquisition period. Therefore, the master processor can enable the first hardware device and can instruct the first hardware device to subsequently send a time synchronization hard-wired signal to both the master processor and the slave processor according to the acquisition period. That is, after power-on, the master processor can complete the setting of the period of the time synchronization hard-wired signal sent by the first hardware device. In the specific embodiment of Figure 2, the master processor MCUA sets the period of the time synchronization hard-wired signal sent by the CPLD via the local bus.

[0161] In addition, it can be understood that after the main processor is powered on, it can also send the acquired value of its own acquisition cycle to the slave processor, so that the slave processor can also determine whether the value of the slave processor's own acquisition cycle is consistent with the value of the acquisition cycle received from the main processor. If they are inconsistent, the slave processor can also enter a safety-oriented state so that each output channel of the slave processor outputs a preset safety level.

[0162] By applying the technical solution provided in the embodiment of the present invention, the LCU is implemented based on the master processor and the slave processor. Data processing is performed only when the collected data of the two are consistent, thereby ensuring system security. In addition, in order to reduce response time, in the solution of the present application, time synchronization between the master processor and the slave processor is not achieved directly through communication between the two. Instead, a first hardware device is specially set up. The first hardware device can simultaneously send a time synchronization hard-wire signal to the master processor and the slave processor, thereby performing time synchronization between the master processor and the slave processor. Since the time synchronization between the master processor and the slave processor is achieved based on the time synchronization hard-wire signal, the time synchronization between the master processor and the slave processor can be achieved quickly, which saves the response time of the master processor in the train signal processing process.

[0163] When processing train signals, the main processor can receive first collected data through its own first input channel, then send the first collected data to the slave processor and receive second collected data sent by the slave processor. The first collected data is the data of the target position collected by the main processor through the first acquisition circuit at the first moment, and the second collected data is the data of the target position collected by the slave processor through the second acquisition circuit at the first moment. Therefore, under normal circumstances, the main processor will determine that the first collected data is consistent with the second collected data, and then perform a preset data processing operation on the first collected data to obtain a first processing result corresponding to the first collected data, and then execute the first processing result. If the first collected data is inconsistent with the second collected data, it means that an abnormal situation has occurred. In order to ensure system safety, the main processor can enter a safety-oriented state so that each output channel of the main processor outputs a preset safety level.

[0164] To sum up, the solution of the present application ensures the security and reliability of the train signal processing process through the setting of the main processor and the slave processor, and since the time synchronization of the main processor and the slave processor is achieved through the time synchronization hard-wired signal sent by the first hardware device, the time synchronization process can be implemented quickly, which saves the response time of the main processor in the train signal processing process. That is, under the premise of ensuring the safety of the system, the device composed of the main processor and the slave processor of the present application has the ability to replace the original key safety hard-wired signal of the train.

[0165] Corresponding to the above embodiment, an embodiment of the present invention further provides a method for processing a train signal, which can be applied to a slave processor. The master processor is communicatively connected to the slave processor, and the first hardware device is used to simultaneously send a time synchronization hardwire signal to the master processor and the slave processor to synchronize the time of the master processor and the slave processor. Referring to FIG. 4 , the method for processing a train signal includes:

[0166] Step S401: receiving second collected data through its own first input channel;

[0167] Step S402: receiving the first collected data sent by the main processor, and sending the second collected data to the main processor;

[0168] Step S403: determining whether the first collected data is consistent with the second collected data;

[0169] If not, then executing step S404: entering a safety-oriented state so that each output channel of the slave processor outputs a preset safety level;

[0170] If yes, then executing step S405: performing a preset data processing operation on the second collected data to obtain a second processing result corresponding to the second collected data;

[0171] Step S406: executing the second processing result;

[0172] The first collected data is the data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is the data of the target position collected by the slave processor through the second collection circuit at the first moment.

[0173] In a specific embodiment of the present invention, it also includes:

[0174] Whenever a time synchronization hard-wire signal sent by the first hardware device is received, verifying whether the period of the time synchronization hard-wire signal is equal to the set acquisition period through a second timer set in the slave processor;

[0175] If not, the system enters a safety-oriented state so that each output channel of the slave processor outputs a preset safety level.

[0176] In a specific embodiment of the present invention, receiving first collected data sent by a main processor and sending second collected data to the main processor includes:

[0177] receiving a first request command sent by a main processor and carrying first collected data and attribute information of the first collected data;

[0178] A first response command carrying the second collected data and attribute information of the second collected data is sent to the main processor.

[0179] In a specific embodiment of the present invention, it also includes:

[0180] After power-on, obtain the value of its own acquisition cycle and send it to the main processor, and receive the value of the main processor's acquisition cycle sent by the main processor;

[0181] Determine whether the value of its own acquisition cycle is consistent with the value of the acquisition cycle of the main processor;

[0182] If not, the system enters a safety-oriented state so that each output channel of the slave processor outputs a preset safety level.

[0183] In a specific embodiment of the present invention, after obtaining the second processing result corresponding to the second collected data, the method further includes:

[0184] receiving a first processing result sent by the main processor;

[0185] Determining whether the first processing result is consistent with the second processing result;

[0186] If not, entering a safety-oriented state so that each output channel of the slave processor outputs a preset safety level;

[0187] If yes, then execute the second processing result;

[0188] The first processing result is a first processing result corresponding to the first collected data obtained after the processor performs a preset data processing operation on the first collected data.

[0189] In a specific embodiment of the present invention, executing the second processing result includes:

[0190] Based on the second processing result, controlling the level state of the first output channel thereof;

[0191] Among them, the first output channel of the main processor is connected to the first input end of the first AND gate circuit, and the first output channel of the slave processor is connected to the second input end of the first AND gate circuit; the level state of the first output channel of the main processor is the level state determined by the main processor based on the first processing result.

[0192] Corresponding to the above method embodiments, an embodiment of the present invention further provides a train signal processing system, which can be applied to a master processor. The master processor is communicatively connected to a slave processor. A first hardware device is used to simultaneously send a time synchronization hardwire signal to the master processor and the slave processor to synchronize the time of the master processor and the slave processor. Referring to FIG. 5 , the train signal processing system may include:

[0193] The first collected data receiving module 501 is used to receive the first collected data through its own first input channel;

[0194] A first synchronization module 502 is configured to send the first collected data to the slave processor and receive the second collected data sent by the slave processor;

[0195] A first judgment module 503 is used to judge whether the first collected data is consistent with the second collected data;

[0196] If not, the first guidance safety module 504 is triggered, and the first guidance safety module 504 is used to: enter the guidance safety state so that each output channel of the main processor outputs a preset safety level;

[0197] If yes, the first processing result determination module 505 is triggered, and the first processing result determination module 505 is used to: perform a preset data processing operation on the first collected data to obtain a first processing result corresponding to the first collected data;

[0198] A first processing result execution module 506, configured to execute the first processing result;

[0199] The first collected data is the data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is the data of the target position collected by the slave processor through the second collection circuit at the first moment.

[0200] An embodiment of the present invention further provides a train signal processing system that can be applied to a slave processor. The master processor is communicatively connected to the slave processor. A first hardware device is used to simultaneously send a time synchronization hardwire signal to the master processor and the slave processor to synchronize the time of the master processor and the slave processor. Referring to FIG. 6 , the train signal processing system includes:

[0201] The second collected data receiving module 601 is used to receive the second collected data through its own first input channel;

[0202] The second synchronization module 602 is configured to receive the first collected data sent by the main processor and send the second collected data to the main processor;

[0203] The second judgment module 603 is used to judge whether the first collected data is consistent with the second collected data;

[0204] If not, the second guide safety module 604 is triggered, and the second guide safety module 604 is used to: enter a guide safety state so that each output channel of the slave processor outputs a preset safety level;

[0205] If yes, the second processing result determination module 605 is triggered, and the second processing result determination module 605 is used to: perform a preset data processing operation on the second collected data to obtain a second processing result corresponding to the second collected data;

[0206] A second processing result execution module 606, configured to execute the second processing result;

[0207] The first collected data is the data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is the data of the target position collected by the slave processor through the second collection circuit at the first moment.

[0208] Corresponding to the above method and system embodiments, an embodiment of the present invention further provides a train signal processing device, including:

[0209] memory for storing computer programs;

[0210] A processor is configured to execute a computer program to implement the steps of the train signal processing method in any one of the embodiments.

[0211] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0212] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0213] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only intended to help understand the technical solutions and core concepts of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A method for processing train signals, characterized in that: Applied in a main processor, the main processor is communicatively connected with a slave processor, the first hardware device is used to simultaneously send a time synchronization hard-line signal to the main processor and the slave processor to perform time synchronization of the main processor and the slave processor, and the train signal processing method includes: Receiving first collected data through its own first input channel; sending the first collected data to the slave processor, and receiving second collected data sent by the slave processor; Determining whether the first collected data is consistent with the second collected data; If not, entering a safety-oriented state so that each output channel of the main processor outputs a preset safety level; If yes, performing a preset data processing operation on the first collected data to obtain a first processing result corresponding to the first collected data; executing the first processing result; The first collected data is data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is data of the target position collected by the slave processor through the second collection circuit at the first moment.

2. The train signal processing method according to claim 1, characterized in that: Also includes: Whenever a time synchronization hard-wire signal sent by the first hardware device is received, verifying whether the period of the time synchronization hard-wire signal is equal to the set acquisition period through a first timer set in the main processor; If not, the system enters a safety-oriented state so that each output channel of the main processor outputs a preset safety level.

3. The train signal processing method according to claim 1, characterized in that: Sending the first collected data to the slave processor, and receiving the second collected data sent by the slave processor, comprises: sending a first request command carrying the first collected data and attribute information of the first collected data to the slave processor; receiving a data packet sent by the slave processor and carrying the second collected data and the second collected data; The first response command of the attribute information of the data.

4. The train signal processing method according to claim 1, characterized in that: The first hardware device is specifically a CPLD.

5. The train signal processing method according to claim 1, characterized in that: The master processor and the slave processor are connected to each other by wired communication and / or wireless communication.

6. The train signal processing method according to claim 1, characterized in that: Also includes: After power-on, obtaining the value of its own acquisition period, and receiving the value of the acquisition period of the slave processor sent by the slave processor; Determine whether the value of its own acquisition period is consistent with the value of the acquisition period of the slave processor; If not, entering a safety-oriented state so that each output channel of the main processor outputs a preset safety level; If yes, the first hardware device is enabled, and the first hardware device is commanded to send a time synchronization hard-line signal to the master processor and the slave processor simultaneously according to the acquisition cycle.

7. The train signal processing method according to any one of claims 1 to 6, characterized in that: After obtaining a first processing result corresponding to the first collected data, the method further includes: receiving a second processing result sent by the slave processor; Determining whether the first processing result is consistent with the second processing result; If not, entering a safety-oriented state so that each output channel of the main processor outputs a preset safety level; If yes, executing the first processing result; The second processing result is a second processing result corresponding to the second collected data obtained after the slave processor performs a preset data processing operation on the second collected data.

8. The train signal processing method according to claim 7, characterized in that: Executing the first processing result includes: Based on the first processing result, controlling the level state of the first output channel thereof; The first output channel of the main processor is connected to the first input channel of the first AND gate circuit. The first output channel of the slave processor is connected to the second input terminal of the first AND gate circuit; the level state of the first output channel of the slave processor is the level state determined by the slave processor based on the second processing result.

9. A method for processing train signals, characterized in that: Applied to a slave processor, the master processor is communicatively connected to the slave processor, the first hardware device is used to simultaneously send a time synchronization hard-line signal to the master processor and the slave processor to perform time synchronization between the master processor and the slave processor, and the train signal processing method includes: Receiving second collected data through its own first input channel; receiving first collected data sent by the main processor, and sending the second collected data to the main processor; Determining whether the first collected data is consistent with the second collected data; If not, entering a safety-oriented state so that each output channel of the slave processor outputs a preset safety level; If yes, performing a preset data processing operation on the second collected data to obtain a second processing result corresponding to the second collected data; executing the second processing result; The first collected data is data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is data of the target position collected by the slave processor through the second collection circuit at the first moment.

10. The train signal processing method according to claim 9, characterized in that: Also includes: Whenever a time synchronization hard-wire signal sent by the first hardware device is received, verifying whether the period of the time synchronization hard-wire signal is equal to the set acquisition period through a second timer set in the slave processor; If not, the system enters a safety-oriented state so that each output channel of the slave processor outputs a preset safety level.

11. The train signal processing method according to claim 9, characterized in that: Receiving first collected data sent by the main processor, and sending the second collected data to the main processor, comprising: receiving a first request command sent by the main processor and carrying the first collected data and attribute information of the first collected data; A first response command carrying the second collected data and attribute information of the second collected data is sent to the main processor.

12. The train signal processing method according to claim 9, characterized in that: Also includes: After power-on, obtain the value of its own acquisition cycle and send it to the main processor, and receive the value of the acquisition cycle of the main processor sent by the main processor; Determine whether the value of its own acquisition cycle is consistent with the value of the acquisition cycle of the main processor; If not, the system enters a safety-oriented state so that each output channel of the slave processor outputs a preset safety level.

13. The train signal processing method according to any one of claims 9 to 12, characterized in that: After obtaining a second processing result corresponding to the second collected data, the method further includes: receiving a first processing result sent by the main processor; Determining whether the first processing result is consistent with the second processing result; If not, entering a safety-oriented state so that each output channel of the slave processor outputs a preset safety level; If yes, executing the second processing result; The first processing result is a first processing result corresponding to the first collected data obtained after the slave processor performs a preset data processing operation on the first collected data.

14. The train signal processing method according to claim 13, characterized in that: Executing the second processing result includes: Based on the second processing result, controlling the level state of the first output channel thereof; Among them, the first output channel of the main processor is connected to the first input end of the first AND gate circuit, and the first output channel of the slave processor is connected to the second input end of the first AND gate circuit; the level state of the first output channel of the main processor is the level state determined by the main processor based on the first processing result.

15. A train signal processing system, characterized in that: Applied to a main processor, the main processor is communicatively connected with a slave processor, the first hardware device is used to simultaneously send a time synchronization hard-line signal to the main processor and the slave processor to perform time synchronization of the main processor and the slave processor, and the train signal processing system includes: A first collected data receiving module, used for receiving first collected data through its own first input channel; A first synchronization module, used for sending the first collected data to the slave processor, and receiving second collected data sent by the slave processor; A first judgment module, used to judge whether the first collected data is consistent with the second collected data; If not, triggering a first guidance safety module, the first guidance safety module is used to: enter a guidance safety state so that each output channel of the main processor outputs a preset safety level; If yes, triggering a first processing result determination module, the first processing result determination module is used to: perform a preset data processing operation on the first collected data to obtain a first processing result corresponding to the first collected data; A first processing result execution module, used for executing the first processing result; The first collected data is data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is data of the target position collected by the slave processor through the second collection circuit at the first moment.

16. A train signal processing system, characterized in that: Applied to a slave processor, the master processor is communicatively connected to the slave processor, the first hardware device is used to simultaneously send a time synchronization hard-line signal to the master processor and the slave processor to perform time synchronization between the master processor and the slave processor, and the train signal processing system includes: A second collected data receiving module, used for receiving second collected data through its own first input channel; A second synchronization module, configured to receive the first collected data sent by the main processor, and send the second collected data to the main processor; The second judgment module is used to judge whether the first collected data and the second collected data are Consistency; If not, triggering a second guidance safety module, the second guidance safety module is used to: enter a guidance safety state so that each output channel of the slave processor outputs a preset safety level; If yes, triggering a second processing result determination module, the second processing result determination module is used to: perform a preset data processing operation on the second collected data to obtain a second processing result corresponding to the second collected data; A second processing result execution module, used for executing the second processing result; The first collected data is data of the target position collected by the main processor through the first collection circuit at the first moment, and the second collected data is data of the target position collected by the slave processor through the second collection circuit at the first moment.

17. A train signal processing device, characterized in that: include: Memory for storing computer programs; A processor, used to execute the computer program to implement the steps of the train signal processing method as described in any one of claims 1 to 8, or to implement the steps of the train signal processing method as described in any one of claims 9 to 14.

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