Gate drive circuit and display panel

Abstract

Provided in the present application are a gate drive circuit and a display panel. The gate drive circuit comprises N cascaded GOA units, wherein an nth-stage GOA unit comprises a pull-up control module, a pull-up module, a pull-down module and a pull-down maintenance module. The pull-up module receives a first clock signal to output a first gate drive signal to a gate signal end of an nth stage, and receives a second clock signal to output a second gate drive signal to a gate signal end of an (n+1)th stage.

Description

Gate drive circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] Gate Drive On Array (GOA) technology integrates scan line driving circuits on the array substrate of a liquid crystal panel, thereby reducing product costs in terms of material costs and manufacturing processes.

[0003] With the advancement of display technology, users are increasingly demanding the appearance of display panels, such as narrow bezels. The bezel area of ​​a display panel is equipped with a gate drive circuit consisting of n-level GOA units. Each level of the GOA unit is equipped with multiple thin-film transistors, making it difficult to further reduce the bezel area. SUMMARY OF THE INVENTION

[0004] The present application provides a gate driving circuit and a display panel to solve the technical problem of a large frame of an existing display panel.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a gate drive circuit, the gate drive circuit including N cascaded GOA units, the n-th stage GOA unit being any one of the N GOA units, the n-th stage GOA unit including a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintaining module, the pull-up control module and the pull-up module being connected to a first control node, the pull-down module being electrically connected to the first control node and a first potential line, and the pull-down maintaining module being electrically connected to the first control node and a second potential line;

[0007] The pull-up control module receives a first-stage transmission signal in the first phase and pulls up the first control node to a first high potential;

[0008] The pull-up module receives a first clock signal and outputs a first gate drive signal to the gate signal terminal of the nth stage according to the potential of the first control node, and the pull-up module receives a second clock signal and outputs a second gate drive signal to the gate signal terminal of the (n+1)th stage according to the potential of the first control node;

[0009] The pull-down module receives the second-stage transmission signal in the third stage and pulls down the potential of the first control node to a first low potential;

[0010] The pull-down holding module receives a third clock signal in the third phase, pulls down the potential of the gate signal terminal of the nth stage to the second DC low level, and pulls down the potential of the gate signal terminal of the (n+1)th stage to the first low level.

[0011] The present application also provides a display panel, wherein the display panel includes a gate drive circuit, the gate drive circuit includes N cascaded GOA units, wherein the n-th stage GOA unit is any one of the N GOA units, the n-th stage GOA unit includes a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintenance module, the pull-up control module and the pull-up module are connected to a first control node, the pull-down module is electrically connected to the first control node and a first potential line, and the pull-down maintenance module is electrically connected to the first control node and a second potential line;

[0012] The pull-up control module receives a first-stage transmission signal in the first phase and pulls up the first control node to a first high potential;

[0013] The pull-up module receives a first clock signal and outputs a first gate drive signal to the gate signal terminal of the nth stage according to the potential of the first control node, and the pull-up module receives a second clock signal and outputs a second gate drive signal to the gate signal terminal of the (n+1)th stage according to the potential of the first control node;

[0014] The pull-down module receives the second-stage transmission signal in the third stage and pulls down the potential of the first control node to a first low potential;

[0015] The pull-down holding module receives a third clock signal in a third phase, pulls down the potential of the gate signal terminal of the nth stage to a second DC low level, and pulls down the potential of the gate signal terminal of the (n+1)th stage to the first low level. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG1 is a structural diagram of a GOA unit in a gate drive circuit of the present application;

[0017] FIG2 is a timing control diagram of the gate drive circuit of the present application;

[0018] FIG3 is a state diagram of the GOA unit in FIG2 during the reset phase;

[0019] FIG4 is a state diagram of the GOA unit in FIG2 in the first stage;

[0020] FIG5 is a state diagram of the GOA unit in FIG2 in the second stage;

[0021] FIG6 is a state diagram of the GOA unit in FIG2 in the third stage;

[0022] FIG7 is a state diagram of the GOA unit in FIG2 in the fourth stage;

[0023] FIG8 is a simplified structural diagram of the display panel of the present application. Modes for Carrying Out the Invention

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0025] With the development of display industry technology, users have increasingly higher requirements for the appearance design of display panels, such as narrow bezel design. The display panel bezel area is provided with a gate drive circuit, which includes n-level GOA units. Each level of GOA unit is provided with multiple thin film transistors, making it impossible to further reduce the bezel area. Based on the above technical problems, this application proposes the following technical solutions:

[0026] Referring to FIG. 1 to FIG. 7 , the present application proposes a gate driving circuit. The gate driving circuit includes N cascaded GOA units 100 . The n-th stage GOA unit 100 is any one of the N GOA units 100 .

[0027] In this embodiment, the nth level GOA unit 100 may include a pull-up control module 10, a bootstrap capacitor Cbt, a pull-up module 20, a pull-down module 30 and a pull-down maintenance module 40, the pull-up control module 10 and the pull-up module 20 are connected to the first control node Q, the pull-down module 30 is electrically connected to the first control node Q and the first potential line VSSQ, and the pull-down maintenance module 40 is electrically connected to the first control node VSSQ and the second potential line VSSG.

[0028] In this embodiment, the pull-up control module 10 receives the first-stage transmission signal in the first stage, pulls up the first control node Q to a first high potential, and charges the bootstrap capacitor Cbt; the bootstrap capacitor Cbt maintains the potential of the first control node Q in the second stage; the pull-up module 20 receives the first clock signal and outputs a first gate drive signal to the gate signal terminal G(n) of the nth stage according to the potential of the first control node Q, and the pull-up module 20 receives the second clock signal and outputs a second gate drive signal to the gate signal terminal G(n+1) of the n+1th stage according to the potential of the first control node Q; the pull-down module 30 receives the second-stage transmission signal in the third stage, pulls down the potential of the first control node Q to a first low potential; the pull-down maintaining module 40 receives the third clock signal in the third stage, pulls down the potential of the gate signal terminal G(n) of the nth stage to a second DC low level, and pulls down the potential of the gate signal terminal G(n+1) of the n+1th stage to the first low potential.

[0029] The present application sets the n-th level gate signal terminal G(n) and the n+1-th level gate signal terminal G(n+1) in a GOA unit 100, so that one GOA unit 100 outputs a two-level gate drive signal to scan two rows of sub-pixels in the display panel, thereby reducing the number of GOA units 100 in the gate drive circuit, that is, reducing the space occupied by the gate drive circuit in the display panel frame, and realizing a narrow frame design; for example, the display panel of the present application has K rows of sub-pixels, and the number of GOA units 100 required is only K / 2, and the number of thin film transistors is reduced by nearly half, so the arrangement of the transistors in the GOA unit 100 can be redesigned to realize a narrow frame design of the display panel.

[0030] Please refer to Figure 1. The pull-up control module 10 is connected to the stage transmission signal terminal ST(nX) of the nX-th stage, the first control node Q, the first high potential line Vgh and the pull-down maintenance module 40. The stage transmission signal terminal ST(nX) of the nX-th stage is used to output the first stage transmission signal; the pull-up control module 10 includes a pull-up control transistor T11, the gate of the pull-up control transistor T11 is connected to the stage transmission signal terminal ST(nX) of the nX-th stage, the source of the pull-up control transistor T11 is connected to the first high potential line Vgh, and the drain of the pull-up control transistor T11 is connected to the first control node Q and the pull-down maintenance module 40.

[0031] In this embodiment, the gate drive circuit may include m clock signal lines, and X is greater than or equal to (m / 2)-1 and less than or equal to (m / 2)+1. For example, when the gate drive circuit includes four clock signal lines, the value of X may be one of 1, 2, and 3; when the gate drive circuit includes eight clock signal lines, the value of X may be one of 3, 4, and 5.

[0032] In this embodiment, the value of X is usually half of the clock signal line in the gate driving circuit.

[0033] Please refer to Figure 1. The pull-up module 20 includes a first pull-up unit 210 and a second pull-up unit 220. The first pull-up unit 210 is connected to the first control node Q, the clock signal line CK(n) of the n-th stage, and the gate signal terminal G(n) of the n-th stage. The second pull-up unit 220 is connected to the first control node Q, the clock signal line CK(n+1) of the n+1-th stage, and the gate signal terminal G(n+1) of the n+1-th stage. The clock signal line CK(n) of the n-th stage is used to provide a first clock signal, and the clock signal line CK(n+1) of the n+1-th stage is used to provide a second clock signal.

[0034] 1 , the first pull-up unit 210 includes a first pull-up transistor T21 , wherein a gate of the first pull-up transistor T21 is connected to a first control node Q, a source of the first pull-up transistor T21 is connected to a clock signal line CK(n) of an n-th stage, and a drain of the first pull-up transistor T21 is connected to a gate signal terminal G(n) of an n-th stage.

[0035] In this embodiment, the second pull-up unit 220 includes a second pull-up transistor T211, the gate of the second pull-up transistor T211 is connected to the first control node Q, the source of the second pull-up transistor T211 is connected to the clock signal line CK(n+1) of the n+1th level, and the drain of the second pull-up transistor T211 is connected to the gate signal terminal G(n+1) of the n+1th level.

[0036] Please refer to Figure 1. The pull-up module 20 also includes a stage transmission unit 230, which includes a stage transmission transistor T22; the gate of the stage transmission transistor T22 is connected to the first control node Q, the source of the stage transmission transistor T22 is connected to the first clock signal line, and the drain of the stage transmission transistor T22 is connected to the stage transmission signal terminal ST(n) of the nth stage.

[0037] Please refer to Figure 1. The pull-down module 30 includes a pull-down transistor T41. The gate of the pull-down transistor T41 is connected to the stage transmission signal terminal ST(n+Y) of the n+Yth stage, the source of the pull-down transistor T41 is connected to the first control node Q, and the drain of the pull-down transistor T41 is connected to the first low potential line VSSQ. The stage transmission signal terminal ST(n+Y) of the n+Yth stage is used to provide a second-stage transmission signal, where Y is an integer.

[0038] 1 , the pull-down holding module 40 includes an inverter 410 and a voltage regulating unit 420 . The voltage regulating unit 420 and the inverter 410 are connected to the second control node P. The inverter 410 is used to control the potential of the second control node P.

[0039] In this embodiment, the voltage regulating unit 420 includes a first regulating transistor T32, a second regulating transistor T321, a third regulating transistor T42, a fourth regulating transistor T412 and a fifth regulating transistor T72;

[0040] The gate of the first regulating transistor T32 is connected to the second control node P, the source of the first regulating transistor T32 is connected to the gate signal terminal G(n) of the nth stage, and the drain of the first regulating transistor T32 is connected to the second low potential line VSSG;

[0041] The gate of the second regulating transistor T321 is connected to the second control node P, the source of the second regulating transistor T321 is connected to the gate signal terminal G(n+1) of the n+1th stage, and the drain of the second regulating transistor T321 is connected to the first low potential line VSSQ;

[0042] The gate of the third regulating transistor T42 is connected to the second control node P, the source of the third regulating transistor T42 is connected to the first control node Q, and the drain of the third regulating transistor T42 is connected to the first low potential line VSSQ;

[0043] The gate of the fourth regulating transistor T412 and the gate of the fifth regulating transistor T72 are connected to the second control node P, the source of the fourth regulating transistor T412 is connected to the first control node Q, the drain of the fourth regulating transistor T412 and the source of the fifth regulating transistor T72 are connected to the stage transmission signal terminal ST(n) of the nth stage, and the drain of the fifth regulating transistor T72 is connected to the first low potential line VSSQ.

[0044] 1 , the inverter 410 includes a first inverter transistor T51, a second inverter transistor T52, a third inverter transistor T53, a fourth inverter transistor T54, a fifth inverter transistor T55, and a sixth inverter transistor T511. The gate of the first inverter transistor T51 is connected to the clock signal line CK(n+Y) of the n+Y stage, the source of the first inverter transistor T51 and the source of the third inverter transistor T53 are connected to the second high potential line VDD, the drain of the first inverter transistor T51 and the gate of the third inverter transistor T53 are connected to the third control node S, and the drain of the third inverter transistor T53 is connected to the second control node P. The gate of the second inverter transistor T52 and the gate of the fourth inverter transistor T55 are connected to the second control node P. The gate of T54 is connected to the drain of the pull-up transistor, the source of the second inverting transistor T52 is connected to the third control node S, the source of the fourth inverting transistor T54 and the source of the fifth inverting transistor T55 are connected to the second control node P, the drain of the second inverting transistor T52, the drain of the fourth inverting transistor T54, and the drain of the fifth inverting transistor T55 are connected to the first low potential line VSSQ; the gate of the sixth inverting transistor T511 and the gate of the fifth inverting transistor T55 are connected to the clock signal line CK(n+YX) of the n+YX stage, the source of the sixth inverting transistor T511 is connected to the third control node S, and the drain of the sixth inverting transistor T511 is connected to the first low potential line VSSQ.

[0045] In this embodiment, the clock signal line CK(n+Y) of the n+Yth stage is used to output the third clock signal, and the clock signal line CK(n+YX) of the n+YXth stage is used to output the fourth clock signal. The third clock signal and the fourth clock signal are mutually coupled signals.

[0046] 1 , the inverter 410 further includes a reset transistor, a gate of the reset transistor connected to the reset signal line Rest, a source of the reset transistor connected to the second high potential line VDD, and a drain of the reset transistor connected to the second control node P.

[0047] 1 , a first plate of the bootstrap capacitor Cbt is connected to the first control node Q and the pull-up module 20 , and a second plate of the bootstrap capacitor Cbt is connected to the gate signal terminal G(n) of the nth stage and the pull-down holding module 40 .

[0048] The gate drive circuit of the present application is described in detail below with reference to the timing control diagram in FIG2 .

[0049] In the reset phase t0, refer to FIG3 , the reset signal line Rest outputs a high level to the gate of the reset transistor, and the second high potential line VDD outputs a high level to the second control node P through the source and drain of the reset transistor, so as to pull the potential of the second control node P to a high potential. Since the second control node P is connected to the gates of the first regulating transistor T32, the second regulating transistor T321, the third regulating transistor T42, the fourth regulating transistor T412, and the fifth regulating transistor T72, ...1, the fourth regulating transistor T412, and the fifth regulating transistor T72 are connected to the gates of the first regulating transistor T32, the second regulating transistor T321, the third regulating transistor T421, the fourth regulating transistor T412, and the fifth regulating transistor T72. 321, the third regulating transistor T42, the fourth regulating transistor T412 and the fifth regulating transistor T72 are turned on to connect the first control node Q to the first low potential line VSSQ, the gate signal terminal G(n) of the nth stage to the second low potential line VSSG, and the gate signal terminal G(n+1) of the n+1th stage to the first low potential line VSSQ, so as to reset the potentials of the first control node Q, the gate signal terminal G(n) of the nth stage, the gate signal terminal G(n+1) of the n+1th stage, and the stage transfer signal terminal ST(n) of the nth stage.

[0050] In the first stage t1, referring to FIG4 , the stage pass signal terminal ST(nX) of the nX-th stage outputs a high level to the gate of the pull-up control transistor T11, the pull-up control transistor T11 is turned on, and the first high potential line Vgh outputs a high level to the first control node Q through the source and drain of the pull-up control transistor T11, thereby pulling the potential of the first control node Q up to the first high potential. The first pull-up transistor T21, the second pull-up transistor T211, and the stage pass transistor T22 are turned on, and the bootstrap capacitor Cbt begins to charge.

[0051] Secondly, since the gates of the second inverting transistor T52 and the fourth inverting transistor T54 are both connected to the first control node Q, the second inverting transistor T52 and the fourth inverting transistor T54 are turned on, the second control node P and the third control node S are both connected to the first low potential line VSSQ, and the potentials of the second control node P and the third control node S are both pulled down to the first low potential, so as to turn off the first regulating transistor T32, the second regulating transistor T321, the third regulating transistor T42, the fourth regulating transistor T412 and the fifth regulating transistor T72.

[0052] In the second stage t2, please refer to Figure 5. The stage transfer signal terminal ST(nX) of the nX-th stage outputs a low level to the gate of the pull-up control transistor T11, and the pull-up control transistor T11 is turned off. The first high potential of the first control node Q maintains the first pull-up transistor T21, the second pull-up transistor T211 and the stage transfer transistor T22 to be turned on. The clock signal line CK(n) of the n-th stage transmits the first gate drive signal to the gate signal terminal G(n) of the n-th stage through the source and drain of the first pull-up transistor T21. The clock signal line CK(n+1) of the n+1-th stage transmits the second gate drive signal to the gate signal terminal G(n+1) of the n+1-th stage through the source and drain of the second pull-up transistor T211. The clock signal line CK(n) of the n-th stage transmits the stage transfer signal to the stage transfer signal terminal ST(n) of the n-th stage through the source and drain of the stage transfer transistor T22.

[0053] At the same time, the clock signal line CK(n) of the nth stage outputs a high level, which will continue to pull up the potential of the first control node Q, so that the potential of the first control node Q is pulled up from the first high potential to the second high potential.

[0054] At the same time, the high potential of the first control node Q keeps the second inverter transistor T52 and the fourth inverter transistor T54 turned on, and the second control node P and the third control node S are continuously connected to the first low potential line VSSQ.

[0055] In the third stage t3, please refer to Figure 6, the stage transfer signal terminal ST(n+Y) of the n+Y stage outputs a high level to the gate of the pull-down transistor T41 to turn on the pull-down transistor T41, and the first control node Q is connected to the first low potential line VSSQ through the source and drain of the pull-down transistor T41 to pull the potential of the first control node Q down to the first low potential, so that the first pull-up transistor T21, the second pull-up transistor T211 and the stage transfer transistor T22 are turned off.

[0056] At the same time, the clock signal line CK(n+Y) of the n+Y stage outputs a high level to the gate of the first inverting transistor T51 to turn on the first inverting transistor T51, and the second high potential line VDD pulls the third control node S to a high potential through the source and drain of the first inverting transistor T51; and the high potential of the third control node S is transmitted to the gate of the third inverting transistor T53 to turn on the third inverting transistor T53, and the high level of the second high potential line VDD pulls the second control node P to a high potential through the source and drain of the third inverting transistor T53.

[0057] In this embodiment, since the potential of the second control node P is a high potential, the first regulating transistor T32, the second regulating transistor T321, the third regulating transistor T42, the fourth regulating transistor T412 and the fifth regulating transistor T72 can be turned on, and the first control node Q is connected to the first low potential line VSSQ through the source and drain of the third inverter transistor T53. At the same time, the first control node Q can also be connected to the first low potential line VSSQ through the source and drain of the fourth inverter transistor T54 and the source and drain of the fifth inverter transistor T55. The gate signal terminal G(n) of the nth stage is connected to the first low potential line VSSQ. The source and drain of the first inverting transistor T51 are connected to the second low potential line VSSG, the gate signal terminal G(n+1) of the n+1th stage, the source and drain of the second inverting transistor T52 are connected to the first low potential line VSSQ, and the stage transmission signal terminal ST(n) of the nth stage is connected to the first low potential line VSSQ via the source and drain of the fourth inverting transistor T54, so as to pull down the potentials of the first control node Q, the stage transmission signal terminal ST(n) of the nth stage, and the gate signal terminal G(n+1) of the n+1th stage to the first low potential, and pull down the potential of the gate signal terminal G(n) of the nth stage to the second low potential.

[0058] In the fourth phase t4, referring to FIG7 , the stage transmission signal terminal ST(n+Y) of the n+Y stage outputs a low level to the gate of the pull-down transistor T41 to turn off the pull-down transistor T41; the clock signal line CK(n+Y) of the n+Y stage outputs a low level to the gate of the first inverter transistor T51 to turn off the first inverter transistor T51; the clock signal line CK(n+YX) of the n+YX stage outputs a high level to the gate of the sixth inverter transistor T511 to turn on the sixth inverter transistor T511, and the third control node S is connected to the first low potential line VSSQ through the source and drain of the sixth inverter transistor T511, and the potential of the third control node S is pulled down to a low potential to turn off the third inverter transistor T53; at the same time, the clock signal line CK(n+YX) of the n+YX stage outputs a high level to the gate of the fifth inverter transistor T55 to turn on the fifth inverter transistor T55, and the second control node P is connected to the first low potential line VSSQ through the source and drain of the fifth inverter transistor T55, and the potential of the second control node P is pulled down to a low potential.

[0059] It should be noted that the timing control diagram in Figure 2 is illustrated using the example of all transistors in the gate drive circuit being N-type transistors. The transistors in the gate drive circuit of this application can also be P-type transistors, or a mixture of P-type transistors or N-type transistors, and different types of transistors have different timing control diagrams.

[0060] 8 , the present application further proposes a display panel 200, which includes a display portion 300 and the aforementioned gate drive circuit 100 disposed on one side of the display portion. The display panel 200 may be a liquid crystal display panel, an organic light emitting diode display panel, or a micro light emitting diode display panel.

[0061] This application also proposes a display device comprising a terminal body and the aforementioned display panel, the terminal body and display panel being integrated into one body. The terminal body may be a device such as a circuit board bound to the display panel. The display device may include electronic devices such as mobile phones, televisions, and laptop computers.

[0062] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0063] The above is a detailed introduction to a display panel and a display terminal provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, comprising N cascaded GOA units, wherein: The n-th level GOA unit is any one of the N GOA units, and the n-th level GOA unit includes a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintaining module, the pull-up control module and the pull-up module are connected to a first control node, the pull-down module is electrically connected to the first control node and a first potential line, and the pull-down maintaining module is electrically connected to the first control node and a second potential line; The pull-up control module receives the first-stage transmission signal in the first stage and pulls up the first control node to a first high potential; The pull-up module receives a first clock signal and outputs a first gate drive signal to a gate signal terminal of the nth stage according to the potential of the first control node, and the pull-up module receives a second clock signal and outputs a second gate drive signal to a gate signal terminal of the n+1th stage according to the potential of the first control node; The pull-down module receives the second-stage transmission signal in the third stage, and pulls down the potential of the first control node to a first low potential; The pull-down holding module receives a third clock signal in the third phase, pulls down the potential of the gate signal end of the nth stage to a second DC low level, and pulls down the potential of the gate signal end of the n+1th stage to the first low level.

2. The gate drive circuit according to claim 1, wherein: The pull-up control module is connected to the level transmission signal end of the nXth level, the first control node, the first high potential line and the pull-down maintaining module, and the level transmission signal end of the nXth level is used to output the first level transmission signal; Among them, the pull-up control module includes a pull-up control transistor, the gate of the pull-up control transistor is connected to the first-level signal transmission end, the source of the pull-up control transistor is connected to the first high potential line, and the drain of the pull-up control transistor is connected to the first control node and the pull-down maintaining module.

3. The gate driving circuit according to claim 1, wherein: The pull-up module includes a first pull-up unit and a second pull-up unit, the first pull-up unit is connected to the first control node, the clock signal line of the nth stage, and the gate signal end of the nth stage, and the second pull-up unit is connected to the first control node, the clock signal line of the n+1th stage, and the gate signal end of the n+1th stage; The clock signal line of the nth stage is used to provide the first clock signal, and the clock signal line of the (n+1)th stage is used to provide the second clock signal.

4. The gate driving circuit according to claim 3, wherein: The first pull-up unit comprises a first pull-up transistor, a gate of the first pull-up transistor is connected to the first control node, a source of the first pull-up transistor is connected to the clock signal line of the nth stage, and a drain of the first pull-up transistor is connected to the gate signal terminal of the nth stage; The second pull-up unit includes a second pull-up transistor, a gate of the second pull-up transistor is connected to the first control node, a source of the second pull-up transistor is connected to the clock signal line of the n+1th stage, and a drain of the second pull-up transistor is connected to the gate signal terminal of the n+1th stage.

5. The gate driving circuit according to claim 4, wherein: The pull-up module further includes a stage transmission unit, and the stage transmission unit includes a stage transmission transistor; The gate of the stage-pass transistor is connected to the first control node, the source of the stage-pass transistor is connected to the first clock signal line, and the drain of the stage-pass transistor is connected to the stage-pass signal terminal of the nth stage.

6. The gate driving circuit according to claim 3, wherein: The pull-down module includes a pull-down transistor, a gate of the pull-down transistor is connected to the level transmission signal end of the n+Yth level, a source of the pull-down transistor is connected to the first control node, a drain of the pull-down transistor is connected to the first low potential line, and the level transmission signal end of the n+Yth level is used to provide the second level transmission signal.

7. The gate driving circuit according to claim 3, wherein: The pull-down maintaining module includes an inverter and a voltage regulating unit. The voltage regulating unit and the inverter are connected to a second control node. The inverter is used to control the potential of the second control node.

8. The gate driving circuit according to claim 7, wherein: The voltage regulating unit includes a first regulating transistor, a second regulating transistor, a third regulating transistor, a fourth regulating transistor and a fifth regulating transistor; The gate of the first regulating transistor is connected to the second control node, the source of the first regulating transistor is connected to the gate signal terminal of the nth stage, and the drain of the first regulating transistor is connected to the second low potential line; The gate of the second regulating transistor is connected to the second control node, the source of the second regulating transistor is connected to the gate signal terminal of the n+1th stage, and the drain of the second regulating transistor is connected to the first low potential line; The gate of the third regulating transistor is connected to the second control node, the source of the third regulating transistor is connected to the first control node, and the drain of the third regulating transistor is connected to the first low potential line; The gate of the fourth regulating transistor and the gate of the fifth regulating transistor are connected to the second control node, the source of the fourth regulating transistor is connected to the first control node, the drain of the fourth regulating transistor and the source of the fifth regulating transistor are connected to the stage transmission signal terminal of the nth stage, and the drain of the fifth regulating transistor is connected to the first low potential line.

9. The gate driving circuit according to claim 8, wherein: The inverter includes a first inverting transistor, a second inverting transistor, a third inverting transistor, a fourth inverting transistor, a fifth inverting transistor, and a sixth inverting transistor; The gate of the first inverting transistor is connected to the clock signal line of the n+Yth stage, the source of the first inverting transistor and the source of the third inverting transistor are connected to the second high potential line, the drain of the first inverting transistor and the gate of the third inverting transistor are connected to the third control node, and the drain of the third inverting transistor is connected to the second control node; The gate of the second inverting transistor and the gate of the fourth inverting transistor are connected to the drain of the pull-up transistor, the source of the second inverting transistor is connected to the third control node, the source of the fourth inverting transistor and the source of the fifth inverting transistor are connected to the second control node, and the drain of the second inverting transistor, the drain of the fourth inverting transistor, and the drain of the fifth inverting transistor are connected to the first low potential line; The gate of the sixth inverter transistor and the gate of the fifth inverter transistor are connected to the clock signal line of the n+YXth stage, the source of the sixth inverter transistor is connected to the third control node, and the drain of the sixth inverter transistor is connected to the first low potential line.

10. The gate driving circuit according to claim 9, wherein: The clock signal line of the n+Yth stage is used to output a third clock signal, and the clock signal line of the n+YXth stage is used to output a fourth clock signal. The third clock signal and the fourth clock signal are mutually coupled signals.

11. The gate driving circuit according to claim 10, wherein: The inverter further includes a reset transistor, a gate of the reset transistor is connected to a reset signal line, a source of the reset transistor is connected to the second high potential line, and a drain of the reset transistor is connected to the second control node.

12. The gate driving circuit according to claim 3, wherein: The gate driving circuit includes m clock signal lines, and X is greater than or equal to (m / 2)-1 and less than or equal to (m / 2)+1.

13. The gate driving circuit according to claim 1, wherein: The n-th level GOA unit further includes a bootstrap capacitor, a first plate of the bootstrap capacitor is connected to the first control node and the pull-up module, and a second plate of the bootstrap capacitor is connected to the n-th level gate signal terminal and the pull-down maintaining module.

14. A display panel, wherein: The display panel includes a gate driving circuit, the gate driving circuit includes N cascaded GOA units, wherein the n-th level GOA unit is any one of the N GOA units, the n-th level GOA unit includes a pull-up control module, a pull-up module, a pull-down module and a pull-down maintaining module, the pull-up control module and the pull-up module are connected to a first control node, the pull-down module is electrically connected to the first control node and a first potential line, and the pull-down maintaining module is electrically connected to the first control node and a second potential line; The pull-up control module receives the first-stage transmission signal in the first stage and pulls up the first control node to a first high potential; The pull-up module receives a first clock signal and outputs a first gate drive signal to a gate signal terminal of the nth stage according to the potential of the first control node, and the pull-up module receives a second clock signal and outputs a second gate drive signal to a gate signal terminal of the n+1th stage according to the potential of the first control node; The pull-down module receives the second-stage transmission signal in the third stage, and pulls down the potential of the first control node to a first low potential; The pull-down holding module receives a third clock signal in the third phase, pulls down the potential of the gate signal end of the nth stage to a second DC low level, and pulls down the potential of the gate signal end of the n+1th stage to the first low level.

15. The display panel according to claim 14, wherein: The pull-up module includes a first pull-up unit and a second pull-up unit, the first pull-up unit is connected to the first control node, the clock signal line of the nth stage, and the gate signal end of the nth stage, and the second pull-up unit is connected to the first control node, the clock signal line of the n+1th stage, and the gate signal end of the n+1th stage; The clock signal line of the nth stage is used to provide the first clock signal, and the clock signal line of the (n+1)th stage is used to provide the second clock signal.

16. The display panel according to claim 15, wherein: The pull-down maintaining module includes an inverter and a voltage regulating unit. The voltage regulating unit and the inverter are connected to a second control node. The inverter is used to control the potential of the second control node.

17. The display panel according to claim 16, wherein: The voltage regulating unit includes a first regulating transistor, a second regulating transistor, a third regulating transistor, a fourth regulating transistor and a fifth regulating transistor; The gate of the first regulating transistor is connected to the second control node, the source of the first regulating transistor is connected to the gate signal terminal of the nth stage, and the drain of the first regulating transistor is connected to the second low potential line; The gate of the second regulating transistor is connected to the second control node, the source of the second regulating transistor is connected to the gate signal terminal of the n+1th stage, and the drain of the second regulating transistor is connected to the first low potential line; The gate of the third regulating transistor is connected to the second control node, the source of the third regulating transistor is connected to the first control node, and the drain of the third regulating transistor is connected to the first low potential line; The gate of the fourth regulating transistor and the gate of the fifth regulating transistor are connected to the second control node, the source of the fourth regulating transistor is connected to the first control node, the drain of the fourth regulating transistor and the source of the fifth regulating transistor are connected to the stage transmission signal terminal of the nth stage, and the drain of the fifth regulating transistor is connected to the first low potential line.

18. The display panel according to claim 17, wherein: The inverter includes a first inverting transistor, a second inverting transistor, a third inverting transistor, a fourth inverting transistor, a fifth inverting transistor, and a sixth inverting transistor; The gate of the first inverting transistor is connected to the clock signal line of the n+Yth stage, the source of the first inverting transistor and the source of the third inverting transistor are connected to the second high potential line, the drain of the first inverting transistor and the gate of the third inverting transistor are connected to the third control node, and the drain of the third inverting transistor is connected to the second control node; The gate of the second inverting transistor and the gate of the fourth inverting transistor are connected to the drain of the pull-up transistor, the source of the second inverting transistor is connected to the third control node, the source of the fourth inverting transistor and the source of the fifth inverting transistor are connected to the second control node, and the drain of the second inverting transistor, the drain of the fourth inverting transistor, and the drain of the fifth inverting transistor are connected to the first low potential line; The gate of the sixth inverter transistor and the gate of the fifth inverter transistor are connected to the clock signal line of the n+YXth stage, the source of the sixth inverter transistor is connected to the third control node, and the drain of the sixth inverter transistor is connected to the first low potential line.

19. The display panel according to claim 18, wherein: The clock signal line of the n+Yth stage is used to output a third clock signal, and the clock signal line of the n+YXth stage is used to output a fourth clock signal. The third clock signal and the fourth clock signal are mutually coupled signals.

20. The display panel according to claim 19, wherein: The inverter further includes a reset transistor, a gate of the reset transistor is connected to a reset signal line, a source of the reset transistor is connected to the second high potential line, and a drain of the reset transistor is connected to the second control node.

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