Array substrate, display panel, and display apparatus

Abstract

An array substrate (11), a display panel (10), and a display apparatus (100). The array substrate (11) comprises a substrate (111), a buffer layer (112), and a thin film transistor (T). The buffer layer (112) is arranged on the substrate (111), and comprises a first buffer layer (1121) and a second buffer layer (1122). The first buffer layer (1121) is arranged between the second buffer layer (1122) and the substrate (111). The refractive index of the first buffer layer (1121) is greater than the refractive index of the substrate (111) and the refractive index of the second buffer layer (1122). The ratio of the refractive index of the first buffer layer (1121) to the refractive index of the substrate (111) is smaller than or equal to 1.25. The thin film transistor (T) is arranged on the side of the buffer layer (112) away from the substrate (111).

Description

Array substrate, display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Liquid Crystal Displays (LCDs) typically consist of a backlight module and a liquid crystal dimming box. The LCD dimming box is composed of a thin-film transistor (TFT) backplane and a color filter substrate. The brightness and quality of the image displayed by the LCD dimming box depend largely on the backlight's transmittance through the LCD dimming box.

[0003] Therefore, how to improve the backlight transmittance of the liquid crystal dimming box is a technical problem that needs to be solved. Technical issues

[0004] The purpose of this application is to provide an array substrate, a display panel and a display device to increase the transmittance of light through the array substrate and improve the stability of the thin film transistors on the array substrate, thereby improving the display effect of the display panel and the display device. Technical Solutions

[0005] In a first aspect, the present application provides an array substrate, comprising:

[0006] substrate;

[0007] a buffer layer disposed on the substrate and comprising a first buffer layer and a second buffer layer, the first buffer layer being disposed between the second buffer layer and the substrate, the refractive index of the first buffer layer being greater than the refractive index of the substrate and the refractive index of the second buffer layer, and the ratio of the refractive index of the first buffer layer to the refractive index of the substrate being less than or equal to 1.25; and

[0008] The thin film transistor is arranged on a side of the buffer layer away from the substrate.

[0009] In some embodiments, a ratio of a refractive index of the first buffer layer to a refractive index of the substrate is greater than or equal to 1.02 and less than or equal to 1.15.

[0010] In some embodiments, a material of the first buffer layer is the same as a material of the second buffer layer.

[0011] In some embodiments, the refractive index of the second buffer layer is less than the refractive index of the substrate.

[0012] In some embodiments, materials of the first buffer layer and the second buffer layer both include silicon oxide, and the substrate includes a glass substrate.

[0013] In some embodiments, the refractive index of the substrate is greater than or equal to 1.45 and less than or equal to 1.55, the refractive index of the first buffer layer is greater than or equal to 1.5 and less than or equal to 1.7, and the refractive index of the second buffer layer is greater than or equal to 1.4 and less than or equal to 1.55.

[0014] In some embodiments, the thickness of the first buffer layer is greater than the thickness of the second buffer layer.

[0015] In some embodiments, the buffer layer further comprises:

[0016] The third buffer layer is disposed between the substrate and the first buffer layer. The material of the third buffer layer is the same as that of the first buffer layer, and the refractive index of the third buffer layer is smaller than that of the first buffer layer.

[0017] In some embodiments, a material of the third buffer layer includes silicon oxide.

[0018] In some embodiments, the thickness of the first buffer layer is greater than the thickness of the third buffer layer.

[0019] In some embodiments, the thickness of the first buffer layer is greater than or equal to 1500 angstroms and less than or equal to 2500 angstroms, and the thickness of the third buffer layer is greater than or equal to 300 angstroms and less than or equal to 600 angstroms.

[0020] In a second aspect, the present application further provides a display panel, comprising:

[0021] An array substrate, comprising:

[0022] substrate;

[0023] a buffer layer disposed on the substrate and comprising a first buffer layer and a second buffer layer, wherein the first buffer layer is disposed between the second buffer layer and the substrate, the refractive index of the first buffer layer is greater than the refractive index of the substrate and the refractive index of the second buffer layer, and the ratio of the refractive index of the first buffer layer to the refractive index of the substrate is less than or equal to 1.25; and

[0024] The thin film transistor is arranged on a side of the buffer layer away from the substrate.

[0025] In a third aspect, the present application further provides a display device, comprising:

[0026] The display panel includes an array substrate, and the array substrate includes:

[0027] substrate;

[0028] a buffer layer disposed on the substrate and comprising a first buffer layer and a second buffer layer, wherein the first buffer layer is disposed between the second buffer layer and the substrate, the refractive index of the first buffer layer is greater than the refractive index of the substrate and the refractive index of the second buffer layer, and the ratio of the refractive index of the first buffer layer to the refractive index of the substrate is less than or equal to 1.25; and

[0029] a thin film transistor, disposed on a side of the buffer layer away from the substrate; and

[0030] The backlight module is located on the back side of the light emitting side of the display panel. Beneficial effects

[0031] The buffer layer is disposed on the substrate and includes a first buffer layer and a second buffer layer. The first buffer layer is disposed between the second buffer layer and the substrate. The refractive index of the first buffer layer is greater than that of the substrate and the second buffer layer. The ratio of the refractive index of the first buffer layer to that of the substrate is less than or equal to 1.25. With this configuration, the ratio of the refractive index of the first buffer layer to that of the substrate is small, the refractive index of the first buffer layer is close to that of the substrate, and the refractive index of the first buffer layer is greater than that of the second buffer layer. The backlight transmits a high rate of light through the substrate, the first buffer layer, and the second buffer layer in sequence, thereby improving the light transmittance through the array substrate. Furthermore, the refractive index of the first buffer layer is greater than that of the substrate, resulting in a high density. The first buffer layer has excellent ion blocking capabilities for the substrate, thereby alleviating the problem of ion diffusion into the thin-film transistor, which can cause threshold voltage drift. Therefore, the array substrate of the present application balances the transmittance of backlight and the stability of the thin-film transistor, thereby improving the transmittance of backlight through the display panel, the operating stability of the display panel, and the display quality of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic cross-sectional view of a display device according to some embodiments of the present application.

[0033] FIG2 is a schematic diagram of a cross-sectional structure of a display panel according to some embodiments of the present application.

[0034] FIG3 is a schematic diagram of the cross-sectional structure of the buffer layer according to some embodiments of the present application.

[0035] FIG4 is a schematic diagram of the cross-sectional structure of the buffer layer according to some other embodiments of the present application.

[0036] FIG5 is a schematic diagram of the cross-sectional structure of the buffer layer of Comparative Example 1.

[0037] FIG6 shows the test results of the backlight transmittance of the array substrate when the buffer layers of Example 1 and Example 2 of the present application and the buffer layer of Comparative Example 1 are respectively applied to the buffer layer of the array substrate shown in FIG2 .

[0038] FIG7 shows the test results of the threshold voltage of the thin film transistor changing with time under the action of bias voltage when the buffer layers of Example 1 and Example 2 and Comparative Example 1 of the present application are respectively applied to the buffer layer of the array substrate shown in FIG2 . Modes for Carrying Out the Invention

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0040] Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a schematic cross-sectional structural diagram of a display device according to some embodiments of the present application, and FIG. 2 is a schematic cross-sectional structural diagram of a display panel according to some embodiments of the present application.

[0041] As shown in FIG1 , the display device 100 includes a display panel 10 and a backlight module 20. The backlight module 20 is located on the back side of the display panel 10, which is the light-emitting side. The display panel 10 can be any of a vertical alignment (VA) liquid crystal display panel, a fringe field switching (FFS) liquid crystal display panel, an in-plane switching (IPS) liquid crystal display panel, and a twisted nematic (TN) liquid crystal display panel. The backlight module 20 is used to emit backlight. After the backlight passes through the display panel 10, the display device 100 can realize display.

[0042] As shown in Figures 1 and 2, the display panel 10 includes an array substrate 11, an opposing substrate 12, and a liquid crystal layer 13. The array substrate 11 and the opposing substrate 12 are disposed opposite each other. The liquid crystal layer 13 is disposed between the array substrate 11 and the opposing substrate 12. The array substrate 11 includes a base 111, a buffer layer 112 disposed on the base 111, and thin-film transistors T. The buffer layer 112 is disposed between the thin-film transistors T and the base 111. The opposing substrate 12 includes an opposing substrate 121 disposed opposite the base 111.

[0043] The substrate 111 and the opposing substrate 121 are both light-transmissive to increase the backlight's transmittance through the substrate 111 and the opposing substrate 121. In some embodiments, the substrate 111 and the opposing substrate 121 each comprise a transparent glass substrate, but are not limited thereto. It is understood that the substrate 111 and the opposing substrate 121 may also each comprise a transparent organic substrate. The refractive index of the substrate 111 and the opposing substrate 121 is greater than or equal to 1.45 and less than or equal to 1.55. For example, the refractive index of the substrate 111 and the opposing substrate 121 is 1.45, 1.48, 1.50, 1.51, 1.52, or 1.55.

[0044] The thin film transistor T includes a gate electrode 114 , an active layer 113 , a source electrode 1151 and a drain electrode 1152 .

[0045] In some embodiments, the thin film transistor T is a top-gate thin film transistor. When the thin film transistor T is a top-gate thin film transistor, the active layer 113 is disposed on the surface of the buffer layer 112 away from the substrate 111. The gate 114 is located on the side of the active layer 113 away from the substrate 111. The source electrode 1151 and the drain electrode 1152 are located on the side of the active layer 113 away from the substrate 111 and are in contact with the active layer 113. A gate insulating layer 116 is disposed between the active layer 113 and the gate 114. The gate insulating layer 116 includes a silicon oxide layer. The refractive index of the gate insulating layer 116 is greater than or equal to 1.4 and less than or equal to 1.55. An interlayer insulating layer 117 is disposed between the gate 114 and the source electrode 1151 and the drain electrode 1152. The interlayer insulating layer 117 includes at least one of a silicon oxide layer and a silicon nitride layer.

[0046] In some embodiments, the active layer 113 includes at least one of polycrystalline silicon, amorphous silicon, single crystal silicon, and metal oxide. In a specific embodiment, the active layer 113 includes polycrystalline silicon.

[0047] In other embodiments, the thin film transistor T may also be a bottom-gate thin film transistor. In this case, the gate electrode 114 is disposed on the buffer layer 112. The active layer 113 is disposed on the side of the gate electrode 114 away from the substrate 111, with a gate insulating layer 116 disposed between the active layer 113 and the gate electrode 114. The source electrode 1151 and the drain electrode 1152 are disposed on the side of the active layer 113 away from the substrate 111 and are in contact with the active layer 113. An interlayer insulating layer 117 may also be disposed between the source electrode 1151 and the drain electrode 1152 and the active layer 113.

[0048] The buffer layer 112 is disposed on the substrate 111 and is in direct contact with the substrate 111. The buffer layer 112 is used to block ions in the substrate 111, such as Na + , K +, diffused into the active layer 113 of the thin film transistor T, thereby improving the problem of threshold voltage shift caused by ion diffusion into the thin film transistor T. After the backlight is incident on the display panel 10, it needs to pass through the array substrate 11, the liquid crystal layer 13, and the opposing substrate 12 before being emitted from the display panel 10. Therefore, the backlight needs to pass through the buffer layer 112, which also affects the transmittance of the backlight through the display panel 10.

[0049] It should be noted that, after a large number of experimental analyses, the inventors of the present application have found that, generally, the greater the refractive index of the film layer, the lower the etching rate of the film layer, and the higher the density of the film layer. The higher the density of the film layer, the better the film layer's barrier performance to ions. Moreover, the more similar the refractive indices of two adjacent film layers are, the higher the transmittance of light through the two film layers. Based on these findings, some embodiments of the present application improve the buffer layer 112, while increasing the transmittance of the buffer layer 112 to backlight, ensuring the buffer layer 112's barrier performance to ions, thereby improving the performance stability of the thin film transistor T.

[0050] 3 , which is a schematic cross-sectional view of a buffer layer according to some embodiments of the present invention. The buffer layer 112 includes a first buffer layer 1121 and a second buffer layer 1122 . The first buffer layer 1121 is disposed between the second buffer layer 1122 and the substrate 111 .

[0051] The first buffer layer 1121 serves to prevent ions in the substrate 111 from diffusing into the active layer 113 of the thin film transistor T. The first buffer layer 1121 has a higher density than the second buffer layer 1122 , and accordingly, an etching rate of the first buffer layer 1121 is lower than an etching rate of the second buffer layer 1122 .

[0052] The second buffer layer 1122 plays a role in heat preservation, so as to ensure better crystallization of the active layer 113. In this way, the performance of the thin film transistor T is more stable.

[0053] The refractive index of the first buffer layer 1121 is greater than that of the substrate 111 and the second buffer layer 1122. The ratio of the refractive index of the first buffer layer 1121 to the refractive index of the substrate 111 is less than or equal to 1.25. With this configuration, the ratio of the refractive index of the first buffer layer 1121 to the refractive index of the substrate 111 is small, the refractive index of the first buffer layer 1121 is close to that of the substrate 111, and the refractive index of the first buffer layer 1121 is greater than that of the second buffer layer 1122. Backlight transmits significantly through the substrate 111, the first buffer layer 1121, and the second buffer layer 1122, thereby improving backlight transmittance through the array substrate 11. Furthermore, the refractive index of the first buffer layer 1121 is greater than that of the substrate 111, resulting in improved density. The first buffer layer 1121 provides excellent barrier properties for ions in the substrate 111, thereby improving the stability of the thin-film transistor T, which could be affected by ion diffusion.

[0054] Therefore, by adopting the design of the above-mentioned buffer layer 112, the array substrate 11 of the present application can balance the transmittance of the backlight and the stability of the thin film transistor, thereby improving the transmittance of the backlight through the display panel 10, and improving the working stability of the display panel 10, thereby improving the display effect of the display device 100.

[0055] In some embodiments, the ratio of the refractive index of the first buffer layer 1121 to the refractive index of the substrate 111 is greater than or equal to 1.02 and less than or equal to 1.15. With this arrangement, the refractive index of the first buffer layer 1121 is greater and the density of the first buffer layer 1121 is higher. The first buffer layer 1121 has better barrier properties to ions in the substrate 111, further improving the problem of ion diffusion into the thin film transistor T and affecting its stability. At the same time, the ratio of the refractive index of the first buffer layer 1121 to the refractive index of the substrate 111 is smaller, the backlight has a higher transmittance through the substrate 111 and the first buffer layer 1121, and the backlight transmittance through the array substrate 11 is further improved.

[0056] Optionally, the ratio of the refractive index of the first buffer layer 1121 to the refractive index of the substrate 111 is greater than or equal to 1.03 and less than or equal to 1.18. Optionally, the ratio of the refractive index of the first buffer layer 1121 to the refractive index of the substrate 111 is greater than or equal to 1.05 and less than or equal to 1.15. The ratio of the refractive index of the first buffer layer 1121 to the refractive index of the substrate 111 is greater than or equal to 1.08 and less than or equal to 1.12.

[0057] In some embodiments, the material of the first buffer layer 1121 is the same as that of the second buffer layer 1122. With this configuration, when the refractive index of the first buffer layer 1121 is greater than that of the second buffer layer 1122, the difference between the refractive indices of the first and second buffer layers 1121, 1122 is reduced, and the refractive indices of the first and second buffer layers 1121, 1122 are similar, further improving the backlight transmittance through the buffer layer 112, and thereby improving the backlight transmittance through the array substrate 11. Furthermore, when the material of the first and second buffer layers 1121, 1122 is the same, controlling the formation conditions of the first and second buffer layers 1121, 1122 allows for continuous formation of the first and second buffer layers 1121, 1122, thereby simplifying the process of manufacturing the array substrate 11.

[0058] In some embodiments, when the material of the first buffer layer 1121 is the same as that of the second buffer layer 1122, the refractive index of the first buffer layer 1121 is greater than that of the second buffer layer 1122. This configuration allows the first buffer layer 1121 to have a higher density than the second buffer layer 1122, resulting in the first buffer layer 1121 having better ion barrier properties against the substrate 111. The second buffer layer 1122 is relatively sparse, making its manufacture less difficult.

[0059] In some embodiments, when the density of the first buffer layer 1121 is greater than the density of the second buffer layer 1122, the first buffer layer 1121 can be formed by at least one of chemical vapor deposition and atomic deposition to produce a dense first buffer layer 1121. The second buffer layer 1122 can be formed by chemical vapor deposition. In a specific embodiment, both the first buffer layer 1121 and the second buffer layer 1122 are formed by chemical vapor deposition to facilitate the continuous preparation of the first buffer layer 1121 and the second buffer layer 1122, thereby simplifying the manufacturing process of the array substrate 11.

[0060] In some embodiments, the difference between the refractive index of the first buffer layer 1121 and the refractive index of the second buffer layer 1122 is greater than 0 and less than or equal to 0.35. Thus, the difference between the refractive index of the first buffer layer 1121 and the refractive index of the second buffer layer 1122 is small, further improving the backlight transmittance through the buffer layer 112, and thereby improving the backlight transmittance through the array substrate 11. Optionally, the difference between the refractive index of the first buffer layer 1121 and the refractive index of the second buffer layer 1122 is greater than 0.05 and less than or equal to 0.3. Optionally, the difference between the refractive index of the first buffer layer 1121 and the refractive index of the second buffer layer 1122 is greater than 0.08 and less than or equal to 0.2. Optionally, the difference between the refractive index of the first buffer layer 1121 and the refractive index of the second buffer layer 1122 is greater than 0.09 and less than or equal to 0.15.

[0061] In some embodiments, the refractive index of the second buffer layer 1122 is less than the refractive index of the substrate 111. Thus, the second buffer layer 1122 can be prepared by a common process, which reduces the difficulty of manufacturing the second buffer layer 1122.

[0062] In some embodiments, the refractive index of the first buffer layer 1121 is greater than or equal to 1.5 and less than or equal to 1.7. Alternatively, the refractive index of the first buffer layer 1121 is greater than or equal to 1.52 and less than or equal to 1.65. Alternatively, the refractive index of the first buffer layer 1121 is greater than or equal to 1.55 and less than or equal to 1.6.

[0063] In some embodiments, the refractive index of the second buffer layer 1122 is greater than or equal to 1.4 and less than or equal to 1.55. Alternatively, the refractive index of the second buffer layer 1122 is greater than or equal to 1.42 and less than or equal to 1.52. Alternatively, the refractive index of the second buffer layer 1122 is greater than or equal to 1.45 and less than or equal to 1.5.

[0064] In a specific embodiment, the materials of the first buffer layer 1121 and the second buffer layer 1122 both include silicon oxide, that is, the first buffer layer 1121 and the second buffer layer 1122 both include silicon oxide layers, but are not limited thereto. In this way, the buffer layer 112 adopts a double-layer full silicon oxide design. The refractive index of the first buffer layer 1121 and the second buffer layer 1122 tends to be the same as the refractive index of the substrate 111, which is beneficial to improving the transmittance of the backlight through the array substrate 11. Moreover, the material of the second buffer layer 1122 both includes silicon oxide. The second buffer layer 1122 has good thermal insulation properties, which facilitates the crystallization of the active layer 113 under the thermal insulation effect of the second buffer layer 1122. It is understandable that the materials of the first buffer layer 1121 and the second buffer layer 1122 can also be other materials different from silicon oxide, as long as the above-mentioned refractive index and thermal insulation requirements are met.

[0065] It should be noted that, after experimental verification, in the relevant technology, when the buffer layer includes a silicon nitride layer, the transmittance of light through the silicon nitride layer is approximately 98.5%. In some embodiments of the present application, when the buffer layer 112 includes a first buffer layer 1121, the transmittance of light through the first buffer layer 1121 is approximately 99.99%. Therefore, the first buffer layer 1121 with a large refractive index and high density can not only significantly improve the transmittance of light through the buffer layer 112, but also has good blocking performance for ions. The first buffer layer 1121 and the second buffer layer 1122 both include a silicon oxide layer, and the refractive index of the first buffer layer 1121 is greater than the refractive index of the second buffer layer 1122. Such a setting can significantly improve the transmittance of backlight through the buffer layer 112, and can also have good blocking performance for ions in the substrate 111, and ensure that the active layer 113 can be better crystallized.

[0066] In some embodiments, the thickness of the first buffer layer 1121 is greater than the thickness of the second buffer layer 1122. Thus, the thickness of the first buffer layer 1121 is greater, and the first buffer layer 1121 has better barrier properties against ions in the substrate 111, further improving the problem of ions in the substrate 111 diffusing into the thin film transistor T and affecting its stability.

[0067] In some embodiments, the thickness of the first buffer layer 1121 is greater than or equal to 1500 angstroms and less than or equal to 2500 angstroms. Alternatively, the thickness of the first buffer layer 1121 is greater than or equal to 1600 angstroms and less than or equal to 2200 angstroms. Alternatively, the thickness of the first buffer layer 1121 is greater than or equal to 1800 angstroms and less than or equal to 2100 angstroms. If the thickness of the first buffer layer 1121 is too thin, it is not conducive to improving the barrier properties of the buffer layer 112. If the thickness of the first buffer layer 1121 is too thick, it increases the difficulty of manufacturing the first buffer layer 1121.

[0068] In some embodiments, the thickness of the second buffer layer 1122 is greater than or equal to 300 angstroms and less than or equal to 1200 angstroms. Alternatively, the thickness of the second buffer layer 1122 is greater than or equal to 400 angstroms and less than or equal to 1000 angstroms. Alternatively, the thickness of the second buffer layer 1122 is greater than or equal to 450 angstroms and less than or equal to 800 angstroms. If the thickness of the second buffer layer 1122 is too thin, it may not be conducive to ensuring the thermal insulation performance of the second buffer layer 1122. If the thickness of the second buffer layer 1122 is too thick, the manufacturing time of the second buffer layer 1122 will increase.

[0069] The array substrate 11 further includes a pixel electrode 118, which is connected to the drain electrode 1152 of the thin film transistor T. The pixel electrode 118 is disposed on a side of the source electrode 1151 and the drain electrode 1152 away from the substrate 111. A passivation layer 119 is disposed between the pixel electrode 118 and the source electrode 1151 and the drain electrode 1152. The pixel electrode 118 is formed of a transparent conductive material. The passivation layer 119 is formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0070] The opposing substrate 12 also includes a filter layer 122 and a common electrode layer 123. In some embodiments, the filter layer 122 is disposed on the surface of the opposing substrate 121 near the substrate 111, and is disposed between the common electrode layer 123 and the opposing substrate 121. The filter layer 122 includes a color filter layer and a black matrix layer. The color filter layer includes multiple color resist units of different colors. The black matrix layer includes multiple openings, and the multiple color resist units are respectively disposed in the multiple openings. In other embodiments, the filter layer 122 and the common electrode layer 123 can also be disposed on the array substrate 11.

[0071] Please refer to Figure 4, which is a schematic diagram of the cross-sectional structure of the buffer layer of other embodiments of the present application. The buffer layer 112 shown in Figure 4 is basically similar to the buffer layer 112 shown in Figure 3, and the similarities are not repeated here. The difference includes that the buffer layer 112 also includes a third buffer layer 1123. The third buffer layer 1123 is arranged between the substrate 111 and the first buffer layer 1121. The material of the third buffer layer 1123 is the same as that of the first buffer layer 1121, and the refractive index of the third buffer layer 1123 is less than the refractive index of the first buffer layer 1121. Therefore, the buffer layer 112 adopts a three-layer stacked design, and the first buffer layer 1121 with a larger refractive index is sandwiched between two third buffer layers 1123 with a smaller refractive index and the second buffer layer 1122.

[0072] In other embodiments of the present application, in addition to the buffer layer 112 comprising a first buffer layer 1121 and a second buffer layer 1122, a third buffer layer 1123 is additionally provided between the first buffer layer 1121 and the substrate 111. The material of the third buffer layer 1123 is the same as that of the first buffer layer 1121, and the refractive index of the third buffer layer 1123 is lower than that of the first buffer layer 1121. This arrangement allows the third buffer layer 1123 with a lower refractive index to be formed first, followed by the first buffer layer 1121 with a higher refractive index. The load of the film-forming equipment is first adjusted to the film-forming conditions corresponding to the third buffer layer 1123, and then to the film-forming conditions for the first buffer layer 1121. This makes the load of the film-forming equipment easier to control, thereby improving the stability of the equipment used to manufacture the first buffer layer 1121. Consequently, the performance of the first buffer layer 1121 with a higher refractive index produced by this equipment is more controllable, and the barrier properties of the first buffer layer 1121 are improved, further alleviating the problem of ion diffusion into the thin-film transistor T affecting its stability.

[0073] It should be noted that the first buffer layer 1121 is a film layer with a high density, and its manufacturing is relatively difficult. When forming the first buffer layer 1121, the load of the equipment for manufacturing the first buffer layer 1121 is directly adjusted to the film forming conditions corresponding to the first buffer layer 1121, and the load of the equipment is difficult to control. A third buffer layer 1123 is added between the first buffer layer 1121 and the substrate 111. The material of the third buffer layer 1123 is the same as that of the first buffer layer 1121, and the refractive index of the third buffer layer 1123 is less than the refractive index of the first buffer layer 1121. With such a setting, the load of the equipment for manufacturing the first buffer layer 1121 can be gradually increased, which can effectively improve the film forming load of the equipment, effectively improve the stability of the production line equipment, and improve the performance of the thin film transistor T.

[0074] In other embodiments, the thickness of the first buffer layer 1121 is greater than the thickness of the third buffer layer 1123. This configuration allows the first buffer layer 1121 to be thicker and provide better barrier properties to ions in the substrate 111, further alleviating the problem of ions in the substrate 111 diffusing into the thin-film transistor T and affecting its stability. Furthermore, the third buffer layer 1123 is thinner, shortening the manufacturing time of the third buffer layer 1123.

[0075] In other embodiments, the thickness of the third buffer layer 1123 is greater than or equal to 300 angstroms and less than or equal to 600 angstroms. Alternatively, the thickness of the third buffer layer 1123 is greater than or equal to 400 angstroms and less than or equal to 550 angstroms. Alternatively, the thickness of the third buffer layer 1123 is greater than or equal to 450 angstroms and less than or equal to 520 angstroms. If the third buffer layer 1123 is too thin, it may not be conducive to the gradual increase in the load of the device. If the second buffer layer 1122 is too thick, the manufacturing time of the third buffer layer 1123 is too long, and the thickness of the display panel 100 is too thick.

[0076] In other embodiments, the material of the third buffer layer 1123 includes silicon oxide, that is, the third buffer layer 1123 also includes a silicon oxide layer. The refractive index of the third buffer layer 1123 is greater than or equal to 1.4 and less than or equal to 1.55. Alternatively, the refractive index of the third buffer layer 1123 is greater than or equal to 1.42 and less than or equal to 1.52. Alternatively, the refractive index of the third buffer layer 1123 is greater than or equal to 1.45 and less than or equal to 1.5.

[0077] In some other embodiments, the refractive index of the third buffer layer 1123 may be the same as the refractive index of the second buffer layer 1122. In some other embodiments, the thickness of the third buffer layer 1123 may be the same as the thickness of the second buffer layer 1122.

[0078] In other embodiments, the refractive index of the third buffer layer 1123 is the same as the refractive index of the second buffer layer 1122. In this way, the third buffer layer 1123 and the second buffer layer 1122 can be formed under the same conditions, simplifying the manufacturing process of the array substrate 11. In still other embodiments, the refractive index of the third buffer layer 1123 can also be different from the refractive index of the second buffer layer 1122. For example, the refractive index of the third buffer layer 1123 can also be greater than the refractive index of the second buffer layer 1122, so that the density of the third buffer layer 1123 is higher than that of the second buffer layer 1122, further improving the barrier performance of the buffer layer 112.

[0079] In another specific embodiment, the first buffer layer 1121, the second buffer layer 1122, and the third buffer layer 1123 all include silicon oxide layers. The refractive index of the first buffer layer 1121 is greater than the refractive index of the second buffer layer 1122 and the refractive index of the third buffer layer 1123. Correspondingly, the density of the first buffer layer 1121 is greater than the density of the second buffer layer 1122 and the density of the third buffer layer 1123. Therefore, the buffer layer 112 is composed of three all-silicon oxide layers, the refractive index of the third buffer layer 1123 is close to the refractive index of the substrate 111, the first buffer layer 1121 has a higher density and a higher refractive index, and the second buffer layer 1122 has a lower refractive index.

[0080] In yet other embodiments, the buffer layer 112 may further include a fourth buffer layer disposed between the third buffer layer 1123 and the substrate 111. The fourth buffer layer is made of the same material as the third buffer layer 1123, and has a refractive index lower than that of the third buffer layer 1123. This configuration gradually increases the load on the equipment used to manufacture the first buffer layer 1121, effectively improving the film-forming load of the equipment, enhancing the stability of the production line equipment, and improving the performance of the thin-film transistor T. In one specific embodiment, the fourth buffer layer comprises a silicon oxide layer.

[0081] It is understood that a third buffer layer 1123 and a fourth buffer layer may be provided, or two or more silicon oxide layers may be provided, depending on the refractive index of the first buffer layer 1121. In the direction from the substrate 111 to the first buffer layer 1121, the refractive index of the silicon oxide layer between the first buffer layer 1121 and the substrate 111 increases.

[0082] The following Table 1, Figures 6 and 7 are test results of the transmittance of the array substrate to backlight and the change of the threshold voltage of the thin film transistor over time under the action of bias voltage when the buffer layers of Example 1, Example 2 and Comparative Example 1 are applied to the buffer layer of the array substrate shown in Figure 2.

[0083] In Example 1, the buffer layer adopts the aforementioned double-layer all-silicon oxide design, comprising a first buffer layer 1121 and a second buffer layer 1122. The first buffer layer 1121 is disposed between the substrate 111 and the second buffer layer 1122. The first buffer layer 1121 is a dense silicon oxide layer with a refractive index of 1.57. The second buffer layer 1122 is also a sparse silicon oxide layer with a refractive index of 1.45. The refractive index of the substrate is 1.51.

[0084] In Example 2, the buffer layer adopts the above-mentioned three-layer all-silicon oxide design. The buffer layer includes a first buffer layer 1121, a second buffer layer 1122, and a third buffer layer 1123. The first buffer layer 1121 is arranged between the second buffer layer 1122 and the third buffer layer 1123. The third buffer layer 1123 is arranged between the substrate 111 and the first buffer layer 1121. The second buffer layer 1122 is arranged on the side of the first buffer layer 1121 away from the substrate 111. The first buffer layer 1121 is a dense silicon oxide layer, and the refractive index of the first buffer layer 1121 is 1.57. The second buffer layer 1122 is also a silicon oxide layer, and the refractive index of the second buffer layer 1122 is 1.45. The refractive index of the substrate is 1.51. The third buffer layer 1123 is also a silicon oxide layer, and the refractive index of the third buffer layer 1123 is 1.45.

[0085] In comparative example 1, the buffer layer includes a silicon nitride layer 31 and a silicon oxide layer 32. The silicon nitride layer 31 is disposed between the substrate 111 and the silicon oxide layer 32. The refractive index of the silicon nitride layer 31 is 1.92, the refractive index of the substrate is 1.51, and the refractive index of the silicon oxide layer is 1.45, as shown in FIG5 .

[0086] In addition, the test results of the thin-film transistor threshold voltage change over time are drift characteristic curves obtained by applying bias stress (BS) to the gate and source of the thin-film transistor. The threshold voltage drift value is equal to the difference between the threshold voltage of the thin-film transistor at a time of 2 hours and the threshold voltage at a time of 0 seconds.

[0087] Table 1 Test results of transmittance and threshold voltage drift values ​​of Example 1, Example 2 and Comparative Example 1

[0088] As shown in Table 1, compared to Comparative Example 1, the buffer layer designs of Examples 1 and 2 of the present application increase the array substrate's backlight transmittance by at least 1%. Testing has shown that when the display device is displaying, an increase in transmittance of at least 1% can increase the display brightness of the display device by at least 7%. Therefore, the increased backlight transmittance of the array substrate can significantly improve the display quality of the display device.

[0089] Furthermore, compared to Comparative Example 1, the buffer layer design of Example 2 of the present application significantly improves the threshold voltage drift over time of the thin-film transistor under the action of a vertical electric field (the electric field formed by the gate bias) and a horizontal electric field (the electric field formed by the source bias). Furthermore, compared to Example 1, the buffer layer design of Example 2 employs three all-silicon oxide layers, significantly improving the threshold voltage of the thin-film transistor.

[0090] Therefore, in some related technologies, the design of the buffer layer only considers its barrier properties while ignoring its impact on the display brightness of the display device. The technical solution of this application improves the film layer of the buffer layer, ensuring that the backlight transmittance through the display panel is improved while also improving the stability of the thin-film transistor, thus balancing the issues of backlight transmittance and device stability, and improving the display effect of the display device.

[0091] It should be noted that the array substrate 11 can also be applied to other display panels, such as organic light-emitting diode (OLED) display panels, sub-millimeter LED (SMD) display panels, micro-LED (micro-LED) display panels, and quantum dot display panels. The design of the array substrate 11 can also be applied to spliced ​​display panels. When applied to these display panels, the array substrate 11 includes at least a base 111, a buffer layer 112, and thin-film transistors T.

[0092] The description of the above embodiments is only used to help understand the technical solutions and core ideas of this application; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, wherein: include: substrate; a buffer layer disposed on the substrate and comprising a first buffer layer and a second buffer layer, wherein the first buffer layer is disposed between the second buffer layer and the substrate, the refractive index of the first buffer layer is greater than the refractive index of the substrate and the refractive index of the second buffer layer, and the ratio of the refractive index of the first buffer layer to the refractive index of the substrate is less than or equal to 1.25; and The thin film transistor is arranged on a side of the buffer layer away from the substrate.

2. The array substrate according to claim 1, wherein: A ratio of a refractive index of the first buffer layer to a refractive index of the substrate is greater than or equal to 1.02 and less than or equal to 1.

15.

3. The array substrate according to claim 1, wherein: The material of the first buffer layer is the same as that of the second buffer layer.

4. The array substrate according to claim 1, wherein: The refractive index of the second buffer layer is lower than the refractive index of the substrate.

5. The array substrate according to claim 1, wherein: The materials of the first buffer layer and the second buffer layer both include silicon oxide, and the substrate includes a glass substrate.

6. The array substrate according to claim 1, wherein: The refractive index of the substrate is greater than or equal to 1.45 and less than or equal to 1.55, the refractive index of the first buffer layer is greater than or equal to 1.5 and less than or equal to 1.7, and the refractive index of the second buffer layer is greater than or equal to 1.4 and less than or equal to 1.

55.

7. The array substrate according to claim 1, wherein: The thickness of the first buffer layer is greater than the thickness of the second buffer layer.

8. The array substrate according to claim 1, wherein: The buffer layer further comprises: The third buffer layer is disposed between the substrate and the first buffer layer. The material of the third buffer layer is the same as that of the first buffer layer, and the refractive index of the third buffer layer is smaller than that of the first buffer layer.

9. The array substrate according to claim 8, wherein: The material of the third buffer layer includes silicon oxide.

10. The array substrate according to claim 8, wherein: The thickness of the first buffer layer is greater than the thickness of the third buffer layer.

11. The array substrate according to claim 8, wherein: The thickness of the first buffer layer is greater than or equal to 1500 angstroms and less than or equal to 2500 angstroms, and the thickness of the third buffer layer is greater than or equal to 300 angstroms and less than or equal to 600 angstroms.

12. A display panel, wherein: include: An array substrate comprises: substrate; a buffer layer disposed on the substrate and comprising a first buffer layer and a second buffer layer, wherein the first buffer layer is disposed between the second buffer layer and the substrate, the refractive index of the first buffer layer is greater than the refractive index of the substrate and the refractive index of the second buffer layer, and the ratio of the refractive index of the first buffer layer to the refractive index of the substrate is less than or equal to 1.25; and The thin film transistor is arranged on a side of the buffer layer away from the substrate.

13. The display panel according to claim 12, wherein: A ratio of a refractive index of the first buffer layer to a refractive index of the substrate is greater than or equal to 1.02 and less than or equal to 1.

15.

14. The display panel according to claim 12, wherein: The material of the first buffer layer is the same as that of the second buffer layer.

15. The display panel according to claim 12, wherein: The refractive index of the second buffer layer is lower than the refractive index of the substrate.

16. The display panel according to claim 12, wherein: The materials of the first buffer layer and the second buffer layer both include silicon oxide, and the substrate includes a glass substrate.

17. The display panel according to claim 12, wherein: The refractive index of the substrate is greater than or equal to 1.45 and less than or equal to 1.55, the refractive index of the first buffer layer is greater than or equal to 1.5 and less than or equal to 1.7, and the refractive index of the second buffer layer is greater than or equal to 1.4 and less than or equal to 1.55; The thickness of the first buffer layer is greater than the thickness of the second buffer layer.

18. The display panel according to claim 12, wherein: The buffer layer further comprises: The third buffer layer is disposed between the substrate and the first buffer layer. The material of the third buffer layer is the same as that of the first buffer layer, and the refractive index of the third buffer layer is smaller than that of the first buffer layer.

19. The display panel according to claim 18, wherein: The material of the third buffer layer includes silicon oxide.

20. A display device, wherein: include: The display panel comprises an array substrate, and the array substrate comprises: substrate; a buffer layer disposed on the substrate and comprising a first buffer layer and a second buffer layer, wherein the first buffer layer is disposed between the second buffer layer and the substrate, the refractive index of the first buffer layer is greater than the refractive index of the substrate and the refractive index of the second buffer layer, and the ratio of the refractive index of the first buffer layer to the refractive index of the substrate is less than or equal to 1.25; and a thin film transistor, disposed on a side of the buffer layer away from the substrate; and The backlight module is located on the back side of the light emitting side of the display panel.

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