Touch display panel and touch display apparatus

Abstract

Provided in the present disclosure are a touch display panel and a touch display apparatus. The touch display panel comprises: a substrate; a first electrode layer, which is located on one side of the substrate and comprises a plurality of first signal lines extending in a first direction and a plurality of electrode portions connected to the plurality of first signal lines; a touch layer, which is located on the same side of the substrate as the first electrode layer and comprises a plurality of touch electrodes spaced apart from each other; a first insulating layer, which is located between the first electrode layer and the touch layer and has a plurality of first via holes, wherein at least some of the plurality of electrode portions are conductively connected to the touch electrodes by means of the first via holes; and a plurality of pixel electrodes, which are located on the same side of the substrate as the first electrode layer, wherein an orthographic projection of each electrode portion on the substrate is only located at an orthographic projection of a gap between some adjacent pixel electrodes on the substrate.

Description

Touch display panel and touch display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on September 18, 2023, with application number 202311203946.3 and invention name "Touch Display Panel and Touch Display Device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a touch display panel and a touch display device. Background Art

[0004] Liquid crystal display (LCD) is the most widely used flat panel display at present. It has gradually become a display with high resolution color screen used in various electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, desktop computers or laptop computers.

[0005] With the advancement of liquid crystal display technology, people have placed higher demands on LCD display quality, appearance design, and human-machine interface. Touch technology has become a hot topic due to its convenient operation and high degree of integration. Touch technology has developed rapidly in recent years, and a variety of touch panels have entered mass production. Existing touch panels can be divided into types based on the location of the touch sensor: those with the touch sensor covered on the liquid crystal cell (on-cell), those embedded within the liquid crystal cell (in-cell), and those with the touch sensor external to the display panel (out-cell). In-cell touch panels, among them, embed the touch function within the liquid crystal pixels. This not only further reduces the thickness of the entire device, but also allows for co-production with the LCD, eliminating the need for additional manufacturing steps and maintaining visibility in bright environments such as outdoor environments. Therefore, research on in-cell touch panels is becoming increasingly popular.

[0006] Summary of the Invention

[0007] The present disclosure provides a touch display panel and a touch display device. The touch display panel includes:

[0008] substrate;

[0009] A first electrode layer is located on one side of the substrate and includes: a plurality of first signal lines extending along a first direction, and a plurality of electrode portions connected to the plurality of first signal lines;

[0010] a touch layer, located on the same side of the substrate as the first electrode layer, and comprising a plurality of touch electrodes spaced apart from each other;

[0011] a first insulating layer, located between the first electrode layer and the touch layer, having a plurality of first via holes; at least some of the plurality of electrode portions are electrically connected to the touch electrodes through the first via holes;

[0012] a plurality of pixel electrodes, located on the same side of the substrate as the first electrode layer;

[0013] The orthographic projection of the electrode portion on the substrate is only located at the orthographic projection of the substrate between a portion of the gaps between adjacent pixel electrodes.

[0014] In a possible implementation manner, all the electrode portions are electrically connected to the touch electrode through the first via hole.

[0015] In a possible implementation, the minimum distance between at least some adjacent two electrode portions projected onto the substrate in the first direction is greater than the length of the pixel electrode projected onto the substrate along the first direction.

[0016] In a possible implementation, the minimum distance between at least two adjacent electrode portions in the second direction and their projections on the substrate is greater than the length of the pixel electrode's projection on the substrate along the second direction, and the second direction is perpendicular to the first direction.

[0017] In a possible implementation, the touch layer includes: a plurality of touch electrode groups extending along the first direction and arranged along the second direction;

[0018] The plurality of electrode portions include: a plurality of electrode portion groups extending along the first direction and arranged along the second direction, wherein an orthographic projection of the touch electrode group on the substrate at least partially overlaps with an orthographic projection of the electrode portion group on the substrate;

[0019] At least one of the plurality of electrode portion groups includes: a plurality of sub-electrode portion groups arranged along the first direction, the sub-electrode portion group including at least one electrode portion; an orthographic projection of the touch electrode on the substrate overlaps at least partially with an orthographic projection of the sub-electrode portion group on the substrate;

[0020] The sub-electrode groups in the same electrode group are staggered and distributed.

[0021] In a possible implementation manner, each electrode portion in the same sub-electrode portion group is located in a gap between two adjacent columns of pixel electrodes.

[0022] In a possible implementation manner, each of the electrode portions in the same sub-electrode portion group is electrically connected to the same first signal line.

[0023] In a possible implementation manner, each of the electrode portions located in the same touch electrode region is located in a gap between two adjacent columns of pixel electrodes.

[0024] In a possible implementation manner, the electrode portions located in the same touch electrode region are all electrically connected to the same first signal line.

[0025] In a possible implementation manner, the distance between two adjacent sub-electrode groups in the second direction is substantially equal to the width of the touch electrode in the second direction.

[0026] In a possible implementation, in the second direction, intervals between at least two adjacent sub-electrode groups are substantially equal.

[0027] In a possible implementation, the electrode portion includes: a first type of electrode portion;

[0028] The touch display panel further includes: an array substrate and an opposite substrate arranged opposite to each other; the opposite substrate is provided with a first spacer on a side facing the array substrate; the first spacer includes a first surface opposite to the array substrate;

[0029] The orthographic projection of at least part of the first-type electrode portion on the substrate has an overlapping area with the orthographic projection of the first surface on the substrate.

[0030] In a possible implementation manner, an orthographic projection of the first via hole on the substrate does not overlap with an orthographic projection of the first surface on the substrate.

[0031] In a possible implementation manner, the electrode portion further includes: a second type of electrode portion; an orthographic projection of the second type of electrode portion on the substrate and an orthographic projection of the first surface on the substrate do not overlap with each other.

[0032] In a possible implementation, the electrode portion includes a first type of electrode portion and a second type of electrode portion, and a length of the first type of electrode portion in the second direction is greater than a length of the second type of electrode portion in the second direction.

[0033] In a possible embodiment, the touch display panel further includes: a plurality of gate lines extending along a second direction; at least one gate line among the plurality of gate lines includes: a plurality of first sub-gate line portions sequentially distributed along the second direction; adjacent first sub-gate line portions are disconnected;

[0034] The touch display panel further includes: a transition portion located on a side of the electrode portion facing away from the first signal line; an orthographic projection of the transition portion on the substrate and an orthographic projection of the first sub-gate line portion on the substrate having an overlapping area;

[0035] The touch display panel further includes: a second insulating layer located between the first electrode layer and the gate line, the second insulating layer having a second via hole; the transfer portion is electrically connected to the first sub-gate line portion through the second via hole.

[0036] In a possible embodiment, the gate line further includes: a connecting end connected to an end portion of the first sub-gate line portion; a width of the connecting end in the first direction is greater than a width of the first sub-gate line portion in the first direction;

[0037] One end of the transition portion is connected to the connecting end of a first sub-gate line portion through a second via hole, and the other end of the transition portion is connected to the connecting end of another first sub-gate line portion through another second via hole, so that adjacent first sub-gate line portions are connected through the transition portion.

[0038] In a possible implementation manner, the gate line further includes: a second sub-gate line portion connected to the first sub-gate line portion;

[0039] The width of the second sub-gate line portion in the first direction is greater than the width of the first sub-gate line portion in the first direction; the width of the second sub-gate line portion in the first direction is substantially equal to the width of the connecting end in the first direction.

[0040] In a possible implementation manner, an orthographic projection of the second sub-gate line portion on the substrate does not overlap with an orthographic projection of the electrode portion on the substrate.

[0041] In a possible implementation manner, the touch display panel further includes: a first electrode of a transistor; the electrode portion includes a second type of electrode portion;

[0042] At least partially between adjacent first signal lines, the transition portion is located between the orthographic projection of the first electrode of the transistor on the substrate and the orthographic projection of the second-type electrode portion on the substrate.

[0043] In a possible implementation manner, a length of the second-type electrode portion in the second direction is smaller than a length of the first electrode of the transistor in the second direction.

[0044] In a possible implementation, a length of the first electrode of the transistor in the second direction is smaller than a length of the transition portion in the first direction.

[0045] In a possible embodiment, the electrode portion includes a first type of electrode portion, and the length of the first type of electrode portion in the second direction is greater than the length of the first electrode of the transistor in the second direction and less than the length of the transition portion in the second direction.

[0046] In a possible implementation, the touch display panel further includes: a plurality of data lines extending along the first direction, a first electrode of a transistor electrically connected to the pixel electrode;

[0047] A first signal line and a data line form a signal routing group. In the same signal routing group, the electrode portion is electrically connected to a side of the first signal line away from the data line, and the first electrode of the transistor is located on a side of the data line away from the first signal line.

[0048] In a possible implementation manner, an orthographic projection of an extension line of an outer edge of the electrode portion parallel to the second direction on the substrate overlaps with an orthographic projection of the first electrode of the transistor on the substrate.

[0049] In a possible implementation manner, the first signal line and the data line are located in the same layer.

[0050] In a possible implementation manner, the touch layer is located between the layer where the data lines are located and the first electrode layer;

[0051] The touch electrode includes: a third via hole; the pixel electrode passes through the third via hole and is connected to the first electrode of the transistor.

[0052] In a possible implementation, the touch electrode further includes a first slit extending along the first direction, and an orthographic projection of the first slit on the substrate at least partially overlaps with an orthographic projection of the first signal line on the substrate.

[0053] An embodiment of the present disclosure further provides a touch display device, which includes the touch display panel provided in the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] FIG1A is a schematic diagram of a stack of some film layers provided by an embodiment of the present disclosure;

[0055] FIG1B is a second schematic diagram of a stack of partial film layers provided in an embodiment of the present disclosure;

[0056] FIG1C is a third schematic diagram of a stack of partial film layers provided in an embodiment of the present disclosure;

[0057] FIG1D is a fourth schematic diagram of a stack of partial film layers provided in an embodiment of the present disclosure;

[0058] FIG1E is a fifth schematic diagram of a stack of partial film layers provided in an embodiment of the present disclosure;

[0059] FIG2A is a schematic top view of a touch display panel according to an embodiment of the present disclosure;

[0060] FIG2B is a schematic diagram of the stacking of other film layers except the pixel electrode layer in FIG2A ;

[0061] FIG2C is a schematic diagram of a single film layer of the light shielding layer in FIG2A ;

[0062] FIG2D is a schematic diagram of a single film layer of the active layer in FIG2A;

[0063] FIG2E is a schematic diagram of a single film layer of the gate line layer in FIG2A ;

[0064] FIG2F is a schematic diagram of a single film layer of the interlayer dielectric layer in FIG2A ;

[0065] FIG2G is a schematic diagram of a single film layer of the data line layer in FIG2A ;

[0066] FIG2H is a schematic diagram of a single film layer of the flat layer in FIG2A ;

[0067] FIG2I is a schematic diagram of a single film layer of the touch electrode layer in FIG2A ;

[0068] FIG2J is a schematic diagram of a single film layer of the passivation layer in FIG2A ;

[0069] FIG2K is a schematic diagram of a single film layer of the pixel electrode layer in FIG2A ;

[0070] FIG2L is a schematic cross-sectional view along the dotted line EF in FIG2A ;

[0071] FIG3 is a schematic top view of a touch display panel provided by an embodiment of the present disclosure under a microscope;

[0072] FIG4 is a schematic diagram of a touch display panel provided by an embodiment of the present disclosure;

[0073] FIG5A is a schematic diagram of a top view of a touch display panel;

[0074] FIG5B is an enlarged schematic diagram of the lower left corner of FIG5A ;

[0075] FIG6 is a schematic diagram showing a comparison of reflectivity of different types of array substrates;

[0076] FIG7 is a schematic diagram of a table comparing reflectivity of different types of array substrates. DETAILED DESCRIPTION

[0077] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0078] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0079] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0080] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0081] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0082] In the Touch In Cell structure, the touch function is achieved through the touch pad (TPM Pad) made of the data line layer. The TPM Pad exists in each group of pixels, but a large part of it is floating (Dummy) and has no practical function. The Dummy TPM Pad will directly lead to the following two problems: On the one hand, it will cause display afterimages. Specifically, in terms of the reflectivity of the array substrate, the Dummy TPM Pad will increase the reflectivity of the array substrate by about 1%. In turn, during the photolithography patterning process, it will cause overexposure, affecting the underlying alignment film layer, resulting in uneven alignment film patterning, further leading to afterimage problems during display. On the other hand, the TPM Pad will cause the space between adjacent traces to become smaller, and the risk of metal residue (Remain) caused by particles falling between adjacent traces will increase accordingly, resulting in the connection of adjacent signal lines and reducing product yield.

[0083] In view of this, referring to Figures 1A-1E, 2A-2K, and Figure 3, Figure 1A is one of the stacking schematic diagrams of some film layers provided in an embodiment of the present disclosure, Figure 1B is a second stacking schematic diagram of some film layers provided in an embodiment of the present disclosure, Figure 1C is a third stacking schematic diagram of some film layers provided in an embodiment of the present disclosure, Figure 1D is a fourth stacking schematic diagram of some film layers provided in an embodiment of the present disclosure, Figure 1E is a fifth stacking schematic diagram of some film layers provided in an embodiment of the present disclosure, Figure 2A is one of the top view schematic diagrams of a touch display panel provided in an embodiment of the present disclosure, and Figure 2B is other than the pixel electrode layer in Figure 2A. FIG2C is a schematic diagram of a single film layer of the light shielding layer in FIG2A , FIG2D is a schematic diagram of a single film layer of the active layer in FIG2A , FIG2E is a schematic diagram of a single film layer of the gate line layer in FIG2A , FIG2F is a schematic diagram of a single film layer of the interlayer dielectric layer in FIG2A , FIG2G is a schematic diagram of a single film layer of the data line layer in FIG2A , FIG2H is a schematic diagram of a single film layer of the planar layer in FIG2A , FIG2I is a schematic diagram of a single film layer of the touch electrode layer in FIG2A , FIG2J is a schematic diagram of a single film layer of the passivation layer in FIG2A , and FIG2K is a schematic diagram of a single film layer of the pixel electrode layer in FIG2A . The present disclosure provides a touch display panel, comprising:

[0084] substrate;

[0085] The first electrode layer 2 is located on one side of the substrate and includes: a plurality of first signal lines 21 extending along a first direction X, and a plurality of electrode portions 22 connected to the plurality of first signal lines 21, namely a touch pad (TPM Pad);

[0086] The touch layer 3 is located on the same side of the substrate as the first electrode layer 2 and includes a plurality of touch electrodes 30 spaced apart from each other;

[0087] The first insulating layer is located on the same side of the substrate as the first electrode layer 2 and between the first electrode layer 2 and the touch layer 3, and has a plurality of first via holes K1; at least some of the plurality of electrode portions 22 are electrically connected to the touch electrodes 30 through the first via holes K1;

[0088] A plurality of pixel electrodes 5 are located on the same side of the substrate as the first electrode layer 2;

[0089] The orthographic projection of the electrode portion 22 on the substrate is only located at the orthographic projection of a portion of the gap between adjacent pixel electrodes 5 on the substrate. Specifically, the gap between adjacent pixel electrodes 5 may be the gap between two adjacent pixel electrodes 5 in the first direction X. Specifically, the orthographic projection of the electrode portion 22 on the substrate may also overlap with the orthographic projection of the pixel electrode 5 on the substrate.

[0090] In the embodiment of the present disclosure, the electrode portion 22 is only located at the orthographic projection of the substrate between some adjacent pixel electrodes 5. Compared with the conventional structure, the electrode portion 22 is provided next to each pixel electrode 5. The electrode portion 22 of the embodiment of the present disclosure is only located next to some pixel electrodes 5. It can improve the problem that too many electrode portions 22 will cause the reflectivity of the array substrate to be too high, affecting the exposure of the alignment film, causing uneven patterning of the alignment film layer, and further causing the problem of afterimage during display. It can also improve the problem that too many electrode portions 22 will cause the space between the first signal line 21 and the data line 22 to become smaller, and particles falling between the first signal line 21 and the data line 22 will cause metal residue, resulting in the connection between the first signal line 21 and the data line 22, and low product yield. Moreover, it does not increase the cost of the touch display panel. That is, the embodiment of the present disclosure can improve the afterimage performance of the touch display panel without increasing the cost, and at the same time reduce the defective rate of the touch display panel.

[0091] It should be noted that in order to clearly illustrate the relationship between the various film layers of the touch panel in FIG2B , the pixel electrode 5 is not shown. The embodiments of the present disclosure are not limited to this. In specific implementation, the touch display panel may be provided with a pixel electrode 5 , as shown in FIG2A .

[0092] In one possible implementation, the touch layer 3 also functions as a common electrode layer, loading signals in a time-sharing manner to implement touch and display functions. For example, during a first period, a common signal is loaded onto the touch layer 3, causing it to function as a common electrode layer and implement the display function. During a second period, a touch signal is loaded onto the touch layer, causing it to function as a touch layer and implement the touch monitoring function.

[0093] In one possible embodiment, all electrode portions 22 are electrically connected to the touch electrodes 30 through the first vias K1. That is, in the disclosed embodiment, the remaining electrode portions 22 are all effective electrode portions 22 electrically connected to the touch electrodes 30, and there are no floating electrode portions 22 that are not loaded with electrical signals. This minimizes the adverse effects of floating electrode portions 22 that are not loaded with electrical signals on the touch display panel.

[0094] In a possible implementation, some of the electrode portions 22 are electrically connected to the touch electrodes 30 through the first via holes K1. That is, in the embodiment of the present disclosure, a small number of floating electrode portions 22 that are not loaded with electrical signals may also exist.

[0095] In one possible embodiment, the minimum distance between at least some of the adjacent two electrode portions 22 in the first direction X and the orthographic projections thereof on the substrate is greater than the length of the orthographic projection of the pixel electrode 5 on the substrate along the first direction X. Specifically, for example, as shown in FIG3 , along the first direction X, the minimum distance b1 between two adjacent electrode portions 22 (the positions indicated by the boxes in FIG3 are where the electrode portions 22 are located) and the orthographic projections thereof on the substrate is greater than the length b2 of the orthographic projection of one pixel electrode 5 on the substrate in the same direction; that is, for example, in the column direction of the first direction X, an electrode portion 22 may be provided at least every other pixel electrode 5.

[0096] Specifically, the minimum distance between all two adjacent electrode portions 22 on the substrate's positive projection in the first direction X may be greater than the length of the pixel electrode 5 on the substrate's positive projection along the first direction X, that is, the minimum distance between any two adjacent electrode portions 22 on the substrate's positive projection may be greater than the length of the pixel electrode 5 on the substrate's positive projection along the first direction X.

[0097] In one possible embodiment, the minimum distance between at least two adjacent electrode portions 22 along the second direction Y and their orthographic projections on the substrate is greater than the length of the pixel electrode 5 along the second direction Y and the orthographic projection on the substrate 2, and the second direction Y is perpendicular to the first direction X. That is, as shown in FIG3 , in the row direction along the second direction Y, an electrode portion 22 may be provided at least every other pixel electrode 5.

[0098] Specifically, the minimum distance between the orthographic projections of any two adjacent electrode portions 22 on the substrate along the second direction Y may be greater than the length of the orthographic projection of the pixel electrode 5 on the substrate 2 along the second direction Y. In other words, the minimum distance between the orthographic projections of any two adjacent electrode portions 22 on the substrate along the second direction Y may be greater than the length of the orthographic projection of the pixel electrode 5 on the substrate 2 along the second direction Y.

[0099] In one possible embodiment, along at least one of the first direction X and the second direction Y, the minimum distance between two adjacent electrode portions 22 projected onto the substrate is greater than the width of at least two pixel electrodes 5 projected onto the substrate in the same direction. That is, for example, as shown in FIG3 , in the first direction X, an electrode portion 22 may be provided for at least every other pixel electrode 5; and for another example, in the second direction Y, an electrode portion 22 may be provided for at least every other pixel electrode 5.

[0100] In a specific implementation, since the orthographic projection area of ​​the touch electrode 30 on the substrate is larger than the orthographic projection area of ​​the pixel electrode 5 on the substrate, the area where one touch electrode 30 is located can cover multiple pixel electrodes 5, and the electrode portion 22 is arranged around the pixel electrode 5. The area where one touch electrode 30 is located can also be covered by multiple electrode portions 22. Specifically, in one possible embodiment, referring to FIG4 , the touch layer 3 includes: multiple touch electrode groups C extending along a first direction X and arranged along a second direction Y; the multiple electrode portions 22 include: multiple electrode portion groups D extending along the first direction X and arranged along a second direction Y, the orthographic projection of the touch electrode group C on the substrate at least partially overlaps with the orthographic projection of the electrode portion group D on the substrate; specifically, the orthographic projection of the touch electrode group C on the substrate can cover the orthographic projection of the electrode portion group D on the substrate; specifically, the touch electrode group C corresponds one-to-one with the electrode portion group D, and the multiple electrode portions 22 in the area covered by the touch electrode group C can be regarded as the electrode portion group D;

[0101] At least one electrode portion group D among the multiple electrode portion groups D includes: multiple sub-electrode portion groups D0 arranged along the first direction X, the sub-electrode portion group D0 includes at least one electrode portion 22; the orthographic projection of the touch electrode 30 on the substrate overlaps with at least part of the orthographic projection of the sub-electrode portion group D0 on the substrate; specifically, the orthographic projection of the touch electrode 30 on the substrate covers the orthographic projection of the sub-electrode portion group D0 on the substrate; specifically, the touch electrode 30 corresponds one-to-one to the sub-electrode portion group D0, and the multiple electrode portions 22 in the area covered by the touch electrode 30 can be used as the sub-electrode portion group D0; the sub-electrode portion groups D0 in the same electrode portion group D are staggered. In the embodiment of the present disclosure, while removing the redundant electrode portion 22 to improve the afterimage of the touch display panel and increase the defective rate, different touch electrodes 30 are electrically connected to different first signal lines 21, so that the first signal line 21 can provide signals to different touch electrodes 30, and / or transmit the signal detected by the touch electrode 30 to the first signal line 21, and then transmit it to the control chip IC by the first signal line 21.

[0102] Specifically, for the staggered distribution of each sub-electrode group D0 in the same electrode group D, the side edge extension lines of the electrode parts 22 in different electrode groups D (for example, the right edge extension lines of the electrode parts 22 in different electrode groups D in Figure 4) do not overlap. Specifically, as shown in FIG4 , for the first touch electrode 30 in the first column from the left, the first touch electrode 30 from top to bottom may retain the electrode portion 22 around the second column of pixel electrodes 5, so as to be electrically connected to the first signal line 21 through the electrode portion 22 around the second column of pixel electrodes 5, and then connected to the IC, and the remaining electrode portions in the area where the touch electrode 30 is located are removed; for the second touch electrode 30 from top to bottom, the electrode portion 22 around the fourth column of pixel electrodes 5 may be retained, so as to be electrically connected to the first signal line 21 through the electrode portion 22 around the fourth column of pixel electrodes 5, and then connected to the IC, and the remaining electrode portions in the area where the touch electrode 30 is located are removed; for the third touch electrode 30 from top to bottom, the electrode portion 22 around the sixth column of pixel electrodes 5 may be retained, so as to be electrically connected to the first signal line 21 through the electrode portion 22 around the sixth column of pixel electrodes 5, and then connected to the IC, and the remaining electrode portions in the area where the touch electrode 30 is located are removed; that is, Each touch electrode 30 selects the electrode portion 22 next to a column of pixel electrodes 5 for connection to the control chip IC, and the rest are removed, and each touch electrode 30 is independently connected to each other without affecting each other; of course, the above is only an example of a connection method between the touch electrode 30 and the electrode portion 22, and the embodiment of the present disclosure is not limited to this, and other distribution methods can also be used. For example, the first touch electrode 30 from top to bottom corresponds to the electrode portion 22 retained around the second column of pixel electrodes 5, the second touch electrode 30 from top to bottom corresponds to the electrode portion 22 retained around the third column of pixel electrodes 5, and the third touch electrode 30 from top to bottom corresponds to the electrode portion 22 retained around the fourth column of pixel electrodes 5; for a column of touch electrodes 30, the electrode portions 5 around different columns of pixel electrodes 5 are selected at equal intervals from top to bottom to be connected to the touch electrode 30, which can make the electrode portion 22 and the first signal line layout 21 more simple and beautiful and match the design of a conventional control chip IC.

[0103] Specifically, for example, referring to FIG5A and FIG5B , FIG5A is a schematic top view of a structure of a first via hole connecting a conductive electrode portion and a touch electrode of a touch display panel, and FIG5B is an enlarged schematic diagram corresponding to the lower left corner of FIG5A . FIG5A shows three rows and five columns of touch electrodes 30, each of which covers a plurality of pixel electrodes 5. Specifically, for a column of touch electrodes 30, the hole groups provided in different touch electrodes 30 may be offset in sequence. For example, for the first column of touch electrodes 30 on the left, the second hole group K12 provided corresponding to the second touch electrode 30 from top to bottom may be offset to the right relative to the first hole group K11 provided corresponding to the first touch electrode 30 from top to bottom; the third hole group K13 provided corresponding to the third touch electrode 30 from top to bottom may be offset further to the right relative to the second hole group K12 provided corresponding to the second touch electrode 30 from top to bottom, and so on. The hole groups are offset in sequence to electrically connect different touch electrodes 30 in the same column to the corresponding electrode portion 22. Specifically, the first hole group K11 , the second hole group K12 , and the third hole group K13 may each include a plurality of first via holes K1 , and each first via hole K1 correspondingly exposes one electrode portion 22 .

[0104] It should be noted that FIG4 is a schematic illustration of a touch display panel having 3 rows and 4 columns of touch electrodes 30, and 3 rows and 6 columns of pixel electrodes 5 in the area where each touch electrode 30 is located. In practice, the touch display panel may include more rows and columns of touch electrodes 30, and the area where each touch electrode 30 is located may include more rows and columns of pixel electrodes 5. The embodiments of the present disclosure are not limited to this. Similarly, FIG4 is only a schematic illustration of the outer contour of the pixel electrode 5 being a rectangle. In practice, the pixel electrode 5 may also be of other shapes, and may also include slits. The embodiments of the present disclosure are not limited to this. In addition, FIG5B shows only a plurality of first vias K1 in order to clearly illustrate the distribution of the third control group K13, without showing other film layer structures. However, the embodiments of the present disclosure are not limited to this.

[0105] In a possible implementation, the area covered by one touch electrode 30 may only include the electrode portions 22 within the sub-electrode portion group D0 , and the electrode portions 22 in the area outside the sub-electrode portion group D0 may not be provided.

[0106] In one possible embodiment, as shown in FIG4 , each electrode portion 22 in the same sub-electrode portion group D0 is located in the same column and faces upward. Specifically, each electrode portion 22 in the same sub-electrode portion group D0 is located in the gap between two adjacent columns of pixel electrodes 5. Specifically, for example, as shown in FIG4 , the first sub-electrode portion group D0 on the left side, from top to bottom, is located in the gap between the first column of pixel electrodes 5 and the second column of pixel electrodes 5.

[0107] In one possible implementation, as shown in FIG4 , different sub-electrode section groups D0 of the same electrode section group D are located in the gaps between pixel electrodes 5 in different columns. For example, as shown in FIG4 , the first sub-electrode section group D0 from top to bottom on the left side is located in the gap between the first column of pixel electrodes 5 and the second column of pixel electrodes 5; for another example, the second sub-electrode section group D0 from top to bottom on the left side is located in the gap between the third column of pixel electrodes 5 and the fourth column of pixel electrodes 5.

[0108] In a possible implementation manner, as shown in FIG. 4 , each electrode portion 22 in the same sub-electrode portion group D0 is electrically connected to the same first signal line 21 .

[0109] In one possible embodiment, as shown in FIG4 , the electrode portions 22 within the region where the same touch electrode 30 is located are located in the same column direction. Specifically, the electrode portions 22 within the region where the same touch electrode 30 is located are located in the gap between two adjacent columns of pixel electrodes 5. Specifically, for example, as shown in FIG4 , the first sub-electrode portion group D0 from the left in the region where the first row of touch electrodes 30 is located is located in the gap between the first column of pixel electrodes 5 and the second column of pixel electrodes 5.

[0110] 4 , each electrode portion 22 within the same touch electrode 30 region is electrically connected to the same first signal line 21 . The region covered by the touch electrode 30 may not include an electrode portion 22 that is not electrically connected to the first signal line 21 .

[0111] In one possible embodiment, as shown in FIG4 , the spacing e1 between two adjacent sub-electrode groups D0 in the second direction Y is substantially equal to the width e2 of the touch electrode 30 in the second direction Y. That is, for the touch electrodes 20 in the second column from the left, the electrode portions 22 selected therefor for conducting with the first signal line 21 can correspond to the positions of the electrode portions 22 selected for conducting with the first signal line 21 in the first column from the left. That is, if the first touch electrode 20 from the top to the bottom in the first column from the left is conducting with the first signal line 21 via the electrode portions 22 surrounding the second column of pixel electrodes 5, then the first touch electrode 20 from the top to the bottom in the second column from the left can also be conducting with the corresponding first signal line 21 via the electrode portions 22 surrounding the second column of pixel electrodes 5 in the area covered by the touch electrode 20. This arrangement has the advantages of being regular, concise, and aesthetically pleasing, and compatible with conventional control chip ICs.

[0112] Specifically, as shown in Figure 4, the distance e1 between two adjacent sub-electrode groups D0 can be the distance between the sides of two adjacent electrode parts 22 in the same row that are electrically connected to the first signal line 21 (for example, the right side of the electrode part 22 connected to the first signal line 21 in Figure 2G).

[0113] Specifically, for the touch electrodes 30 in the same row, no other electrode portion 22 may be provided between two sub-electrode portion groups D0 within the corresponding coverage areas of adjacent touch electrodes 30. That is, as shown in FIG4 , in the area covered by the first row of touch electrodes 30, no other electrode portion 22 is provided between the first sub-electrode portion group D0 from the left and the second sub-electrode portion group D0 from the left.

[0114] In one possible embodiment, as shown in FIG4 , the spacing e1 between at least two adjacent sub-electrode segment groups D0 in the second direction Y is substantially equal. For example, within the area covered by the first row of touch electrodes 30, the distance between the second sub-electrode segment group D0 and the third sub-electrode segment group D0 is substantially equal to the distance between the third sub-electrode segment group D0 and the fourth sub-electrode segment group D0. Specifically, in a direction perpendicular to the first direction X, the spacing e1 between any adjacent sub-electrode segment groups D0 can be substantially equal.

[0115] In one possible embodiment, as shown in FIG2A , the electrode portion 22 includes: a first type of electrode portion 221; the touch display panel further includes: an array substrate and an opposing substrate arranged opposite to each other; the opposing substrate is provided with a first spacer PS1 on the side facing the array substrate, and the first spacer PS1 includes a first surface opposite to the array substrate (specifically, the first spacer PS1 may have a top surface and a bottom surface, wherein the bottom surface may be in contact with the opposing substrate, the top surface may be opposite to the array substrate, and the first surface may specifically be the top surface of the first spacer PS); the orthographic projection of at least part of the first type of electrode portion 221 on the substrate has an overlapping area with the orthographic projection of the first surface on the substrate. In another possible embodiment, the orthographic projection of part of the first type of electrode portion 221 on the substrate may not have an overlapping area with the orthographic projection of the first surface on the substrate, as shown in FIG2A .

[0116] It should be noted that the first spacer PS1 shown in FIG. 2A may be an orthographic projection of the first surface of the first spacer PS1 on the array substrate.

[0117] In one possible embodiment, as shown in FIG1B , the orthographic projection of the first via K1 on the substrate does not overlap with the orthographic projection of the first surface on the substrate 1. In the disclosed embodiment, the orthographic projection of the first via K1 on the substrate does not overlap with the orthographic projection of the first surface on the substrate 1. This prevents the first spacer PS1 from being positioned in the area where the first via K1 is located, which could affect the electrical connection between the electrode portion 22 and the touch electrode 30. Furthermore, when the first spacer PS1 is positioned in the area where the first via K1 is located, the contact surface is uneven, making it easy for the spacer PS1 to move and thus failing to provide stable support.

[0118] In a possible embodiment, as shown in Figure 2A, the opposing substrate may further be provided with a second spacer PS2; specifically, the height of the first spacer PS1 in a direction perpendicular to the substrate 1 may be greater than the height of the second spacer PS2 in a direction perpendicular to the substrate 1, that is, the first spacer PS1 may be a main spacer, and the second spacer PS2 may be a secondary spacer. In a specific implementation, the first surface of the first spacer PS1 may contact the array substrate, and the second spacer PS2 may not contact the array substrate; in the embodiment of the present disclosure, for the column where the first spacer PS1 is located, the length of the electrode portion 22 retained in the column in the second direction Y may be made longer (as the first type of electrode portion 221), and for the column where the first spacer PS is not provided, the electrode portion 22 may be made shorter (as the second type of electrode portion 222) to avoid the first spacer PS1 contacting the array substrate when the first spacer PS1 is placed at the position of the electrode portion 22 of the column. If the first spacer PS1 contacts the first via K1, it will affect the support effect.

[0119] During specific implementation, a second spacer PS2 may also be provided for the column where the first spacer PS is located. Since the second spacer PS2 may only contact the array substrate when the display panel is pressed, and may be in a non-contact state with the array substrate when not pressed, the orthographic projection of the second spacer PS2 on the substrate 1 may overlap with the orthographic projection of the first via hole K1, or may not overlap with the orthographic projection of the first via hole K1.

[0120] In a possible implementation, as shown in FIG1B , the electrode portion 22 further includes: a second-type electrode portion 222 ; the orthographic projection of the second-type electrode portion 222 on the substrate does not overlap with the orthographic projection of the first surface on the substrate.

[0121] In one possible embodiment, as shown in conjunction with FIG1B and FIG2G , the electrode portion 22 includes: a first type of electrode portion 221 and a second type of electrode portion 222; the length a1 of the first type of electrode portion 221 in the second direction Y is greater than the length a2 of the second type of electrode portion 222 in the second direction Y. In the disclosed embodiment, for the electrode portion 22 in the column where the first spacer PS1 is provided, the length of the electrode portion 22 in the first direction X can be made longer, serving as the first type of electrode portion 221; whereas for the electrode portion 22 in the column where the first spacer PS1 is not provided, the length of the electrode portion 22 can be made shorter, serving as the second type of electrode portion 222; thereby minimizing the adverse effects of the electrode portion 22 on the touch display panel.

[0122] In a possible embodiment, in combination with Figures 1C, 2E and 2F, the touch display panel further includes: a plurality of gate lines 6 extending along the second direction Y; at least one gate line 6 among the plurality of gate lines 6 includes: a plurality of first sub-gate line portions 61 sequentially distributed along the second direction Y; adjacent first sub-gate line portions 61 are disconnected; the touch display panel further includes: a transition portion 23 located on the side of the electrode portion 22 facing away from the first signal line 21; the orthographic projection of the transition portion 23 on the substrate has an overlapping area with the orthographic projection of the first sub-gate line portion 61 on the substrate; the touch display panel further includes: a second insulating layer 71 located between the first electrode layer 2 and the gate line 6, the second insulating layer 71 having a second via K2; the transition portion 23 is electrically connected to the first sub-gate line portion 61 through the second via K2. In the embodiment of the present disclosure, the gate line 6 is divided into a plurality of first sub-gate line portions 61 that are disconnected from each other, which can avoid the problem of static electricity being easily generated when the gate line 6 is too long, causing the gate line 6 to be easily burned.

[0123] In a possible embodiment, in combination with Figures 1C, 2E and 2F, the gate line 6 also includes: a connecting end 62 connected to the end of the first sub-gate line portion 61; the width d3 of the connecting end 62 in the first direction X is greater than the width d1 of the first sub-gate line portion 61 in the first direction X; one end of the transition portion 23 is connected to the connecting end 62 of a first sub-gate line portion 61 through a second via K2, and the other end of the transition portion 23 is connected to the connecting end 62 of another first sub-gate line portion 61 through another second via K2, so that adjacent first sub-gate line portions 61 are connected through the transition portion 23. In the embodiment of the present disclosure, when the electrode portion 22 is only provided around a portion of the pixel electrode 5, there can be more wiring space, and the position of the adapter portion 23 can be flexibly set as needed. Specifically, in order to avoid the problem that the gate line 6 is long and prone to static electricity, the adapter portion 23 is provided to perform a jumper design through the layer where the data line 25 is located. When the adapter portion 23 is located between the first pole 24 of the transistor and the electrode portion 22, the space (Space) between the first pole 24 of the transistor, the electrode portion 22 and the intermediate adapter portion 23 will become smaller, and the size of the electrode portion 22 will be compressed accordingly. At this time, the distance (Margin) between the outer edge of the first via K1 and the outer edge of the electrode portion 22 will become smaller, and the risk of metal residue (Remain) / broken wire (Open) will increase accordingly. In addition, the first via K1 will also be closer to the overlapping position of the layer where the gate line 6 and the data line 25 are located, increasing the risk of the spacer falling off the first via K1, resulting in poor display. Specifically, for example, in a 200PPI product, the space between the first electrode 24 of the transistor and the strip-shaped transition portion 23 is 3μm, which is the lower limit of the current design rules. When the PPI increases, if the space is still to be maintained above 3μm, the size of the transition portion 23 needs to be compressed; the overlap margin between the first via K1 and the electrode portion 22 is correspondingly reduced, increasing the problem of hole exposure / overlap offset, resulting in dark spots / flickering (Crack) or poor display of the first via K1 due to the spacer falling off; further, in the embodiment of the present disclosure, when the electrode portion 22 is only provided around part of the pixel electrode 5, the wiring distribution space of the transition portion 23 is larger, the wiring is more flexible, and can be actually adjusted according to the different designs of different models of touch display panels, and the overall yield risk is greatly reduced.

[0124] In one possible embodiment, as shown in FIG2E , the gate line 6 further includes: a second sub-gate line portion 63 connected to the first sub-gate line portion 61; a width d2 of the second sub-gate line portion 63 in the first direction X is greater than a width d1 of the first sub-gate line portion 61 in the first direction X; and a width d2 of the second sub-gate line portion 63 in the first direction X is substantially equal to a width d3 of the connecting end 62 in the first direction X. In the disclosed embodiment, the gate line 6 further includes a second sub-gate line portion 63 having a wider line width, which can reduce the resistance of the gate line 6 and improve the problem of the gate line 6 having a large line resistance affecting signal transmission.

[0125] In a possible embodiment, as shown in Figure 2E, the width d1 of the first sub-gate line portion 61 in the first direction X may be 1μm to 10μm; in a possible embodiment, the width d1 of the first sub-gate line portion 61 in the first direction X may be 2μm to 8μm; in a possible embodiment, the width d1 of the first sub-gate line portion 61 in the first direction X may be 2μm, 3μm, 3.5μm, 4μm, 5μm, 6μm, 7μm, or 8μm.

[0126] In a possible implementation, as shown in FIG. 2E , a width d2 of the second sub-gate line portion 63 in the first direction X may be substantially equal to a width d3 of the connecting end 62 in the first direction X.

[0127] In a possible embodiment, as shown in Figure 2E, the width d3 of the connecting end 62 in the first direction X may be 1 μm to 10 μm; in a possible embodiment, the width d3 of the connecting end 62 in the first direction X may be 3 μm to 8 μm; in a possible embodiment, the width d3 of the connecting end 62 in the first direction X may be 3 μm, 4 μm, 5 μm, 5.9 μm, 6 μm, 7 μm, or 8 μm.

[0128] In one possible embodiment, as shown in FIG1C , the orthographic projection of the second sub-gate line portion 63 on the substrate does not overlap with the orthographic projection of the electrode portion 22 (including the first-type electrode portion 21 and the second-type electrode portion 22 ) on the substrate. This prevents the second sub-gate line portion 63 and the electrode portion 22 from generating a large overlap capacitance that could affect signal transmission on the gate line 6 .

[0129] In a possible embodiment, in combination with what is shown in FIG2G , the touch display panel further includes: a first electrode 24 of a transistor; the electrode portion 22 includes a second type of electrode portion 222; and between at least some adjacent first signal lines 21, the transfer portion 23 is located, as an orthographic projection of the substrate, between the orthographic projection of the first electrode 24 of the transistor and the orthographic projection of the second type of electrode portion 222 on the substrate.

[0130] In one possible embodiment, as shown in FIG2G , the electrode portion 22 includes a first-type electrode portion 221; a length a2 of the second-type electrode portion 222 in the second direction Y is less than a length a3 of the first electrode 24 of the transistor in the second direction Y. In one possible embodiment, the length a2 of the second-type electrode portion 222 in the second direction Y may also be substantially equal to the length a3 of the first electrode 24 of the transistor in the second direction Y. In one possible embodiment, the length a2 of the second-type electrode portion 222 in the second direction Y may also be greater than the length a3 of the first electrode 24 of the transistor in the second direction Y.

[0131] In one possible embodiment, as shown in FIG2G , the length a3 of the transistor first electrode 24 in the second direction Y is less than the length a4 of the transition portion 23 in the first direction X. In one possible embodiment, the length a3 of the transistor first electrode 24 in the second direction Y may also be greater than the length a4 of the transition portion 23 in the first direction X. In one possible embodiment, the length a3 of the transistor first electrode 24 in the second direction Y may also be equal to the length a4 of the transition portion 23 in the first direction X.

[0132] In one possible embodiment, as shown in FIG2G , the length a1 of the first-type electrode portion 221 in the second direction Y is greater than the length a3 of the first electrode 24 of the transistor in the second direction Y, and less than the length a4 of the transition portion 23 in the second direction Y. In one possible embodiment, the length a1 of the first-type electrode portion 221 in the second direction Y may also be greater than or equal to the length a3 of the first electrode 24 of the transistor in the second direction Y. In one possible embodiment, the length a1 of the first-type electrode portion 221 in the second direction Y may also be greater than or equal to the length a4 of the transition portion 23 in the second direction Y.

[0133] In a possible embodiment, referring to FIG2G , the length a1 of the first type of electrode portion 221 in the second direction Y may be 10 μm to 20 μm; in a possible embodiment, the length a1 of the first type of electrode portion 221 in the second direction Y may be 12 μm to 18 μm; in a possible embodiment, the length a1 of the first type of electrode portion 221 in the second direction Y may be 12 μm, 14 μm, 14.9 μm, 15 μm, 16 μm, 17 μm, or 18 μm.

[0134] In a possible embodiment, as shown in Figure 2G, the length a2 of the second type of electrode portion 222 in the second direction Y can be 1 μm to 10 μm; in a possible embodiment, the length a2 of the second type of electrode portion 222 in the second direction Y can be 5 μm to 8 μm; in a possible embodiment, the length a2 of the second type of electrode portion 222 in the second direction Y can be 5 μm, 6 μm, 6.1 μm, 6.5 μm, 7 μm, or 8 μm.

[0135] In one possible embodiment, as shown in Figure 2G, the length a3 of the first electrode 24 of the transistor in the second direction Y can be 5μm to 15μm; in one possible embodiment, the length a3 of the first electrode 24 of the transistor in the second direction Y can be 8μm to 13μm; in one possible embodiment, the length a3 of the first electrode 24 of the transistor in the second direction Y can be 8μm, 9μm, 10μm, 10.5μm, 11μm, or 12μm.

[0136] In a possible embodiment, as shown in Figure 2G, the length a4 of the transition portion 23 in the second direction Y can be 15μm to 25μm; in a possible embodiment, the length a4 of the transition portion 23 in the second direction Y can be 18μm to 23μm; in a possible embodiment, the length a4 of the transition portion 23 in the second direction Y can be 18μm, 19μm, 19.5μm, 20μm, 21μm, 22μm, or 23μm.

[0137] In one possible embodiment, referring to FIG2G , the length a5 of the first type of electrode portion 221 in the first direction X may be approximately equal to the length a6 of the second type of electrode portion 222 in the first direction X; in one possible embodiment, referring to FIG2G , the length a6 of the second type of electrode portion 222 in the first direction X may be approximately equal to the length a7 of the first pole 24 of the transistor in the first direction X; in one possible embodiment, referring to FIG2G , the length a6 of the second type of electrode portion 222 in the first direction X may be greater than the length a8 of the adapter portion 23 in the first direction X.

[0138] In a possible embodiment, as shown in Figure 2G, the length a8 of the transition portion 23 in the first direction X may be 5μm to 15μm; in a possible embodiment, the length a8 of the transition portion 23 in the first direction X may be 6μm to 10μm; in a possible embodiment, the length a8 of the transition portion 23 in the first direction X may be 6μm, 7μm, 7.2μm, 7.5μm, 8μm, 9μm, or 10μm.

[0139] In one possible embodiment, as shown in FIG2G , the length a1 of the first type of electrode portion 221 in the second direction Y may be greater than the length of the first via K1 in the second direction Y; in one possible embodiment, as shown in FIG2G , the length a2 of the second type of electrode portion 222 in the second direction Y may be greater than the length of the first via K1 in the second direction Y.

[0140] In one possible embodiment, the distance between the centers of adjacent pixel electrodes 5 in the first direction X may be 5 μm to 15 μm; in one possible embodiment, the distance between the centers of adjacent pixel electrodes 5 in the first direction X may be 5 μm, 6 μm, 7 μm, 8 μm, 8.5 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm or 15 μm.

[0141] In one possible embodiment, the distance between the centers of adjacent pixel electrodes 5 in the second direction Y may be 5 μm to 15 μm; in one possible embodiment, the distance between the centers of adjacent pixel electrodes 5 in the second direction Y may be 5 μm, 6 μm, 7 μm, 8 μm, 8.5 μm, 9 μm, 9.8 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm or 15 μm.

[0142] In a possible implementation, the distance between the centers of adjacent pixel electrodes 5 in the second direction Y may be greater than the distance between the centers of adjacent pixel electrodes 5 in the first direction X.

[0143] In one possible embodiment, the sum of the length a1 of the first type of electrode portion 221 in the second direction Y and the length a3 of the first electrode of the transistor 24 in the second direction Y may be less than one third of the length of the pixel unit in the second direction Y; in one possible embodiment, the sum of the length a2 of the second type of electrode portion 222 in the second direction Y, the length a3 of the first electrode of the transistor 24 in the second direction Y, and the length a4 of the transition portion 23 in the second direction Y may be less than one third of the length of the pixel unit in the second direction Y; specifically, the pixel unit may include three sub-pixels of red, green, and blue.

[0144] In one possible embodiment, the length of the pixel unit in the second direction Y may be 30 μm to 200 μm; in one possible embodiment, the length of the pixel unit in the second direction Y may be 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 165 μm, 167.1 μm, 170 μm, 180 μm, 190 μm or 200 μm.

[0145] In a possible embodiment, as shown in Figure 2G, the touch display panel also includes: a plurality of data lines 25 extending along the first direction Y, and a first electrode 24 of a transistor electrically connected to the pixel electrode 5; a first signal line 21 and a data line 25 form a signal routing group 200, in which the electrode portion 22 is electrically connected to the side of the first signal line 21 away from the data line 25, and the first electrode 24 of the transistor is located on the side of the data line 25 away from the first signal line 21.

[0146] Specifically, as shown in FIG2G , the region of the data line 25 between two adjacent gate lines 6 may include: a first data portion 251 arranged along a first direction X, and a second data line portion 252. The extension lines of the first data portion 251 and the second data portion 252 do not overlap. Specifically, the first angle α1 formed by the first data line portion 251 and the second data portion 252 may be an obtuse angle. Specifically, the region of the first signal line 21 between two adjacent gate lines 6 may include a first signal portion 211 and a second signal portion 212 sequentially arranged along the first direction X. The extension lines of the first signal portion 211 and the second signal portion 212 do not overlap. Specifically, the second angle α2 formed by the first signal portion 211 and the second signal portion 212 may be an obtuse angle. Specifically, the first data portion 251 and the first signal portion 211 may be parallel, the second data portion 252 and the second signal portion 212 may be parallel, and the first angle α1 and the second angle α2 may be equal.

[0147] In one possible embodiment, as shown in FIG2G , the orthographic projection of an extension line L of the outer edge of the electrode portion 22 parallel to the second direction Y on the substrate overlaps the orthographic projection of the transistor first electrode 24 on the substrate. That is, the electrode portion 22 and the transistor first electrode 24 can be arranged in approximately the same row and in an upward direction.

[0148] In one possible implementation, as shown in FIG2G , the first signal line 21 and the data line 25 are located in the same layer. In this way, the first signal line 21 can be formed at the same time as the data line 25, thereby simplifying the manufacturing process of the touch display panel.

[0149] In one possible embodiment, the touch layer 3 is located between the first electrode layer 2 and the layer where the pixel electrode 5 is located; as shown in FIG2I , the touch electrode 30 includes: a third via K3; the pixel electrode 5 passes through the third via K3 and is connected to the first electrode 24 of the transistor.

[0150] In one possible embodiment, as shown in conjunction with FIG1D and FIG2I , the touch electrode 30 further includes a first slit S1 extending along the first direction X. The orthographic projection of the first slit S1 on the substrate at least partially overlaps with the orthographic projection of the first signal line 21 on the substrate. Specifically, as shown in FIG2I , the first slit S1 may include a first sub-slit S11 and a second sub-slit S12 arranged along the first direction X. Specifically, the extension lines of the first sub-slit S11 and the second sub-slit S12 may not overlap. Specifically, the third angle α3 formed by the first sub-slit S11 and the second sub-slit S12 may be an obtuse angle. Specifically, the third angle α3 may be approximately equal to the first angle α1.

[0151] In one possible embodiment, as shown in FIG. 2K , the pixel electrode 5 may have multiple second slits S2 . The second slits S2 may include a third sub-slit portion S21 and a fourth sub-slit portion S22 sequentially distributed along the first direction X. The extension lines of the third sub-slit portion S21 and the fourth sub-slit portion S22 may not overlap. Specifically, the fourth angle α4 formed between the third sub-slit portion S21 and the fourth sub-slit portion S22 may be an obtuse angle. Specifically, the fourth angle α4 may be substantially equal to the first angle α1. Specifically, the first slit S1 may have a similar shape to the second slit S2.

[0152] In one possible embodiment, the first insulating layer 4 may be a flat layer. The first electrode layer 2 may be the layer where the data line 25 is located; the first electrode layer 2 may be located on the side of the gate line 6 facing away from the substrate; the touch layer 3 may be located on the side of the first electrode layer 2 facing away from the substrate, and the pixel electrode layer 5 may be located on the side of the touch layer 3 facing away from the substrate; an active layer 9 may be provided between the substrate and the layer where the gate line 6 is located; a light shielding layer 8 may be provided between the substrate and the active layer 9; a second insulating layer 71 may be provided between the gate line 6 and the layer where the data line 25 is located; and a passivation layer 72 may be provided between the touch layer 3 and the layer where the pixel electrode 5 is located. As shown in Figures 2A to 2L, Figure 2L is a cross-sectional schematic diagram along the dotted line EF in Figure 2A. The touch display panel can be provided with the following in sequence on one side of the substrate 1: a buffer layer 73, a light-shielding layer 8 (including multiple light-shielding patterns 80), an active layer 9 (including multiple active patterns 90), a gate insulating layer 74, a gate line 6, a second insulating layer 71 (which can be an interlayer dielectric layer), a first electrode layer 2 (the layer where the data line 25, the electrode portion 22, and the first electrode 24 of the transistor are located), a first insulating layer 4 (which can also be a flat layer), a touch layer 3, and a passivation layer 72.

[0153] In a possible implementation, as shown in FIG. 2L , the display panel may further include an eighth via hole K8 penetrating the second insulating layer 71 and the gate insulating layer 74 , and the first electrode 24 of the transistor contacts the active pattern 90 through the eighth via hole K8 .

[0154] In a possible embodiment, as shown in FIG. 2H and FIG. 2L , the first insulating layer 4 may further have a plurality of seventh via holes K7 , so that the pixel electrode 5 passes through the third via hole K3 , the fourth via hole K4 , and the seventh via hole K7 and is connected to the first electrode 24 of the transistor.

[0155] In one possible embodiment, in combination with FIG2L , the orthographic projection of the seventh via K7 on the substrate 1 may have an overlapping area with the orthographic projection of the eighth via K8 on the substrate 1; in one possible embodiment, the orthographic projection of the seventh via K7 on the substrate 1 may not have an overlapping area with the orthographic projection of the eighth via K8 on the substrate 1; in one possible embodiment, in combination with FIG2L , the orthographic projection of the third via K3 on the substrate 1 may have an overlapping area with the orthographic projection of the eighth via K8 on the substrate 1; in one possible embodiment, the orthographic projection of the third via K3 on the substrate 1 may not have an overlapping area with the orthographic projection of the eighth via K8 on the substrate 1; in one possible embodiment, in combination with FIG2L , the orthographic projection of the fourth via K4 on the substrate 1 may have an overlapping area with the orthographic projection of the eighth via K8 on the substrate 1; in one possible embodiment, the orthographic projection of the fourth via K4 on the substrate 1 may not have an overlapping area with the orthographic projection of the eighth via K8 on the substrate 1.

[0156] In a possible embodiment, in combination with Figure 2L, the slope angle β1 formed by the first insulating layer 4 at the seventh via hole K7 may be in the range of 30° to 80°; in a possible embodiment, the slope angle β1 formed by the first insulating layer 4 at the seventh via hole K7 may be in the range of 40° to 70°; in a possible embodiment, the slope angle β1 formed by the first insulating layer 4 at the seventh via hole K7 may be in the range of 50° to 65°; in a possible embodiment, the slope angle β1 formed by the first insulating layer 4 at the seventh via hole K7 may be in the range of 50°, 51°, 52°, 53°, 54°, 55°, 56°, 57°, 58°, 59°, 60°, 61°, 62°, 63°, 64°, or 65°.

[0157] In a possible embodiment, with reference to FIG2L , the slope angle β2 formed by the passivation layer 72 at the fourth via hole K4 may be in the range of 80° to 110°; in a possible embodiment, the slope angle β2 formed by the passivation layer 72 at the fourth via hole K4 may be in the range of 85° to 100°; in a possible embodiment, the slope angle β2 formed by the passivation layer 72 at the fourth via hole K4 may be in the range of 85°, 86°, 87°, 88°, 89°, 90°, 91°, 92°, 93°, 94°, or 95°.

[0158] Specifically, the second insulating layer 71 can be an interlayer dielectric layer. As shown in FIG2F , the second insulating layer 71 can further include: a fifth via K5 and a sixth via K6. The active layer 9 can include multiple active patterns 90. The active pattern 90 can include a source region 91 and a drain region 92. The source region 91 can be electrically connected to the data line 25 via the fifth via K5, and the drain region 92 can be electrically connected to the first electrode 24 of the transistor via the sixth via K6 (as shown in FIG1E ). The light shielding layer 8 can have multiple light shielding patterns 80. The light shielding patterns 80 can shield at least part of the active pattern 90 of the transistor to prevent external light from affecting the active pattern. The passivation layer 72 can include multiple fourth vias K4 to allow the pixel electrode 5 to pass through the third and fourth vias K3 and K4 and be electrically connected to the first electrode 24 of the transistor.

[0159] Specifically, referring to Figures 6 and 7, the reflectivity of array substrates with similar PPI and different structures, including the number of data lines and the presence or absence of Dummy TPM Pads, is tested; Figure 6 includes: different reflectivity line graphs corresponding to the 0Dual Source structure array substrate 0DS, the 1Dual Source structure array substrate 1DS, the 3Dual Source structure array substrate 3DS, and the 3Dual Source structure array substrate without the Dummy TPM Pad 3DSD; Figure 7 includes: the reflectivity values ​​of the 0Dual Source structure array substrate 0DS, the 1Dual Source structure array substrate 1DS, the 3Dual Source structure array substrate 3DS, and the 3Dual Source structure array substrate without the Dummy TPM Pad 3DSD at different exposure wavelengths, as well as the average reflectivity (Ave). According to Figures 6 and 7, it can be clearly seen that under similar PPI, the more electrode portions 22 (TPM Pads) there are (that is, the number of electrode portions 22 of the 0Dual Source structure array substrate 0DS is less than the number of electrode portions 22 of the 1Dual Source structure array substrate 1DS is less than the number of electrode portions 22 of the 3Dual Source structure array substrate Source structure array substrate 3DS, 3Dual Source removed Dummy TPM Pad structure array substrate 3DSD (the number of electrode portions 22 is less than 3Dual Source structure array substrate 3DS), the higher the reflectivity, the reflectivity can be reduced by about 1% by removing the Dummy Pad.

[0160] In specific implementation, the dummy TPM pads can be removed in a periodic arrangement to the greatest extent possible, which can improve the problem of false detection during automated optical inspection (AOI) of the array substrate. Specifically, the dummy pads can be removed in a periodic arrangement to the greatest extent possible by:

[0161] 1. Get the distributed TPM Pad;

[0162] 2. To improve the efficiency of drawing and editing AOI inspection recipes, you can periodically remove the Dummy TPM Pad.

[0163] 3. Find the position of the electrode part (TPM Pad) according to the touch electrode, find the minimum period of the electrode part (TPM Pad) distribution by column / row, and then arrange the array horizontally according to the minimum period;

[0164] 4. For touch display panel models that are arranged in a vertically staggered manner, find the minimum period by column;

[0165] 5. Based on the overall distribution evaluation, after the minimum longitudinal period is removed, it can ensure that the dummy pad is removed to the maximum extent without affecting the drawing and detection efficiency;

[0166] In summary, whether to periodically remove the Dummy Pad or use manual maximum removal should be selected based on the actual situation of the model, comprehensive Dummy Pad removal rate, AOI inspection, drawing cost, and improvement effect.

[0167] Based on the same inventive concept, the present disclosure also provides a touch display device, including the touch display panel provided in the present disclosure. The implementation of the touch display device can refer to the above embodiment of the touch display panel, and the repeated parts will not be repeated.

[0168] In specific implementations, in the embodiments of the present disclosure, the touch display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0169] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0170] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A touch display panel, wherein: include: substrate; A first electrode layer, located at one side of the substrate, comprises: a plurality of first signal lines extending along a first direction, and a plurality of electrode portions connected to the plurality of first signal lines; A touch layer, located on the same side of the substrate as the first electrode layer, comprising a plurality of touch electrodes spaced apart from each other; A first insulating layer is located between the first electrode layer and the touch control layer, and has a plurality of first via holes; at least some of the plurality of electrode portions are electrically connected to the touch control electrodes through the first via holes; a plurality of pixel electrodes, located on the same side of the substrate as the first electrode layer; The orthographic projection of the electrode portion on the substrate is only located at the orthographic projection of a portion of the gaps between adjacent pixel electrodes on the substrate.

2. The touch display panel according to claim 1, wherein: All the electrode parts are electrically connected to the touch electrode through the first via hole.

3. The touch display panel according to claim 2, wherein: The minimum distance between at least two adjacent electrode portions in the first direction and their orthographic projections on the substrate is greater than the length of the orthographic projection of the pixel electrode on the substrate along the first direction.

4. The touch display panel according to any one of claims 1 to 3, wherein: The minimum distance between at least two adjacent electrode portions in the second direction and their orthographic projections on the substrate is greater than the length of the orthographic projection of the pixel electrode on the substrate along the second direction, and the second direction is perpendicular to the first direction.

5. The touch display panel according to claim 4, wherein: The touch layer includes: a plurality of touch electrode groups extending along the first direction and arranged along the second direction; The plurality of electrode portions include: a plurality of electrode portion groups extending along the first direction and arranged along the second direction, the orthographic projection of the touch electrode group on the substrate at least partially overlapping with the orthographic projection of the electrode portion group on the substrate; At least one electrode portion group among the plurality of electrode portion groups comprises: a plurality of sub-electrode portion groups arranged along the first direction, the sub-electrode portion group comprising at least one electrode portion; an orthographic projection of the touch electrode on the substrate overlaps at least part of an orthographic projection of the sub-electrode portion group on the substrate; The sub-electrode sections in the same electrode section group are distributed in a staggered manner.

6. The touch display panel according to claim 5, wherein: Each of the electrode portions in the same sub-electrode portion group is located at a gap between two adjacent columns of pixel electrodes.

7. The touch display panel according to claim 5, wherein: Each of the electrode portions in the same sub-electrode portion group is electrically connected to the same first signal line.

8. The touch display panel according to claim 5, wherein: Each of the electrode portions located in the same area where the touch electrode is located is located in a gap between two adjacent columns of pixel electrodes.

9. The touch display panel according to claim 5, wherein: The electrode portions located in the same touch electrode region are all electrically connected to the same first signal line.

10. The touch display panel according to claim 5, wherein: The distance between two adjacent sub-electrode groups in the second direction is substantially equal to the width of the touch electrode in the second direction.

11. The touch display panel according to claim 5, wherein: In the second direction, intervals between at least two adjacent sub-electrode groups are substantially equal.

12. The touch display panel according to claim 4, wherein: The electrode portion includes: a first type of electrode portion; The touch display panel comprises: an array substrate and an opposite substrate arranged opposite to each other; the opposite substrate is provided with a first spacer on a side facing the array substrate; the first spacer comprises a first surface opposite to the array substrate; The orthographic projection of at least part of the first-type electrode portion on the substrate has an overlapping area with the orthographic projection of the first surface on the substrate.

13. The touch display panel according to claim 12, wherein: The orthographic projection of the first via hole on the substrate does not overlap with the orthographic projection of the first surface on the substrate.

14. The touch display panel according to claim 12, wherein: The electrode portion further includes: a second type of electrode portion; an orthographic projection of the second type of electrode portion on the substrate and an orthographic projection of the first surface on the substrate do not overlap each other.

15. The touch display panel according to claim 4, wherein: The electrode portion includes a first type of electrode portion and a second type of electrode portion, and a length of the first type of electrode portion in the second direction is greater than a length of the second type of electrode portion in the second direction.

16. The touch display panel according to claim 1, wherein: The touch display panel further comprises: a plurality of gate lines extending along a second direction; at least one gate line among the plurality of gate lines comprises: a plurality of first sub-gate line portions sequentially distributed along the second direction; adjacent first sub-gate line portions are disconnected; The touch display panel further comprises: a transfer portion located at a side of the electrode portion away from the first signal line; an orthographic projection of the transfer portion on the substrate and an orthographic projection of the first sub-gate line portion on the substrate have an overlapping area; The touch display panel further includes: a second insulating layer located between the first electrode layer and the gate line, the second insulating layer having a second via hole; and the transfer portion is electrically connected to the first sub-gate line portion through the second via hole.

17. The touch display panel according to claim 16, wherein: The gate line further comprises: a connection end connected to an end of the first sub-gate line portion; a width of the connection end in the first direction is greater than a width of the first sub-gate line portion in the first direction; One end of the transition portion is connected to the connecting end of a first sub-gate line portion through a second via hole, and the other end of the transition portion is connected to the connecting end of another first sub-gate line portion through another second via hole, so that adjacent first sub-gate line portions are connected through the transition portion.

18. The touch display panel according to claim 17, wherein: The gate line further comprises: a second sub-gate line portion connected to the first sub-gate line portion; The width of the second sub-gate line portion in the first direction is greater than the width of the first sub-gate line portion in the first direction; the width of the second sub-gate line portion in the first direction is substantially equal to the width of the connecting end in the first direction.

19. The touch display panel according to claim 18, wherein: An orthographic projection of the second sub-gate line portion on the substrate does not overlap with an orthographic projection of the electrode portion on the substrate.

20. The touch display panel according to claim 4, wherein: The touch display panel further includes: a first electrode of a transistor; the electrode portion includes a second type of electrode portion; At least partially between adjacent first signal lines, the transition portion is located between the orthographic projection of the first electrode of the transistor on the substrate and the orthographic projection of the second-type electrode portion on the substrate.

21. The touch display panel according to claim 20, wherein: A length of the second-type electrode portion in the second direction is smaller than a length of the first electrode of the transistor in the second direction.

22. The touch display panel according to claim 20, wherein: The length of the first electrode of the transistor in the second direction is smaller than the length of the switching portion in the first direction.

23. The touch display panel according to claim 20, wherein: The electrode portion includes a first type of electrode portion, and a length of the first type of electrode portion in the second direction is greater than a length of the first electrode of the transistor in the second direction and less than a length of the switching portion in the second direction.

24. The touch display panel according to claim 1, wherein: The touch display panel further includes: a plurality of data lines extending along the first direction, and a first electrode of a transistor electrically connected to the pixel electrode; A first signal line and a data line form a signal routing group. In the same signal routing group, the electrode portion is electrically connected to a side of the first signal line away from the data line, and the first electrode of the transistor is located on a side of the data line away from the first signal line.

25. The touch display panel according to claim 24, wherein: An orthographic projection of an extension line of an outer edge of the electrode portion parallel to the second direction on the substrate overlaps with an orthographic projection of the first electrode of the transistor on the substrate.

26. The touch display panel according to claim 24, wherein: The first signal line and the data line are located in the same layer.

27. The touch display panel according to claim 24, wherein: The touch control layer is located between the first electrode layer and the layer where the pixel electrodes are located; The touch electrode comprises: a third via hole; the pixel electrode passes through the third via hole and is connected to the first electrode of the transistor.

28. The touch display panel according to claim 27, wherein: The touch electrode further includes a first slit extending along the first direction, wherein an orthographic projection of the first slit on the substrate overlaps at least a portion of an orthographic projection of the first signal line on the substrate.

29. A touch display device, wherein: Comprising a touch display panel as described in any one of claims 1-28.

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