Processing element scheduling apparatus and method, chip, and related device

Abstract

Embodiments of the present application provide a processing element scheduling apparatus and method, a chip, and a related device. The processing element scheduling apparatus comprises a first arbiter and M processing elements connected to the first arbiter, M being a positive integer greater than or equal to 2. Each processing element is used for sending a first request signal to the first arbiter, the first request signal being used for requesting the corresponding processing element to switch from a first power consumption state to a second power consumption state, and the power in the first power consumption state being lower than that in the second power consumption state; and the first arbiter is used for: receiving the first request signal sent by one or more processing elements among the M processing elements, and performing arbitration to obtain a first response sequence for one or more first request signals; and on the basis of the first response sequence, controlling the one or more processing elements to switch from the first power consumption state to the second power consumption state. Implementation of the embodiments of the present application can reduce the phenomenon of functional errors of a circuit caused by voltage undershoot, and improve the circuit performance.

Description

A processing unit scheduling device, method, chip and related equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on September 21, 2023, with application number 202311227739.1, and priority to the Chinese patent application entitled “A processing unit scheduling device, method, chip and related equipment”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip technology, and in particular to a processing unit scheduling device, method, chip and related equipment. Background Art

[0003] With the continuous advancement of technology, chips have also gradually evolved. Current high-performance chips, such as general-purpose processors (CPUs), neural network accelerators (NPUs), and general-purpose graphics processing units (GPGPUs), typically integrate dozens to hundreds of processing elements (PEs). Within each PE, there may be a high-power unit (HPU), such as a vector / matrix accelerator. When all or even some of the HPUs in a chip's PEs operate simultaneously, they may affect each other, leading to signal integrity (PI) issues. For example, when the HPUs in all PEs on a chip simultaneously transition from standby mode (i.e., idle state) to the second-lowest power state, the on-chip power supply network may be unable to provide sufficient current to all HPUs, causing the output voltage of the on-chip power supply network to undershoot, resulting in a reduced output voltage. This voltage undershoot can cause functional errors in the chip's internal circuits that require stable voltage supply, ultimately leading to chip malfunction. For example, when the instantaneous output voltage is lower than the minimum voltage Vmin at which a complementary metal oxide semiconductor (CMOS) tube can operate normally, the CMOS tube may be shut down or may malfunction.

[0004] Therefore, how to reduce the phenomenon of functional errors in circuits caused by voltage undershoot is a technical problem that needs to be solved urgently.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a processing unit scheduling device, method, chip and related equipment to reduce the phenomenon of functional errors in circuits caused by voltage undershoot and improve circuit performance.

[0007] In a first aspect, an embodiment of the present application provides a processing unit scheduling device, the device comprising a first arbitrator and M processing units PE connected to the first arbitrator, where M is a positive integer greater than or equal to 2; wherein,

[0008] Each of the processing units is configured to: send a first request signal to the first arbitrator, wherein the first request signal is configured to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, wherein the power of the first power consumption state is lower than the power of the second power consumption state;

[0009] The first arbitrator is used to: receive the first request signals sent by one or more processing units among the M processing units, arbitrate to obtain a first response sequence of one or more of the first request signals; and control the one or more processing units to switch from the first power consumption state to the second power consumption state based on the first response sequence.

[0010] In order to avoid voltage undershoot and functional errors caused by multiple processing units entering a high power state from a low power state at the same time, an embodiment of the present application provides a processing unit scheduling device, which can prevent multiple processing units from entering a high power state from a low power state at the same time from a hardware perspective, reduce the undershoot amplitude of the voltage undershoot, and make the minimum instantaneous voltage of the voltage undershoot higher than the normal operating voltage of the circuit, thereby ensuring the signal integrity of the chip. Among them, the processing unit scheduling device can be applied to a chip or a related circuit module, and the processing unit scheduling device includes a first arbitrator and M processing units PE connected to the first arbitrator. When any processing unit among the multiple processing units connected to the first arbitrator is about to enter a high power state from a low power state (that is, from a first power state with lower power to a second power state with higher power), each processing unit must send a first request signal to the first arbitrator to request to switch the power consumption state. Upon receiving the first request signal sent by the connected processing unit, the first arbitrator can arbitrate the received first request signal and determine the corresponding response order. The first arbitrator can then sequentially control the corresponding processing units to switch from a low-power state to a high-power state according to the response order. This prevents all of the multiple processing units connected to the first arbitrator from switching from a low-power state to a high-power state simultaneously, which could cause voltage undershoot, functional errors, and compromise signal integrity. For example, if the instantaneous voltage falls below the minimum voltage Vmin for proper operation of a MOS transistor, the MOS transistor may shut down, leading to chip functional errors. With the arbitrator connected between multiple processing units, each processing unit undergoes arbitration by the arbitrator when switching power states. This allows the arbitrator to schedule the power state switching of some of the multiple processing units. Furthermore, compared to software algorithm-based scheduling within a device or apparatus, this significantly reduces the overhead of the device or apparatus and reduces the probability of scheduling errors causing all processing units to switch from a low-power state to a high-power state simultaneously, thereby ensuring the chip's signal performance.

[0011] In one possible implementation, the first arbitrator is specifically used to: based on the first response sequence, send a first response signal to the one or more processing units respectively, and the first response signal is used to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state; wherein, in the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal was sent to the corresponding processing unit is greater than or equal to a first preset time interval.

[0012] In an embodiment of the present application, the first arbitrator can control the processing unit to switch the power consumption state through a response signal. For example, when the processing unit receives the first response signal sent by the first puncher, it can switch from a low power consumption state to a high power consumption state immediately or within a preset time. Among them, when the first arbitrator sends the first response signal to one or more processing units in accordance with the first response order, the time interval between any two orders of sending the first response signal is greater than or equal to the first preset time interval. For example, based on the first request signal, when the first arbitrator continuously pulls up different processing units, or continuously pulls up the same processing unit multiple times, the time interval between any two orders needs to exceed the first preset time interval. The first preset time interval can be determined based on the number and performance of the processing units connected to the arbitrator, for example, it can be between 10 nanoseconds and 1 microsecond. This sending method in which the time interval between any two orders needs to exceed the first preset time interval can ensure that all processing units will not be pulled up at the same time, thereby avoiding the phenomenon of voltage undershoot causing the instantaneous voltage to be less than the minimum voltage for the circuit or functional module to work normally, resulting in functional errors.

[0013] In one possible implementation, the first arbitrator sends the corresponding first response signal to the one or more processing units respectively through a serial and / or parallel sending manner; wherein, when the first arbitrator sends the corresponding first response signal to the one or more processing units through a parallel sending manner, the parallelism of the parallel sending is less than or equal to M.

[0014] In an embodiment of the present application, the first arbiter can control one processing unit to switch to a high power state at a time, or it can control multiple processing units to switch to a high power state simultaneously. Where the current total power consumption is low and controlling multiple processing units to switch to a high power state simultaneously does not affect normal operation of the circuit, the maximum number of processing units that can switch to a high power state simultaneously can be equal to the total number of processing units connected to the arbiter, i.e., the parallelism of the first arbiter's parallel transmission is less than or equal to M. Where the current total power consumption is high and controlling multiple processing units to switch to a high power state simultaneously may cause voltage undershoot, resulting in malfunction of the circuit, the maximum number of processing units that can switch to a high power state simultaneously must be less than the total number of processing units connected to the arbiter, i.e., the parallelism of the first arbiter's parallel transmission is less than M. The first arbiter can control some processing units to switch to a high power state simultaneously without simultaneously controlling all processing units to switch to a high power state, thereby improving arbitration efficiency and ensuring the performance of the processing units.

[0015] In one possible implementation, each of the processing units includes one or more high power consumption units HPU, and the first response signal is used to instruct some or all of the high power consumption units in the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0016] In an embodiment of the present application, each processing unit may include a high-power unit, such as a vector / matrix accelerator. When a high-power unit is in operation, it consumes high power, thereby increasing the power consumption of the corresponding processing unit. Therefore, after the processing unit receives the first response signal, it controls some or all of the high-power units within it to switch from the first power consumption state to the second power consumption state. This ensures that the high-power units in the processing unit will not autonomously switch to the high-power consumption state without receiving the first response signal.

[0017] In one possible implementation, each of the processing units also includes a prediction module; the prediction module is used to: detect the power consumption state of the one or more high-power consumption units in the corresponding processing unit; and send the first request signal to the first arbitrator when it is detected that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0018] In an embodiment of the present application, each processing unit may further include a prediction module, which can be used to detect the power consumption status of one or more high-power consumption units in the corresponding processing unit in real time or periodically, so that when some or all of the high-power consumption units are about to switch to the second power consumption state, a first request signal is promptly sent to the first arbitrator to request that the high-power consumption unit be switched from the first power consumption state to the second power consumption state, thereby improving the accuracy and switching efficiency of the processing unit switching the power consumption state.

[0019] In one possible implementation, the processing unit also includes a task sending queue, which is used to send a task descriptor of the task; the task descriptor is used to indicate whether the task calls the one or more high-power consumption units in the corresponding processing unit; the prediction module is specifically used to: when the task descriptor indicates that the current task calls some or all of the high-power consumption units in the corresponding processing unit, determine that the some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0020] In an embodiment of the present application, each processing unit may further include a task sending queue. One of the methods by which the prediction module predicts that the high-power consumption unit is about to enter the high-power consumption state from the low-power consumption state is to determine the high-power consumption state by using the task descriptor of the current task in the task sending queue. The task descriptor can be used to indicate whether the current task needs to call the high-power consumption unit in the processing unit. If it indicates that the high-power consumption unit in the processing unit needs to be called, it indicates that the called high-power consumption unit is about to enter the high-power consumption state, and the prediction module needs to send a first request signal to the first arbitrator to control the high-power consumption unit to enter the high-power consumption state.

[0021] In one possible implementation, each of the processing units also includes an instruction sending queue; the instruction sending queue is used to send operation instructions; the prediction module is specifically used to: when it is detected that the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue exceeds a preset threshold number, determine that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0022] In an embodiment of the present application, one of the methods for the prediction module to predict that the processing unit is about to enter a high power consumption state from a low power consumption state is by detecting the number of operation instructions in the instruction sending queue of the processing unit; when the number of operation instructions corresponding to the high power consumption unit in the instruction sending queue is accumulated in large quantities (for example, exceeding a preset threshold number), it indicates that the high power consumption unit is about to enter a high power consumption state, and the prediction module needs to send a first request signal to the first arbitrator to control the high power consumption unit to enter a high power consumption state.

[0023] In one possible implementation, the first arbitrator is specifically configured to arbitrate and obtain the first response order of one or more first request signals according to a preset polling rule or a response priority of one or more processing units among the M processing units.

[0024] In an embodiment of the present application, the first arbitrator can arbitrate the first response sequence of the first request signal according to a preset polling rule or response priority so as to reply to the first response signal in order. For example: the earlier the first request signal is received, the earlier the response sequence corresponding to the first request signal is replied. For another example: the first response signal of the same processing unit will not be replied to continuously at the same time. For another example: the higher the response priority of the corresponding processing unit, the earlier the response sequence corresponding to the first request signal is replied. This arbitration of the response sequence between multiple processing units according to preset rules can improve the arbitration accuracy of the first arbitrator and avoid poor chip performance caused by errors.

[0025] In a possible implementation, the first arbitrator is disposed in the middle of the multiple processing units; or the sum of the communication distances between the first arbitrator and each of the processing units is the shortest.

[0026] In the embodiment of the present application, the first arbitrator is set in the middle of multiple processing units or the sum of the communication distances between the first arbitrator and the multiple processing units is the shortest, which can greatly reduce the communication delay between the first arbitrator and the processing units, improve processing efficiency, and ensure processing performance.

[0027] In one possible implementation, the first arbitrator includes M groups of communication interfaces, each group of the communication interfaces corresponds to one of the processing units, and each group of the communication interfaces includes a request interface and a response interface; wherein each of the request interfaces is used to receive the first request signal sent by the corresponding processing unit, and each of the response interfaces is used to send the first response signal to the corresponding processing unit.

[0028] In an embodiment of the present application, the first arbitrator and each processing unit can communicate through a dedicated interface module, that is, the first arbitrator includes multiple groups of communication interfaces, each group of communication interfaces corresponds to a processing unit, and each group of communication interfaces includes a request interface for transmitting a first request signal and a response interface for transmitting a response signal, so that the first arbitrator and the processing unit can communicate normally, and the communication efficiency between the first arbitrator and multiple processing units is greatly improved, thereby avoiding the situation where the first arbitrator cannot receive the first request signal in time when multiple processing units send the first request signal to the first arbitrator at the same time.

[0029] In one possible implementation, each of the processing units corresponds to a standby state and multiple high power consumption states, each of the high power consumption states has a different power size, the second power consumption state is one of the multiple high power consumption states, and the first power consumption state is the standby state or one of the multiple high power consumption states whose power is less than that of the second power consumption state; wherein the first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state that the processing unit is in after switching; each of the processing units is also used to: send current power consumption level information to the first arbitrator, and the current power consumption level information is used to indicate the first power consumption state that the processing unit is currently in.

[0030] In the embodiment of the present application, the processing unit can have multiple high-power consumption states. Each time the processing unit switches to a higher power consumption state, it must send a first request signal to the first arbitrator, which then determines the corresponding adjusted high-power consumption state level. This allows the processing unit to enter different high-power consumption states at will, causing voltage undershoot and resulting in a reduction in output voltage. This method of adjusting the power consumption state of the processing unit controlled by the first arbitrator can globally control the overall power consumption of multiple processing units, which is beneficial for ensuring the stability of the power supply network output voltage and chip performance.

[0031] In one possible implementation, each group of the communication interfaces further includes an energy level interface, wherein each of the energy level interfaces is used to receive the current power consumption level information sent by the corresponding processing unit, and each of the response interfaces is also used to send the target power consumption level information.

[0032] In the embodiment of the present application, since the processing units may have multiple high-power consumption states, each set of communication interfaces may also include an interface for transmitting current power consumption level information in order to facilitate each processing unit to transmit its current power consumption state to the first arbitrator. Furthermore, to reduce control costs and improve control efficiency, each set of response interfaces may also be used to transmit target power consumption level information. For example, the first response signal may carry the corresponding target power consumption level information.

[0033] In one possible implementation, the first arbitrator and the M processing units constitute a first processing cluster; the apparatus further includes a second arbitrator and a plurality of the first processing clusters, the second arbitrator being connected to the first arbitrator in each of the first processing clusters; each of the first arbitrators being specifically configured to: upon receiving the first request signal, send a second request signal to the second arbitrator; the second arbitrator being configured to: receive the second request signal sent by one or more of the first arbitrators; arbitrate to obtain a second response sequence of the one or more second request signals; and control the one or more first arbitrators based on the second response sequence.

[0034] In an embodiment of the present application, a multi-level arbitration architecture can also be provided, that is, the first arbitrator performs arbitration for switching to a high power consumption state at the granularity of one processing unit, and the second arbitrator performs arbitration for switching to a high power consumption state at the granularity of one first processing cluster. That is, at the same time, only some of the first processing clusters are used, which greatly reduces the number of processing units that enter high power consumption at the same time in the global state, further ensuring the stability of the output voltage of the power supply network and the performance of the chip.

[0035] In one possible implementation, the second arbitrator is specifically used to: send a second response signal to one or more of the first arbitrators based on the second response sequence, and the second response signal is used to instruct the corresponding first arbitrator to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0036] In this embodiment of the present application, the response of the first arbitrator can be controlled by a second response signal. For example, only after the second arbitrator sends the second response signal to the corresponding first arbitrator can the first arbitrator sequentially control the corresponding processing unit to switch from the first power consumption state to the second power consumption state. This control method based on response signals can more easily control the arbitrators at all levels, reduce the error rate, and ensure the operational performance of the chip.

[0037] In a possible implementation, in the second response sequence, a time interval between each sending of the second response signal to the corresponding second arbitrator and the last sending of the second response signal to the corresponding second arbitrator is greater than or equal to a second preset time interval.

[0038] In the embodiment of the present application, similar to the first arbitrator, to ensure that voltage undershoot does not cause the instantaneous voltage to be lower than the voltage at which the circuit structure in the device can operate normally, thereby causing chip malfunction, the time interval between each response of the second arbitrator to the first arbitration can be greater than or equal to a second preset time interval. The second preset time interval and the first preset time interval can be different or the same, and the maximum number of processing units that can be pulled high at a time can be adjusted by configuring the second preset time interval and the first preset time interval to accommodate a wider range of application scenarios.

[0039] In a second aspect, an embodiment of the present application provides a processing unit scheduling method, which is applied to a processing unit scheduling device, wherein the processing unit scheduling device includes a first arbitrator and M processing units (PEs) connected to the first arbitrator, where M is a positive integer greater than or equal to 2; the method includes:

[0040] receiving first request signals respectively sent by one or more processing units among the M processing units, and arbitrating to obtain a first response sequence of the one or more first request signals, wherein the first request signal is used to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, where power in the first power consumption state is lower than power in the second power consumption state;

[0041] Based on the first response sequence, the one or more processing units are controlled to switch from the first power consumption state to the second power consumption state.

[0042] In one possible implementation, controlling the one or more processing units to switch from the first power consumption state to the second power consumption state based on the first response sequence includes: sending a first response signal to the one or more processing units respectively based on the first response sequence, the first response signal being used to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state; wherein, in the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal is sent to the corresponding processing unit is greater than or equal to a first preset time interval.

[0043] In one possible implementation, the first arbitrator sends the corresponding first response signal to the one or more processing units respectively through a serial and / or parallel sending manner; wherein, when the first arbitrator sends the corresponding first response signal to the one or more processing units through a parallel sending manner, the parallelism of the parallel sending is less than or equal to M.

[0044] In one possible implementation, each of the processing units includes one or more high power consumption units HPU, and the first response signal is used to instruct some or all of the high power consumption units in the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0045] In one possible implementation, each of the processing units also includes a prediction module; the method also includes: detecting the power consumption state of the one or more high-power consumption units in the corresponding processing unit through the prediction module; and sending the first request signal to the first arbitrator when it is detected that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0046] In one possible implementation, each of the processing units further includes a task sending queue, which is used to send a task descriptor of the current task; the task descriptor is used to indicate whether the current task calls the one or more high-power consumption units in the corresponding processing unit; detecting the power consumption state of the one or more high-power consumption units in the corresponding processing unit through the prediction module includes: obtaining the task descriptor of the current task in the task sending queue, wherein, when the task descriptor indicates that the current task calls some or all of the high-power consumption units in the corresponding processing unit, determining that the some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0047] In one possible implementation, each of the processing units also includes an instruction sending queue; the instruction sending queue is used to send operation instructions; the detection of the power consumption state of the one or more high-power consumption units in the corresponding processing unit through the prediction module includes: detecting the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue, wherein, when it is detected that the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue exceeds a preset threshold number, it is determined that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0048] In one possible implementation, the arbitration obtains the first response order of one or more of the first request signals, including: according to a preset polling rule or the response priority of one or more processing units among the M processing units, the arbitration obtains the first response order of one or more of the first request signals.

[0049] In a possible implementation, the first arbitrator is disposed in the middle of the multiple processing units; or the sum of the communication distances between the first arbitrator and each of the processing units is the shortest.

[0050] In one possible implementation, the first arbitrator includes M groups of communication interfaces, each group of the communication interfaces corresponds to one of the processing units, and each group of the communication interfaces includes a request interface and a response interface; wherein each of the request interfaces is used to receive the first request signal sent by the corresponding processing unit, and each of the response interfaces is used to send the first response signal to the corresponding processing unit.

[0051] In one possible implementation, each of the processing units corresponds to a standby state and multiple high power consumption states, each of the high power consumption states has a different power size, the second power consumption state is one of the multiple high power consumption states, and the first power consumption state is the standby state or one of the multiple high power consumption states whose power is less than that of the second power consumption state; wherein the first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state that the processing unit is in after switching; the method also includes: receiving current power consumption level information sent by one or more processing units among the M processing units, and the current power consumption level information is used to indicate the first power consumption state that the corresponding processing unit is currently in.

[0052] In one possible implementation, each group of the communication interfaces further includes an energy level interface, wherein each of the energy level interfaces is used to receive the current power consumption level information sent by the corresponding processing unit, and each of the response interfaces is also used to send the target power consumption level information.

[0053] In one possible implementation, the first arbitrator and the M processing units constitute a first processing cluster; the apparatus further includes a second arbitrator and a plurality of the first processing clusters, the second arbitrator being connected to the first arbitrator in each of the first processing clusters; the method further includes: receiving, through the second arbitrator, a second request signal sent by one or more of the first arbitrators upon receiving the first request signal; obtaining, through arbitration by the second arbitrator, a second response sequence for the one or more second request signals; and controlling the corresponding one or more first arbitrators based on the second response sequence.

[0054] In one possible implementation, controlling the corresponding one or more first arbitrators based on the second response sequence includes: sending a second response signal to the corresponding one or more first arbitrators based on the second response sequence, the second response signal being used to instruct the corresponding first arbitrator to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0055] In a possible implementation, in the second response sequence, a time interval between each sending of the second response signal to the corresponding second arbitrator and the last sending of the second response signal to the corresponding second arbitrator is greater than or equal to a second preset time interval.

[0056] In a third aspect, an embodiment of the present application provides a chip, including a circuit and a processing unit scheduling device as described in the first aspect and the first aspect applied to the circuit.

[0057] In a fourth aspect, an embodiment of the present application provides a server, comprising: a circuit board and the processing unit scheduling device as described in the first aspect and the first aspect above; the circuit board is electrically connected to the processing unit scheduling device.

[0058] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and the processing unit scheduling device as described in the first aspect and the first aspect above; the circuit board is electrically connected to the processing unit scheduling device.

[0059] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium for storing computer software instructions used for a processing unit scheduling device provided in the first aspect above, which includes a program involved in executing a processing unit scheduling method provided in the second aspect above.

[0060] In a seventh aspect, an embodiment of the present application provides a computer program, which includes instructions. When the computer program is executed by a computer, the computer can execute the process executed by a processing unit scheduling device provided in the first aspect above.

[0061] It should be understood that the processing unit scheduling method provided in the second aspect of this application, the chip provided in the third aspect, the server provided in the fourth aspect, the electronic device provided in the fifth aspect, the computer-readable storage medium provided in the sixth aspect, and the computer program provided in the seventh aspect are consistent with the technical solution of the first aspect of this application. Their specific contents and beneficial effects can be referred to the processing unit scheduling device provided in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0063] FIG1 is a schematic structural diagram of a high-performance chip provided in an embodiment of the present application.

[0064] FIG2 is a schematic structural diagram of a processing unit scheduling device provided in an embodiment of the present application.

[0065] FIG3A is a schematic structural diagram of another processing unit scheduling device provided in an embodiment of the present application.

[0066] FIG3B is a schematic structural diagram of another processing unit scheduling device provided in an embodiment of the present application.

[0067] 4A and 4B are schematic structural diagrams of a group of processing unit scheduling devices provided in an embodiment of the present application.

[0068] FIG5 is a schematic structural diagram of another processing unit scheduling device provided in an embodiment of the present application.

[0069] FIG6 is a schematic diagram of a communication interface of a first arbitrator provided in an embodiment of the present application.

[0070] FIG7 is a schematic structural diagram of another processing unit scheduling device provided in an embodiment of the present application.

[0071] FIG8 is a flow chart of a processing unit scheduling method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0073] The terms "first," "second," and the like in the specification, claims, and accompanying drawings of this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0074] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0075] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0076] As used in this specification, the terms "component," "module," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0077] First, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0078] (1) Scheduling: Controlling the timing or order in which processing units switch from a low-power state to a high-power state. In the embodiment of the present application, each processing unit is independent of each other and has no dependencies. That is, each processing unit can switch from a low-power state to a high-power state at will. In order to ensure that all processing units do not switch from a low-power state to a high-power state at the same time, global scheduling can be achieved by controlling the order in which processing units switch to a high-power state.

[0079] (2) Processing Element (PE), which can be understood as a logical core. A logical core can run one or more tasks or one or more threads. A network composed of multiple identical processing elements (PEs) according to certain interconnection rules can be called a systolic array. In the embodiments of the present application, the connection method between multiple processing elements is not limited.

[0080] (3) Arbiter. When multiple functional modules occupy the same resource, the arbiter can be used to arbitrate which module will occupy the resource, or which module will occupy the resource first. For example, a module that requests to occupy a resource must generate a request. After all requests are sent to the arbiter, the arbiter can perform arbitration. In addition, the arbiter can also return a grant, and the module that receives the grant can occupy the resource.

[0081] (4) High Power Unit (HPU): A functional module with high power consumption density. That is, when in operation, this functional module consumes a large amount of power or resources. Among them, the high power unit can be a matrix accelerator, vector accelerator, multiplication accelerator, etc.

[0082] (5) Task sending queue: a container or queue that stores tasks or task descriptors during the task sending process. It can relay or send tasks or task descriptors from the source to the target and can act as a container in the process. Its main purpose is to provide routing and ensure the delivery or sending of tasks or task descriptors.

[0083] (6) Instruction send queue: A container or queue that stores instructions during the instruction issuance process. Instructions in the queue can be sent to the corresponding target. If the receiver of a sent instruction is unavailable or temporarily unavailable, the instruction send queue will retain the instruction until it can be successfully delivered.

[0084] Secondly, in order to facilitate understanding of the embodiments of the present application, the technical problems that need to be solved and the applicable application scenarios of the embodiments of the present application are analyzed in detail below.

[0085] With the continuous advancement of technology, chips are also gradually developing. Current high-performance chips, such as general-purpose processors (CPUs), neural network accelerators (NPUs), and general-purpose graphics processing units (GPGPUs), generally integrate dozens to hundreds of processing elements (PEs). Figure 1 is a schematic diagram of the structure of a high-performance chip provided by an embodiment of the present application. Within each processor element, there may be a high-power unit (HPU), such as a vector / matrix accelerator, which can be called a high-power unit. When all or even some of the HPUs in the PEs on a chip are started simultaneously, they may affect each other, resulting in signal integrity (PI) issues. For example, when all or most of the HPUs in the PEs on a chip simultaneously enter the working state from standby mode (i.e., idle state) and start high-power mode, the on-chip power supply network may not be able to provide sufficient current to all PEs, resulting in a voltage undershoot in the voltage output of the on-chip power supply network, causing the output voltage to decrease. When the instantaneous output voltage drops below the normal operating voltage required by the chip's internal circuitry due to a voltage undershoot, the relevant functional modules may experience circuit malfunctions due to the voltage undershoot, ultimately leading to chip malfunctions. For example, when a complementary metal oxide semiconductor (CMOS) transistor reaches its minimum normal operating voltage (Vmin), the CMOS transistor may shut down or malfunction, ultimately causing chip malfunctions. Another example is that voltage undershoot can cause voltage instability, which can also cause malfunctions in functional modules that require stable voltages.

[0086] To ensure that the output voltage of the on-chip power supply network never falls below the operating voltage V, which ensures normal chip operation, one existing solution is to increase the input voltage V0 of the on-chip power supply network. This way, when multiple HPUs are simultaneously powered up and voltage undershoot occurs, the output voltage V1 of the on-chip power supply network, while lower than V0, remains at or above the operating voltage V, ensuring normal chip operation. However, because chip power consumption is proportional to the square of the voltage, increasing the input voltage V0 of the on-chip power supply network significantly increases chip power consumption.

[0087] Another solution is to circumvent the problem through software scheduling of the HPUs in the PEs. Specifically, software scheduling can be used to prevent the simultaneous startup of the HPUs in multiple PEs. As long as the number of PEs started simultaneously is small enough, voltage undershoot will not occur, thereby addressing the voltage undershoot problem at its source. However, due to the imprecision of software calls, the possibility of multiple HPUs starting simultaneously cannot be completely avoided. Furthermore, software scheduling generally incurs significant overhead, which can affect the chip's native performance. Furthermore, this solution requires the software designer or user to understand the basic architecture of the software-scheduling chip, which is difficult for most software designers or users to achieve.

[0088] To this end, an embodiment of the present application provides a high-power unit scheduling device and related method, which can ensure that the time for increasing the HPU power consumption of multiple PEs is staggered from a hardware perspective, avoiding the instantaneous voltage caused by voltage undershoot being lower than the normal operating voltage of the MOS tube when multiple PEs simultaneously enter the high-power state from a low-power state, thereby achieving the purpose of protecting the chip PI. The high-power unit scheduling device includes: a first arbitrator and M processing units PE connected to the first arbitrator, where M is a positive integer greater than or equal to 2; each processing unit is configured to: send a first request signal to the first arbitrator, the first request signal being used to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, where the power of the first power consumption state is lower than the power of the second power consumption state; the first arbitrator is configured to: receive the first request signals respectively sent by one or more processing units among the M processing units, arbitrate to obtain a first response order of the one or more first request signals; and control the one or more processing units to switch from the first power consumption state to the second power consumption state based on the first response order.

[0089] Among them, the specific implementation method of the embodiment of the present application can also refer to the relevant description of the following embodiment, and the embodiment of the present application will not be repeated here.

[0090] Based on the technical issues raised above and to facilitate understanding of the embodiments of the present application, one of the processing unit scheduling devices on which the embodiments of the present application are based is described below.

[0091] Please refer to FIG. 2 , which is a schematic structural diagram of a processing unit scheduling device provided in an embodiment of the present application.

[0092] As shown in FIG2 , a processing unit scheduling device 001 can be applied to various high-performance chips or processing devices. The device includes a first arbitrator 01 and M processing units PE connected to the first arbitrator, where M is a positive integer greater than or equal to 2.

[0093] Each processing element PE is configured to send a first request signal to the first arbiter 01, wherein the first request signal is configured to request that the corresponding processing element PE be switched from a first power consumption state to a second power consumption state, wherein the power of the first power consumption state is lower than the power of the second power consumption state. For example, the first request signal is configured to request that the corresponding processing element PE be switched from a low power consumption state (i.e., the first power consumption state) to a high power consumption state (i.e., the second power consumption state). It is understood that the processing element scheduling apparatus shown in FIG2 is illustrative of an example in which one first arbiter 01 is connected to four processing elements PE. When any of the four processing elements PE connected to the first arbiter 01 needs to switch from a low power consumption state to a high power consumption state (i.e., from a first power consumption state with a lower power consumption to a second power consumption state with a higher power consumption), the processing element PE must send a first request signal to the first arbiter 01 to request that the power consumption state be switched. The processing element PE connected to the first arbiter 01 cannot directly enter a higher power consumption state without arbitration by the first arbiter 01.

[0094] The first arbiter 01 is configured to receive first request signals respectively transmitted by one or more of the M processing units PE, arbitrate to obtain a first response order for the one or more first request signals, and control the one or more processing units PE to switch from the first power consumption state to the second power consumption state based on the first response order. For example, when any one or more of the four processing units PE connected to the first arbiter 01 transmits a first request signal to the first arbiter 01, the first arbiter 01 may arbitrate based on the received one or more first request signals to obtain a first response order corresponding to the one or more first request signals, thereby sequentially controlling the processing units that transmitted the first request signals to switch from the first power consumption state to the second power consumption state based on the first response order. In this embodiment, an arbiter is connected between multiple processing units, and each processing unit switches power consumption state through arbitration by the arbiter. This allows the arbiter to schedule the power consumption state switching of some of the multiple processing units. Furthermore, compared to software algorithm-based scheduling within a device or apparatus, this significantly reduces the overhead of the device or apparatus and reduces the probability of scheduling errors causing all processing units to simultaneously switch from a low power consumption state to a high power consumption state, thereby ensuring the signal performance of the chip.

[0095] In addition, the present embodiment of the present application uses a first arbiter 01 connected to four processing units PE as an example for illustration, and the present embodiment of the present application does not impose any specific limitation on this. For example, please refer to Figure 3A, which is a schematic diagram of the structure of another processing unit scheduling device provided in an embodiment of the present application. As shown in Figure 3A, a first arbiter 01 can be connected to eight processing units PE, and under the control of the first arbiter 01, the eight processing units PE will not all switch from a low power consumption state to a high power consumption state at the same time.

[0096] It should be noted that, please refer to Figure 3B, which is a schematic diagram of the structure of another processing unit scheduling device provided in an embodiment of the present application. As shown in Figure 3B, the processing unit scheduling device may include multiple first arbiters and M processing units connected to each first arbiter. The number of processing units connected to each first arbiter is the same. When all processing units in the processing unit scheduling device are about to switch from a low-power state to a high-power state, arbitration is performed by multiple first arbiters. This will result in only some processing units being able to switch from a low-power state to a high-power state at the same time in the global state, thereby improving the minimum instantaneous voltage during voltage undershoot and ensuring chip performance. For example, when a first arbiter is connected to four processing units, and each first arbiter can only control one processing unit to enter a high-power state at a time, then in the global state, at most only one-quarter of the processing units can switch from a low-power state to a high-power state at the same time. Compared to when all processing units are switched from a low-power state to a high-power state at the same time in the global state, the voltage undershoot phenomenon will be greatly alleviated, greatly reducing the probability of chip functional errors caused by voltage undershoot.

[0097] In other embodiments, a processing unit may continuously send multiple first request signals to the first arbitrator. When the sending time of the multiple first request signals is within a preset time range, only one of the multiple first request signals (which may be the one with the earliest sending time or the latest sending time) is valid, and the remaining first request signals are invalid. For example, if three first request signals are sent within 10 nanoseconds, the first arbitrator may only respond to or arbitrate one first request signal among the three first request signals. When the sending time of every two first request signals when sending the multiple first request signals is outside the preset time range, the multiple first request signals are all valid. For example, if the processing unit sends a first request signal every 100 nanoseconds, the first request signals sent are all valid until the processing unit switches to the highest power consumption state.

[0098] In some embodiments, the first arbitrator is specifically used to: based on the first response sequence, send a first response signal to the one or more processing units respectively, and the first response signal is used to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state; wherein, in the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal was sent to the corresponding processing unit is greater than or equal to a first preset time interval.

[0099] Based on the first response sequence, in response to one or more first request signals, the first arbitrator may respectively send a first response signal to the one or more processing units, and control the processing units to switch from a low power consumption state to a high power consumption state via the response signal. For example, upon receiving the first response signal sent by the first arbitrator, the processing units may switch from a low power consumption state to a high power consumption state immediately or within a preset time.

[0100] In addition, the first response sequence is the order in which the first arbitrator sends first response signals to the processing units. In the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal is sent to the corresponding processing unit is greater than or equal to the first preset time interval. When the first arbitrator receives multiple first request signals, the first arbitrator arbitrates to obtain the first response sequence corresponding to the multiple first request signals, and the time interval between any two times the first response signals are sent in the first response sequence is greater than or equal to the first preset time interval. Exemplarily, when the first arbitrator receives four first request signals, the first arbitrator arbitrates to obtain the first response sequences corresponding to the multiple first request signals as 1, 2, 3, and 4, respectively. Then, the time interval between the time point when the first response signal is sent for the first time and the time point when the first response signal is sent for the second time is greater than or equal to the first preset time interval.

[0101] It should be noted that, based on the first request signal, when the first arbiter continuously raises different processing units, or continuously raises the same processing unit multiple times, the time interval between any two such orders must exceed a first preset time interval. The first preset time interval can be determined based on the number of processing units connected to the arbiter or the current global power consumption state or performance of the processing unit scheduling device, that is, it can be an adjustable time interval based on the current state of the processing unit scheduling device. The first preset time interval can also be a default configured time interval, and the interval of the first preset time interval can be zero or non-zero.

[0102] For example: when the first preset time interval is the default configured time interval, the first preset time interval may not be 0, such as: it may be between 10 nanoseconds and 1 microsecond. This sending method in which the time interval between any two sequences needs to be at least more than 10 nanoseconds can ensure that all processing units will not be pulled up at the same time, thereby avoiding the phenomenon that the voltage undershoot causes the instantaneous voltage to be less than the minimum voltage V for the circuit to work properly, causing the circuit to fail to work properly and the circuit function to be erroneous. For another example: when the current global power consumption state of the processing unit scheduling device is lower or the performance is stronger, the preset time interval can be 0, that is, the first response signal can be sent at the same time to control the corresponding processing unit to switch from a low power consumption state to a high power consumption state. Moreover, the first preset time interval can be adjusted in time according to the current performance (such as: the instantaneous voltage of the output of the on-chip power supply network) to prevent the instantaneous voltage from being lower than the minimum voltage for the normal operation of the circuit.

[0103] It should also be noted that, in some embodiments, when only one first request signal is received, the first arbitrator needs to determine whether the time at which the processing unit was last controlled to switch to the high power consumption state is too close. If the time is too close, it may easily cause multiple processing units to switch to the high power consumption state at similar time points. At the same time, in order to avoid the first arbitrator being unable to control the processing unit to switch to the high power consumption state in a timely manner, resulting in poor chip processing performance, therefore, when the first arbitrator receives only the first request signal sent by one processing unit, the first arbitrator needs to confirm whether the time interval since the last time the first response signal was sent to the processing unit is greater than or equal to a first preset time interval when sending a first response signal to the processing unit. If the time interval is greater than or equal to the first preset time interval, the first response signal can be sent; if the time interval is less than the first preset time interval, the first response signal cannot be sent immediately and needs to wait until the time interval since the last time the first response signal was sent to the processing unit is greater than or equal to the first preset time interval before sending it. That is, when only one first request signal is received or in the first response sequence, the time point when the control processing unit switches to the high power consumption state in the first order needs to be a time interval with the last time the control processing unit switched to the high power consumption state, for example: it can be between 10 nanoseconds and 1 microsecond.

[0104] In addition, in other embodiments, when the current global power consumption state is low or the first preset time interval is 0, when only one first request signal is received, the first arbitrator may not need to determine the last time the control processing unit switched to a high power consumption state, and may directly respond to the first request signal and reply with a corresponding first response signal.

[0105] In some embodiments, the first arbitrator sends the corresponding first response signal to the one or more processing units respectively through serial and / or parallel sending methods; wherein, when the first arbitrator sends the corresponding first response signal to the one or more processing units through parallel sending methods, the parallelism of the parallel sending is less than or equal to M.

[0106] The first arbitrator may send the corresponding first response signal to one or more processing units in a serial or parallel manner, respectively, in accordance with the first response sequence. For example, the first arbitrator may send the corresponding first response signal to one or more processing units only in a serial manner, or only in a parallel manner, or may send the corresponding first response signal to one or more processing units using a combination of serial and parallel modes. That is, the first arbitrator may send one first response signal at a time to control one processing unit to switch to a high power consumption state; or it may send multiple first response signals at a time to control multiple processing units to switch to a high power consumption state simultaneously.

[0107] When controlling multiple processing units to switch to a high power consumption state at the same time, the number of processing units that switch to the high power consumption state at the same time may be less than the total number of processing units connected to the first arbitrator, that is, the parallelism of the parallel transmission of the first arbitrator is less than or equal to N, and N is a positive integer greater than 1 and less than M; the number of processing units that can switch to the high power consumption state at the same time may be equal to the total number M of processing units connected to the first arbitrator.

[0108] Exemplarily, a total of four processing units send first request signals to the first arbitrator. After arbitrating the four first request signals, the first arbitrator obtains the corresponding first response sequence, wherein the first response signals are sent to two processing units for the first time, and the first response signals are sent to the remaining two processing units for the second and third times. The number of the two processing units sent for the first time is less than the total number of processing units connected to the first arbitrator. It is understood that the first arbitrator can control some processing units to switch to a high power consumption state simultaneously, without simultaneously controlling all processing units to switch from a low power consumption state to a high power consumption state, so as to improve arbitration efficiency and ensure the performance of the processing units.

[0109] For example, if the first arbiter determines that the current on-chip power supply can meet the normal operation of the circuit when all processing units are simultaneously switched to a high power state, for example, if the first arbiter obtains information that the overall power consumption is currently low, or obtains information indicating that all processing units can be simultaneously switched to a high power state, or if the first arbiter is subject to higher-level regulation or scheduling, the first arbiter may raise the power consumption of all processing units upon receiving the first request signal. Specifically, if controlling multiple processing units to simultaneously switch to a high power state does not affect the normal operation of the circuit, the maximum number of processing units that can be simultaneously switched to a high power state can be equal to the total number of processing units connected to the arbiter, i.e., the parallelism of the first arbiter's parallel transmission can be less than or equal to M. If the current total power consumption is high and controlling multiple processing units to simultaneously switch to a high power state may cause voltage undershoot, resulting in the circuit not being able to operate normally, the maximum number of processing units that can be simultaneously switched to a high power state must be less than the total number of processing units connected to the arbiter, i.e., the parallelism of the first arbiter's parallel transmission is less than M. The first arbitrator can control some processing units to switch to the high power consumption state while not controlling all processing units to switch to the high power consumption state at the same time, thereby improving arbitration efficiency and ensuring the performance of the processing units.

[0110] In some embodiments, each of the processing units includes one or more high power consumption units HPU, and the first response signal is used to instruct some or all of the high power consumption units in the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0111] As shown in FIG2 and FIG3A above, each processing unit may include one or more high-power consumption units, such as a vector accelerator, a matrix accelerator, etc. When a high-power consumption unit is in a working state, the power consumption is high, which will also cause the power consumption of the corresponding processing unit to increase. Therefore, the processing unit sending a first request signal to the first arbitrator can be understood as a request to switch some or all of the high-power consumption units in the processing unit from a standby state to a working state, that is, from a low-power consumption state to a high-power consumption state, and after the processing unit receives the first response signal, it controls some or all of the high-power consumption units to switch from a low-power consumption state to a high-power consumption state. This method can ensure that the high-power consumption units in the processing unit will not autonomously switch to a high-power consumption state without receiving the first response signal.

[0112] In some embodiments, each of the processing units further includes a prediction module; the prediction module is used to: detect the power consumption status of one or more high-power consumption units in the corresponding processing unit; each of the processing units is specifically used to: send the first request signal to the first arbitrator when the prediction module detects that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0113] Please refer to Figures 4A and 4B, which are schematic diagrams of the structure of a group of processing unit scheduling devices provided in an embodiment of the present application. For ease of explanation, other processing units connected to the first arbitrator are not shown in Figures 4A and 4B. In an embodiment of the present application, as shown in Figures 4A and 4B, each processing unit may further include a prediction module, which can be used to detect the power consumption state of each high-power consumption unit in the corresponding processing unit in real time or periodically, and when some or all of the high-power consumption units are about to switch to the second power consumption state, a first request signal is promptly sent to the first arbitrator to request that the high-power consumption unit be switched from the first power consumption state to the second power consumption state, thereby improving the accuracy and switching efficiency of the processing unit switching power consumption state.

[0114] In some embodiments, the processing unit also includes a task sending queue, which is used to send a task descriptor of the task; the task descriptor is used to indicate whether the task calls the one or more high-power consumption units in the corresponding processing unit; the prediction module is specifically used to: when the task descriptor indicates that the current task calls some or all of the high-power consumption units in the corresponding processing unit, determine that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0115] As shown in FIG4A , a method for a prediction module to predict that a processing unit is about to enter a high power consumption state from a low power consumption state is to determine whether the processing unit or a high power consumption unit in the processing unit is about to enter a high power consumption state from a low power consumption state by judging the task descriptor of the current task in the task sending queue in the processing unit. The task descriptor can be used to indicate whether the current task needs to call the high power consumption unit in the processing unit. When it indicates that the high power consumption unit in the processing unit needs to be called, it indicates that the called high power consumption unit is about to enter a high power consumption state, and the prediction module needs to send a first request signal to the first arbitrator to control the high power consumption unit to enter a high power consumption state. Exemplarily, the processing unit may include a matrix accelerator, and when the prediction module can predict whether the matrix accelerator will be used based on the characteristics of the currently assigned task in the task sending queue (i.e., the task descriptor). For example, when the task descriptor of the currently assigned task in the task sending queue indicates that the task needs to call the matrix accelerator, it can be determined that the matrix accelerator in the processing unit is about to enter a high power consumption state from a low power consumption state to complete the corresponding task.

[0116] In some embodiments, each of the processing units also includes an instruction sending queue; the instruction sending queue is used to send operation instructions; the prediction module is specifically used to: when it is detected that the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue exceeds a preset threshold number, determine that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0117] As shown in FIG4B , another method for the prediction module to predict that the processing unit is about to enter a high power consumption state from a low power consumption state is to determine whether the processing unit or the high power consumption unit in the processing unit is about to enter a high power consumption state from a low power consumption state by detecting the number of operation instructions in the instruction sending queue of the processing unit. When the number of operation instructions corresponding to the high power consumption unit in the instruction sending queue is accumulated in large quantities (for example, exceeding a preset threshold number), it indicates that the processing unit is about to enter a high power consumption state, and the prediction module needs to send a first request signal to the first arbitrator so that the first arbitrator controls the processing unit to enter a high power consumption state. For example, when the prediction module detects that there are a large number of calls or instructions for the matrix accelerator in the instruction sending queue of the processing unit, it indicates that the matrix accelerator needs to enter a working state, that is, it indicates that the processing unit is about to enter a high power consumption state from a low power consumption state to complete the corresponding task. Among them, the preset threshold number can be set by default, and can also be dynamically adjusted according to the power consumption of the current processing unit or the total power consumption of the global processing unit. The embodiment of the present application does not specifically limit the specific value of the preset threshold number.

[0118] It should be noted that the manner in which the prediction module in each processing unit predicts the power consumption state of the processing unit may be the same or different, and the embodiment of the present application does not impose any specific limitation on this.

[0119] In some embodiments, the first arbitrator is specifically configured to arbitrate and obtain the first response order of one or more first request signals according to a preset polling rule or a response priority of one or more processing units among the M processing units.

[0120] The first arbitrator can arbitrate the first response sequence of the first request signal according to a preset polling rule or response priority so as to reply to the first response signal in order. For example: the earlier the first request signal is received, the earlier the response sequence corresponding to the first request signal will be replied. For another example: the first response signal of the same processing unit will not be replied to continuously at the same time. For another example: the higher the response priority of the corresponding processing unit, the earlier the response sequence corresponding to the first request signal will be replied. This arbitration of the response sequence between multiple processing units according to preset rules can improve the arbitration accuracy of the first arbitrator and avoid poor chip performance caused by errors.

[0121] In some embodiments, the first arbitrator is located in the middle of the plurality of processing units; or the sum of the communication distances between the first arbitrator and each of the processing units is the shortest.

[0122] It should be noted that the first arbitrator being disposed in the middle of the plurality of processing units can be located substantially in the middle, or can be understood as being located at the center of a geometric pattern formed by the plurality of processing units, and is not strictly speaking located in the middle. Furthermore, the position where the sum of the communication distances between the first arbitrator and each of the processing units is the shortest can refer to the position where the time consumed by the first arbitrator in communicating with all of the plurality of processing units is the shortest. As shown in FIG2 and FIG3A above, the first arbitrator can be disposed in the middle of the plurality of processing units or at a position where the sum of the communication distances between the first arbitrator and the processing units is the shortest. This placement in the middle can significantly reduce communication delays between the first arbitrator and the processing units, improve processing efficiency, and ensure processing performance.

[0123] In some embodiments, the first arbitrator includes M groups of communication interfaces, each group of the communication interfaces corresponds to one of the processing units, and each group of the communication interfaces includes a request interface and a response interface; wherein each of the request interfaces is used to receive the first request signal sent by the corresponding processing unit, and each of the response interfaces is used to send the first response signal to the corresponding processing unit.

[0124] The first arbitrator can communicate with each processing unit through a dedicated interface module. Please refer to Figure 5, which is a structural diagram of another processing unit scheduling device provided by an embodiment of the present application. As shown in Figure 5, the first arbitrator includes multiple groups of communication interfaces, each of which corresponds to a processing unit. For example, the first request signal req and the first response signal grant are transmitted between the processing unit A and the first arbitrator through the communication interface A; the first request signal req and the first response signal grant are transmitted between the processing unit B and the first arbitrator through the communication interface B. Each group of communication interfaces includes a request interface for transmitting the first request signal req and a response interface for transmitting the response signal grant, so that the first arbitrator and the processing unit can communicate normally, and the communication efficiency between the first arbitrator and the multiple processing units is greatly improved, avoiding the first arbitrator being unable to receive the first request signal in time when multiple processing units send the first request signal to the first arbitrator at the same time.

[0125] In other embodiments, the request interface and response interface for transmitting signals include an input module and an output module provided at the corresponding processing unit and the first arbitrator, respectively. For example, the request interface is provided at the output module of the corresponding processing unit and connected to the input module of the first arbitrator, for transmitting the first request signal req; the response interface is provided at the input module of the corresponding processing unit and connected to the output module of the first arbitrator, for transmitting the first response signal grant.

[0126] In other embodiments, the request interface and response interface for transmitting signals may also be equivalent to including a request output pin and a response output pin set at the corresponding processing unit and the first arbitrator, respectively. It can be understood that when the electrical signal output by the request output pin changes from a low level to a high level, it can be regarded as the corresponding processing unit transmitting the first request signal req to the first arbitrator; when the electrical signal output by the response output pin changes from a low level to a high level, it can be regarded as the first arbitrator transmitting the first response signal grant to the corresponding processing unit, that is, the handshake signal is transmitted between the first arbitrator and the corresponding processing unit through each group of communication interfaces.

[0127] In some embodiments, each of the processing units corresponds to a standby state and multiple high power consumption states, each of the high power consumption states has a different power size, the second power consumption state is one of the multiple high power consumption states, and the first power consumption state is the standby state or one of the multiple high power consumption states with less power than the second power consumption state; wherein, the first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state that the processing unit is in after switching; each of the processing units is also used to: send current power consumption level information to the first arbitrator, and the current power consumption level information is used to indicate the first power consumption state that the processing unit is currently in.

[0128] Among them, the processing unit will have multiple high power consumption states. For example, the highest power consumption level of the processing unit is 3 and the lowest is 0. Then the processing unit corresponds to 3 high power consumption states of levels 1-3 and 1 standby state of level 0, a total of 4 power consumption states. Among them, the power levels of the 4 power consumption states are different. Each time the processing unit switches to the second power consumption state, it is one of the multiple high power consumption states. The original first power consumption state is the standby state or a high power consumption state in the multiple high power consumption states with less power than the second power consumption state. Moreover, each time the processing unit switches to a higher power consumption state, it needs to send a first request signal to the first arbitrator, and then the first arbitrator determines the level of the corresponding adjusted high power consumption state, so that the processing unit can enter different high power consumption states at will, causing the phenomenon of voltage undershoot, resulting in a decrease in output voltage. It should be noted that the definition of power consumption levels by each processing unit and the first arbitrator is consistent.

[0129] In other embodiments, the one or more high-power units included in the processing unit may be consistent with the power consumption levels defined by the processing unit and the first arbitrator. For example, a high-power unit may have three high-power states, levels 1-3, and one standby state, level 0, for a total of four power consumption states. Each time a high-power unit switches to a higher power consumption state, the corresponding processing unit must send a first request signal to the first arbitrator. Upon receiving a response, the processing unit will control the corresponding high-power unit to switch to the higher power consumption state.

[0130] In other embodiments, one or more high-power consumption units included in the processing unit may be inconsistent with the power consumption levels defined by the processing unit and the first arbitrator. For example, a high-power consumption unit may have only two power consumption states: a standby state and one high-power consumption state (i.e., an active state). In this case, each of the multiple high-power consumption states of the processing unit corresponds to a different number of high-power consumption units in the active state. For example, a processing unit may include three high-power consumption units. When one high-power consumption unit is in the active state and the remaining two high-power consumption units are in the standby state, the power consumption of the processing unit may be one-third of the maximum power consumption, and the corresponding level may be 1. When two high-power consumption units are in the active state and the remaining one high-power consumption unit is in the standby state, the power consumption of the processing unit may be two-thirds of the maximum power consumption, and the corresponding level may be 2. When all three high-power consumption units are in the active state, the power consumption of the processing unit may be the maximum power consumption, and the corresponding level may be 3. It is also understood that if the number of high-power consumption units in the processing unit that enter the high-power consumption state from the low-power consumption state is different, the power consumption of the corresponding high-power consumption state of the processing unit will also be different.

[0131] The first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state that the processing unit is in after switching; each of the processing units is also used to: send current power consumption level information to the first arbitrator, and the current power consumption level information is used to indicate the first power consumption state that the processing unit is currently in.

[0132] When a processing unit has multiple power consumption levels, that is, multiple high power consumption states, each processing unit, when sending a first request signal to the first arbitrator, is also configured to send current power consumption level information indicating the first power consumption state the processing unit is currently in to the first arbitrator, and further receive target power consumption level information from the first arbitrator indicating the second power consumption state the processing unit will be in after switching. For example, if a processing unit is in power consumption state level 2 and needs to switch to a higher power consumption state, it needs to send a first request signal and current power consumption level information indicating the current power consumption state (level 2) to the first arbitrator; then, it needs to receive a first response signal from the first arbitrator carrying target power consumption level information (e.g., level 4), which allows the processing unit to switch to the higher power consumption state, and can switch to power consumption state level 4. This method of adjusting the power consumption state of the processing unit controlled by the first arbitrator can globally control the overall power consumption of multiple processing units, which is beneficial for ensuring the stability of the power supply network output voltage and the performance of the chip.

[0133] In some embodiments, each group of the communication interfaces also includes a power level (Power_level) interface, wherein each of the power level interfaces is used to receive the current power consumption level (Current Power_level) information sent by the corresponding processing unit, and each of the response interfaces is also used to send the target power consumption level information (Grant Power_level).

[0134] Since the processing unit may have multiple high power consumption states, in order to facilitate each processing unit to send its current power consumption state to the first arbitrator in a timely manner, each group of communication interfaces may also include an interface for transmitting current power consumption level information. Please refer to Figure 6, which is a schematic diagram of the communication interface of a first arbitrator provided in an embodiment of the present application, wherein for the sake of convenience of explanation, the processing unit connected to the first arbitrator is not illustrated in Figure 6. In an embodiment of the present application, as shown in Figure 6, each group of communication interfaces in the first arbitrator includes a request interface for transmitting a first request signal req, an energy level interface for transmitting current power consumption level information K1 bits, and a response interface for transmitting a first response signal grant carrying target power consumption level information K2 bits. In addition, in order to reduce control costs and improve control efficiency, the response interface in each group of communication interfaces can also be used to send target power consumption level information. For example: the first response signal can carry corresponding target power consumption level information.

[0135] In other embodiments, each group of communication interfaces may further be provided with another energy level interface for transmitting target power consumption level information to the corresponding processing unit. The embodiments of the present application do not impose any specific limitation on this.

[0136] In some embodiments, the first arbitrator and the M processing units constitute a first processing cluster; the device also includes a second arbitrator and multiple first processing clusters, the second arbitrator is connected to the first arbitrator in each of the first processing clusters; each of the first arbitrators is specifically configured to: upon receiving the first request signal, send a second request signal to the second arbitrator; the second arbitrator is configured to: receive the second request signal sent by one or more of the first arbitrators; arbitrate to obtain a second response sequence of one or more of the second request signals; and control one or more of the first arbitrators based on the second response sequence.

[0137] Please refer to Figure 7, which is a schematic diagram of the structure of another processing unit scheduling device provided in an embodiment of the present application. In an embodiment of the present application, a multi-level arbitration architecture can also be provided. As shown in Figure 7, an embodiment of the present application provides a two-level arbitration architecture for the processing unit scheduling device. Specifically, the first-level arbitration architecture refers to a first arbitrator 01 that arbitrates the switching of multiple processing units PE to a high power state at the granularity of a processing unit PE. The second-level arbitration architecture refers to a second arbitrator 02 that arbitrates the switching of multiple processing units PE to a high power state at the granularity of a first processing cluster. For example, as shown in Figure 7, when processing unit PE-A is about to switch from a first power state to a second power state, it sends a first request signal to the first arbitrator 01-A. After receiving the first request signal, the first arbitrator 01-A sends a second request signal to the second arbitrator 02. The second arbitrator 02 arbitrates the received second request signal, obtains a corresponding second response order, and controls the first arbitrator 01-A to respond to the first request signal sent by processing unit PE-A according to the second response order. Therefore, this multi-level arbitration architecture is implemented. In the global state, only some processing units in the first processing cluster can enter the high power consumption state at the same time, which greatly reduces the number of processing units entering high power consumption at the same time, further ensuring the stability of the power supply network output voltage and the performance of the chip.

[0138] It should be noted that the multi-level arbitration structure of the processing unit scheduling device can be adaptively adjusted according to the application scenario. For example, the processing unit scheduling device can also include more levels of arbitration structures, such as a three-level arbitration structure or a four-level arbitration structure, etc., which is not specifically limited in the embodiments of the present application.

[0139] In some embodiments, the second arbitrator is specifically used to: send a second response signal to one or more of the first arbitrators based on the second response sequence, and the second response signal is used to instruct the corresponding first arbitrator to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0140] The second arbitrator 02 controls the first arbitrator's response via a second response signal. The second arbitrator 02 arbitrates the second request signal A received from the first arbitrator 01-A, obtains a second response sequence corresponding to the second request signal A, and then sends a second response signal to the first arbitrator 01-A according to the second response sequence. Only after receiving the second response signal does the first arbitrator 01-A control the processing unit PE-A to switch from the first power consumption state to the second power consumption state according to the first response sequence obtained through arbitration. Only after the second arbitrator sends the second response signal to the corresponding first arbitrator can the first arbitrator sequentially control the corresponding processing unit to switch from the first power consumption state to the second power consumption state. That is, before the first arbitrator 01 receives the second response signal, it will not control the corresponding processing unit to switch to the high-power consumption state according to the first response sequence. This control method based on response signals simplifies the control of arbitrators at all levels, reduces error rates, and ensures chip performance.

[0141] In some embodiments, in the second response sequence, a time interval between each sending of the second response signal to the corresponding second arbitrator and the last sending of the second response signal to the corresponding second arbitrator is greater than or equal to a second preset time interval.

[0142] Similar to the first arbitrator, to ensure that voltage undershoot does not cause the instantaneous voltage to fall below the minimum voltage V for normal operation of the circuit, thereby preventing chip malfunction, the time interval between each response of the second arbitrator to the first arbitrator may be greater than or equal to a second preset time interval. The second preset time interval is not specifically limited in this embodiment of the present application. The second preset time interval may or may not be zero. Furthermore, the second preset time interval may be different from or the same as the first preset time interval.

[0143] Similar to the first arbitrator, when the second arbitrator determines that all processing units in multiple first processing clusters can be switched to a high power consumption state at the same time and the current on-chip power supply can still meet the normal operation of the circuit, the second preset time interval can be 0. For example: when the second arbitrator obtains information that the current overall power consumption is low, or is subject to higher-level regulation or scheduling, etc. After receiving the second request signal, the second arbitrator can control the first arbitrators in all first processing clusters and instruct them to pull up the connected processing units. The second arbitrator can simultaneously control the processing units in all first processing clusters to switch to a high power consumption state, which can improve arbitration efficiency and ensure the performance of the processing units.

[0144] In addition, the second preset time interval and the first preset time interval can both be fixed time intervals set by default, or can be dynamically adjustable time intervals. In other embodiments, the maximum number of processing units that can be pulled up at a time can be adaptively adjusted by configuring the second preset time interval and the first preset time interval to adapt to more application scenarios. For example: when the global power consumption state is very low, the first preset time interval and the second preset time interval can both be set to 0, and the power consumption state of all processing units can be switched at the same time; when the global power consumption state is relatively low, the first preset time interval can be set to non-0, and the second preset time interval can be set to 0; or the first preset time interval is set to 0, and the second preset time interval is set to non-0, and the power consumption state of some processing units can be switched at the same time. When the global power consumption state is relatively high, the first preset time interval and the second preset time interval can both be set to non-0, and the power consumption state of a small number of processing units can be switched at the same time.

[0145] In other embodiments, the second arbitrator can be controlled by a higher-level controller, that is, it can be understood that the working state of the second arbitrator can also be controlled according to the current global power consumption state. For example, when only a small part of the current global processing units (that is, all the processing units in the first processing cluster) are about to switch to high power consumption, and the other processing units are in a low power consumption state, the second arbitrator can be in a standby state. At this time, the first arbitrator of the first processing cluster does not need to send a second request signal to the second arbitrator, and can directly arbitrate and respond to the first request signal. Alternatively, the second arbitrator can be in a normal working state, and the second preset time interval can be directly set to 0 at this time to respond to the first arbitrator faster and improve performance. When a large part of the current global processing units are about to switch to high power consumption, the second arbitrator can be in a normal working state, and the second preset time interval can be set to non-0 to reduce and weaken the voltage undershoot phenomenon and maintain the normal function of the circuit.

[0146] In summary, in order to avoid voltage undershoot and functional errors caused by multiple processing units entering a high power state from a low power state at the same time, an embodiment of the present application provides a processing unit scheduling device, which can prevent multiple processing units from entering a high power state from a low power state at the same time from a hardware perspective, reduce the undershoot amplitude of the voltage undershoot, and make the minimum instantaneous voltage of the voltage undershoot higher than the normal operating voltage of the circuit, thereby ensuring the signal integrity of the chip. Among them, the processing unit scheduling device can be applied to a chip or a related circuit module, and the processing unit scheduling device includes a first arbitrator and M processing units PE connected to the first arbitrator. When any one of the multiple processing units connected to the first arbitrator is about to enter a high power state from a low power state (that is, from a first power state with lower power to a second power state with higher power), each processing unit must send a first request signal to the first arbitrator to request to switch the power consumption state. Upon receiving the first request signal sent by the connected processing unit, the first arbitrator can arbitrate the received first request signal and determine the corresponding response order. The first arbitrator can then sequentially control the corresponding processing units to switch from a low-power state to a high-power state according to the response order. This prevents all of the multiple processing units connected to the first arbitrator from switching from a low-power state to a high-power state simultaneously, which could cause voltage undershoot, functional errors, and compromise signal integrity. For example, if the instantaneous voltage falls below the minimum voltage Vmin for proper operation of a MOS transistor, the MOS transistor may shut down, leading to chip functional errors. With the arbitrator connected between multiple processing units, each processing unit undergoes arbitration by the arbitrator when switching power states. This allows the arbitrator to schedule the power state switching of some of the multiple processing units. Furthermore, compared to software algorithm-based scheduling within a device or apparatus, this significantly reduces the overhead of the device or apparatus and reduces the probability of scheduling errors causing all processing units to switch from a low-power state to a high-power state simultaneously, thereby ensuring the chip's signal performance.

[0147] Based on the structure of the processing unit scheduling device provided in FIG. 2 above, the technical problems raised in this application are specifically analyzed and solved in combination with the processing unit scheduling method provided in the embodiments of this application.

[0148] Please refer to FIG. 8 , which is a flowchart of a processing unit scheduling method provided in an embodiment of the present application. The method is applied to the processing unit scheduling device shown in FIG. 2 to FIG. 7 . The processing unit scheduling device includes a first arbitrator and M processing units (PEs) connected to the first arbitrator, where M is a positive integer greater than or equal to 2. The method includes:

[0149] Step S201: receiving a first request signal respectively sent by one or more processing units among the M processing units.

[0150] Specifically, the first arbitrator receives a first request signal sent by one or more of the M processing units connected to it, and the first request signal is used to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, and the power of the first power consumption state is lower than the power of the second power consumption state.

[0151] Optionally, each of the processing units also includes a prediction module; the method also includes: detecting the power consumption status of one or more high-power consumption units in the corresponding processing unit through the prediction module; when the prediction module detects that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state, sending the first request signal to the first arbitrator through the corresponding processing unit.

[0152] Optionally, each of the processing units further includes a task sending queue, which is used to send a task descriptor of the current task; the task descriptor is used to indicate whether the current task calls the one or more high-power consumption units in the corresponding processing unit; detecting the power consumption state of the one or more high-power consumption units in the corresponding processing unit through the prediction module includes: obtaining the task descriptor of the current task in the task sending queue, wherein, when the task descriptor indicates that the current task calls some or all of the high-power consumption units in the corresponding processing unit, determining that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0153] Optionally, each of the processing units further includes an instruction sending queue; the instruction sending queue is used to send operation instructions; the detection of the power consumption state of the one or more high-power consumption units in the corresponding processing unit through the prediction module includes: detecting the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue, wherein, when it is detected that the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue exceeds a preset threshold number, it is determined that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0154] Optionally, the first arbitrator is arranged in the middle of the multiple processing units; or the sum of the communication distances between the first arbitrator and each of the processing units is the shortest.

[0155] Step S202: obtain a first response sequence of one or more first request signals through arbitration.

[0156] Specifically, the first arbitrator performs arbitration on the received one or more first request signals, and obtains a first response sequence of the one or more first request signals through arbitration.

[0157] Optionally, the arbitration obtains the first response order of one or more first request signals, including: arbitrating according to a preset polling rule or the response priority of one or more processing units among the M processing units to obtain the first response order of one or more first request signals.

[0158] Step S203: Based on the first response sequence, control one or more processing units to switch from the first power consumption state to the second power consumption state.

[0159] Specifically, the first arbitrator controls one or more processing units to switch from the first power consumption state to the second power consumption state based on the first response sequence.

[0160] Optionally, controlling the one or more processing units to switch from the first power consumption state to the second power consumption state based on the first response sequence includes: sending a first response signal to the one or more processing units respectively based on the first response sequence, the first response signal being used to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state; wherein, in the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal is sent to the corresponding processing unit is greater than or equal to a first preset time interval.

[0161] Optionally, the first arbitrator sends the corresponding first response signal to the one or more processing units respectively through a serial and / or parallel sending manner; wherein, when the first arbitrator sends the corresponding first response signal to the one or more processing units through a parallel sending manner, the parallelism of the parallel sending is less than or equal to M.

[0162] Optionally, each of the processing units includes one or more high power consumption units HPU, and the first response signal is used to instruct some or all of the high power consumption units in the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0163] Optionally, the first arbitrator includes M groups of communication interfaces, each group of the communication interfaces corresponds to one of the processing units, and each group of the communication interfaces includes a request interface and a response interface; wherein each of the request interfaces is used to receive the first request signal sent by the corresponding processing unit, and each of the above-mentioned response interfaces is used to send the first response signal to the corresponding processing unit.

[0164] Optionally, each of the processing units corresponds to a standby state and multiple high power consumption states, each of the high power consumption states has a different power size, the second power consumption state is one of the multiple high power consumption states, and the first power consumption state is the standby state or a high power consumption state among the multiple high power consumption states, and the power is less than that of the second power consumption state; wherein, the first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state that the processing unit is in after switching; the method also includes: receiving current power consumption level information sent by one or more processing units among the M processing units, and the current power consumption level information is used to indicate the first power consumption state that the corresponding processing unit is currently in.

[0165] Optionally, each group of the communication interfaces further includes an energy level interface, wherein each of the energy level interfaces is used to receive the current power consumption level information sent by the corresponding processing unit, and each of the response interfaces is further used to send the target power consumption level information.

[0166] Optionally, the first arbitrator and the M processing units constitute a first processing cluster; the device also includes a second arbitrator and multiple first processing clusters, and the second arbitrator is connected to the first arbitrator in each of the first processing clusters; the method also includes: receiving, through the second arbitrator, a second request signal sent by one or more first arbitrators when receiving the first request signal; obtaining a second response sequence of one or more second request signals through arbitration by the second arbitrator; and controlling the corresponding one or more first arbitrators based on the second response sequence.

[0167] Optionally, controlling the corresponding one or more first arbitrators based on the second response sequence includes: sending a second response signal to the corresponding one or more first arbitrators based on the second response sequence, the second response signal being used to instruct the corresponding first arbitrator to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0168] Optionally, in the second response sequence, a time interval between each sending of the second response signal to the corresponding second arbitrator and the last sending of the second response signal to the corresponding second arbitrator is greater than or equal to a second preset time interval.

[0169] It should be noted that for the relevant descriptions of steps S201 to S203 in the method embodiments described in the embodiments of the present application, please refer to the relevant descriptions of the functions of the various functional units of the processing unit scheduling device in the device embodiments shown in Figures 2 to 7 above, and the embodiments of the present application will not be repeated here.

[0170] In addition, an embodiment of the present application further provides a chip, which includes a circuit and a processing unit scheduling device as described in any of the above embodiments and applied to the circuit. The chip may also include a power supply network that can be used to power the processing unit scheduling device.

[0171] An embodiment of the present application further provides an electronic device, comprising: a circuit board and the processing unit scheduling device involved in any of the aforementioned embodiments; the circuit board is electrically connected to the processing unit scheduling device.

[0172] An embodiment of the present application further provides a server comprising a circuit board and the processing unit scheduling device described in any of the aforementioned embodiments; the circuit board is electrically connected to the processing unit scheduling device. Optionally, the server further comprises an on-chip power supply system to power the processing unit scheduling device.

[0173] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program code is stored. When the processor executes the computer program code, the computer executes the method in any of the aforementioned embodiments.

[0174] An embodiment of the present application further provides a computer program product, which, when executed on a computer, enables the computer to execute the method in any of the aforementioned embodiments.

[0175] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0176] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0177] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0178] In addition, the functional units in the embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0179] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to execute all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0180] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A processing unit scheduling device, characterized in that: The device comprises a first arbitrator and M processing units PE connected to the first arbitrator, where M is a positive integer greater than or equal to 2; wherein, Each of the processing units is used to: send a first request signal to the first arbitrator, wherein the first request signal is used to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, wherein the power of the first power consumption state is lower than the power of the second power consumption state; The first arbitrator is used to: receive the first request signals respectively sent by one or more processing units among the M processing units, and arbitrate to obtain a first response sequence of one or more of the first request signals; based on the first response sequence, control the one or more processing units to switch from the first power consumption state to the second power consumption state.

2. The device according to claim 1, characterized in that: The first arbitrator is specifically configured to: send a first response signal to the one or more processing units respectively based on the first response sequence, wherein the first response signal is used to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state; Among them, in the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal was sent to the corresponding processing unit is greater than or equal to a first preset time interval.

3. The device according to claim 2, characterized in that: The first arbitrator sends the corresponding first response signal to the one or more processing units respectively in a serial and / or parallel sending manner; In which, when the first arbitrator sends the corresponding first response signal to the one or more processing units in a parallel sending manner, the parallel degree of the parallel sending is less than or equal to M.

4. The device according to claim 2 or 3, characterized in that: Each of the processing units includes one or more high power consumption units HPU, and the first response signal is used to instruct part or all of the high power consumption units in the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

5. The device according to claim 4, characterized in that: Each of the processing units also includes a prediction module; The prediction module is used to: detect the power consumption state of one or more high power consumption units in the corresponding processing unit; and send the first request signal to the first arbitrator when it is detected that some or all of the high power consumption units will switch from the first power consumption state to the second power consumption state.

6. The device according to claim 5, characterized in that: Each of the processing units further comprises a task sending queue, wherein the task sending queue is used to send a task descriptor of a current task; the task descriptor is used to indicate whether the current task calls the one or more high power consumption units in the corresponding processing unit; The prediction module is specifically used to: when the task descriptor indicates that the current task calls part or all of the high power consumption units in the corresponding processing unit, determine that the part or all of the high power consumption units will switch from the first power consumption state to the second power consumption state.

7. The device according to claim 5, characterized in that: Each of the processing units also includes an instruction sending queue; the instruction sending queue is used to send operation instructions; The prediction module is specifically used to: when it is detected that the number of operation instructions corresponding to some or all of the high power consumption units in the instruction sending queue exceeds a preset threshold number, determine that some or all of the high power consumption units will switch from the first power consumption state to the second power consumption state.

8. The device according to any one of claims 1 to 7, characterized in that: The first arbitrator is arranged in the middle of the plurality of processing units; or the sum of the communication distances between the first arbitrator and each of the processing units is the shortest.

9. The device according to any one of claims 1 to 8, characterized in that: The first arbitrator includes M groups of communication interfaces, each group of the communication interfaces corresponds to one of the processing units, and each group of the communication interfaces includes a request interface and a response interface; wherein each of the request interfaces is used to receive the first request signal sent by the corresponding processing unit, and each of the above-mentioned response interfaces is used to send a first response signal to the corresponding processing unit.

10. The device according to claim 9, characterized in that: Each of the processing units corresponds to a standby state and a plurality of high power consumption states, each of the high power consumption states has a different power level, the second power consumption state is one of the plurality of high power consumption states, and the first power consumption state is the standby state or a high power consumption state in the plurality of high power consumption states whose power is less than that in the second power consumption state; The first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state of the processing unit after switching; Each of the processing units is further used for sending current power consumption level information to the first arbitrator, where the current power consumption level information is used for indicating the first power consumption state that the processing unit is currently in.

11. The device according to claim 10, characterized in that: Each group of the communication interfaces further includes an energy level interface, wherein each of the energy level interfaces is used to receive the current power consumption level information sent by the corresponding processing unit, and each of the response interfaces is also used to send the target power consumption level information.

12. The device according to any one of claims 1 to 11, characterized in that: The first arbitrator and the M processing units form a first processing cluster; the device further comprises a second arbitrator and a plurality of the first processing clusters, the second arbitrator being connected to the first arbitrator in each of the first processing clusters; Each of the first arbitrators is specifically configured to: upon receiving the first request signal, send a second request signal to the second arbitrator; The second arbitrator is used for: receiving the second request signal sent by one or more first arbitrators; Arbitrating to obtain a second response sequence of one or more of the second request signals; Based on the second response order, one or more of the first arbitrators are controlled.

13. The device according to any one of claim 12, characterized in that: The second arbitrator is specifically used to: send a second response signal to one or more of the first arbitrators based on the second response sequence, and the second response signal is used to instruct the corresponding first arbitrator to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

14. The device according to any one of claim 12, characterized in that: In the second response sequence, a time interval between each sending of the second response signal to the corresponding second arbitrator and the last sending of the second response signal to the corresponding second arbitrator is greater than or equal to a second preset time interval.

15. A processing unit scheduling method, characterized in that: Applied to a processing unit scheduling device, the processing unit scheduling device includes a first arbitrator and M processing units PE connected to the first arbitrator, M being a positive integer greater than or equal to 2; the method includes: receiving first request signals respectively sent by one or more processing units among the M processing units, and obtaining a first response sequence of one or more of the first request signals by arbitration, wherein the first request signal is used to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, and the power of the first power consumption state is lower than the power of the second power consumption state; Based on the first response sequence, the one or more processing units are controlled to switch from the first power consumption state to the second power consumption state.

16. A chip, characterized in that: It comprises a circuit and a processing unit scheduling device as claimed in any one of claims 1 to 14 applied to the circuit.

17. A server, characterized in that: The server comprises a circuit board and a device as described in any one of claims 1 to 14; the circuit board is electrically connected to the device.

18. An electronic device, characterized in that: The electronic device comprises: a circuit board and a device as described in any one of claims 1 to 14; the circuit board is electrically connected to the device.

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