Semiconductor device

Abstract

Provided is a highly reliable semiconductor device. The semiconductor device includes an oxide semiconductor layer, first to third electroconductive layers, and first to third insulating layers. The first insulating layer is positioned on the first electroconductive layer. The second electroconductive layer is positioned on the first insulating layer. The first electroconductive layer has a first recess. The first insulating layer and the second electroconductive layer have a first opening at a position overlapping the first recess. The second insulating layer is in contact, in the first opening, with at least the side surface of the first insulating layer. The oxide semiconductor layer is in contact with the upper surface of the second electroconductive layer and the bottom surface and the side surface of the first recess, and is in contact, in the first opening, with the second insulating layer. The third insulating layer is located, in the first opening, on the inner side of the oxide semiconductor layer. The third conductive layer is located, in the first opening, on the inner side of the third insulating layer. The first insulating layer has a barrier property against hydrogen. The second insulating layer has a function of capturing or fixing hydrogen.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use large-scale integration (LSI), central processing units (CPUs), memories, etc. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance. Another object of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio. Another object of one embodiment of the present invention is to provide a highly reliable transistor, a semiconductor device, a display device, or a memory device. Another object of one embodiment of the present invention is to provide a semiconductor device, a display device, or a memory device with low power consumption. Another object of one embodiment of the present invention is to provide a memory device with high operating speed. Another object of one embodiment of the present invention is to provide a manufacturing method of the transistor, the semiconductor device, the display device, or the memory device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first conductive layer has a first recess. The first insulating layer and the second conductive layer have a first opening overlapping the first recess. The second insulating layer is in contact with at least a side surface of the first insulating layer in the first opening. The oxide semiconductor layer is in contact with a top surface of the second conductive layer and a bottom surface and side surfaces of the first recess, and is in contact with the second insulating layer in the first opening. The third insulating layer is located inside the oxide semiconductor layer in the first opening. The third conductive layer is located inside the third insulating layer in the first opening. The first insulating layer has a barrier property against hydrogen. The second insulating layer has the function of trapping or fixing hydrogen.

[0014] In the above semiconductor device, it is preferable that the first insulating layer contains silicon and nitrogen, and the second insulating layer contains one or both of hafnium and aluminum, and oxygen.

[0015] In the above semiconductor device, it is preferable that the second insulating layer includes a first layer in contact with the first insulating layer and a second layer located between the first layer and the oxide semiconductor layer, the first layer having a function of capturing or fixing hydrogen, and the second layer having a region containing excess oxygen.

[0016] In the above semiconductor device, it is preferable that the first insulating layer contains silicon and nitrogen, the first layer contains one or both of hafnium and aluminum, and oxygen, and the second layer contains one or both of silicon and aluminum, and oxygen.

[0017] In the above semiconductor device, it is preferable that the semiconductor device further includes a fourth insulating layer, the third insulating layer covers the top surface and side surfaces of the oxide semiconductor layer on the first insulating layer, the fourth insulating layer is located on the third insulating layer, and has a second opening at a position overlapping with the first opening, and the third conductive layer has a portion that faces the oxide semiconductor layer via the third insulating layer in the first opening, and a portion that is located in the second opening.

[0018] In the semiconductor device, the width of the second opening is preferably narrower than the width of the first opening.

[0019] In the above semiconductor device, it is preferable that the first conductive layer has a fourth conductive layer and a fifth conductive layer on the fourth conductive layer, the fifth conductive layer has a second recess, the first opening overlaps the second recess, and the second insulating layer contacts the bottom and side surfaces of the second recess.

[0020] In the semiconductor device, it is preferable that the oxide semiconductor layer contains indium, and that, when a cross section of the oxide semiconductor layer is observed using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to a side surface of the first insulating layer in the first opening are confirmed.

[0021] In the above semiconductor device, it is preferable that the oxide semiconductor layer contains indium, the oxide semiconductor layer has a first region, a second region in contact with the first region, and a third region in contact with the second region, and that, in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction parallel to a side surface of the first insulating layer in the first opening are confirmed in each of the first region, the second region, and the third region.

[0022] In the above semiconductor device, it is preferable that the indium content in the first region is higher than the indium content in the second region, and the indium content in the third region is higher than the indium content in the second region.

[0023] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first conductive layer has a first recess. The first insulating layer and the second conductive layer have a first opening overlapping the first recess. The second insulating layer is in contact with at least a side surface of the first insulating layer in the first opening. The oxide semiconductor layer is in contact with a top surface of the second conductive layer and a bottom surface and side surfaces of the first recess, and is in contact with the second insulating layer in the first opening. The third insulating layer is located inside the oxide semiconductor layer in the first opening. The third conductive layer is located inside the third insulating layer in the first opening. The second insulating layer includes a first layer in contact with the first insulating layer and a second layer between the first layer and the oxide semiconductor layer. The first insulating layer includes a third layer, a fourth layer on the third layer, and a fifth layer on the fourth layer. Each of the first layer, the third layer, and the fifth layer has a barrier property against hydrogen. The second layer has a function of capturing or fixing hydrogen.

[0024] In the above-described semiconductor device, it is preferable that the first layer, the third layer, and the fifth layer each contain silicon and nitrogen, and the second layer contain one or both of hafnium and aluminum, and oxygen.

[0025] In the above semiconductor device, the second insulating layer preferably includes a sixth layer located between the second layer and the oxide semiconductor layer, and the sixth layer preferably includes a region containing excess oxygen.

[0026] In the above-described semiconductor device, it is preferable that the first layer, the third layer, and the fifth layer each contain silicon and nitrogen, the second layer contain one or both of hafnium and aluminum, and oxygen, and the sixth layer contain one or both of silicon and aluminum, and oxygen.

[0027] In the above semiconductor device, it is preferable that the semiconductor device further includes a fourth insulating layer, the third insulating layer covers the top surface and side surfaces of the oxide semiconductor layer on the first insulating layer, the fourth insulating layer is located on the third insulating layer, and has a second opening at a position overlapping with the first opening, and the third conductive layer has a portion that faces the oxide semiconductor layer via the third insulating layer in the first opening, and a portion that is located in the second opening.

[0028] In the semiconductor device, the width of the second opening is preferably narrower than the width of the first opening.

[0029] In the above semiconductor device, it is preferable that the first conductive layer has a fourth conductive layer and a fifth conductive layer on the fourth conductive layer, the fifth conductive layer has a second recess, the first opening overlaps the second recess, and the second insulating layer contacts the bottom and side surfaces of the second recess.

[0030] In the semiconductor device, it is preferable that the oxide semiconductor layer contains indium, and that, when a cross section of the oxide semiconductor layer is observed using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to a side surface of the first insulating layer in the first opening are confirmed.

[0031] In the above semiconductor device, it is preferable that the oxide semiconductor layer contains indium, the oxide semiconductor layer has a first region, a second region in contact with the first region, and a third region in contact with the second region, and that, in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction parallel to a side surface of the first insulating layer in the first opening are confirmed in each of the first region, the second region, and the third region.

[0032] In the above semiconductor device, it is preferable that the indium content in the first region is higher than the indium content in the second region, and the indium content in the third region is higher than the indium content in the second region.

[0033] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a transistor with high on-state current can be provided. According to another embodiment of the present invention, a transistor with low parasitic capacitance can be provided. According to another embodiment of the present invention, a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to another embodiment of the present invention, a highly reliable transistor, a semiconductor device, a display device, or a memory device can be provided. According to another embodiment of the present invention, a semiconductor device, a display device, or a memory device with low power consumption can be provided. According to another embodiment of the present invention, a memory device with high operating speed can be provided. According to another embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, display device, or memory device can be provided.

[0034] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0035] FIGS. 1A and 1B are perspective views showing an example of a semiconductor device. FIGS. 2A1 and 2A2 are plan views showing an example of a semiconductor device. FIGS. 2B to 2E are cross-sectional views showing an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing an example of a semiconductor device. FIG. 4 is a cross-sectional view showing an example of a semiconductor device. FIG. 5 is a cross-sectional view showing an example of a semiconductor device. FIG. 6 is a cross-sectional view showing an example of a semiconductor device. FIGS. 7A to 7C are cross-sectional views showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing an example of a semiconductor device. FIGS. 10A and 10B are perspective views showing an example of a semiconductor device. FIG. 11A is a plan view showing an example of a semiconductor device. FIGS. 11B to 11E are cross-sectional views showing an example of a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing an example of a semiconductor device. FIG. 13A is a plan view showing an example of a semiconductor device. FIGS. 13B to 13E are cross-sectional views showing an example of a semiconductor device. FIG. 14 is a cross-sectional view showing an example of a semiconductor device. FIG. 15A is a plan view showing an example of a semiconductor device. 15B to 15E are cross-sectional views showing an example of a semiconductor device. FIG. 16 is a cross-sectional view showing an example of a semiconductor device. FIGS. 17A to 17D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 18A to 18C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 19A to 19F are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 20A to 20F are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 21A1 and 21A2 are plan views showing an example of a semiconductor device. FIGS. 21B to 21E are cross-sectional views showing an example of a semiconductor device. FIGS. 22A and 22B are cross-sectional views showing an example of a semiconductor device. FIGS. 23A and 23B are cross-sectional views showing an example of a semiconductor device. FIGS. 24A and 24B are cross-sectional views showing an example of a semiconductor device. FIGS. 25A and 25B are cross-sectional views showing an example of a semiconductor device. FIG. 26 is a cross-sectional view showing an example of a semiconductor device. FIGS. 27A and 27B are cross-sectional views showing an example of a semiconductor device. FIGS. 28A and 28B are perspective views showing an example of a semiconductor device. 29A1 and 29A2 are plan views showing an example of a semiconductor device.29B to 29E are cross-sectional views illustrating an example of a semiconductor device. FIGS. 30A and 30B are cross-sectional views illustrating an example of a semiconductor device. FIG. 31 is a cross-sectional view illustrating an example of a semiconductor device. FIGS. 32A and 32B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 33A and 33B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 34A and 34B are cross-sectional views illustrating an example of a semiconductor device. FIG. 35 is a cross-sectional view illustrating an example of a semiconductor device. FIGS. 36A to 36D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 37A to 37D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIG. 38A is a plan view illustrating an example of a memory device. FIGS. 38B and 38C are cross-sectional views illustrating an example of a memory device. FIGS. 39A and 39B are cross-sectional views illustrating an example of a memory device. FIG. 40A is a plan view illustrating an example of a memory device. FIG. 40B is a cross-sectional view illustrating an example of a memory device. FIG. 41 is a cross-sectional view illustrating an example of a memory device. FIG. 42 is a cross-sectional view illustrating an example of a memory device. FIG. 43 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 44A to 44G are diagrams illustrating circuit configuration examples of a memory cell. FIGS. 45A and 45B are perspective views illustrating a configuration example of a semiconductor device. FIG. 46 is a block diagram illustrating a CPU. FIGS. 47A and 47B are perspective views of a semiconductor device. FIGS. 48A and 48B are perspective views of a semiconductor device. FIGS. 49A and 49B are diagrams illustrating various memory devices by layer. FIGS. 50A and 50B are circuit diagrams of a semiconductor device according to one embodiment of the present invention, and FIG. 50C is a diagram illustrating an example of an electronic component using a semiconductor device according to one embodiment of the present invention. FIGS. 51A and 51B are perspective views of an example of a display device. FIG. 52 is a cross-sectional view of an example of a display device. FIG. 53 is a cross-sectional view of an example of a display device. FIGS. 54A to 54C are diagrams illustrating a configuration example of a display device. FIG. 55 is a diagram illustrating an example of an electronic component. FIGS. 56A to 56C are diagrams illustrating an example of a mainframe computer. FIG. 56D is a diagram illustrating an example of space equipment. Fig. 56E is a diagram showing an example of a storage system applicable to a data center. Figs. 57A to 57F are diagrams showing examples of electronic equipment.58A to 58G are diagrams showing an example of an electronic device. 59A to 59F are diagrams showing an example of an electronic device. 60A to 60D are SIMS analysis results of samples fabricated in Examples. 61A to 61E are TDS analysis results of samples fabricated in Examples.

[0036] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0037] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0038] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0039] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0040] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0041] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0042] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0043] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0044] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0045] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0046] To analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0047] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0048] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0049] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0050] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0051] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0052] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0053] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0054] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0055] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0056] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0057] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0058] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0059] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0060] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0061] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0062] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0063] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0064] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0065] A semiconductor device of one embodiment of the present invention includes an oxide semiconductor layer, first to third conductive layers, and first to third insulating layers.

[0066] The oxide semiconductor layer functions as a semiconductor layer of a transistor, the first conductive layer functions as one of a source electrode and a drain electrode of the transistor, the second conductive layer functions as the other of the source electrode and the drain electrode of the transistor, and the third conductive layer functions as a gate electrode of the transistor. The third insulating layer functions as a gate insulating layer of the transistor.

[0067] The first insulating layer is located on the first conductive layer, and the second conductive layer is located on the first insulating layer, the first conductive layer having a first recess, and the first insulating layer and the second conductive layer have a first opening overlapping the first recess. The second insulating layer contacts at least a side surface of the first insulating layer within the first opening. The oxide semiconductor layer contacts an upper surface of the second conductive layer and a bottom surface and side surface of the first recess, and contacts the second insulating layer within the first opening. The third insulating layer is located inside the oxide semiconductor layer within the first opening. The third conductive layer is located inside the third insulating layer within the first opening.

[0068] A semiconductor device according to one embodiment of the present invention has a structure in which a first insulating layer surrounds an oxide semiconductor layer in a plan view. In particular, when the oxide semiconductor layer located in the first opening has a circular shape in a plan view, the first insulating layer surrounds the oxide semiconductor layer in a ring shape. Furthermore, a second insulating layer is disposed between the first insulating layer and the oxide semiconductor layer. Therefore, it is preferable that the first insulating layer has a barrier property against hydrogen, and the second insulating layer has a function of capturing or fixing hydrogen. With such a structure, impurities such as hydrogen in the oxide semiconductor layer can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be enhanced.

[0069] Note that the second insulating layer may be composed of multiple layers. For example, the second insulating layer can be composed of two layers: a first layer in contact with the first insulating layer and a second layer located between the first layer and the oxide semiconductor layer. When the second insulating layer is composed of two layers, the first layer preferably has a function of capturing or fixing hydrogen, and the second layer preferably has a region containing excess oxygen. With such a structure, one or both of oxygen vacancies and impurities in the oxide semiconductor layer can be reduced.

[0070] Furthermore, the semiconductor device of one embodiment of the present invention can have a structure in which the first layer has a barrier property against hydrogen, and the second layer has a function of capturing or adhering hydrogen. With such a structure, the oxide semiconductor layer can be surrounded by the first layer having a barrier property against hydrogen in a ring shape, and the second layer having a function of capturing or adhering hydrogen can be disposed between the first layer and the oxide semiconductor layer. In this case, the material used for the first insulating layer is not particularly limited. For example, the first insulating layer can have a stacked structure of a third layer, a fourth layer on the third layer, and a fifth layer on the fourth layer. In this case, it is preferable that the third layer and the fifth layer have a barrier property against hydrogen.

[0071] In a transistor according to one embodiment of the present invention, a first recess is provided in the first conductive layer. This allows the height of the bottom surface of the third insulating layer and the bottom surface of the third conductive layer in the first opening to be lower than in a case where the first recess is not provided. Therefore, a gate electric field can be easily applied to the oxide semiconductor layer, thereby improving the electrical characteristics of the transistor. Here, the height of each surface can be determined, for example, based on the surface on which the transistor is formed.

[0072] Furthermore, if the parasitic capacitance generated between the source electrode or drain electrode and the gate wiring is large, the operation of the transistor may become slow, and the frequency characteristics of a circuit using the transistor may be degraded.

[0073] Therefore, the transistor of one embodiment of the present invention preferably has a structure in which parasitic capacitance generated between the second conductive layer and the third conductive layer is reduced, thereby enabling the transistor to operate at high speed and providing a semiconductor device with favorable electrical characteristics.

[0074] For example, the semiconductor device of one embodiment of the present invention preferably further includes a fourth insulating layer. In this case, it is preferable that the third insulating layer covers the top surface and side surfaces of the oxide semiconductor layer over the first insulating layer, the fourth insulating layer is located over the third insulating layer and has a second opening at a position overlapping with the first opening, and the third conductive layer has a portion facing the oxide semiconductor layer in the first opening with the third insulating layer therebetween and a portion located in the second opening. Alternatively, it is preferable that the fourth insulating layer is located over the first insulating layer and covers the top surface and side surfaces of the oxide semiconductor layer over the first insulating layer and has the second opening at a position overlapping with the first opening, the third insulating layer has a portion located in the second opening, and the third conductive layer is located inside the third insulating layer in the second opening.

[0075] The third conductive layer has a portion facing the oxide semiconductor layer through the third insulating layer in the first opening and a portion located in the second opening. In this case, the gate wiring is disposed on the fourth insulating layer, thereby increasing the physical distance between the second conductive layer and the gate wiring. Therefore, the parasitic capacitance generated between the second conductive layer and the gate wiring can be reduced. Note that a portion of the third conductive layer (the portion located on the fourth insulating layer) may function as the gate wiring, or a gate wiring may be provided on the fourth insulating layer separately from the third conductive layer.

[0076] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0077] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0078] Furthermore, the channel length of the transistor of one embodiment of the present invention can be controlled by the thicknesses of the first insulating layer, the second conductive layer, and the like. Therefore, a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor, can be realized. Therefore, a transistor with a small occupation area and large on-state current can be realized.

[0079] Furthermore, since a transistor including an oxide semiconductor has a small off-state current, when used in a memory device, for example, stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. By using the transistor of one embodiment of the present invention in a memory device, high integration and low power consumption of the memory device can be achieved.

[0080] <Structural Example 1 of Semiconductor Device> A structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 5 . FIG.

[0081] 1A and 1B are schematic perspective views of a semiconductor device having a transistor 200. Fig. 1B is a perspective view with a portion cut away from Fig. 1A. In Fig. 1A and 1B, only the outlines of some components (such as interlayer insulating layers) are indicated by dashed lines.

[0082] 1A and 1B, the X direction, the Y direction, and the Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in both Fig. 1A and Fig. 1B, the directions do not necessarily have to match.

[0083] FIG. 2A1 is a plan view of a semiconductor device having a transistor 200. FIG. 2A2 is a plan view showing an example in which a plurality of transistors 200 are arranged. FIG. 2B is a cross-sectional view taken along dashed dotted lines A1-A2 in FIG. 2A1. FIG. 2C is a cross-sectional view taken along dashed dotted lines A3-A4 in FIG. 2A1. FIGS. 2D and 2E are cross-sectional views taken along dashed dotted lines A5-A6 in FIG. 2B. FIG. 2E corresponds to an example of an enlarged view of FIG. 2D. FIGS. 2D and 2E can also be considered cross-sectional views of the XY plane including the insulating layer 280. Note that some elements are omitted in the plan views of FIGS. 2A1 and 2A2 for clarity. Some elements may also be omitted in the subsequent plan views.

[0084] 3A to 5 are cross-sectional views taken along dashed line A1-A2 in Fig. 2A1, and are examples of enlarged views of Fig. 2B, each showing an example of the configuration of each layer in more detail.

[0085] 1A to 2E includes an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. The insulating layer 210 and the insulating layer 280 function as interlayer films.

[0086] [Transistor 200] The transistor 200 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 240a over the insulating layer 280, a conductive layer 240b over the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, a conductive layer 265a over the insulating layer 250, and a conductive layer 265b over the conductive layer 265a.

[0087] Note that, hereinafter, the conductive layers 220a and 220b may be collectively referred to as the conductive layer 220. Furthermore, the conductive layers 240a and 240b may be collectively referred to as the conductive layer 240. Furthermore, the conductive layers 265a and 265b may be collectively referred to as the conductive layer 265. That is, Figures 2B and 2C show an example in which the conductive layer 220 has a two-layer structure of the conductive layer 220a and the conductive layer 220b on the conductive layer 220a.

[0088] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 265 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode. The conductive layer 265 also functions as a gate wiring.

[0089] The oxide semiconductor layer 230 has a region overlapping with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200. One of the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 and the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0090] As shown in FIGS. 2B and 2C, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280, the conductive layer 240a, and the conductive layer 240b.

[0091] The opening 290 includes an opening in the insulating layer 280, an opening in the conductive layer 240a, and an opening in the conductive layer 240b. In other words, the opening in the region where the insulating layer 280 overlaps with the conductive layer 220a is one part of the opening 290, the opening in the region where the conductive layer 240a overlaps with the conductive layer 220a is another part of the opening 290, and the opening in the region where the conductive layer 240b overlaps with the conductive layer 220a is another part of the opening 290. The shape and size of the opening 290 in a planar view may differ depending on the layer. Furthermore, when the top surface shape of the opening 290 is circular, the openings in each layer may or may not be concentric.

[0092] At least some of the components of the transistor 200 are disposed in the opening 290. Specifically, at least some of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265 are disposed in the opening 290.

[0093] The insulating layer 235 is provided along at least a part of the sidewall of the opening 290. The insulating layer 235 has at least a region located between the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 235 can also be called a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0094] Portions of the oxide semiconductor layer 230 and the insulating layer 250 that are disposed within the opening 290 are provided to reflect the shape of the opening 290. Specifically, the oxide semiconductor layer 230 is provided so as to cover the bottom and sidewalls of the opening 290 with the insulating layer 235 interposed therebetween. That is, the oxide semiconductor layer 230 is in contact with the insulating layer 235 within the opening 290. The insulating layer 250 is also provided so as to cover the oxide semiconductor layer 230. Then, a conductive layer 265a is provided so as to fill at least a portion of the recess in the insulating layer 250 that reflects the shape of the opening 290.

[0095] The transistor 200 includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. That is, the transistor 200 can be said to be an OS transistor.

[0096] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) may generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0097] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or impurities such as hydrogen, nitrogen, or a metal element.

[0098] As described above, the oxide semiconductor layer 230 is provided inside the opening 290. In addition, the transistor 200 has a structure in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located below and the other of the source electrode and the drain electrode (here, the conductive layer 240) is located above, and thus, a current flows vertically. That is, a channel is formed along the side surface of the opening 290.

[0099] 2D and 2E , the positional relationship of each layer in the opening 290 will be described. The insulating layer 235 is in contact with the outer surface of the oxide semiconductor layer 230. The insulating layer 250 is in contact with the outer surface of the conductive layer 265a. The oxide semiconductor layer 230 surrounds the entire outer periphery of the conductive layer 265a with the insulating layer 250 interposed therebetween. Thus, the channel formation region of the transistor 200 can be formed over the entire outer surface of the oxide semiconductor layer 230 in the opening 290 (the entire region in contact with the insulating layer 235).

[0100] 2D and 2E , the semiconductor device of this embodiment has a configuration in which, in a plan view, the insulating layer 280 annularly surrounds the periphery of the oxide semiconductor layer 230. In addition, the semiconductor device of this embodiment has a configuration in which, in a plan view, the insulating layer 235 is disposed between the insulating layer 280 and the oxide semiconductor layer 230.

[0101] As described above, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of the oxide semiconductor. In particular, it is preferable that hydrogen be reduced as much as possible in the channel formation region of the oxide semiconductor.

[0102] Therefore, a barrier insulator against hydrogen is preferably used for the insulating layer 280 provided outside the oxide semiconductor layer 230. When the insulating layer 280 has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film is preferably used as the insulating layer 280, and a silicon nitride film is more preferably used.

[0103] The suppression of diffusion of hydrogen into the oxide semiconductor layer 230 can reduce the hydrogen concentration in the oxide semiconductor, suppress a negative shift in the initial characteristics of the transistor 200, and enable the transistor 200 to have normally-off characteristics. In addition, negative drift degradation in a +GBT (Gate Bias-Temperature) stress test can also be suppressed.

[0104] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280, oxygen can be prevented from being extracted from the oxide semiconductor layer 230, and excessive oxygen vacancies can be prevented from being formed in the oxide semiconductor layer 230.

[0105] Furthermore, the use of silicon nitride for the insulating layer 280 can prevent excess oxygen from being supplied to the oxide semiconductor layer 230. Thus, excess oxygen can be prevented from being contained in the channel formation region of the oxide semiconductor layer 230, thereby improving the reliability of the transistor 200.

[0106] The insulating layer 235 provided in contact with the oxide semiconductor layer 230 is preferably an insulator having a function of capturing or fixing hydrogen. When the insulating layer 235 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 235, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. For example, a hafnium oxide film, a hafnium aluminate film, or an aluminum oxide film is preferably used for the insulating layer 235. In this case, the insulating layer 235 contains one or both of hafnium and aluminum, and oxygen. For example, a hafnium silicate film is preferably used for the insulating layer 235.

[0107] Note that a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film has a barrier property against oxygen, and therefore, by forming the insulating layer 235 in contact with the conductive layer 240 using these materials, oxidation of the conductive layer 240 can be suppressed, which is preferable.

[0108] The insulating layer 235 preferably has a region containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen). In this way, oxygen can be supplied from the insulating layer 235 to the oxide semiconductor layer 230, and oxygen vacancies in the oxide semiconductor layer 230 can be reduced. For example, the insulating layer 235 is preferably a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film.

[0109] As described above, by wrapping the oxide semiconductor layer 230 in a ring shape with a barrier insulating layer against hydrogen and providing an insulating layer having a function of capturing or fixing hydrogen or an insulating layer including a region containing excess oxygen near the oxide semiconductor layer 230, it is possible to reduce one or both of oxygen vacancies and impurities in the oxide semiconductor layer 230. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0110] When an oxide insulating film such as a silicon oxide film is used for the insulating layer 235, which is a surface on which the oxide semiconductor layer 230 is to be formed, the oxide semiconductor layer 230 is preferably formed by an ALD method. When the oxide semiconductor layer 230 has a stacked-layer structure, a layer of the oxide semiconductor layer 230 in contact with the insulating layer 235 is preferably formed by an ALD method. When the oxide semiconductor layer 230 is formed by an ALD method, ozone (O ３ With such a structure, oxygen can be injected into the insulating layer 235, which is a surface where the oxide semiconductor layer 230 is to be formed. Thus, excess oxygen in the insulating layer 235 can be increased.

[0111] The semiconductor device of this embodiment has a configuration in which insulating layers are provided above and below the oxide semiconductor layer 230. Examples of the insulating layer provided above or below the oxide semiconductor layer 230 include an insulating layer 210 and an insulating layer 250.

[0112] The insulating layer 210 provided below the oxide semiconductor layer 230 is preferably made of a barrier insulator against hydrogen. When the insulating layer 210 has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. For example, the insulating layer 210 is preferably made of silicon nitride.

[0113] An insulator having a function of capturing or fixing hydrogen is preferably used for the insulating layer 210. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210 through the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0114] 2B and 2C show an example in which the insulating layer 210 has a single-layer structure. Note that the insulating layer 210 can have a stacked structure of two or more layers. FIG. 3A shows an example in which the insulating layer 210 has a two-layer structure of an insulating layer 210a and an insulating layer 210b on the insulating layer 210a. In this case, for example, it is preferable to use a barrier insulator against hydrogen as the insulating layer 210a and an insulator having a function of capturing or fixing hydrogen as the insulating layer 210b. Specifically, it is preferable to use a silicon nitride film as the insulating layer 210a and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the insulating layer 210b.

[0115] The insulating layer 250 covers the top surface and side surfaces of the oxide semiconductor layer 230 over the insulating layer 280. The insulating layer 250 provided above the oxide semiconductor layer 230 is preferably a barrier insulator against hydrogen. When the insulating layer 250 has a barrier property against hydrogen, diffusion of hydrogen contained in the conductive layer 265 into the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0116] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulator that has a function of capturing or fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0117] The insulating layer 250 is preferably an insulating layer having a region containing excess oxygen, which allows oxygen to be supplied from the insulating layer 250 to the oxide semiconductor layer 230 and reduces oxygen vacancies in the oxide semiconductor layer 230. A silicon oxide film, a silicon oxynitride film, or the like is suitable for the insulating layer 250 because it has a structure that is stable against heat.

[0118] 2B and 2C show an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers.

[0119] 3A illustrates an example in which the insulating layer 250 has a two-layer structure including an insulating layer 250a and an insulating layer 250b over the insulating layer 250a. In this case, the insulating layer 250a is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulator capable of capturing or fixing hydrogen as the insulating layer 250a, and a barrier insulator against hydrogen as the insulating layer 250b. With such a structure, the oxide semiconductor layer 230 can be sandwiched between the insulating layers capable of capturing or fixing hydrogen, thereby further reducing the hydrogen concentration in the oxide semiconductor layer 230. Furthermore, the oxide semiconductor layer 230 can be sandwiched between barrier insulating layers against hydrogen with the insulating layer interposed therebetween, thereby suppressing diffusion of hydrogen into the oxide semiconductor layer 230. Therefore, a highly reliable transistor can be realized.

[0120] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the insulating layer 250a and a barrier insulator against hydrogen as the insulating layer 250b. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the insulating layer 250a and an insulator having a function of capturing or fixing hydrogen as the insulating layer 250b.

[0121] FIG. 3B shows an example in which the insulating layer 250 has a three-layer structure including an insulating layer 250c, an insulating layer 250a on the insulating layer 250c, and an insulating layer 250b on the insulating layer 250a.

[0122] In the structure shown in FIG. 3B , for example, it is preferable to use an insulating layer made of a material with a low dielectric constant as the insulating layer 250c, an insulator having a function of capturing or fixing hydrogen as the insulating layer 250a, and an insulator having barrier properties against hydrogen and oxygen as the insulating layer 250b. Silicon oxide or silicon oxynitride is preferably used as the material with a low dielectric constant. The insulating layer 250c is a layer in contact with the oxide semiconductor layer 230. Using an oxide for the insulating layer 250c can supply oxygen to the oxide semiconductor layer 230. Furthermore, providing the insulating layer 250b can suppress diffusion of oxygen contained in the insulating layer 250c into the conductive layer 265, thereby suppressing oxidation of the conductive layer 265. Furthermore, it is possible to suppress a decrease in the amount of oxygen supplied from the insulating layer 250c to the oxide semiconductor layer 230.

[0123] FIG. 4 shows an example in which the insulating layer 250 has a four-layer structure including an insulating layer 250d, an insulating layer 250c on the insulating layer 250d, an insulating layer 250a on the insulating layer 250c, and an insulating layer 250b on the insulating layer 250a.

[0124] It is preferable that the insulating layer 250d be made of an insulator having a barrier property against oxygen, the insulating layer 250c be made of an insulating layer containing a material with a low dielectric constant, the insulating layer 250a be made of an insulator having a function of capturing or fixing hydrogen, and the insulating layer 250b be made of an insulator having a barrier property against hydrogen and oxygen. The insulating layers 250a to 250c can have a structure similar to that of the layers used in the above-described three-layer structure. The insulating layer 250d is in contact with the oxide semiconductor layer 230. The insulating layer 250d has a barrier property against oxygen, which can prevent oxygen from being released from the oxide semiconductor layer 230. For example, an aluminum oxide film may be used as the insulating layer 250d. Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable for the insulating layer 250d in contact with the oxide semiconductor layer 230. Specifically, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0125] Each layer constituting the insulating layer 250 is preferably a thin film. For example, the insulating layer 250 has a thickness of 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value), which is one of the transistor characteristics. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0126] The thickness of each layer constituting the insulating layer 250 (corresponding to insulating layers 250a to 250d in the case of the configuration shown in FIG. 4) is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-described thickness in at least a portion thereof.

[0127] Typically, the thicknesses of the insulating layer 250d, the insulating layer 250c, the insulating layer 250a, and the insulating layer 250b are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0128] 4, the insulating layer 250b may not be provided. For example, an insulator having a barrier property against oxygen can be used as the insulating layer 250d, an insulating layer containing a material with a low dielectric constant can be used as the insulating layer 250c, and an insulator having a function of capturing or fixing hydrogen can be used as the insulating layer 250a. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side can be used.

[0129] As described above, by surrounding the oxide semiconductor layer 230 with a barrier insulating layer against hydrogen and providing an insulating layer having a function of capturing or fixing hydrogen or an insulating layer having a region containing excess oxygen near the oxide semiconductor layer 230, one or both of oxygen vacancies and impurities in the oxide semiconductor layer 230 can be further reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. Furthermore, a semiconductor device with good electrical characteristics can be provided. Furthermore, a highly reliable semiconductor device can be provided. Furthermore, a semiconductor device with little variation in the electrical characteristics of the transistor can be provided. Furthermore, a semiconductor device with large on-state current can be provided.

[0130] The conductive layer 220 includes a conductive layer 220a and a conductive layer 220b on the conductive layer 220a, and a recess is provided in the conductive layer 220b. In other words, the conductive layer 220 has a recess, the bottom surface of which corresponds to the bottom surface of the recess in the conductive layer 220b, and the side surface of which corresponds to the side surface of the recess in the conductive layer 220b. Specifically, the conductive layer 220b has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located below (closer to the insulating layer 210) than the bottom surface of the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220b, and then, when processing the insulating layer 235, the first recess is provided in the conductive layer 220b. 2B and other figures, the side surface of the first recess is aligned with the surface of the insulating layer 235 facing the oxide semiconductor layer 230, and the side surface of the second recess is aligned with the side surface of the insulating layer 280 or the like facing the opening 290. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0131] The opening 290 overlaps with the recess in the conductive layer 220b. Here, the bottom of the opening 290 includes the bottom surface of the recess in the conductive layer 220b, and the sidewall of the opening 290 includes the side surface of the recess in the conductive layer 220b, the side surface of the insulating layer 280, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b.

[0132] 2B and other figures, the insulating layer 235 is in contact with the bottom surface and side surfaces of the recess (specifically, the second recess) of the conductive layer 220, and is also in contact with the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 240a, and the side surfaces of the conductive layer 240b within the opening 290. The oxide semiconductor layer 230 is in contact with the bottom surface and side surfaces of the recess (specifically, the first recess) of the conductive layer 220, the insulating layer 235, and the top surface of the conductive layer 240b. The insulating layer 250 is located inside the oxide semiconductor layer 230 within the opening 290, and the conductive layer 265a is located inside the insulating layer 250 within the opening 290.

[0133] 2B and other figures, the first recess of the conductive layer 220b is preferably deeper than the second recess of the conductive layer 220b. This allows the oxide semiconductor layer 230 to be in contact with the side surface of the first recess of the conductive layer 220b in addition to the bottom surface of the first recess of the conductive layer 220b. This configuration can increase the contact area between the conductive layer 220b and the oxide semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220b and the oxide semiconductor layer 230. Therefore, a decrease in the on-state current of the transistor 200 due to the contact resistance between the conductive layer 220b and the oxide semiconductor layer 230 can be suppressed.

[0134] In the transistor of one embodiment of the present invention, at least one layer constituting the conductive layer 265 is provided in the opening 290. When the conductive layer 265 has a stacked structure, it becomes more difficult to arrange all of the layers constituting the conductive layer 265 in the opening 290 as the transistor 200 is miniaturized and the diameter of the opening 290 becomes smaller. In FIGS. 2B and 2C , an example is shown in which the conductive layer 265 has a two-layer structure, in which only the conductive layer 265a is provided in the opening 290, and the conductive layer 265b over the conductive layer 265a is provided so as to overlap with the opening 290. Note that depending on the diameter of the opening 290, the thickness of the conductive layer 265a, and the like, both the conductive layer 265a and the conductive layer 265b may be located in the opening 290.

[0135] By providing a recess in the conductive layer 220b at a position overlapping with the opening 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 265a in the opening 290 can be lower than the height of the top surface of the conductive layer 220b that is in contact with the insulating layer 280, relative to the top surface of the insulating layer 210, as compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0136] 5 , the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220b that contacts the insulating layer 280 is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. This increases the contact area between the side surface of the conductive layer 220b and the oxide semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220b and the oxide semiconductor layer 230. Therefore, a decrease in the on-state current of the transistor 200 due to the contact resistance between the conductive layer 220b and the oxide semiconductor layer 230 can be suppressed. Note that the shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 within the opening 290.

[0137] 5 , the shortest distance Tc is preferably equal to or greater than the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 265a, and more preferably longer than the shortest distance Tb. This makes it easier to apply a gate electric field to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200. Furthermore, since the gate electric field is also easier to apply to a region of the oxide semiconductor layer 230 in contact with the conductive layer 220b, the on-state current of the transistor 200 can be increased. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved. Note that the shortest distance Tb can be determined based on the bottom surface of the conductive layer 265a in the opening 290.

[0138] The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recesses of the conductive layer 220b and the top surface of the conductive layer 240b. The recesses in the conductive layer 220b can increase the area in which the oxide semiconductor layer 230 is in contact with the conductive layer 220b. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b can be reduced.

[0139] The conductive layer 220b is preferably formed using a conductive material containing oxygen, which can reduce contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b.

[0140] When the conductive layer 220 and the conductive layer 240 have a stacked structure, it is preferable to use a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, because this can reduce contact resistance with the oxide semiconductor layer 230. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 220b and the conductive layer 240b, for example.

[0141] Alternatively, when the conductive layer 220 and the conductive layer 240 have a stacked structure, a conductive material containing oxygen is used for a layer of the stacked structure that is closest to a channel formation region, and the contact resistance with the oxide semiconductor layer 230 is reduced, thereby shortening the current path between the source and the drain, and thereby increasing the on-state current of the transistor. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 220b and the conductive layer 240a, for example.

[0142] As the conductive material containing oxygen, it is preferable to use a metal oxide having conductivity (also called an oxide conductor).

[0143] 2B illustrates a structure in which the end portions of the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230 are aligned outside the opening 290. As described in a manufacturing method example below, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. This is preferable because the number of masks required for manufacturing the semiconductor device can be reduced. Note that the present invention is not limited to this. For example, in the X direction or the Y direction, any one of the end portions of the oxide semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b may be located inside or outside the other end portions.

[0144] The conductive layer 240 has an opening 290 in a region overlapping with the conductive layer 220. Furthermore, it is preferable that the conductive layer 240 is not located inside the opening 290 of the insulating layer 280 or the like. That is, it is preferable that the conductive layer 240 does not have a region in contact with the side surface of the insulating layer 280 within the opening 290. With this configuration, the opening 290 can be formed simultaneously in the conductive layer 240 and the insulating layer 280. Furthermore, if the side surfaces of the conductive layer 240 and the insulating layer 280 are aligned within the opening 290, the film thickness distribution of the insulating layer 235, the oxide semiconductor layer 230, and the like provided within the opening 290 can be made uniform. Furthermore, it is possible to prevent the insulating layer 235, the oxide semiconductor layer 230, and the like from being separated by a step or the like between the conductive layer 240 and the insulating layer 280.

[0145] 2B and 2C show a configuration in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 are flush (or can be said to be aligned or approximately aligned), but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280 in the opening 290 may differ from each other. In this case, for example, it is preferable that the taper angle of the side surface of the conductive layer 240 in the opening 290 is smaller than the taper angle of the side surface of the insulating layer 280 in the opening 290. With such a configuration, the coverage of the oxide semiconductor layer 230 on the side surface of the conductive layer 240 in the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when insulating layer 280 has a laminated structure, the inclination of the side surface of each layer within opening 290 may be different. Similarly, when conductive layer 240 has a laminated structure, the inclination of the side surface of each layer within opening 290 may be different.

[0146] The channel length of the transistor 200 can be considered to be the distance between the source region and the drain region. In other words, the channel length of the transistor 200 can be said to be determined by the height of the insulating layer 235. Furthermore, the channel length of the transistor 200 can be said to be determined by the depth of the recess (specifically, the second recess) in the conductive layer 220, the thickness of the insulating layer 280 on the conductive layer 220, and the thickness of the conductive layer 240. When the channel length of the transistor 200 is considered to be the distance between the source region and the drain region, the channel length of the transistor 200 can be considered to be the length L1 shown in FIG. 5 .

[0147] In a planar transistor, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. However, in one embodiment of the present invention, the channel length can be set by the depth of the recess (specifically, the second recess) in the conductive layer 220, the film thickness of the insulating layer 280, and the film thickness of the conductive layer 240. Therefore, the channel length of the transistor 200 can be made into an extremely fine structure (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more) that is equal to or less than the exposure limit of photolithography. This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0148] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.

[0149] 2A2 shows an example in which a plurality of transistors 200 are arranged in a matrix. Specifically, FIG. 2A2 shows an example in which 5×5 transistors are arranged in the X and Y directions. As shown in FIG. 2A2, the transistor 200 is provided at the intersection of a conductive layer 265 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 2A2, the diameter of the opening 290 can be made smaller than both the width of the short side of the conductive layer 240 and the width of the short side of the conductive layer 265. In this way, the transistor 200 can be said to have a structure that allows for high integration and miniaturization.

[0150] 2D and 2E , the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are arranged concentrically. Therefore, the side surface of the conductive layer 265a located in the center faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, the entire periphery of the oxide semiconductor layer 230 becomes a channel formation region in a plan view. In this case, for example, the channel width of the transistor 200 is determined by the periphery of the oxide semiconductor layer 230. That is, the channel width of the transistor 200 can be determined by the width of the opening 290 (or the diameter when the opening 290 is circular in a plan view). In FIGS. 2B , 2C , and 2E , the width D of the opening 290 is shown, and in FIG. 2E , the channel width W of the transistor 200 is shown. Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current.

[0151] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 240 on the opening 290 side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 290 in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening 290 at the highest position in the conductive layer 240, the width of the opening 290 at the lowest position, the width of the opening 290 at a midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D is determined using the width of the opening 290 in the conductive layer 240, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 on the opening 290 side may be used as the width D. Alternatively, the width of the opening 290 at the highest position in the insulating layer 280, the width of the opening 290 at the lowest position, the width of the opening 290 at a midpoint between these, or the average value of these three widths may be used as the width D.

[0152] When the opening 290 is formed by photolithography, the width D of the opening 290 is set by the exposure limit of photolithography. The width D of the opening 290 is set by the film thickness of each of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Here, as shown in FIG. 5 , the width (film thickness) of the insulating layer 235 is defined as a width T ＳＷ When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W is "(D-2×T ＳＷ ) × π”.

[0153] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0154] As described above, by forming the opening 290 so as to have a circular shape in a plan view, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are provided concentrically. As a result, the distance between the conductive layer 265a and the oxide semiconductor layer 230 becomes approximately uniform, and therefore, a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0155] Although the present embodiment illustrates an example in which the opening 290 is circular in plan view, the present invention is not limited thereto. In plan view, the opening 290 may be, for example, a circle, an approximately circle such as an ellipse, a polygon such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). As shown in FIG. 2A1 and other figures, the opening 290 is preferably circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. In this specification and other figures, the term "circular" is not limited to a perfect circle.

[0156] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0157] [Oxide Semiconductor Layer 230] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0158] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0159] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is low, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0160] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor of one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0161] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region. Examples of such another semiconductor material include semiconductors made of simple elements or compound semiconductors. Examples of semiconductors made of simple elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that the aforementioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0162] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0163] The semiconductor layer of the transistor may include a layer material that functions as a semiconductor. Note that the layer material will be described in detail in Embodiment 5.

[0164] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 235, insulating layer 280, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0165] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, materials can be selected depending on the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0166] Examples of high-dielectric-constant (high-k) materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0167] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0168] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of the semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of zirconium atoms to the number of element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close to 1:1. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0169] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0170] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0171] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, may also be used.

[0172] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0173] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0174] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0175] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, the manifestation of ferroelectricity is presumed to depend on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, as this will result in the manifestation of ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of cubic, tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0176] Furthermore, adding a Group 3 element (also referred to as a IIIa element) in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide and make it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0177] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride.

[0178] Specifically, examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride.

[0179] An insulating layer, such as a gate insulating layer, that is in contact with or near an oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating. For example, when an insulating layer having a region containing excess oxygen is in contact with or near an oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that are likely to have a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0180] Examples of materials for insulating layers capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adsorb hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferably used. Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0181] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0182] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0183] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0184] Since the insulating layer 210 functions as an interlayer film, a material with a low relative dielectric constant can be used. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0185] The concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0186] The insulating layer 280 can include the above-described insulating oxide, insulating oxynitride, or insulating layer having a region containing excess oxygen.

[0187] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method in which hydrogen-containing molecules are not used as a deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By forming at least a part of the layers constituting the insulating layer 280 by sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0188] The concentration of impurities such as water and hydrogen is preferably reduced in the insulating layer 280. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0189] Note that the thickness of the insulating layer 280 on the conductive layer 220 affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately in accordance with the design value of the channel length of the transistor 200 .

[0190] The insulating layer having the function of capturing and fixing hydrogen may be made of, for example, hafnium silicate, etc. The insulating layer preferably has an amorphous structure.

[0191] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. Suppressing the formation of crystal grain boundaries can improve the flatness of the insulating layer. This makes the film thickness distribution of the insulating layer uniform, reducing areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. Furthermore, it is possible to uniform the film thickness distribution of a film provided on the insulating layer.

[0192] Furthermore, by suppressing the formation of grain boundaries in the insulating layer, leakage current due to defect levels in the grain boundaries can be reduced, allowing the insulating layer to function as an insulating film with low leakage current.

[0193] Furthermore, since hafnium oxide is a high dielectric constant (high-k) material, hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. It is also possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0194] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0195] Furthermore, the insulating layer 250 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0196] The insulating layer 250 preferably has a barrier insulating layer against oxygen, which can suppress oxidation of the conductive layer 240, the conductive layer 265, and the like. When the insulating layer 250 has a stacked structure, a layer in contact with the conductive layer 240 is preferably a barrier insulating layer against oxygen. In particular, among the layers constituting the insulating layer 250, a layer in contact with the conductive layer 240 and a layer in contact with the conductive layer 265 are preferably barrier insulating layers against oxygen.

[0197] The use of a barrier insulating layer against hydrogen and oxygen for a layer of the insulating layer 250 that is in contact with the conductive layer 265 can suppress oxidation of the conductive layer 265. Furthermore, oxygen contained in the oxide semiconductor layer 230 can be prevented from diffusing into the conductive layer 265, which can suppress formation of oxygen vacancies in the oxide semiconductor layer 230.

[0198] Examples of the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0199] The layer of the insulating layer 250 that is in contact with the conductive layer 240 is preferably impermeable to oxygen. The layer has a barrier property against oxygen, which can prevent the side surfaces of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0200] The silicon oxide film included in the insulating layer 250 is preferably formed by a PEALD method. The thickness of the silicon oxide film included in the insulating layer 250 is preferably 0.7 nm to 3 nm. The ALD method allows atoms to be deposited layer by layer, and thus has advantages such as enabling ultrathin film formation, film formation on a structure with a high aspect ratio or a surface with large steps, film formation with few defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Therefore, in the transistor of one embodiment of the present invention, the ALD method can improve the coverage of the insulating layer 250 on the sidewalls and bottom surface of the opening 290, and the insulating layer 250 with a uniform thickness can be formed. Furthermore, the PEALD method enables film formation at a lower temperature by using plasma. Furthermore, the use of plasma can increase the film formation rate and productivity.

[0201] The insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 using two or more types of films, the insulating layer 250 can be endowed with multiple functions. Examples of the functions of the insulating layer 250 include the function of extracting hydrogen from the oxide semiconductor layer 230 and the function of suppressing hydrogen diffusion into the oxide semiconductor layer 230. It is preferable to use the ALD process two or more times in forming the insulating layer 250. For example, the insulating layer 250 preferably has a stacked structure of multiple insulating films, and two or more of the multiple insulating films are preferably formed using the ALD process. Forming at least two or more insulating films using the ALD process can improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, successively forming two or more types of films, for example, two or more insulating films, using the ALD process can increase productivity.

[0202] The insulating layer 235 preferably includes a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer 230 and improve the reliability of the transistor 200. For example, the insulating layer 235 is preferably made of aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide.

[0203] The silicon nitride film of the insulating layer 235 is preferably formed using the PEALD method, which can improve the coverage of the insulating layer 235 on the sidewall of the opening 290 and form an insulating layer 235 with a uniform thickness.

[0204] Furthermore, the insulating layer 235 may be made of the above-mentioned material that can have ferroelectricity.

[0205] For example, the insulating layer 235 can have a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, or a three-layer structure of a silicon nitride film, a silicon oxide film, and a silicon nitride film. In the case of a two-layer structure of a silicon oxide film and a silicon nitride film, for example, it is preferable to provide a silicon oxide film on the oxide semiconductor layer 230 side and a silicon nitride film on the insulating layer 280 side. This makes it possible to efficiently supply oxygen to the oxide semiconductor layer 230 and to suppress the diffusion of impurities such as hydrogen into the oxide semiconductor layer 230. Alternatively, a silicon nitride film may be provided on the oxide semiconductor layer 230 side and a silicon oxide film may be provided on the insulating layer 280 side.

[0206] [Conductive Layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 265, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0207] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0208] Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.

[0209] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0210] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0211] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0212] By using a conductive material containing oxygen for the conductive layer 220 or the conductive layer 240, the conductive layer 220 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0213] 3A illustrates an example in which the conductive layer 220 has a three-layer structure including a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2. In other words, FIG. 3A illustrates an example in which the conductive layer 220a has a two-layer structure including a conductive layer 220a1 and a conductive layer 220a2 on the conductive layer 220a1. In this case, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 220a1, a highly conductive material as the conductive layer 220a2, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 220b. Specifically, it is preferable to use, for example, titanium nitride as the conductive layer 220a1, tungsten as the conductive layer 220a2, and an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) as the conductive layer 220b. In this case, titanium nitride is in contact with the insulating layer 210, and the oxide conductor is in contact with the oxide semiconductor layer 230. The oxide conductor is used in the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared to tungsten, the oxide conductor has lower contact resistance with the oxide semiconductor layer 230, so the current path between the source and drain can be shortened, and the on-state current of the transistor can be increased. With this structure, the conductive layer 220 can maintain conductivity even when in contact with the oxide semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 can be suppressed by the insulating layer 210. Furthermore, by using a metal material (here, tungsten) having higher conductivity than the oxide conductor and titanium nitride as the conductive layer 220a2, the conductivity of the conductive layer 220 can be increased.

[0214] 3A shows an example in which the conductive layer 240 has a two-layer structure including a conductive layer 240a and a conductive layer 240b on the conductive layer 240a. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240b and a material having higher conductivity than the conductive layer 240b for the conductive layer 240a. Specifically, for example, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) for the conductive layer 240b and tungsten for the conductive layer 240a. Furthermore, ruthenium, titanium nitride, tantalum nitride, or the like may be used for the conductive layer 240a.

[0215] Of the conductive layer 240, the layer that is mainly in contact with the oxide semiconductor layer 230 is the conductive layer 240b. Using an oxide conductor for the conductive layer 240b is preferable because contact resistance with the oxide semiconductor layer 230 can be reduced. Furthermore, using a material having higher conductivity than an oxide conductor for the layer that constitutes the conductive layer 240 is preferable because the conductivity of the conductive layer 240 can be increased.

[0216] Note that a conductive material containing oxygen can be used for the conductive layer 240a, and a material having higher conductivity than that of the conductive layer 240a can be used for the conductive layer 240b. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor can be increased.

[0217] The conductive layer 265 is preferably made of a highly conductive material such as tungsten. Furthermore, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 265. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 265.

[0218] The conductive layer 265 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the above-described metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0219] 3A shows an example in which the conductive layer 265 has a two-layer structure including a conductive layer 265a and a conductive layer 265b over the conductive layer 265a. In this case, for example, it is preferable to use titanium nitride for the conductive layer 265a and tungsten for the conductive layer 265b. Alternatively, it is preferable to use tantalum nitride for the conductive layer 265a and copper for the conductive layer 265b. With such a structure, the conductivity of the conductive layer 265 can be increased.

[0220] The conductive layer 265 may also have a stacked structure of three or more layers, such as a three-layer structure of tantalum nitride, titanium nitride on the tantalum nitride, and tungsten on the titanium nitride.

[0221] The conductive layer 265 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 265. For example, a two-layer structure of titanium nitride and tungsten may be used.

[0222] [Substrate] Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0223] 6 to 16 , examples of the configuration of a transistor that is partially different from the transistor 200 will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be denoted by the same reference numerals and their descriptions may be omitted.

[0224] [Transistor 200A] FIG. 6 is a cross-sectional view of a semiconductor device having a transistor 200A.

[0225] FIG. 6 shows an example in which the sidewall of the opening 290 has a tapered shape. Tapering the sidewall of the opening 290 improves coverage of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the like, and reduces defects such as voids. When the sidewall of the opening 290 has a tapered shape, for example, the taper angle θ280 of the side surface of the insulating layer 280 in the opening 290 is preferably 45 degrees or more and less than 90 degrees. Specifically, a taper angle θ280 of 80 degrees or more and less than 90 degrees is preferable, as described above, because this allows for miniaturization or high integration of the semiconductor device. Furthermore, a taper angle θ280 of 45 degrees or more, or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, because it improves coverage of the film formed in the opening 290.

[0226] Alternatively, for example, the sidewall of the opening 290 may have an inverse tapered shape. In other words, the taper angle θ280 of the side surface of the insulating layer 280 in the opening 290 may be greater than 90 degrees.

[0227] [Transistor 200B] FIG. 7A is a cross-sectional view of a semiconductor device having a transistor 200B.

[0228] Transistor 200B differs from transistor 200 primarily in that conductive layer 220b has only one recess.

[0229] A recess may be formed in the conductive layer 220b in one or both of the steps of forming the opening 290 and forming the insulating layer 235. The transistor 200 shows an example in which a recess is formed in the conductive layer 220b in both steps, whereas the transistor 200B shows an example in which a recess is not formed in the conductive layer 220b in the step of forming the opening 290, but is formed in the step of forming the insulating layer 235.

[0230] In the transistor 200B, the insulating layer 235 is in contact with the side surface of the insulating layer 280, the side surface of the conductive layer 240a, the side surface of the conductive layer 240b, and the top surface of the conductive layer 220b in the opening 290. The oxide semiconductor layer 230 is in contact with the bottom surface and side surface of the recess of the conductive layer 220b.

[0231] When a recess is formed in the conductive layer 220b in at least one of the steps of forming the opening 290 and forming the insulating layer 235, the height of the bottom surface of the conductive layer 265a in the opening 290 can be reduced, making it easier for a gate electric field to be applied to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200B.

[0232] When a recess is formed in the conductive layer 220b in the process of forming the insulating layer 235, the oxide semiconductor layer 230 can be in contact with the bottom and side surfaces of the recess in the conductive layer 220b, the contact area between the oxide semiconductor layer 230 and the conductive layer 220b is increased, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced, which is preferable.

[0233] [Transistor 200C] FIG. 7B is a cross-sectional view of a semiconductor device having a transistor 200C.

[0234] Transistor 200C differs from transistor 200 primarily in that insulating layer 235 does not cover the side surfaces of conductive layer 240b.

[0235] 7B is in contact with the bottom and side surfaces of the recess of the conductive layer 220, and is in contact with the side surface of the insulating layer 280 within the opening 290. The insulating layer 235 is in contact with part of the side surface of the conductive layer 240a, but is not in contact with the side surface of the conductive layer 240b. The insulating layer 235 may be in contact with one or more of the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 240a, and the side surfaces of the conductive layer 240b within the opening 290, or may cover part or all of each side surface.

[0236] When at least a portion of the side surface of the conductive layer 240b is not covered with the insulating layer 235, that portion is in contact with the oxide semiconductor layer 230. This makes it possible to increase the contact area between the oxide semiconductor layer 230 and the conductive layer 240, and to reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240, which is preferable. Similarly, when the insulating layer 235 does not cover the side surface of the conductive layer 240b and also does not cover at least a portion of the side surface of the conductive layer 240a, that portion is in contact with the oxide semiconductor layer 230. This makes it possible to increase the contact area between the oxide semiconductor layer 230 and the conductive layer 240, and to reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240, which is preferable.

[0237] [Transistor 200D] FIG. 7C is a cross-sectional view of a semiconductor device including a transistor 200D.

[0238] The transistor 200D differs from the transistor 200 mainly in that the side surfaces of the conductive layer 220 are aligned with the side surfaces of the conductive layer 240 in the opening 290 and with the side surfaces of the insulating layer 280.

[0239] In a cross-sectional view, the width of the conductive layer 220 is equal to the width of the opening 290. This configuration is preferable because it can reduce the parasitic capacitance generated between the conductive layer 220 and the conductive layer 240.

[0240] [Transistors 200E and 200F] Fig. 8A is a cross-sectional view of a semiconductor device including a transistor 200E. Fig. 8B is a cross-sectional view of a semiconductor device including a transistor 200F.

[0241] The transistor 200E differs from the transistor 200 mainly in that the transistor 200E does not include the conductive layer 265a and the conductive layer 265b but includes the conductive layer 265 having a single-layer structure.

[0242] Like the conductive layer 265 of the transistor 200E, a conductive layer functioning as a gate electrode may have a single-layer structure. The conductive layer 265 is preferably provided so as to fill the opening 290.

[0243] Transistor 200F differs from transistor 200 primarily in that both conductive layer 265a and conductive layer 265b are located within opening 290.

[0244] In the transistor 200F, the conductive layer 265b is located in the opening 290. As described above, depending on the diameter of the opening 290, the thickness of the conductive layer 265a, and the like, not only the conductive layer 265a but also the conductive layer 265b may be provided in the opening 290.

[0245] [Transistor 200G] FIGS. 9A and 9B are cross-sectional views of a semiconductor device having a transistor 200G.

[0246] The transistor 200G differs from the transistor 200 mainly in that it includes a conductive layer 255 and an insulating layer 281 .

[0247] The conductive layer 255 is located over the insulating layer 280, and the insulating layer 281 is located over the conductive layer 255 and the insulating layer 280. The conductive layer 240a is located over the insulating layer 281. The insulating layer 281 functions as an interlayer film.

[0248] As shown in FIGS. 9A and 9B, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280, the conductive layer 255, the insulating layer 281, the conductive layer 240a, and the conductive layer 240b.

[0249] In transistor 200G, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 265 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 235 functions as a second gate insulating layer.

[0250] The oxide semiconductor layer 230 has a region that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween and with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200G.

[0251] Since the transistor 200G includes a conductive layer that functions as a back gate electrode, the threshold voltage of the transistor 200G can be controlled by the potential applied to the conductive layer. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0252] In the transistor 200G, either the conductive layer 255 or the conductive layer 265 may be used as a gate electrode or a back gate electrode. In particular, the transistor 200G may have a structure in which the conductive layer 265 is used as a gate electrode and the conductive layer 255 is used as a back gate electrode. When the conductive layer 265, which has a larger region facing the oxide semiconductor layer 230 than the conductive layer 255, is used as the gate electrode, a gate electric field can be applied to the oxide semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor.

[0253] When the conductive layer 265 functions as a gate electrode and the conductive layer 255 functions as a back gate electrode, the insulating layer 250 functions as a gate insulating layer and the insulating layer 235 functions as a back gate insulating layer.

[0254] The conductive layer 255 can be formed using a conductive material that can be used for the conductive layer 265. The insulating layer 281 can be formed using an insulating material that can be used for the insulating layer 280.

[0255] [Transistor 201] Figures 10A and 10B are schematic perspective views of a semiconductor device having a transistor 201. Figure 10B is a perspective view with a portion cut away from Figure 10A. In Figures 10A and 10B, only the outlines of some components (interlayer insulating layers, etc.) are indicated by dashed lines.

[0256] 11A is a plan view of a semiconductor device including a transistor 201. FIG. 11B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 11A. FIG. 11C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 11A. FIGS. 11D and 11E are cross-sectional views taken along dashed dotted line A5-A6 in FIG. 11B. FIG. 11E corresponds to an example of an enlarged view of FIG. 11D. Note that FIGS. 11D and 11E have the same configuration as FIGS. 2D and 2E except that they do not have the conductive layer 265a but have the conductive layer 260, and therefore detailed description thereof will be omitted.

[0257] 10A to 11E includes an insulating layer 210 over a substrate (not shown), a transistor 201 over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 283, an insulating layer 285 over the insulating layer 283, and a conductive layer 265 over the conductive layer 260, the insulating layer 283, and the insulating layer 285. The insulating layer 210, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0258] The transistor 201 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 240a over the insulating layer 280, a conductive layer 240b over the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. Note that the conductive layer 265 may be considered a component of the transistor 201. The insulating layer 283 is provided over the insulating layer 250.

[0259] The conductive layer 260 functions as a gate electrode of the transistor 201, and the conductive layer 265 functions as a gate wiring. The conductive layer 260 can be formed using any of the materials that can be used for the conductive layer 265.

[0260] In the transistor 201, the stacked structure from the conductive layer 220a to the insulating layer 250 is similar to that of the transistor 200, and therefore detailed description thereof will be omitted.

[0261] 11B and 11C , an opening 270 that reaches the insulating layer 250 is provided in the insulating layer 283 at a position that overlaps the opening 290. The conductive layer 260 is disposed so that at least a portion of the conductive layer 260 is located within the opening 270. The conductive layer 260 contacts the insulating layer 250 within the opening 270.

[0262] The conductive layer 260 is provided so as to fill at least a part of the opening 290 and the opening 270. The conductive layer 260 has a portion that faces the oxide semiconductor layer 230 in the opening 290 with the insulating layer 250 interposed therebetween, and a portion that is located in the opening 270.

[0263] In the transistor 201, at least one layer constituting the conductive layer 260 is provided in the opening 290 and the opening 270. When the conductive layer 260 has a stacked structure, as the transistor becomes smaller and the diameters of the openings 290 and 270 become smaller, it becomes more difficult to arrange all of the layers constituting the conductive layer 260 in the openings 290 and 270. FIGS. 11B and 11C show an example in which the conductive layer 260 has a two-layer structure, in which only the first conductive layer of the conductive layer 260 is provided in the opening 290, and the first and second conductive layers of the conductive layer 260 are provided in the opening 270. Note that depending on the diameter of the opening 290, the thickness of the conductive layer 260, and the like, both the first and second conductive layers of the conductive layer 260 may be located in the opening 290. Furthermore, depending on the diameter of the opening 270, the thickness of the conductive layer 260, and the like, only the first conductive layer of the conductive layer 260 may be located in the opening 270.

[0264] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layer 283 and the insulating layer 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween.

[0265] 11B and 11C show an example in which the width of the opening 270 is narrower than the width D of the opening 290. The narrower the width of the opening 270, the greater the physical distance between the conductive layer 240 and the conductive layer 260 can be, and the smaller the parasitic capacitance that occurs between the conductive layer 240 and the conductive layer 260 can be, which is preferable. For example, the width of the opening 270 is preferably the same as or smaller than the width of the opening 290.

[0266] It is preferable that the height of the top surface of the conductive layer 260 and the height of the top surface of the insulating layer 285 are the same or approximately the same. The conductive layer 265 is provided on the insulating layer 285, the insulating layer 283, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other. The insulating layer 283 and the insulating layer 285 are located between the conductive layer 265 and the conductive layer 240. This allows the physical distance between the conductive layer 265 and the conductive layer 240 to be increased, and the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240 to be reduced.

[0267] That is, the transistor 201 has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0268] In this embodiment, an example in which the opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 270 are the same as the shapes that can be applied to the opening 290 described above.

[0269] The width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 283 in a cross-sectional view.

[0270] A barrier insulating layer against hydrogen is preferably used for the insulating layer 283. This can suppress diffusion of hydrogen from above the insulating layer 283 to the oxide semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 283.

[0271] It is particularly preferable to use silicon nitride formed by a sputtering method as the insulating layer 283. The sputtering method does not require the use of molecules containing hydrogen in the deposition gas, and therefore can reduce the hydrogen concentration in the insulating layer 283. Furthermore, by forming the insulating layer 283 by a sputtering method, silicon nitride with high density can be formed.

[0272] Alternatively, an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 283. With such a structure, diffusion of hydrogen from above the insulating layer 283 to the oxide semiconductor layer 230 can be suppressed, and further, hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. For the insulating layer 283, aluminum oxide, hafnium oxide, hafnium silicate, or the like can be used.

[0273] Alternatively, the insulating layer 283 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 283 may be a stacked film of aluminum oxide and silicon nitride over the aluminum oxide.

[0274] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0275] [Transistor 201A] FIG. 12A is a cross-sectional view of a semiconductor device having a transistor 201A.

[0276] 12A shows an example in which the sidewalls of the opening 290 are tapered. For details of the case in which the sidewalls of the opening 290 are tapered, the description of the transistor 200A shown in FIG. 6 can be referred to.

[0277] [Transistor 201B] FIG. 12B is a cross-sectional view of a semiconductor device having a transistor 201B.

[0278] 12B , the width of opening 270 can be made larger than the width of opening 290. This allows the area of ​​conductive layer 260 to be increased in a plan view, and the contact area between conductive layer 260 and conductive layer 265 to be increased.

[0279] The transistor 201 can be modified in shape and details, similarly to the transistor 200. Specifically, the transistor 201 can have the same structure as the transistors 200A to 200G.

[0280] [Transistor 202] Fig. 13A is a plan view of a semiconductor device having a transistor 202. Fig. 13B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 13A. Fig. 13C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 13A. Figs. 13D and 13E are cross-sectional views taken along dashed dotted line A5-A6 in Fig. 13B. Fig. 13E corresponds to an example of an enlarged view of Fig. 13D. Note that Figs. 13D and 13E have the same configuration as Figs. 2D and 2E, and therefore detailed description thereof will be omitted.

[0281] 13A to 13E includes an insulating layer 210 over a substrate (not shown), a transistor 202 over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 283, and an insulating layer 285 over the insulating layer 283. The insulating layer 210, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0282] The transistor 202 includes a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, a conductive layer 240a on the insulating layer 280, a conductive layer 240b on the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, a conductive layer 265a on the insulating layer 250 and the insulating layer 285, and a conductive layer 265b on the conductive layer 265a.

[0283] In the transistor 202, the stacked structure from the conductive layer 220a to the insulating layer 250 is similar to that of the transistor 200, and therefore detailed description thereof will be omitted.

[0284] 13B and 13C , an opening 270 that reaches the insulating layer 250 is provided in the insulating layer 283 at a position overlapping the opening 290. The conductive layer 265a is arranged so that at least a portion thereof is located within the opening 270. Furthermore, the conductive layer 265b may also be arranged so that at least a portion thereof is located within the opening 270. The conductive layer 265a contacts the insulating layer 250 within the opening 270.

[0285] The conductive layer 265 a is provided so as to fill at least a part of the opening 290 and the opening 270 .

[0286] In the transistor 202, at least one layer constituting the conductive layer 265 is provided in the opening 290 and the opening 270. When the conductive layer 265 has a stacked structure, it becomes more difficult to arrange all of the layers constituting the conductive layer 265 in the opening 290 and the opening 270 as the diameters of the opening 290 and the opening 270 become smaller with the miniaturization of the transistor. FIGS. 13B and 13C show an example in which the conductive layer 265 has a two-layer structure, in which only the conductive layer 265a is provided in the opening 290, and the conductive layer 265a and the conductive layer 265b are provided in the opening 270. Note that depending on the diameter of the opening 290 and the thickness of the conductive layer 265a, both the conductive layer 265a and the conductive layer 265b may be located in the opening 290. Furthermore, depending on the diameter of the opening 270, the thickness of the conductive layer 265a, and the thickness of the conductive layer 265b, only the conductive layer 265a may be located in the opening 270.

[0287] The portions of the conductive layers 265a and 265b that do not overlap with the opening 290 are mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layer 283 and the insulating layer 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240 and reduce the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have overlapping portions without the insulating layer 285 being therebetween.

[0288] 13B and 13C show an example in which the width of the opening 270 is narrower than the width D of the opening 290. The narrower the width of the opening 270, the narrower the region where the conductive layer 240 and the conductive layer 265 overlap without the insulating layer 285 therebetween can be made, and the parasitic capacitance generated between the conductive layer 240 and the conductive layer 265 can be reduced, which is preferable. For example, the width of the opening 270 is preferably the same as or smaller than the width of the opening 290.

[0289] The width of the opening 270 may be larger than the width of the opening 290. For example, the width of the opening 270 is preferably smaller than the width of the short side of the conductive layer 265 (the maximum value of the width of the conductive layers 265a and 265b in FIG. 13C ). This allows the area of ​​the overlapping portion between the conductive layer 240 and the conductive layer 265 without the insulating layer 285 therebetween to be sufficiently smaller than the area of ​​the overlapping portion between the conductive layer 240 and the conductive layer 265 with the insulating layer 285 therebetween, thereby reducing the parasitic capacitance generated between the conductive layer 240 and the conductive layer 265.

[0290] That is, the transistor 202 has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0291] [Transistor 202A] FIG. 14 is a cross-sectional view of a semiconductor device having a transistor 202A.

[0292] 14 shows an example in which the sidewalls of the opening 290 have a tapered shape. For details of the case in which the sidewalls of the opening 290 have a tapered shape, the description of the transistor 200A shown in FIG. 6 can be referred to.

[0293] The transistor 202 may be modified in shape and details, similar to the transistor 200. Specifically, the transistor 202 may have the same structure as the transistors 200A to 200G.

[0294] [Transistor 203] FIG. 15A is a plan view of a semiconductor device including a transistor 203. FIG. 15B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 15A. FIG. 15C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 15A. FIG. 15D and FIG. 15E are cross-sectional views taken along dashed dotted line A5-A6 in FIG. 15B. FIG. 15E corresponds to an example of an enlarged view of FIG. 15D. Note that FIGS. 15D and 15E have the same configuration as FIGS. 2D and 2E except that they do not have conductive layer 265a but have conductive layer 260, and therefore detailed description thereof will be omitted.

[0295] 15A to 15E includes an insulating layer 210 over a substrate (not shown), a transistor 203 over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 283, an insulating layer 285 over the insulating layer 283, and a conductive layer 265 over the insulating layer 285. The insulating layer 210, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0296] The transistor 203 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 240a over the insulating layer 280, a conductive layer 240b over the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. Note that the conductive layer 265 may be considered as a component of the transistor 203. The insulating layer 283 is provided over the insulating layer 250.

[0297] The conductive layer 260 functions as a gate electrode of the transistor 203, and the conductive layer 265 functions as a gate wiring. The conductive layer 260 can be formed using any of the materials that can be used for the conductive layer 265.

[0298] In the transistor 203, the stacked structure from the conductive layer 220a to the oxide semiconductor layer 230 is similar to that of the transistor 200, and therefore detailed description thereof will be omitted.

[0299] 15B and 15C , an opening 270 that reaches the oxide semiconductor layer 230 is provided in the insulating layer 283 at a position overlapping with the opening 290. At least some of the components of the transistor 203 are disposed in the opening 270. Specifically, the insulating layer 250 and the conductive layer 260 are disposed such that at least a portion of each is located in the opening 270. The insulating layer 250 is in contact with the oxide semiconductor layer 230 and the insulating layer 283 in the opening 270.

[0300] The portion of insulating layer 250 that is disposed within opening 270 is provided to reflect the shape of opening 270. Specifically, insulating layer 250 is provided so as to cover the sidewall of opening 270 (the side surface of insulating layer 283). Then, conductive layer 260 is provided so as to fill at least a portion of the recess in insulating layer 250 that reflects the shape of opening 270.

[0301] In the transistor 203, the conductive layer 260 does not overlap with the top surface of the conductive layer 240, so that the parasitic capacitance generated between the conductive layer 240 and the conductive layer 260 can be reduced. As shown in FIGS. 15B and 15C , the maximum width of the conductive layer 260 is smaller than the width D of the opening 290 in a cross-sectional view. When the maximum width of the conductive layer 260 is smaller than the width D of the opening 290, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be reduced, which is preferable. Note that, for example, as shown in FIG. 15B or 15C , the magnitude relationship between the two widths in the semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.

[0302] 15B and 15C show an example in which the width of opening 270 is the same as the width of opening 290 (the same as width D). It is more preferable that the width of opening 270 is the same as or smaller than the width of opening 290. This is preferable because conductive layer 260 does not overlap the upper surface of conductive layer 240 and the parasitic capacitance generated between conductive layer 260 and conductive layer 240 can be reduced.

[0303] Note that, although the present embodiment mainly shows an example in which the conductive layer 260 does not overlap with the upper surface of the conductive layer 240, the conductive layer 260 may have a portion that overlaps with the upper surface of the conductive layer 240. The smaller the overlapping portion, the smaller the parasitic capacitance that occurs between the conductive layer 260 and the conductive layer 240, which is preferable. For example, the width of the opening 270 is preferably smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265 in FIG. 15C ). Furthermore, for example, the maximum width of the conductive layer 265 is preferably the same as or smaller than the maximum width of the conductive layer 260.

[0304] That is, the transistor 203 has a structure in which the parasitic capacitance generated between the gate electrode and the other of the source electrode and the drain electrode and the parasitic capacitance generated between the gate wiring and the other of the source electrode and the drain electrode are reduced, thereby improving the frequency characteristics of a circuit using the transistor.

[0305] [Transistor 203A] FIG. 16 is a cross-sectional view of a semiconductor device having a transistor 203A.

[0306] 16 shows an example in which the sidewalls of the opening 290 are tapered. For details of the case in which the sidewalls of the opening 290 are tapered, the description of the transistor 200A shown in FIG. 6 can be referred to.

[0307] The transistor 203 can be modified in shape and details, similarly to the transistor 200. Specifically, the transistor 203 can have the same structure as the transistors 200A to 200G.

[0308] [Region Having a Halogen Element and Region Having a First Element] In the semiconductor device of one embodiment of the present invention, at least one of the side surface of the insulating layer 280 on the opening 290 side and its vicinity, the insulating layer 235, and the oxide semiconductor layer 230 may have a region having a halogen element.

[0309] The halogen element is preferably one or more selected from chlorine, fluorine, bromine, and iodine, and more preferably chlorine or fluorine. From the viewpoint of substituting oxygen, it is preferable to use fluorine, which has a higher electronegativity than oxygen.

[0310] When the insulating layer 280 or the insulating layer 235 contains a halogen element, the halogen element can be supplied to the oxide semiconductor layer 230. The halogen element (X) can form an oxygen vacancy (V Ｏ ) with a defect (V Ｏ For example, when chlorine (Cl) is used as the halogen element, Cl becomes V in the oxide semiconductor layer 230 (particularly, at the interface between the insulating layer 235 and the oxide semiconductor layer 230 and in the vicinity thereof). Ｏ It exists stably in the state of Cl. At this time, Cl is Ｏ Not only does it penetrate into the Ｏ It can be in the Cl state.

[0311] On the other hand, the oxygen substituted by Cl (also called excess oxygen) has the function of trapping electrons. Ｏ Carrier trapping by oxygen occurs preferentially over carrier generation by Cl. Therefore, negative charges (also referred to as negative fixed charges) are formed at the interface between the insulating layer 235 and the oxide semiconductor layer 230 and in the vicinity thereof. The presence of negative charges in the channel formation region can positively shift the threshold voltage of the transistor. Therefore, even when the transistor has a miniaturized structure or an extremely short channel length, the transistor can have normally-off characteristics.

[0312] In the semiconductor device of one embodiment of the present invention, the source region and the drain region of the oxide semiconductor layer 230 preferably contain an impurity element. The impurity element is preferably the first element. Alternatively, the impurity element is preferably both the first element and hydrogen.

[0313] Note that at least one of the conductive layer 240a, the conductive layer 240b, the conductive layer 220a, and the conductive layer 220b may also contain an impurity element.

[0314] As the first element, it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0315] The first element is not limited to the above elements, and may be one or more of first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and elements included in rare earth elements.

[0316] By supplying the first element to the source region and the drain region, the first element deprives these regions of oxygen, causing oxygen vacancies in these regions. The oxygen vacancies then bond with hydrogen in the film, generating carriers, thereby reducing the resistance of the source region and the drain region. This reduces the sheet resistance of the oxide semiconductor layer 230, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240. This increases the on-state current of the transistor. Increasing the on-state current reduces the operating voltage of the transistor. This reduces the power consumption of the semiconductor device.

[0317] When an element that easily bonds with oxygen is used as the first element, the first element exists in a state bonded to oxygen in the semiconductor layer. Furthermore, when an element that bonds with oxygen to stabilize the semiconductor layer is used as the first element, the first element in the semiconductor layer exists stably in an oxidized state, and is therefore less likely to be desorbed by heat or the like applied during the manufacturing process of the semiconductor device, thereby achieving a stable low-resistance region with low electrical resistance. For this reason, it is preferable to use an element whose oxide can exist as a solid at 25°C and 1 atmosphere as the first element. Specifically, preferred first elements include typical nonmetallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals), and particularly preferred first elements include boron, phosphorus, magnesium, aluminum, and silicon.

[0318] For these reasons, it is preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements, and it is particularly preferable to use boron or phosphorus as one of the first elements.

[0319] Furthermore, hydrogen is suitable as an impurity element because it has the function of bonding with oxygen vacancies in addition to the function of causing the oxygen vacancies.

[0320] By using both the first element and hydrogen as the impurity elements, the electrical resistance of the source region and the drain region in the oxide semiconductor layer 230 can be easily reduced and the low electrical resistance can be stably maintained.

[0321] Furthermore, when both the first element and hydrogen are supplied, ions generated from the source gas can be added without mass separation, which is preferable because it is possible to increase productivity. ２ H ６ By using the gas, boron and hydrogen can be supplied as impurity elements. ３ By using the gas, phosphorus and hydrogen can be supplied as impurity elements. However, the method of supplying the impurity elements is not limited to this. For example, a specific element may be added by ionizing the source gas and mass-separating the ions. For example, B ２ H ６A gas may be used, and boron may be added after mass separation.

[0322] Note that the impurity element might be supplied also to a channel formation region in the oxide semiconductor layer 230. Alternatively, due to the influence of heat during a manufacturing process, part of the impurity element contained in the source region or the drain region might diffuse into the channel formation region.

[0323] In manufacturing the semiconductor device of one embodiment of the present invention, the source region and the drain region of the oxide semiconductor layer 230 are preferably doped with an impurity element more easily than the channel formation region. Therefore, the impurity element is preferably doped from a direction perpendicular or substantially perpendicular to the top surface of the substrate. In this case, the amount of the impurity element doped is smaller in a surface of the oxide semiconductor layer 230 that is inclined with respect to the top surface of the substrate than in a surface that is parallel or substantially parallel to the top surface of the substrate. That is, the amount of the impurity element doped is larger in the source region and the drain region of the oxide semiconductor layer 230 than in the channel formation region. Therefore, the resistance of the source region and the drain region can be preferentially reduced.

[0324] 17A to 20F, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts similar to those described above may be omitted.

[0325] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0326] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0327] CVD methods can be further classified into plasma-enhanced CVD (PECVD), which utilizes plasma, thermal CVD (TCVD), which utilizes heat, and photo-CVD (photo-CVD), which utilizes light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0328] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0329] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0330] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of the following conditions: a high substrate temperature during film formation and / or an impurity removal treatment. Therefore, the amounts of carbon and chlorine contained in the film may be smaller than those in the case of using the ALD method without these conditions.

[0331] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0332] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0333] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0334] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0335] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0336] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0337] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0338] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0339] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0340] [Example of Manufacturing Method of Transistor 200] An example of a manufacturing method of a semiconductor device including the above-described transistor 200 (see FIGS. 2A1 to 2E) will be described with reference to FIGS. 17A to 18C.

[0341] First, as shown in FIG. 17A, an insulating layer 210 is formed on a substrate (not shown), a conductive layer 220a is formed on the insulating layer 210, a conductive layer 220b is formed on the conductive layer 220a, and an insulating layer 280 is formed on the conductive layer 220b.

[0342] The insulating layer 280 can be formed using two types of film formation methods. For example, a silicon nitride film can be formed as the insulating layer 280 by the ALD method, and then a silicon nitride film can be formed by the sputtering method. The ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for forming thin films and for covering the surfaces of openings or layers with high aspect ratios. The sputtering method has a higher film formation rate than the ALD method, so it can improve productivity.

[0343] Note that after the insulating layer 280 is formed, planarization treatment is preferably performed to planarize the top surface of the insulating layer 280. As the planarization treatment, planarization treatment (also referred to as CMP treatment) using a chemical mechanical polishing (CMP) method is preferable. Alternatively, planarization treatment using etching (also referred to as etch-back treatment) may be performed. By performing the planarization treatment on the insulating layer 280, the surface on which the conductive layer 240a is to be formed can be flattened, and discontinuity of the conductive layer 240a can be suppressed. Note that the planarization treatment is not necessarily performed, and in that case, manufacturing costs can be reduced.

[0344] Subsequently, as shown in FIG. 17A, a conductive layer 240a is formed on the insulating layer 280, and a conductive layer 240b is formed on the conductive layer 240a.

[0345] 17B , openings 290 are formed in conductive layer 240b, conductive layer 240a, and insulating layer 280 at positions that overlap conductive layer 220a. At this time, a recess is preferably provided in conductive layer 220b at a position that overlaps opening 290. By forming opening 290, the bottom and side surfaces of the recess in conductive layer 220b are preferably exposed.

[0346] To facilitate microfabrication and reduce the size of the transistor, it is preferable to use anisotropic etching to process a portion of the conductive layer 220b, a portion of the conductive layer 240a, a portion of the conductive layer 240b, and a portion of the insulating layer 280 when forming the opening 290. Dry etching is particularly preferable because it is suitable for microfabrication. The opening 290 may be formed under different processing conditions depending on the layer. Note that the slope of the side surface of the conductive layer 220b, the side surface of the conductive layer 240a, the side surface of the conductive layer 240b, and the side surface of the insulating layer 280 may differ within the opening 290 depending on the materials and processing conditions of the conductive layer 220b, the conductive layer 240a, the conductive layer 240b, and the insulating layer 280.

[0347] Furthermore, by a process for forming the opening 290 or the like, a region containing a halogen element may be provided on at least one of the bottom and side surfaces of the recess in the conductive layer 220b, the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 240a, and the top and side surfaces of the conductive layer 240b. Examples of such a region include a region containing fluorine, a region containing chlorine, or a region containing fluorine and chlorine. For example, a halogen element derived from the etching gas used in the dry etching may remain in such a region.

[0348] Subsequently, heat treatment may be performed at a temperature of, for example, 250° C. to 650° C., preferably 300° C. to 500° C., and more preferably 320° C. to 450° C.

[0349] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above heat treatment, impurities such as water contained in the insulating layer 280 and the like can be reduced before the formation of the oxide semiconductor layer 230.

[0350] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 280 and the like as much as possible.

[0351] 17C , an insulating layer 235 is formed to cover the opening 290. The insulating layer 235 is provided in contact with the bottom and side surfaces of the recess of the conductive layer 220b, the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 240a, and the top and side surfaces of the conductive layer 240b.

[0352] The insulating layer 235 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method, since it is a layer provided in the opening 290. This allows the insulating layer 235 to be provided with good coverage.

[0353] 17D, insulating layer 235 is processed to expose the top surface of conductive layer 240b and to expose conductive layer 220b in opening 290. In opening 290, it is preferable that the bottom surface of the recess of conductive layer 220b be exposed.

[0354] By processing the insulating layer 235 by anisotropic etching, it is possible to remove the region of the insulating layer 235 located on the top surface of the conductive layer 240b and the region located on the bottom surface of the opening 290, and to leave the insulating layer 235 only on the side surface within the opening 290. It is preferable to process the insulating layer 235 by performing highly anisotropic etching using a dry etching method.

[0355] As shown in FIG. 17D, when processing the insulating layer 235, a portion of the conductive layer 220b may be removed to provide a recess in the conductive layer 220b.

[0356] 18A , an oxide semiconductor layer 230 is formed to cover the opening 290. The oxide semiconductor layer 230 is provided in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220b, the insulating layer 235, and the upper surface of the conductive layer 240b.

[0357] The oxide semiconductor layer 230 can be formed by, for example, sputtering, CVD, molecular beam epitaxy (MBE), PLD, or ALD.

[0358] The oxide semiconductor layer 230 is preferably formed as a film with as uniform a thickness as possible along the bottom and side surfaces of the recesses of the conductive layer 220b, the insulating layer 235, and the top surface of the conductive layer 240b. By forming the oxide semiconductor layer 230 using the ALD method, a thin film can be formed with good controllability. Therefore, the oxide semiconductor layer 230 is preferably formed using the ALD method.

[0359] Furthermore, when the oxide semiconductor layer 230 has high crystallinity, diffusion of impurities in the oxide semiconductor layer 230 is suppressed, which makes it difficult for the electrical characteristics of the transistor to fluctuate and improves reliability. Forming the oxide semiconductor layer 230 by a sputtering method is preferable because it makes it easier to form a layer with high crystallinity than forming the oxide semiconductor layer 230 by an ALD method.

[0360] When the oxide semiconductor layer 230 is formed by a sputtering method, oxygen or a mixed gas of oxygen and a noble gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased. When the oxide film is formed by a sputtering method, an In-M-Zn oxide target or the like can be used.

[0361] When the oxide semiconductor layer 230 is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide semiconductor layer can be improved by performing film formation while heating the substrate.

[0362] For a method for forming an oxide semiconductor layer, the description in Embodiment 2 can be referred to.

[0363] Next, heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range in which the oxide semiconductor layer 230 does not become polycrystallized. The temperature of the heat treatment is preferably from 100° C. to 650° C., more preferably from 250° C. to 600° C., and still more preferably from 350° C. to 550° C. For details of the heat treatment, refer to the above description.

[0364] The gas used in the heat treatment is preferably highly purified. When the heat treatment is performed using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor layer 230 as much as possible.

[0365] In this embodiment, the heat treatment is performed at 450° C. for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. By such heat treatment using oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230 can be reduced. Reducing the impurities in the film in this manner improves the crystallinity of the oxide semiconductor layer 230, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor layer 230, reducing in-plane variations in the crystalline regions in the oxide semiconductor layer 230. Therefore, in-plane variations in the electrical characteristics of the transistor can be reduced.

[0366] In the case where at least one of the insulating layer 280 and the insulating layer 235 contains oxygen, oxygen is preferably supplied from the insulating layer containing oxygen to the channel formation region of the oxide semiconductor layer 230 by heat treatment. Ｏ H can be reduced.

[0367] In this manner, excess oxygen is sometimes supplied to the oxide semiconductor layer 230 from an insulating layer in contact with the oxide semiconductor layer 230 or an insulating layer located near the oxide semiconductor layer 230. The excess oxygen has a function of trapping electrons, which makes it easier for negative charges to be formed. Therefore, the threshold voltage of the transistor is shifted in the positive direction, and a normally-off transistor can be realized.

[0368] 18B , the oxide semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b are processed into island shapes to expose part of the top surface of the insulating layer 280. The oxide semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b can be processed using the same mask, which is preferable because it reduces the number of masks required to manufacture a semiconductor device.

[0369] 18C , an insulating layer 250 is formed to cover the opening 290, and a conductive layer 265a is formed over the insulating layer 250. Furthermore, a conductive layer 265b is formed over the conductive layer 265a. The insulating layer 250 is provided in contact with the oxide semiconductor layer 230. The conductive layer 265a is preferably provided to fill the opening 290. Note that depending on the diameter of the opening 290, the thickness of the conductive layer 265a, and the like, the conductive layer 265b may also be provided in the opening 290.

[0370] The insulating layer 250 and the conductive layer 265a are each formed in the opening 290 with a large aspect ratio. Therefore, for forming the insulating layer 250 and the conductive layer 265a, it is preferable to use a film formation method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.

[0371] In this manner, the transistor 200 can be manufactured.

[0372] [Example of Manufacturing Method of Transistor 202] An example of a manufacturing method of a semiconductor device including the above-described transistor 202 (see FIGS. 13A to 13E) will be described with reference to FIGS. 19A to 19F. Note that detailed description of parts similar to those in the example of the manufacturing method of the transistor 200 will be omitted.

[0373] 17A to 18B are performed in the same manner as in the example of the method for manufacturing the transistor 200. Then, as shown in FIG. 19A , an insulating layer 250 is formed to cover the insulating layer 280, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230.

[0374] Thereafter, a sacrificial layer 262 is formed on the insulating layer 250. A spin-on-carbon (SOC) film and a spin-on-glass (SOG) film are suitable for the sacrificial layer 262. The sacrificial layer 262 preferably has a two-layer structure, for example, an SOC film and an SOG film on the SOC film.

[0375] Providing the sacrificial layer 262 on and in contact with the insulating layer 250 is preferable because damage to the oxide semiconductor layer 230 can be reduced in a manufacturing process of the semiconductor device compared to providing the sacrificial layer 262 on and in contact with the oxide semiconductor layer 230. On the other hand, providing the sacrificial layer 262 on and in contact with the oxide semiconductor layer 230 as in an example of a manufacturing method of the transistor 202 described later is preferable because damage to the insulating layer 250 can be reduced in a manufacturing process of the semiconductor device. Note that when the insulating layer 250 has a stacked structure, some layers constituting the insulating layer 250 may be formed before the sacrificial layer 262 is formed, and the remaining layers may be formed after the sacrificial layer 262 is removed.

[0376] 19B , a portion of the sacrificial layer 262 is removed. Gate electrodes (conductive layers 265 a and 265 b) will be provided in a later step in the region where the sacrificial layer 262 remains. Therefore, it is preferable that the sacrificial layer 262 has a small portion that overlaps with the upper surface of the conductive layer 240 b, and it is more preferable that the sacrificial layer 262 does not overlap with the upper surface of the conductive layer 240 b. As shown in FIG. 19B , in a cross-sectional view, the maximum width of the sacrificial layer 262 is preferably shorter than the width D of the opening 290.

[0377] Subsequently, as shown in FIG. 19C, an insulating layer 283 is formed so as to cover the insulating layer 250 and the sacrificial layer 262, and an insulating layer 285 is formed on the insulating layer 283.

[0378] By increasing the thickness of the insulating layer 285, the distance between the conductive layer 240b and the conductive layer 265a can be increased, and the parasitic capacitance generated between the conductive layer 240b and the gate electrode (or gate wiring) can be reduced.

[0379] For example, the insulating layer 285 is preferably a silicon oxide film formed by a sputtering method.

[0380] Here, if the insulating layer 283 is not provided, when a silicon oxide film is formed as the insulating layer 285 by a sputtering method, the sacrificial layer 262 is exposed to plasma containing oxygen, and thus part or all of the sacrificial layer 262 may be etched. As described above, depending on the method for forming the insulating layer 285, the shape of the sacrificial layer 262 may be reduced or the sacrificial layer 262 may be lost. For this reason, it is preferable that the insulating layer formed on the sacrificial layer 262 has a stacked structure of the insulating layer 283 and the insulating layer 285, rather than a single layer of the insulating layer 285. This provides the effects of broadening the range of choices for the materials of the sacrificial layer 262 and the insulating layer 285, reducing the difficulty of manufacturing a semiconductor device, and so forth.

[0381] When an oxide film is used for the insulating layer 283, it is preferable to form it by a method other than a sputtering method, for example, an ALD method. For example, it is preferable to form an aluminum oxide film or a hafnium oxide film by an ALD method as the insulating layer 283. Alternatively, it is preferable to use a nitride film (such as a silicon nitride film) for the insulating layer 283. This can prevent the sacrificial layer 262 from being unintentionally processed when the insulating layer 283 and the insulating layer 285 are formed.

[0382] The insulating layer 283 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method, so that the insulating layer 283 can be provided with good coverage even on the side surfaces of the sacrificial layer 262, etc.

[0383] 19D , a planarization process is performed to expose the upper surface of the sacrificial layer 262, the insulating layer 283, and the insulating layer 285, and the upper surfaces of the sacrificial layer 262, the insulating layer 283, and the insulating layer 285 are planarized. CMP is a suitable planarization process. In the planarization process, at least a portion of the insulating layer 283 and the insulating layer 285 is removed. Furthermore, a portion of the sacrificial layer 262 may be removed.

[0384] Next, as shown in Fig. 19E, the sacrificial layer 262 is removed. There is no particular limitation on the method for removing the sacrificial layer 262. For example, the sacrificial layer 262 can be removed by dry etching. Here, as shown in Fig. 19E, it can be said that the insulating layer 283 has an opening 270 at a position overlapping the opening 290.

[0385] 19F, a conductive layer 265a is formed to cover the opening 270 and the opening 290. The conductive layer 265a is provided in contact with the insulating layer 250 and the insulating layer 283 in the opening 270 and the opening 290. The conductive layer 265a is preferably provided to fill the opening 290. Furthermore, a conductive layer 265b is formed over the conductive layer 265a. Here, an example in which the conductive layer 265b is provided in the opening 270 is shown.

[0386] The conductive layer 265a and the conductive layer 265b are each formed in one or both of the openings 290 and 270, which have a large aspect ratio. Therefore, the conductive layer 265a and the conductive layer 265b are preferably formed by a film formation method with good coverage, and more preferably by a CVD method, an ALD method, or the like.

[0387] Depending on the diameter of the opening 270, the diameter of the opening 290, the thickness of the conductive layer 265a, and the thickness of the conductive layer 265b, the conductive layer 265b may also be provided in the opening 290. Alternatively, the conductive layer 265a may fill the opening 270, and the conductive layer 265b may not be provided in the opening 270.

[0388] In this manner, the transistor 202 can be manufactured.

[0389] 20A to 20F , an example of a method for manufacturing a semiconductor device including the above-described transistor 203 (see FIGS. 15A to 15E ) will be described. Note that detailed description of the same parts as those in the example of the method for manufacturing the transistors 200 and 202 will be omitted.

[0390] 17A to 18B are performed in the same manner as in the example of the method for manufacturing the transistor 200. Then, as shown in FIG. 20A , a sacrificial layer 262 is formed to cover the insulating layer 280, the conductive layer 240 a, the conductive layer 240 b, and the oxide semiconductor layer 230.

[0391] Next, as shown in FIG. 20B , a portion of the sacrificial layer 262 is removed. A gate insulating layer and a gate electrode (insulating layer 250 and conductive layer 260) will be provided in the remaining region of the sacrificial layer 262 in a later process. Therefore, it is preferable that the sacrificial layer 262 has a small portion that overlaps with the upper surface of the conductive layer 240a, and it is more preferable that the sacrificial layer 262 does not overlap with the upper surface of the conductive layer 240a. In a cross-sectional view, it is preferable that the width of the sacrificial layer 262 does not exceed the sum of the width D of the opening 290 and twice the thickness of the insulating layer 250 to be formed later. FIG. 20B shows an example in which the width of the sacrificial layer 262 is the width D of the opening 290.

[0392] Next, as shown in FIG. 20C , an insulating layer 283 is formed to cover the insulating layer 280, the conductive layer 240a, the conductive layer 240b, the oxide semiconductor layer 230, and the sacrificial layer 262, and an insulating layer 285 is formed over the insulating layer 283.

[0393] By increasing the thickness of the insulating layer 285, the distance from the top surface of the conductive layer 240b to the gate wiring (conductive layer 265) can be increased, and the parasitic capacitance generated between the conductive layer 240b and the gate wiring can be reduced.

[0394] Subsequently, as shown in FIG. 20D, a planarization process is performed to expose the upper surface of the sacrificial layer 262, and the upper surfaces of the sacrificial layer 262, the insulating layer 283, and the insulating layer 285 are planarized.

[0395] Subsequently, as shown in FIG. 20E, the sacrificial layer 262 is removed.

[0396] 20F , an insulating layer 250 is formed to cover the openings 270 and 290, and a conductive layer 260 is formed over the insulating layer 250. Next, by performing planarization treatment, the top surfaces of the insulating layer 283 and the insulating layer 285 are exposed, and the top surfaces of the conductive layer 260, the insulating layer 250, the insulating layer 283, and the insulating layer 285 are planarized.

[0397] The insulating layer 250 is provided in contact with the oxide semiconductor layer 230 and the insulating layer 283 .

[0398] The insulating layer 250 and the conductive layer 260 are respectively formed in the openings 290 and 270, which have a large aspect ratio. Therefore, for forming the insulating layer 250 and the conductive layer 260, it is preferable to use a film formation method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.

[0399] The planarization process is preferably a CMP process, which removes at least the portions of the conductive layer 260 and the insulating layer 250 that overlap with the upper surface of the insulating layer 285. This makes it possible to remove the portion of the conductive layer 260 that overlaps with the upper surface of the conductive layer 240, thereby suppressing the occurrence of parasitic capacitance between the conductive layer 260 and the conductive layer 240.

[0400] By removing the portion of the conductive layer 260 that overlaps with the top surface of the conductive layer 240 using CMP treatment, an increase in the number of masks can be suppressed compared to the case of using dry etching or the like.

[0401] 20F , it is preferable that the height of the upper surface of insulating layer 285 and the height of the upper surface of conductive layer 260 are the same. Alternatively, one of the height of the upper surface of insulating layer 285 and the height of the upper surface of conductive layer 260 may be higher than the other. The height relationship between the upper surfaces of the two layers can be controlled by the difference in polishing rate between the materials of insulating layer 285 and conductive layer 260.

[0402] Subsequently, as shown in FIG. 20F, a conductive layer 265 is formed on the insulating layer 250, the insulating layer 283, the insulating layer 285, and the conductive layer 260.

[0403] The insulating layer 283 and the insulating layer 285 are located between the conductive layer 265 and the conductive layer 240b, which increases the physical distance between the conductive layer 265 and the conductive layer 240b and reduces the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240b.

[0404] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0405] [Method of Adding Element] As described above, a region containing a halogen element may be provided in at least one of the insulating layer 280, the insulating layer 235, and the oxide semiconductor layer 230. A region containing the first element may be provided in the oxide semiconductor layer 230. A region containing the first element may be provided in at least one of the conductive layer 220a, the conductive layer 220b, the conductive layer 240a, and the conductive layer 240b.

[0406] 17B is formed, a halogen element may be supplied to the side surface of the opening 290 in the insulating layer 280. Note that the halogen element may also be supplied to one or more of the conductive layer 240a, the conductive layer 240b, the conductive layer 220a, and the conductive layer 220b.

[0407] 17B shows an example in which the sidewall of the opening 290 is perpendicular to the top surface of the substrate. In the semiconductor device of one embodiment of the present invention, the sidewall of the opening 290 is perpendicular or approximately perpendicular to the top surface of the substrate, or has a tapered shape. Therefore, if the halogen element is added perpendicular or approximately perpendicular to the top surface of the substrate, it may be difficult to uniformly supply the halogen element to a desired region.

[0408] Therefore, it is preferable that the halogen element be added from a direction tilted at an angle greater than 0 degrees and less than 90 degrees with respect to the upper surface of the substrate. This makes it easier to supply the halogen element to the side surface of the opening 290 in the insulating layer 280. Furthermore, the addition is not limited to one direction, and it is preferable to supply the halogen element in stages by changing the rotation angle, which allows the halogen element to be supplied more uniformly to the desired region.

[0409] The elements that can be used as the halogen element are as described above.

[0410] The halogen element can be preferably supplied by plasma ion doping or ion implantation, which allows the concentration profile in the depth direction to be controlled with high precision by adjusting the ion acceleration voltage, dose, etc.

[0411] It should be noted that, for example, by tilting one or both of the substrate to be processed and the ion irradiation unit of the apparatus, the angle at which the halogen element is added can be set within the above range.

[0412] The purity of the supplied halogen element can be increased by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before addition, while the productivity can be increased by using a plasma ion doping method in which a source gas is ionized and the ions are added without mass separation.

[0413] The ion implantation equipment or ion doping equipment used to supply the halogen element is also used in the manufacture of Si transistors such as LTPS transistors, so that the equipment in the existing LTPS manufacturing line can be used, which is preferable because no new capital investment is required, thereby reducing the capital investment costs involved in the manufacture of semiconductor devices.

[0414] As a source gas of a halogen element, a gas containing the above-mentioned halogen element can be used. As the gas, either a gas of a halogen element or a halide gas can be used. When fluorine is supplied, typically, F ２ Gas, BF ３ Gas, C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, CH ３ F gas or the like can be used. When chlorine is supplied, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, CCl ４ A gas can be used. A mixed gas obtained by diluting these source gases with hydrogen or a noble gas can also be used. The ion source is not limited to a gas, and a solid or liquid can also be heated and vaporized.

[0415] The supply of the halogen element can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the composition, density, thickness, etc. of the insulating layer 280 .

[0416] The method for supplying the halogen element is not limited, and may be, for example, plasma treatment or treatment utilizing thermal diffusion by heating. In the case of plasma treatment, the halogen element can be supplied by generating plasma in a gas atmosphere containing the halogen element to be supplied and performing plasma treatment. The apparatus for generating the plasma may be a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like.

[0417] The halogen element supplying step may be performed while heating the substrate, thereby repairing damage to the insulating layer 280 that occurs when the halogen element is added. That is, the addition of the halogen element to the insulating layer 280 and the repair of the damage caused by the addition can be performed in parallel.

[0418] The substrate temperature in the halogen element supply step is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.

[0419] Furthermore, after forming the insulating layer 235 shown in FIG. 17C or 17D, a halogen element may be supplied to the insulating layer 235 located in the opening 290.

[0420] After that, by forming the oxide semiconductor layer 230 while heating the substrate, a halogen element can be supplied from the insulating layer 280 or the insulating layer 235 to the oxide semiconductor layer 230 in some cases. Furthermore, during heat treatment performed after the oxide semiconductor layer 230 is formed, a halogen element can be supplied from the insulating layer 280 or the insulating layer 235 to the oxide semiconductor layer 230 in some cases.

[0421] In this manner, by adding a halogen element to an insulating layer in contact with or near the oxide semiconductor layer 230 and then supplying the halogen element from the insulating layer to the oxide semiconductor layer 230, it is possible to suppress damage to the channel formation region of the oxide semiconductor layer 230 due to the addition of the element, suppress deterioration in the crystallinity of the channel formation region due to the addition of the element, and so on, thereby improving the reliability of the transistor.

[0422] Furthermore, after the oxide semiconductor layer 230 shown in FIG. 18A or 18B is formed, a halogen element may be supplied to the side surface of the oxide semiconductor layer 230 located in the opening 290 .

[0423] After the opening 290 shown in FIG. 17B is formed, an impurity element may be supplied to the top surface of the conductive layer 220b and the top surface of the conductive layer 240b.

[0424] After that, the oxide semiconductor layer 230 is formed and subjected to heat treatment or the like, whereby the impurity elements can be supplied from the conductive layers 220b and 240b to the source and drain regions of the oxide semiconductor layer 230.

[0425] Supplying the impurity element to the oxide semiconductor layer 230 through the conductive layer 220 or the conductive layer 240 can suppress a decrease in the crystallinity of the oxide semiconductor layer 230 compared to a case in which the impurity element is directly added to the oxide semiconductor layer 230. Therefore, an increase in electrical resistance due to a decrease in crystallinity can be suppressed.

[0426] 17B and before the step of forming the conductive layer 265a in FIG. 18C . That is, the impurity element may be supplied to the oxide semiconductor layer 230 after the oxide semiconductor layer 230 is formed. Alternatively, the impurity element may be added to the oxide semiconductor layer 230 through the insulating layer 250.

[0427] By adding an impurity element to the oxide semiconductor layer 230, the sheet resistance of the oxide semiconductor layer 230, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0428] By directly adding the impurity element to the oxide semiconductor layer 230 and then forming the insulating layer 250 over the oxide semiconductor layer 230, damage to the insulating layer 250 due to the addition of the impurity element can be suppressed.

[0429] Alternatively, by supplying the impurity element to the oxide semiconductor layer 230 through the insulating layer 250, a decrease in the crystallinity of the oxide semiconductor layer 230 can be suppressed compared to the case where the impurity element is directly added to the oxide semiconductor layer 230. Therefore, an increase in electrical resistance due to a decrease in crystallinity can be suppressed.

[0430] Furthermore, if the insulating layer 250 is formed after the impurity element is added, there is a risk of contamination of the inside of a deposition chamber for the insulating layer 250. For this reason, it is preferable to add the impurity element after the insulating layer 250 is formed.

[0431] Here, the thickness of the insulating layer 250 in the direction in which the impurity element is added is larger in a region provided along the side surface of the insulating layer 235 than in a region provided along the top surface of the conductive layer 220b or the top surface of the conductive layer 240b. As a result, the amount of the impurity element added is larger in the region of the oxide semiconductor layer 230 provided along the top surface of the conductive layer 220b or the top surface of the conductive layer 240b than in the region provided along the side surface of the insulating layer 235. In this way, the impurity element can be prevented from entering the channel formation region of the oxide semiconductor layer 230, and the resistance of the source region and the drain region can be preferentially reduced.

[0432] The impurity element is preferably added from a direction perpendicular or substantially perpendicular to the top surface of the substrate. In this case, the amount of the impurity element added to a surface of the oxide semiconductor layer 230 that is inclined with respect to the top surface of the substrate or a surface that is perpendicular or substantially perpendicular to the top surface of the substrate is smaller than that to a surface that is parallel or substantially parallel to the top surface of the substrate. That is, the amount of the impurity element added to the source and drain regions of the oxide semiconductor layer 230 is larger than that to the channel formation region. Therefore, the resistance of the source and drain regions can be preferentially reduced.

[0433] The elements that can be used as the impurity elements are as described above.

[0434] The impurity element can be preferably supplied by plasma ion doping or ion implantation, which allows highly accurate control of the concentration profile in the depth direction by adjusting the ion acceleration voltage, dose, etc.

[0435] The purity of the supplied impurity element can be increased by using an ion implantation method in which a source gas is ionized and the ions are mass-separated and added. When using the ion implantation method, it is preferable to use the first element described above as the impurity element, and it is more preferable to use boron or phosphorus. By using an element that bonds with oxygen to stabilize the impurity element, a stable low-resistance region with low electrical resistance can be realized.

[0436] Furthermore, productivity can be improved by using a plasma ion doping method in which a source gas is ionized and the ions are added without mass separation. When using the plasma ion doping method, it is preferable to use both the first element and hydrogen as the impurity element, and it is more preferable to use both boron or phosphorus and hydrogen. By using both an element that bonds with oxygen to stabilize the material and hydrogen as the impurity element, it is easy to reduce the electrical resistance of the low resistance region and to stably maintain the low electrical resistance state.

[0437] The ion implantation equipment or ion doping equipment used to supply impurity elements is also used in the manufacture of Si transistors such as LTPS transistors, so that equipment from existing LTPS manufacturing lines can be used, which is preferable because no new capital investment is required, thereby reducing the capital investment costs involved in the manufacture of semiconductor devices.

[0438] In the supplying treatment of the impurity element, the treatment conditions are preferably controlled so that the concentration of the impurity element in a portion of the oxide semiconductor layer 230 that overlaps with the top surface of the conductive layer 220b or the top surface of the conductive layer 240b is higher than the concentration of the impurity element in other regions. In this way, the impurity element can be supplied at an optimum concentration to the source and drain regions of the oxide semiconductor layer 230.

[0439] As the source gas of the impurity element, a gas containing the above-mentioned impurity element can be used. When boron is supplied, a representative gas is B ２ H ６ Gas, BF ３ In addition, when phosphorus is supplied, a typical example is a PH ３ A mixed gas obtained by diluting these source gases with hydrogen or a noble gas may also be used.

[0440] Other raw material gases include CH ４ , N ２ , N.H. ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , H.F., H. ２ , (C ５ H ５ ) ２ Mg, noble gases, etc. can be used. The ion source is not limited to gas, and a solid or liquid may be heated and vaporized.

[0441] For example, it is preferable to supply boron and hydrogen as the impurity elements using a gas containing boron and hydrogen, since the impurity elements can be added without mass separation and the resistance of the oxide semiconductor layer 230 can be easily reduced, thereby improving both the productivity and characteristics of the semiconductor device.

[0442] Furthermore, it is preferable to use the same source gas in the halogen element supplying step and the impurity element supplying step, since this reduces the manufacturing cost. ３By ionizing the gas and mass-separating the ions, fluorine can be supplied as a halogen element, and boron can be supplied as an impurity element.

[0443] The supply of the impurity element can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the oxide semiconductor layer 230 .

[0444] The method for supplying the impurity element is not limited, and may be, for example, a plasma treatment or a treatment using thermal diffusion by heating. In the case of a plasma treatment, the impurity element can be supplied by generating plasma in a gas atmosphere containing the impurity element to be supplied and performing the plasma treatment. The apparatus for generating the plasma may be a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like.

[0445] The step of supplying the impurity element is preferably performed while heating the substrate, which allows damage to the oxide semiconductor layer 230 caused when the impurity element is added to be repaired. That is, the addition of the impurity element to the oxide semiconductor layer 230 and the repair of the damage caused by the addition can be performed in parallel.

[0446] The substrate temperature in the impurity element supply step is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or even more preferably 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.

[0447] After the impurity element is supplied, heat treatment may be performed. By performing the heat treatment, damage to the oxide semiconductor layer 230 that occurs in the step of supplying the impurity element can be repaired.

[0448] By using an element that bonds with oxygen to stabilize the semiconductor device as the impurity element, it is possible to prevent the impurity element from being desorbed due to heat applied during the manufacturing process of the semiconductor device, etc. Therefore, even if heat treatment is performed or a film formation process is performed while the substrate is heated after the impurity element is added, the impurity element is not desorbed and a low electrical resistance can be maintained.

[0449] 21A1 to 22B , a configuration example of a transistor that is partially different from the transistor 200 will be described. Note that a description of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be denoted by the same reference numerals and their descriptions may be omitted.

[0450] FIG. 21A1 is a plan view of a semiconductor device having a transistor 204. FIG. 21A2 is a plan view showing an example in which a plurality of transistors 204 are arranged. FIG. 21B is a cross-sectional view taken along dashed dotted lines A1-A2 in FIG. 21A1. FIG. 21C is a cross-sectional view taken along dashed dotted lines A3-A4 in FIG. 21A1. FIGS. 21D and 21E are cross-sectional views taken along dashed dotted lines A5-A6 in FIG. 21B. FIG. 21E corresponds to an example of an enlarged view of FIG. 21D. FIGS. 21D and 21E can also be considered cross-sectional views of the XY plane including the insulating layer 280. Note that some elements are omitted in the plan views of FIGS. 21A1 and 21A2 for clarity. Some elements may also be omitted in the subsequent plan views.

[0451] 22A and 22B are cross-sectional views taken along dashed line A1-A2 in Fig. 21A1, and are examples of enlarged views of Fig. 21B, showing examples of the configuration of each layer in more detail.

[0452] 21A1 to 21E includes an insulating layer 210 over a substrate (not shown), a transistor 204 over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. The insulating layer 210 and the insulating layer 280 function as interlayer films.

[0453] [Transistor 204] The transistor 204 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 240a over the insulating layer 280, a conductive layer 240b over the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, a conductive layer 265a over the insulating layer 250, and a conductive layer 265b over the conductive layer 265a. The transistor 204 differs from the transistor 200 mainly in that the insulating layer 235 has a stacked structure.

[0454] 21A1 to 21E show an example in which the insulating layer 235 has two layers: an insulating layer 235a in contact with the insulating layer 280 and an insulating layer 235b located between the insulating layer 235a and the oxide semiconductor layer 230. The insulating layer 235 shown in FIGS. 21A1 to 21E can be said to have a two-layer structure including the insulating layer 235a and the insulating layer 235b on the insulating layer 235a. In this case, for example, one of the insulating layers 235a and 235b is preferably an insulator having a function of capturing or fixing hydrogen. Furthermore, the other of the insulating layers 235a and 235b is preferably an insulating layer having a region containing excess oxygen. This can reduce the hydrogen concentration in the oxide semiconductor layer 230 and supply oxygen from the insulating layer 235a or 235b to the oxide semiconductor layer 230, thereby improving the reliability of the transistor. Typically, the insulating layer 235a can be an insulator having a function of capturing or fixing hydrogen, and the insulating layer 235b can be an insulating layer having a region containing excess oxygen.

[0455] For example, it is preferable to use a hafnium oxide film, a hafnium aluminate film, or an aluminum oxide film for the insulating layer 235a, and a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film for the insulating layer 235b. In this case, the insulating layer 235a contains one or both of hafnium and aluminum, and oxygen, and the insulating layer 235b contains one or both of silicon and aluminum, and oxygen. Alternatively, for example, a hafnium silicate film may be used for the insulating layer 235a. Alternatively, it is preferable to use a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film for the insulating layer 235a, and a hafnium oxide film, a hafnium aluminate film, or an aluminum oxide film for the insulating layer 235b. In this case, the insulating layer 235a contains one or both of silicon and aluminum, and oxygen, and the insulating layer 235b contains one or both of hafnium and aluminum, and oxygen. For example, the insulating layer 235b may be a hafnium silicate film.

[0456] As described above, by wrapping the oxide semiconductor layer 230 in a ring shape with a barrier insulating layer against hydrogen and providing an insulating layer having a function of capturing or fixing hydrogen or an insulating layer including a region containing excess oxygen near the oxide semiconductor layer 230, it is possible to reduce one or both of oxygen vacancies and impurities in the oxide semiconductor layer 230. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0457] As described above in <Structural Example 1 of Semiconductor Device>, the semiconductor device of this embodiment has a structure in which insulating layers are provided above and below the oxide semiconductor layer 230. Examples of the insulating layer provided above or below the oxide semiconductor layer 230 include the insulating layer 210 and the insulating layer 250.

[0458] The configurations of insulating layer 210 and insulating layer 250 can be referred to in the description of <Configuration Example 1 of Semiconductor Device> above. For example, as shown in FIG. 22A , insulating layer 210 may have a two-layer structure including insulating layer 210a and insulating layer 210b on insulating layer 210a. Alternatively, insulating layer 250 may have a three-layer structure including insulating layer 250c, insulating layer 250a on insulating layer 250c, and insulating layer 250b on insulating layer 250a. Alternatively, as shown in FIG. 22B , insulating layer 250 may have a four-layer structure including insulating layer 250d, insulating layer 250c on insulating layer 250d, insulating layer 250a on insulating layer 250c, and insulating layer 250b on insulating layer 250a.

[0459] 22A illustrates an example in which the insulating layer 235a is provided in contact with the bottom and side surfaces of the recess of the conductive layer 220b, and the insulating layer 235b is provided on the insulating layer 235a. For example, an insulating film to be the insulating layer 235a and an insulating film to be the insulating layer 235b are stacked, and then the two insulating films are processed to form the insulating layer 235a and the insulating layer 235b having the structure illustrated in FIG. 22A. Therefore, it can be said that this structure can be manufactured relatively easily.

[0460] 23A to 27B , examples of the configuration of a transistor that is partially different from the configuration of the transistor 204 will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0461] [Transistors 204A and 204B] Fig. 23A is a cross-sectional view of a semiconductor device having a transistor 204A. Fig. 23B is a cross-sectional view of a semiconductor device having a transistor 204B.

[0462] In the transistor 204A, an example is shown in which the insulating layer 235a is provided in contact with the bottom and side surfaces of the recess of the conductive layer 220b, and the insulating layer 235b is located inside the insulating layer 235a in the opening 290 and is provided in contact with the bottom of the recess of the conductive layer 220b.

[0463] In transistor 204B, conductive layer 220b has a first recess, a second recess located outside the first recess, and a third recess located outside the second recess. The first recess is deeper than the second recess, and the second recess is deeper than the third recess. The third recess is provided in conductive layer 220b when forming opening 290, and then the second recess is provided in conductive layer 220b when processing insulating layer 235a, and then the first recess is provided in conductive layer 220b when processing insulating layer 235b. Therefore, in FIG. 23B , the side of the first recess is aligned with the surface of insulating layer 235b facing the oxide semiconductor layer 230, the side of the second recess is aligned with the surface of insulating layer 235a facing the insulating layer 235b, and the side of the third recess is aligned with the side of insulating layer 280 facing the opening 290.

[0464] In the transistor 204B, an example is shown in which the insulating layer 235a is provided in contact with the bottom and side surfaces of the third recess of the conductive layer 220b, and the insulating layer 235b is provided in contact with the bottom and side surfaces of the second recess of the conductive layer 220b.

[0465] 23A or 23B can be formed by providing the insulating layer 235a on the sidewall of the opening 290 and then forming and processing an insulating film to be the insulating layer 235b. Compared to the transistor 204, the region where the insulating layer 235a is in contact with the oxide semiconductor layer 230 is reduced, and a configuration in which the insulating layer 235b is in contact with the oxide semiconductor layer 230 can be realized.

[0466] [Transistor 204C] FIG. 24A is a cross-sectional view of a semiconductor device having a transistor 204C.

[0467] The transistor 204C differs from the transistor 200 mainly in that the insulating layer 235 is made up of three layers.

[0468] The transistor 204C includes an insulating layer 235a in contact with the insulating layer 280, an insulating layer 235b located between the insulating layer 235a and the oxide semiconductor layer 230, and an insulating layer 235c located between the insulating layer 235b and the oxide semiconductor layer 230. In other words, the transistor 204C includes the insulating layer 235a, the insulating layer 235b over the insulating layer 235a, and the insulating layer 235c over the insulating layer 235b.

[0469] At least one of the insulating layers 235a, 235b, and 235c preferably includes an insulating layer having a region containing excess oxygen.Furthermore, at least one of the insulating layers 235a, 235b, and 235c preferably includes an insulator that has a function of capturing or fixing hydrogen.

[0470] This allows oxygen to be supplied to the oxide semiconductor layer 230 from at least one of the insulating layer 235a, the insulating layer 235b, and the insulating layer 235c, and also prevents hydrogen from diffusing into the oxide semiconductor layer 230, thereby improving the reliability of the transistor.

[0471] For example, it is preferable to use a hafnium oxide film or a hafnium silicate film for the insulating layer 235a, a silicon oxide film for the insulating layer 235b, and an aluminum oxide film for the insulating layer 235c.

[0472] The configurations of insulating layer 210 and insulating layer 250 can be referred to in the description of <Configuration Example 1 of Semiconductor Device> above. For example, as shown in FIG. 24B , insulating layer 210 may have a two-layer structure including insulating layer 210a and insulating layer 210b on insulating layer 210a. Alternatively, insulating layer 250 may have a four-layer structure including insulating layer 250d, insulating layer 250c on insulating layer 250d, insulating layer 250a on insulating layer 250c, and insulating layer 250b on insulating layer 250a.

[0473] The insulating layer 235 having a three-layer structure in the transistor 204C can be considered a modified example of the insulating layer 235 having a two-layer structure in the transistor 204 ( FIG. 22A ). When the insulating layer 235 having a three-layer structure is used, it is not limited to the configuration shown in the transistor 204C. For example, the insulating layer 235 having a two-layer structure in the transistor 204A ( FIG. 23A ) or the transistor 204B ( FIG. 23B ) can also have a three-layer structure.

[0474] For the configurations of insulating layer 210 and insulating layer 250, the contents described above in <Configuration Example 1 of Semiconductor Device> can be referred to. For example, as shown in Fig. 24B , insulating layer 210 may have a two-layer structure including insulating layer 210a and insulating layer 210b on insulating layer 210a. Also, as shown in Fig. 24B , insulating layer 250 may have a four-layer structure including insulating layer 250d, insulating layer 250c on insulating layer 250d, insulating layer 250a on insulating layer 250c, and insulating layer 250b on insulating layer 250a.

[0475] [Transistor 204D] FIG. 25A is a cross-sectional view of a semiconductor device having a transistor 204D.

[0476] The transistor 204D is different from the transistor 201 mainly in that the insulating layer 235 has a two-layer structure. For details of the insulating layer 235 having a two-layer structure, refer to the description of the transistor 204 (FIGS. 21A1 to 21E).

[0477] [Transistor 204E] FIG. 25B is a cross-sectional view of a semiconductor device having a transistor 204E.

[0478] The transistor 204E differs from the transistor 202 mainly in that the insulating layer 235 has a two-layer structure. For details of the insulating layer 235 having a two-layer structure, refer to the description of the transistor 204 (FIGS. 21A1 to 21E).

[0479] [Transistor 204F] FIG. 26 is a cross-sectional view of a semiconductor device having a transistor 204F.

[0480] The transistor 204F differs from the transistor 203 mainly in that the insulating layer 235 has a two-layer structure. For details of the insulating layer 235 having a two-layer structure, refer to the description of the transistor 204 (FIGS. 21A1 to 21E).

[0481] [Transistors 204G and 204H] FIG. 27A is a cross-sectional view of a semiconductor device having a transistor 204G.

[0482] The transistor 204G differs from the transistor 204 mainly in that it includes a metal oxide layer 227 instead of the insulating layer 235b.

[0483] The metal oxide layer 227 is preferably made of a metal oxide material that can be used for the oxide semiconductor layer 230. For example, the metal oxide layer 227 preferably contains one or both of gallium and zinc. When the metal oxide layer 227 contains gallium, oxygen contained in the oxide semiconductor layer 230 can be prevented from diffusing into the insulating layer 235a and the like, and oxygen vacancies can be prevented from being formed in the oxide semiconductor layer 230. Furthermore, when the metal oxide layer 227 contains zinc, the crystallinity of the metal oxide layer 227 is increased, and the crystallinity of the oxide semiconductor layer 230 provided over the metal oxide layer 227 can be improved.

[0484] For example, gallium oxide, zinc oxide, indium gallium oxide, gallium zinc oxide, aluminum zinc oxide, indium gallium zinc oxide, or the like can be used as a single layer or a stacked layer for the metal oxide layer 227. When indium gallium zinc oxide is used for the metal oxide layer 227, specifically, a metal oxide having a composition of In:M:Zn=1:3:2 (atomic ratio) or a composition therearound, or an atomic ratio of In:M:Zn=1:3:4 (atomic ratio) or a composition therearound may be used.

[0485] The metal oxide layer 227 can be thinner than the oxide semiconductor layer 230, for example, from 0.1 nm to 1 nm, or from 0.1 nm to 0.5 nm.

[0486] By providing the metal oxide layer 227 between the insulating layer 235a and the oxide semiconductor layer 230, it is possible to suppress the diffusion of impurity components such as hydrogen contained in the insulating layer 235a into the oxide semiconductor layer 230. This can improve the crystallinity of the oxide semiconductor layer 230. Furthermore, when the metal oxide layer 227 can sufficiently suppress the diffusion of impurity components such as hydrogen contained in the insulating layer 235a, an insulating material that is relatively permeable to hydrogen, such as silicon oxide, can also be used for the insulating layer 235a.

[0487] When the insulating layer 235a has a function of capturing or fixing hydrogen, the insulating layer 235a preferably has a large thickness, for example, preferably thicker than the metal oxide layer 227. When the insulating layer 235a is made thick, hydrogen in the oxide semiconductor layer 230 can be diffused into the insulating layer 235a and the hydrogen can be captured or fixed. However, since the insulating layer 235a is provided inside the opening 290, it is preferable that the insulating layer 235a be a thin film. For example, the thickness of the insulating layer 235a can be set to 1 nm to 10 nm, 1 nm to 5 nm, or 3 nm to 5 nm.

[0488] Note that the transistor included in the semiconductor device of this embodiment can have a structure in which a metal oxide layer 227 is provided instead of the insulating layer 235c of the transistor 204C shown in Fig. 24A or the transistor 204C shown in Fig. 24B. A transistor 204H including a metal oxide layer 227 instead of the insulating layer 235c of the transistor 204C shown in Fig. 24B is shown in Fig. 27B.

[0489] 21B to 27B show examples in which the insulating layer 235 is made up of two or three layers. Note that the insulating layer 235 may be made up of four or more layers.

[0490] The transistor 204 can be modified in shape and details, similarly to the transistor 200. Specifically, the transistor 204 can have the same structure as the transistors 200A to 200G.

[0491] 28A to 30B , a configuration example of a transistor that is partially different from the transistor 200 will be described. Note that a description of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be denoted by the same reference numerals and their descriptions may be omitted.

[0492] 28A and 28B are schematic perspective views of a semiconductor device having a transistor 205. Fig. 28B is a perspective view with a portion cut away from Fig. 28A. In Fig. 28A and 28B, only the outlines of some components (interlayer insulating layers, etc.) are shown by dashed lines.

[0493] FIG. 29A1 is a plan view of a semiconductor device having a transistor 205. FIG. 29A2 is a plan view showing an example in which a plurality of transistors 205 are arranged. FIG. 29B is a cross-sectional view taken along dashed-dotted lines A1-A2 in FIG. 29A1. FIG. 29C is a cross-sectional view taken along dashed-dotted lines A3-A4 in FIG. 29A1. FIGS. 29D and 29E are cross-sectional views taken along dashed-dotted lines A5-A6 in FIG. 29B. FIG. 29E corresponds to an example of an enlarged view of FIG. 29D. FIGS. 29D and 29E can also be considered cross-sectional views of the XY plane including the insulating layer 280a. Note that some elements are omitted in the plan views of FIGS. 29A1 and 29A2 for clarity. Some elements may also be omitted in subsequent plan views.

[0494] 30A and 30B are cross-sectional views taken along dashed line A1-A2 in Fig. 29A1, and are examples of enlarged views of Fig. 30B, each showing an example of the configuration of each layer in more detail.

[0495] 28A to 29E includes an insulating layer 210 over a substrate (not shown), a transistor 205 over the insulating layer 210, and an insulating layer 280a over the insulating layer 210. The insulating layer 210 and the insulating layer 280a function as interlayer films.

[0496] [Transistor 205] The transistor 205 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 240a over the insulating layer 280a, a conductive layer 240b over the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, a conductive layer 265a over the insulating layer 250, and a conductive layer 265b over the conductive layer 265a. The transistor 205 differs mainly from the transistor 200 in that the insulating layer 235 is composed of two layers. The transistor 205 also differs mainly from the transistor 200 in that the transistor 205 includes an insulating layer 280a instead of the insulating layer 280.

[0497] 29D and 29E show an example in which the insulating layer 235 is configured of two layers: an insulating layer 235a in contact with the insulating layer 280a, and an insulating layer 235b located between the insulating layer 235a and the oxide semiconductor layer 230. As shown in Figures 29D and 29E, the transistor 205 has a structure in which the insulating layer 235a surrounds the oxide semiconductor layer 230 in a ring shape in a plan view. Furthermore, the semiconductor device has a structure in which the insulating layer 235b is disposed between the insulating layer 235a and the oxide semiconductor layer 230 in a plan view.

[0498] When the insulating layer 235 has a two-layer structure, the insulating layer 235a provided on the outer side of the oxide semiconductor layer 230 can be a barrier insulator against hydrogen, and the insulating layer 235b provided in contact with the oxide semiconductor layer 230 can be an insulator that has a function of capturing or fixing hydrogen. With such a structure, hydrogen in the oxide semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. For example, the threshold voltage V ｔｈ This will result in a positive shift.

[0499] For example, it is preferable to use a silicon nitride film for the insulating layer 235a. In this case, the insulating layer 235a contains silicon and nitrogen. It is also preferable to use a hafnium oxide film, a hafnium aluminate film, or an aluminum oxide film for the insulating layer 235b. In this case, the insulating layer 235b contains oxygen and one or both of hafnium and aluminum. It is more preferable to use a hafnium oxide film for the insulating layer 235b. In this case, the insulating layer 235b contains hafnium and oxygen.

[0500] The insulating layer 235a provided outside the oxide semiconductor layer 230 can be a barrier insulator against hydrogen, and the insulating layer 235b provided in contact with the oxide semiconductor layer 230 can be an insulating layer including a region containing excess oxygen. With such a structure, one or both of oxygen vacancies and hydrogen in the oxide semiconductor layer 230 can be reduced. Therefore, the electrical characteristics and reliability of the transistor can be improved.

[0501] Note that by configuring the insulating layer 235 as described above, the range of insulating materials to be used for the insulating layer 280a can be broadened, thereby improving yield and reliability. For example, a material with a low dielectric constant can be used for the insulating layer 280a. This reduces parasitic capacitance between wirings. For example, silicon oxide or silicon oxynitride can be used for the insulating layer 280a. Note that the insulating layer 280a may be made of any of the insulating materials applicable to the insulating layer 280 described above.

[0502] For example, a silicon nitride film is preferably used for the insulating layer 235a. In this case, the insulating layer 235a contains silicon and nitrogen. Furthermore, a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film is preferably used for the insulating layer 235b. Furthermore, a silicon oxide film is more preferably used for the insulating layer 235b. In this case, the insulating layer 235b contains silicon and oxygen.

[0503] Silicon nitride, which can be used for the insulating layer 235a, also has a barrier property against oxygen. The insulating layer 235a is in contact with the side surface of the conductive layer 240 in the opening 290. Therefore, by forming the insulating layer 235a in contact with the conductive layer 240 using silicon nitride, oxidation of the conductive layer 240 can be suppressed.

[0504] On the other hand, the transistor 200 described in the above <Structure Example 1 of Semiconductor Device> can reduce the number of stacked insulating layers 235 provided in the opening 290 and increase the channel width per unit area, compared to the transistor 205. Therefore, the on-state current of the transistor 200 can be increased, and frequency characteristics can be improved.

[0505] 30B , the insulating layer 280a may have a three-layer structure including an insulating layer 280a1, an insulating layer 280a2 on the insulating layer 280a1, and an insulating layer 280a3 on the insulating layer 280a2. In this case, it is preferable to use a material with a low dielectric constant as the insulating layer 280a2, and to use barrier insulating layers against oxygen as the insulating layers 280a1 and 280a3. This can suppress oxidation of the conductive layer 220 and the conductive layer 240, thereby preventing the conductive layer 220 and the conductive layer 240 from becoming high in resistance.

[0506] Alternatively, the insulating layer 280a2 may be made of the above-described material having a low dielectric constant, and the insulating layers 280a1 and 280a3 may be barrier insulating layers against hydrogen. With this structure, the insulating layer 280a2 can be surrounded by the insulating layers 280a1, 280a3, and 235a. This is preferable because it can suppress diffusion of impurities such as hydrogen from the insulating layer 280a2 to the oxide semiconductor layer 230.

[0507] For example, it is preferable to use a silicon nitride film or an aluminum oxide film as the insulating layer 280a1 and the insulating layer 280a3, and a silicon oxide film as the insulating layer 280a2.

[0508] 30A , the conductive layer 220 may have a three-layer structure including a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2.

[0509] The configurations of the insulating layer 210 and the insulating layer 250 can be referred to the contents described above in <Configuration Example 1 of Semiconductor Device>. For example, as shown in Fig. 31 , the insulating layer 210 may have a two-layer structure including an insulating layer 210a and an insulating layer 210b on the insulating layer 210a. Alternatively, the insulating layer 250 may have a four-layer structure including an insulating layer 250d, an insulating layer 250c on the insulating layer 250d, an insulating layer 250a on the insulating layer 250c, and an insulating layer 250b on the insulating layer 250a.

[0510] 32A to 35 , examples of the configuration of a transistor that is partially different from the transistor 205 will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and descriptions thereof may be omitted.

[0511] [Transistor 205A] FIG. 32A is a cross-sectional view of a semiconductor device having a transistor 205A.

[0512] The transistor 205A differs from the transistor 205 mainly in that the insulating layer 235 is made up of three layers.

[0513] The transistor 205A includes an insulating layer 235a in contact with the insulating layer 280a, an insulating layer 235b located between the insulating layer 235a and the oxide semiconductor layer 230, and an insulating layer 235c located between the insulating layer 235b and the oxide semiconductor layer 230. The transistor 205A can be said to include the insulating layer 235a, the insulating layer 235b over the insulating layer 235a, and the insulating layer 235c over the insulating layer 235b.

[0514] The insulating layer 235a is preferably a barrier insulator against hydrogen. One of the insulating layer 235b and the insulating layer 235c preferably includes an insulating layer having a region containing excess oxygen. The other of the insulating layer 235b and the insulating layer 235c is preferably an insulator that has a function of capturing or fixing hydrogen. With such a structure, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed and oxygen can be supplied to the oxide semiconductor layer 230, thereby improving the reliability of the transistor.

[0515] For example, the insulating layer 235a is preferably a silicon nitride film or an aluminum oxide film, and more preferably a silicon nitride film. The insulating layer 235b is preferably a hafnium oxide film, a hafnium aluminate film, or an aluminum oxide film. In this case, the insulating layer 235b contains oxygen and one or both of hafnium and aluminum. Also, the insulating layer 235b is preferably a hafnium silicate film. The insulating layer 235c is preferably a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. In this case, the insulating layer 235c contains oxygen and one or both of silicon and aluminum.

[0516] Note that the transistor included in the semiconductor device of this embodiment can have a structure in which a metal oxide layer 227 is provided instead of the insulating layer 235c of the transistor 205A illustrated in Figure 32A or the transistor 205A illustrated in Figure 32B. For metal oxide materials that can be used for the metal oxide layer 227, the content described above in <Structural example 2 of semiconductor device> can be referred to.

[0517] For the configurations of insulating layer 210 and insulating layer 250, the contents described above in <Configuration Example 1 of Semiconductor Device> can be referred to. For example, as shown in FIG. 32B , insulating layer 210 may have a two-layer structure including insulating layer 210a and insulating layer 210b on insulating layer 210a. Alternatively, insulating layer 250 may have a four-layer structure including insulating layer 250d, insulating layer 250c on insulating layer 250d, insulating layer 250a on insulating layer 250c, and insulating layer 250b on insulating layer 250a.

[0518] [Transistor 205B] FIG. 33A is a cross-sectional view of a semiconductor device having a transistor 205B.

[0519] The transistor 205B differs from the transistor 205 mainly in that the insulating layer 235 is made up of four layers.

[0520] The transistor 205B includes an insulating layer 235a in contact with the insulating layer 280, an insulating layer 235b located between the insulating layer 235a and the oxide semiconductor layer 230, an insulating layer 235c located between the insulating layer 235b and the oxide semiconductor layer 230, and an insulating layer 235d located between the insulating layer 235c and the oxide semiconductor layer 230. The transistor 205B can be said to include the insulating layer 235a, the insulating layer 235b over the insulating layer 235a, the insulating layer 235c over the insulating layer 235b, and the insulating layer 235d over the insulating layer 235c.

[0521] The insulating layer 235a is preferably a barrier insulator against hydrogen. At least one of the insulating layers 235b to 235d preferably includes an insulating layer having a region containing excess oxygen. At least one of the insulating layers 235b to 235d is preferably an insulator that has a function of capturing or fixing hydrogen. With such a structure, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed and oxygen can be supplied to the oxide semiconductor layer 230, thereby improving the reliability of the transistor.

[0522] For example, it is preferable to use a silicon nitride film or an aluminum oxide film for the insulating layer 235a, a hafnium oxide film or a hafnium silicate film for the insulating layer 235b, a silicon oxide film for the insulating layer 235c, and an aluminum oxide film for the insulating layer 235d.

[0523] Each layer constituting the insulating layer 235 is preferably a thin film. By reducing the thickness of the insulating layer 235, it is possible to prevent the channel width of the transistor from becoming smaller and the on-state current from becoming smaller. On the other hand, by increasing the thickness of the insulating layer 235, it is possible to improve the functions of the insulating layer 235 (for example, the barrier property against hydrogen, the function of capturing or fixing hydrogen, etc.). For example, the insulating layer 235 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm.

[0524] The thickness of each layer constituting the insulating layer 235 (corresponding to insulating layers 235a to 235d in the case of the configuration shown in FIG. 33A ) is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 235 has a region with the above-described thickness in at least a portion thereof.

[0525] Note that the transistor included in the semiconductor device of this embodiment can have a structure in which a metal oxide layer 227 is provided instead of the insulating layer 235d of the transistor 205B illustrated in Figure 33A or the transistor 205B illustrated in Figure 33B. For metal oxide materials that can be used for the metal oxide layer 227, the content described above in <Structural example 2 of semiconductor device> can be referred to.

[0526] The configurations of insulating layer 210 and insulating layer 250 can be referred to in the description of <Configuration Example 1 of Semiconductor Device> above. For example, as shown in FIG. 33B , insulating layer 210 may have a two-layer structure including insulating layer 210a and insulating layer 210b on insulating layer 210a. Alternatively, insulating layer 250 may have a four-layer structure including insulating layer 250d, insulating layer 250c on insulating layer 250d, insulating layer 250a on insulating layer 250c, and insulating layer 250b on insulating layer 250a.

[0527] 29B to 33B show examples in which the insulating layer 235 is made up of two, three, or four layers. Note that the insulating layer 235 may be made up of five or more layers.

[0528] [Transistor 205C] FIG. 34A is a cross-sectional view of a semiconductor device having a transistor 205C.

[0529] The transistor 205C differs from the transistor 201 mainly in that the insulating layer 235 has a two-layer structure and in that an insulating layer 280a is provided instead of the insulating layer 280. Note that Figure 34A shows a configuration in which the insulating layer 280a has a three-layer structure of insulating layers 280a1 to 280a3. For details of the insulating layer 235 and the insulating layer 280a shown in Figure 34A, the description of the transistor 205 (Figures 29A1 to 30B) can be referred to.

[0530] [Transistor 205D] FIG. 34B is a cross-sectional view of a semiconductor device having a transistor 205D.

[0531] The transistor 205D differs from the transistor 202 mainly in that the insulating layer 235 has a two-layer structure and in that an insulating layer 280a is provided instead of the insulating layer 280. Note that Figure 34B shows a configuration in which the insulating layer 280a has a three-layer structure of insulating layers 280a1 to 280a3. For details of the insulating layer 235 and the insulating layer 280a shown in Figure 34B, the description of the transistor 205 (Figures 29A1 to 30B) can be referred to.

[0532] [Transistor 205E] FIG. 35 is a cross-sectional view of a semiconductor device having a transistor 205E.

[0533] The transistor 205E differs from the transistor 203 mainly in that the insulating layer 235 has a two-layer structure and that an insulating layer 280a is provided instead of the insulating layer 280. Note that Figure 35 shows a configuration in which the insulating layer 280a has a three-layer structure of insulating layers 280a1 to 280a3. For details of the insulating layer 235 and the insulating layer 280a shown in Figure 35, the description of the transistor 205 (Figures 29A1 to 30B) can be referred to.

[0534] The transistor 205 may have a different shape and details, similar to the transistor 200. Specifically, the same structure as the transistors 200A to 200G may be applied to the transistor 205. The same structure as the transistors 201 to 203 may be applied to the transistor 205.

[0535] In a semiconductor device according to one embodiment of the present invention, an oxide semiconductor layer is surrounded by a barrier insulating layer against hydrogen, and one or both of an insulating layer having a function of capturing or adhering hydrogen and an insulating layer having a region containing excess oxygen are provided near the oxide semiconductor layer, whereby oxygen vacancies and / or impurities in the oxide semiconductor layer can be reduced, thereby improving the electrical characteristics and reliability of the transistor.

[0536] The semiconductor device according to one embodiment of the present invention has a structure in which parasitic capacitance between a source electrode or a drain electrode and a gate electrode and between a source electrode or a drain electrode and a gate wiring are reduced, thereby improving the frequency characteristics of a circuit using the semiconductor device.

[0537] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0538] Embodiment 2 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0539] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0540] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts. When metal atoms are arranged in a layered manner in the crystal parts, a group of bright spots (specifically, bright spots arranged in a layered manner) reflecting the layered arrangement of the metal atoms is observed in a cross section of the oxide semiconductor layer observed using a TEM image.

[0541] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the metal is formed. In the CAAC structure, metal atoms are arranged in layers parallel or approximately parallel to the surface on which the metal is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the metal is formed.

[0542] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0543] When an oxide semiconductor layer having a CAAC structure is subjected to electron diffraction, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed or a normal vector of the surface of the oxide semiconductor layer.

[0544] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0545] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0546] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the layer has crystallinity. Furthermore, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0547] A method for creating a Voronoi diagram will now be described. First, image analysis of a TEM image involves performing FFT processing, filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal regions enclosed by the lines connecting the Voronoi points are defined as Voronoi regions. In this way, a Voronoi diagram can be created.

[0548] As an example of the observation range of the TEM in creating a Voronoi diagram, a rectangular region of 50 nm in length and 50 nm in width can be observed, but the observation range is not limited to this.

[0549] Furthermore, when the distribution of the orientation of the hexagonal lattice is analyzed using lattice points extracted by image analysis of a planar TEM image, the difference in the orientation of the hexagonal lattice at the boundary between two structures with different hexagonal lattice orientations is small, and the boundary is observed to be blurred, and it appears that the two structures are connected in a manner that makes them intertwine. In other words, no clear boundary is observed in the CAAC structure.

[0550] The orientation of the hexagonal lattice can be calculated by calculating the orientation of a hexagon formed by the six lattice points closest to each lattice point.

[0551] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0552] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain element M. Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain element M. Note that element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0553] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Furthermore, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0554] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum. Examples of usable metal oxides include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include ITSO, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as the metal oxide according to one embodiment of the present invention.

[0555] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0556] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0557] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0558] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0559] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0560] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0561] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed by two different deposition methods may be referred to as a hybrid OS.

[0562] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0563] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a crystalline metal oxide is deposited by the first deposition method. The deposited metal oxide preferably has a CAAC structure. For example, a metal oxide deposited by a sputtering method is likely to have crystallinity.

[0564] When a metal oxide is formed using the first film-forming method, a mixed layer may be formed at the interface between the metal oxide and a layer on which the metal oxide is to be formed. For example, when a sputtering method is used as the first film-forming method, the mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy imparted to the substrate by the sputtering particles. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide.

[0565] For example, when an insulating layer having silicon, such as silicon oxide, is used as a surface to be formed, silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide using the first film formation method, and there is a concern that the mixing of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide.

[0566] Therefore, in one embodiment of the present invention, a metal oxide is formed by a second film formation method before a metal oxide is formed by a first film formation method. That is, a metal oxide is formed as a first layer by the second film formation method, and then a metal oxide is formed as a second layer on the first layer by the first film formation method. In this case, it is preferable to use a film formation method that causes less damage to the formation surface than the first film formation method as the second film formation method. By using a film formation method that causes less damage to the formation surface as the second film formation method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, since incorporation of impurities such as silicon into the second layer can be suppressed, crystallinity can be potentially improved. For example, ALD and CVD are suitable as the second film formation methods because they can suppress damage to the formation surface compared to sputtering.

[0567] In addition, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure may be formed as the first layer. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0568] In the oxide semiconductor layer of one embodiment of the present invention, it is preferable that a metal oxide be first formed over a surface to be formed by the second film formation method, and then a metal oxide be formed above the metal oxide by the first film formation method.

[0569] The first film formation method may be, for example, a sputtering method or a PLD method.

[0570] Examples of the second film formation method include ALD, plasma CVD, thermal CVD, photo-CVD, metal organic CVD, and MBE. The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed. Also, a wet method can be used as the second film formation method. The wet method is one of the film formation methods that causes little damage to the surface on which the film is formed. Examples of the wet method include spray coating.

[0571] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by the second deposition method and then forming a metal oxide as a second layer by the first deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method. The metal oxide formed by the first deposition method preferably has a CAAC structure.

[0572] Furthermore, a third layer can be further formed on the second layer. Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0573] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0574] The third layer is an uppermost layer of the oxide semiconductor layer, and is in contact with, for example, a gate insulating film when the oxide semiconductor layer is used as a semiconductor layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating film, carrier mobility can be increased when the transistor is in an on state.

[0575] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by the second deposition method, forming a metal oxide as a second layer by the first deposition method, and forming a metal oxide as a third layer by the second deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method. The metal oxide formed by the first deposition method preferably has a CAAC structure. The ALD method has better coverage than the sputtering method. The use of the ALD method for the first and third layers can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0576] [Method for Manufacturing Oxide Semiconductor Layer] The oxide semiconductor layer 230 can be manufactured by, for example, forming an oxide semiconductor 230a over a layer 229 that is a surface to be formed by an ALD method, forming an oxide semiconductor 230b on the oxide semiconductor 230a by a sputtering method, and forming an oxide semiconductor 230c on the oxide semiconductor 230b by an ALD method. After the oxide semiconductor layer 230 is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer 230. The heat treatment here is not limited to heat treatment. For example, heat applied during the manufacturing process may be used. The layer 229 is an insulating film, such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film.

[0577] The oxide semiconductor layer 230 can be used as the oxide semiconductor layer 230 included in each transistor described in Embodiment 1. The layer 229 corresponds to one or more of the conductive layer 220, the insulating layer 235, the conductive layer 240, and the like described in Embodiment 1. That is, in Embodiment 1, the surface on which the oxide semiconductor layer 230 is to be formed refers to the side surface of the insulating layer 235 in the opening 290.

[0578] The layer 229 does not need to be crystalline. When the layer 229 is crystalline, it may have a crystal structure with low lattice matching with a metal oxide contained in the oxide semiconductor layer 230.

[0579] An example of a method for manufacturing the oxide semiconductor layer 230 will be described with reference to FIGS. 36A to 37D.

[0580] First, an oxide semiconductor 230a is formed on the layer 229 (FIG. 36A). Subsequently, an oxide semiconductor 230b is formed on the oxide semiconductor 230a (FIG. 36B).

[0581] The oxide semiconductor 230b is preferably formed by a sputtering method and has a composition suitable for forming a CAAC structure.

[0582] The oxide semiconductor 230a is preferably formed by a deposition method that causes less damage to a surface on which the oxide semiconductor 230a is formed than the deposition method for the oxide semiconductor 230b. Here, the oxide semiconductor 230a is formed by an ALD method.

[0583] When a metal oxide film is formed by sputtering, damage to the surface on which the film is to be formed may cause alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed.

[0584] In a method for forming an oxide semiconductor layer according to one embodiment of the present invention, the oxide semiconductor 230a is formed over the layer 229, and then the oxide semiconductor 230b is formed by a sputtering method. The oxide semiconductor 230a is preferably formed by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is to be formed. By forming the oxide semiconductor 230a between the oxide semiconductor 230b and the layer 229 by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is to be formed, alloying of components contained in the oxide semiconductor layer 230 and components contained in the layer 229 can be suppressed, and the crystallinity of the oxide semiconductor layer 230 can be further improved.

[0585] By using the above structure, the thickness of the alloyed region can be reduced, or made so thin that the alloyed region is not observable. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figures 36A and 36B show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor 230a.

[0586] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0587] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 230a being the depth direction. Next, in the profile of quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 230a contains In) that is the main component of the oxide semiconductor 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 230a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0588] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0589] For example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the oxide semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0×10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0590] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0591] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor layer 230 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably between more than 0 nm and 2 nm, more preferably between 1 nm and 2 nm.

[0592] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of the oxide semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0593] When the oxide semiconductor 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 36A , the oxide semiconductor 230a may have a region having lower crystallinity than the oxide semiconductor 230b.

[0594] After the oxide semiconductor 230a is formed, microwave plasma treatment is preferably performed.

[0595] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0596] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor layer 230 can be reduced. Examples of impurities include hydrogen and carbon. Although the above example illustrates a structure in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0597] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0598] When performing microwave plasma treatment, the substrate may be heated to a temperature of at least room temperature (e.g., 25°C), at least 100°C, at least 200°C, at least 300°C, or at least 400°C, and at most 500°C or at most 450°C.

[0599] Alternatively, after the microwave plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The heat treatment temperature is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0600] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. By performing the microwave plasma treatment in an atmosphere containing oxygen, the oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by the oxygen gas plasma can act on the oxide semiconductor layer. The V in the oxide semiconductor layer can be formed by the action of the plasma, microwaves, oxygen radicals, and the like. Ｏ By splitting H into oxygen vacancies and hydrogen, it is possible to remove hydrogen as an impurity from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0601] Furthermore, microwave plasma treatment can improve the crystallinity of the oxide semiconductor 230a. Here, the principle of how microwave plasma treatment improves the crystallinity of an oxide semiconductor will be described. First, activated species such as oxygen radicals excited by microwaves arrive at the surface of the oxide semiconductor, and a substitution reaction occurs between the activated species and oxygen in the oxide semiconductor. At this time, nuclei or seeds are formed. Furthermore, lateral growth of the nuclei or seeds is induced. Note that it is preferable that the activated species excited by microwaves contain oxygen (typically, oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this lateral growth is promoted. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, thereby improving the crystallinity of the oxide semiconductor.

[0602] On the other hand, a reaction occurs between part of the oxygen in the oxide semiconductor that exists before the microwave plasma treatment and hydrogen in the oxide semiconductor. In other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２ The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0603] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0604] The increased crystallinity of the oxide semiconductor 230a can further increase the crystallinity of the oxide semiconductor 230b formed over the oxide semiconductor 230a, thereby increasing the crystallinity of the entire oxide semiconductor layer.

[0605] Oxygen supplied to the oxide semiconductor layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions having an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer may be in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0606] After the oxide semiconductor 230a is formed by an ALD method, an In-M-Zn oxide is formed as the oxide semiconductor 230b over the oxide semiconductor 230a by a sputtering method.

[0607] Here, when the oxide semiconductor 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, when the oxide semiconductor 230b is formed, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, causing at least a part of the oxide semiconductor 230a to crystallize.

[0608] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0609] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0610] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0611] In the formation of the oxide semiconductor 230b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, a metal oxide with high crystallinity can be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide. In the formation of the oxide semiconductor 230b by a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0612] As a result, as shown in FIG. 36B, an oxide semiconductor 230a can be formed over the layer 229 and an oxide semiconductor 230b can be formed over the oxide semiconductor 230a.

[0613] Next, the oxide semiconductor 230c is formed on the oxide semiconductor 230b (FIG. 36C). Here, the oxide semiconductor 230c is formed by an ALD method. For the formation of the oxide semiconducto...

Claims

an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer overlies the first conductive layer; the second conductive layer is located on the first insulating layer; the first conductive layer has a first recess; the first insulating layer and the second conductive layer have a first opening at a position overlapping the first recess; the second insulating layer contacts at least a side surface of the first insulating layer in the first opening; the oxide semiconductor layer is in contact with an upper surface of the second conductive layer and a bottom surface and a side surface of the first recess, and is in contact with the second insulating layer within the first opening; the third insulating layer is located inside the oxide semiconductor layer within the first opening, the third conductive layer is located inside the third insulating layer within the first opening; the first insulating layer has a barrier property against hydrogen; The second insulating layer has a function of capturing or fixing hydrogen. 　 In claim 1, the first insulating layer comprises silicon and nitrogen; The second insulating layer comprises one or both of hafnium and aluminum, and oxygen. 　 In claim 1, the second insulating layer has a first layer in contact with the first insulating layer and a second layer located between the first layer and the oxide semiconductor layer; The first layer has a function of capturing or fixing hydrogen, The second layer has a region containing excess oxygen. 　 In claim 3, the first insulating layer comprises silicon and nitrogen; the first layer comprises hafnium and / or aluminum, and oxygen; The second layer comprises one or both of silicon and aluminum, and oxygen. 　 In any one of claims 1 to 4, A fourth insulating layer is provided. the third insulating layer covers an upper surface and a side surface of the oxide semiconductor layer on the first insulating layer; the fourth insulating layer is located on the third insulating layer and has a second opening at a position overlapping the first opening; the third conductive layer has a portion facing the oxide semiconductor layer in the first opening with the third insulating layer interposed therebetween, and a portion located in the second opening. 　 In claim 5, The semiconductor device, wherein the second opening has a width smaller than a width of the first opening. 　 In any one of claims 1 to 4, the first conductive layer has a fourth conductive layer and a fifth conductive layer on the fourth conductive layer; the fifth conductive layer has a second recess; the first opening overlaps with the second recess; The second insulating layer contacts a bottom surface and a side surface of the second recess. 　 In any one of claims 1 to 4, the oxide semiconductor layer contains indium, A semiconductor device, wherein, in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots are confirmed that are arranged in layers in a direction parallel to a side surface of the first insulating layer in the first opening. 　 In any one of claims 1 to 4, the oxide semiconductor layer contains indium, the oxide semiconductor layer has a first region, a second region in contact with the first region, and a third region in contact with the second region; a first region, a second region, and a third region, and a second region are each formed on the oxide semiconductor layer by a first insulating layer, the first region being parallel to the side surface of the first insulating layer in the first opening. 　 In claim 9, a content of indium in the first region is higher than a content of indium in the second region; A semiconductor device, wherein the third region has a higher indium content than the second region.

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