Semiconductor device

Abstract

Provided is a semiconductor device having a small footprint. This semiconductor device has a first transistor, a second transistor, and a first insulating layer. The first transistor has a first electroconductive layer, a first metal oxide layer, a gate insulating layer, and a first gate electrode. The second transistor has a second electroconductive layer, a third electroconductive layer, a second metal oxide layer, a gate insulating layer, and a second gate electrode. The first insulating layer is positioned on the first electroconductive layer and the second electroconductive layer and has a first opening reaching the first electroconductive layer. The first insulating layer and the third electroconductive layer have a second opening reaching the second electroconductive layer. The first metal oxide layer has a first region in contact with the upper surface of the first electroconductive layer, a second region in contact with the side surface of the first insulating layer, and a third region in contact with the upper surface of the first insulating layer. The third region is in contact with the second region. The second metal oxide layer is in contact with the upper surface of the second electroconductive layer, the side surface of the first insulating layer, and the side surface of the third electroconductive layer.

Description

Semiconductor Devices

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced by reducing the area occupied by a transistor, and resolution can be increased. Therefore, miniaturized transistors are in demand.

[0005] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0006] 2. Description of the Related Art As display devices, for example, light-emitting devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] International Publication No. 2016 / 038508

[0009] An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with a small size. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a transistor with a small occupation area. Another object is to provide a semiconductor device including a transistor with high saturation. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a first metal oxide layer, a gate insulating layer, and a first gate electrode. The second transistor includes a second conductive layer, a third conductive layer, a second metal oxide layer, a gate insulating layer, and a second gate electrode. The first insulating layer is located over the first conductive layer and the second conductive layer. The third conductive layer has a region overlapping with the second conductive layer via the first insulating layer. The first insulating layer has a first opening reaching the first conductive layer. The first insulating layer and the third conductive layer have second openings reaching the second conductive layer. The first metal oxide layer has a first region in contact with the top surface of the first conductive layer at the first opening, a second region in contact with a side surface of the first insulating layer at the first opening, and a third region in contact with the top surface of the first insulating layer. The third region is in contact with the second region. The second metal oxide layer has a region in contact with the top surface of the second conductive layer at the second opening, a region in contact with a side surface of the first insulating layer at the second opening, and a region in contact with a side surface of the third conductive layer at the second opening. The gate insulating layer is located on the first metal oxide layer and the second metal oxide layer and is in contact with the first metal oxide layer and the second metal oxide layer. The first gate electrode has a region overlapping the first metal oxide layer via the gate insulating layer at the first opening. The second gate electrode has a region overlapping the second metal oxide layer via the gate insulating layer at the second opening.

[0012] In the semiconductor device described above, the first insulating layer preferably includes a second insulating layer and a third insulating layer on the second insulating layer. The second insulating layer preferably includes silicon and oxygen. The third insulating layer preferably includes silicon, nitrogen, and hydrogen.

[0013] In the semiconductor device described above, the first insulating layer preferably has a fourth insulating layer between the second insulating layer and the third insulating layer. The fourth insulating layer preferably contains silicon and nitrogen. The third insulating layer preferably has a region having a higher hydrogen concentration than the fourth insulating layer.

[0014] In the semiconductor device described above, the first insulating layer preferably has a fourth insulating layer between the second insulating layer and the third insulating layer. The fourth insulating layer preferably contains one or both of aluminum and hafnium, and oxygen. The third insulating layer preferably has a region having a higher hydrogen concentration than the fourth insulating layer.

[0015] In the semiconductor device described above, the first insulating layer preferably includes a fifth insulating layer between the first conductive layer, the second conductive layer, and the second insulating layer, and the fifth insulating layer preferably includes silicon and nitrogen.

[0016] In the semiconductor device described above, the first insulating layer preferably includes a sixth insulating layer between the first conductive layer, the second conductive layer, and the fifth insulating layer, and the sixth insulating layer preferably includes silicon, nitrogen, and hydrogen.

[0017] The semiconductor device preferably includes a sixth insulating layer. The sixth insulating layer preferably has a region in contact with a lower surface of the first conductive layer, a lower surface of the second conductive layer, and a lower surface of the first insulating layer. The sixth insulating layer preferably includes silicon, nitrogen, and hydrogen.

[0018] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a transistor with a small occupancy area can be provided. Alternatively, a semiconductor device including a transistor with high saturation property can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupancy area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0019] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0020] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A to 2D are perspective views showing an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing an example of a semiconductor device. FIG. 4A is a top view showing an example of a semiconductor device. FIGS. 4B and 4C are cross-sectional views showing an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views showing an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of a semiconductor device. FIG. 7 is a cross-sectional view showing an example of a semiconductor device. FIGS. 8A to 8C are cross-sectional views showing an example of a semiconductor device. FIGS. 9A to 9C are cross-sectional views showing an example of a semiconductor device. FIGS. 10A to 10C are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing an example of a semiconductor device. FIG. 13A is a top view showing an example of a semiconductor device. FIGS. 13B and 13C are cross-sectional views showing an example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a semiconductor device. 15A to 15G are cross-sectional views showing an example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing an example of a semiconductor device. FIGS. 17A to 17E are circuit diagrams showing an example of a semiconductor device. FIG. 18A is a top view showing an example of a semiconductor device. FIG. 18B is a cross-sectional view showing an example of a semiconductor device. FIG. 19A is a top view showing an example of a semiconductor device. FIG. 19B is a cross-sectional view showing an example of a semiconductor device. FIG. 20A is a top view showing an example of a semiconductor device. FIG. 20B is a cross-sectional view showing an example of a semiconductor device. FIG. 21A is a top view showing an example of a semiconductor device. FIGS. 21B and 21C are cross-sectional views showing an example of a semiconductor device. FIG. 22A is a top view showing an example of a semiconductor device. FIG. 22B is a cross-sectional view showing an example of a semiconductor device. FIGS. 23A to 23E are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 24A to 24D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 25A to 25D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 26A is a perspective view showing an example of a display device. FIG. 26B is a block diagram showing an example of a display device.27A to 27D are circuit diagrams of pixel circuits. FIGS. 28A to 28C are circuit diagrams of pixel circuits. FIGS. 29A and 29B are cross-sectional views showing an example of a display device. FIG. 30 is a cross-sectional view showing an example of a display device. FIGS. 31A to 31C are cross-sectional views showing an example of a display device. FIGS. 32A and 32B are cross-sectional views showing an example of a display device. FIG. 33 is a cross-sectional view showing an example of a display device. FIG. 34 is a cross-sectional view showing an example of a display device. FIG. 35 is a cross-sectional view showing an example of a display device. FIG. 36 is a cross-sectional view showing an example of a display device. FIGS. 37A to 37F are cross-sectional views showing an example of a method for manufacturing a display device. FIGS. 38A to 38D are views showing an example of an electronic device. FIGS. 39A to 39F are views showing an example of an electronic device. FIGS. 40A to 40G are views showing an example of an electronic device.

[0021] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0022] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0023] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0024] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0025] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0026] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0027] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

[0028] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0029] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0030] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the gate-source voltage (also referred to as Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the gate-source voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0031] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0032] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0033] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top surface view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0034] In this specification, the phrase "top surface shapes are approximately the same" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the phrase "top surface shapes are approximately the same" may also be used. Furthermore, when the top surface shapes are the same or approximately the same, it can also be said that the edges are aligned or approximately aligned.

[0035] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0036] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0037] In this specification and the like, a structure in which light-emitting layers are separately formed for light-emitting elements (also called light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure.

[0038] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0039] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0040] In this specification, the sacrificial layer is located above at least the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that constitute the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0041] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0042] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 20B. FIG.

[0043] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer.

[0044] The first transistor includes a first conductive layer, a first metal oxide layer, a gate insulating layer, and a first gate electrode. In the first transistor, the first conductive layer functions as one of a source electrode and a drain electrode. The first metal oxide layer has a region that functions as the other of the source electrode and the drain electrode of the first transistor and also has a channel formation region.

[0045] The second transistor includes a second conductive layer, a third conductive layer, a second metal oxide layer, a gate insulating layer, and a second gate electrode. In the second transistor, the second conductive layer functions as one of a source electrode and a drain electrode, and the third conductive layer functions as the other of the source electrode and drain electrode. The second metal oxide layer includes a channel formation region of the second transistor.

[0046] The first insulating layer is located on the first conductive layer and the second conductive layer. The third conductive layer has a region overlapping the second conductive layer through the first insulating layer. The first insulating layer has a first opening reaching the first conductive layer. The first insulating layer and the third conductive layer have second openings reaching the second conductive layer.

[0047] The first metal oxide layer has a first region in contact with the top surface of the first conductive layer at the first opening, a second region in contact with the side surface of the first insulating layer at the first opening, and a third region in contact with the top surface of the first insulating layer. The third region is in contact with the second region.

[0048] The second metal oxide layer has a region in contact with the top surface of the second conductive layer in the second opening, a region in contact with the side surface of the first insulating layer in the second opening, and a region in contact with the side surface of the third conductive layer in the second opening.

[0049] The gate insulating layer is located on the first metal oxide layer and the second metal oxide layer and is in contact with the first metal oxide layer and the second metal oxide layer. The first gate electrode has a region that overlaps with the first metal oxide layer through the gate insulating layer in the first opening. The second gate electrode has a region that overlaps with the second metal oxide layer through the gate insulating layer in the second opening.

[0050] The channel lengths of the first transistor and the second transistor can be controlled by the thickness of an insulating layer sandwiched between the source electrode and the drain electrode. In other words, the channel lengths of the first transistor and the second transistor are not affected by the exposure performance of the exposure equipment used for fabrication. Therefore, the channel lengths of the first transistor and the second transistor can be made shorter than the minimum dimension that the exposure equipment can expose (hereinafter also referred to as the minimum dimension). By shortening the channel length, the transistor can have a large on-state current. Furthermore, since the source electrode, the layer having the channel formation region, and the drain electrode can be provided in an overlapping manner, the area occupied by the semiconductor device can be significantly reduced.

[0051] The first insulating layer preferably has a stacked structure. Furthermore, the top layer of the first insulating layer preferably emits impurities that reduce the electrical resistance of the first metal oxide layer. The first metal oxide layer has a region in contact with the top layer of the first insulating layer, and this region functions as the other of the source electrode and drain electrode of the first transistor. Because the first metal oxide layer has a region that functions as the other of the source electrode and drain electrode, there is no need to separately provide a conductive layer that functions as the other of the source electrode and drain electrode. Therefore, the area occupied by the first transistor can be reduced.

[0052] Depending on the material used for the first metal oxide layer, the electrical resistance of the third conductive layer functioning as the other of the source electrode and drain electrode of the second transistor may be lower than the electrical resistance of the region functioning as the other of the source electrode and drain electrode of the first transistor. When the other of the source electrode and drain electrode functions as a wiring and the wiring resistance required for the wiring is relatively low, the second transistor can be preferably used.

[0053] A more specific example will be described below with reference to the drawings.

[0054] <Configuration Example 1> [Configuration Example 1-1] A semiconductor device according to one embodiment of the present invention will be described. FIG. 1A shows a top view (also referred to as a plan view) of a semiconductor device 10. FIG. 1B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 1C shows cross-sectional views of cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4. Note that FIG. 1A omits some of the components of the semiconductor device 10 (such as a gate insulating layer). As with FIG. 1A , some of the components are also omitted from the top views of the semiconductor device in the following drawings.

[0055] The semiconductor device 10 includes a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 10 is provided on an insulating surface. FIGS. 1B and 1C show a configuration in which the semiconductor device 10 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 10 may be provided on the insulating film. The transistor 100 and the transistor 200 have different structures and can be formed on the same substrate using some common processes.

[0056] 2A and 2B are perspective views of the transistor 100. FIG. 2B shows a cross section taken along dashed-dotted line C1-C2 in FIG. 2A. FIGS. 2C and 2D are perspective views of the transistor 200. FIG. 2D shows a cross section taken along dashed-dotted line C3-C4 in FIG. 2C. In FIGS. 2A to 2D, the insulating layers 110 and 106 are shown in a transparent manner, with their outlines indicated by dashed lines. FIG. 3A shows an enlarged view of the transistor 100 shown in FIG. 1B, and FIG. 3B shows an enlarged view of the transistor 200.

[0057] The transistor 100 includes a conductive layer 104, an insulating layer 106, a layer 108, and a conductive layer 112. In the transistor 100, the conductive layer 104 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. In the transistor 100, the conductive layer 112 functions as one of a source electrode and a drain electrode. The layer 108 includes a semiconductor material. The layer 108 includes a channel formation region and a region functioning as the other of the source electrode and the drain electrode.

[0058] The transistor 200 includes a conductive layer 204, an insulating layer 106, a layer 208, a conductive layer 212a, and a conductive layer 212b. In the transistor 200, the conductive layer 204 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. In the transistor 200, the conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other of the source electrode and drain electrode. The layer 208 includes a semiconductor material.

[0059] The conductive layer 112 and the conductive layer 212a are provided over the substrate 102, the insulating layer 110 is provided over the conductive layer 112 and the conductive layer 212a, and the conductive layer 212b is provided over the insulating layer 110. The insulating layer 110 has a region in contact with the top surface and side surfaces of the conductive layer 112, the top surface and side surfaces of the conductive layer 212a, and the top surface of the substrate 102. The conductive layer 212b has a region in contact with the top surface of the insulating layer 110. The conductive layer 212b has a region that overlaps with the conductive layer 212a with the insulating layer 110 interposed therebetween. It can also be said that the insulating layer 110 has a region sandwiched between the conductive layer 212a and the conductive layer 212b. The conductive layer 212a can be formed in the same process as the conductive layer 112. For example, the conductive layer 112 and the conductive layer 212a can be formed by forming a film that will become the conductive layer 112 and the conductive layer 212a and then processing the film. Alternatively, the conductive layer 212a can be formed in a different process from that of the conductive layer 112. By forming the conductive layer 212a and the conductive layer 112 in different processes, different materials can be used for the conductive layer 212a and the conductive layer 112, thereby widening the range of material selection.

[0060] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0061] The insulating layer 110 has an opening 141 that reaches the conductive layer 112 and an opening 241 that reaches the conductive layer 212a. It can be said that the conductive layer 112 is exposed in the opening 141, and the conductive layer 212a is exposed in the opening 241. The opening 241 can be formed in the same process as the opening 141. For example, the insulating layer 110 having the openings 141 and 241 can be formed by forming a film that will become the insulating layer 110 over the conductive layer 112 and the conductive layer 212a and processing the film. Alternatively, the opening 241 can be formed in a process different from that for the opening 141.

[0062] The conductive layer 212b has an opening 243 in a region overlapping with the conductive layer 212a. The opening 243 is provided in a region overlapping with the opening 241. Note that in FIG. 1B and the like, the opening 241 in the insulating layer 110 and the opening 243 in the conductive layer 212b are denoted by different reference numerals, but these openings can be collectively referred to as one opening. In other words, the insulating layer 110 and the conductive layer 212b can be said to have openings that reach the conductive layer 212a.

[0063] The layer 108 is provided so as to cover the opening 141. The layer 108 is provided along the opening 141. The layer 108 has a region in contact with the top surface of the conductive layer 112 in the opening 141, a region in contact with the side surface of the insulating layer 110 in the opening 141, and a region in contact with the top surface of the insulating layer 110. The layer 108 has a shape that follows the shapes of the top surface and side surface of the insulating layer 110 and the top surface of the conductive layer 112.

[0064] The layer 108 has a first region in contact with the conductive layer 112 at the opening 141, a second region in contact with the side surface of the insulating layer 110 at the opening 141, and a third region in contact with the top surface of the insulating layer 110. The third region is in contact with the second region. The second region is in contact with the first region. It can also be said that the third region is continuous with the second region, and the second region is continuous with the first region. Alternatively, it can be said that the third region is continuous with the second region, and the second region is continuous with the first region. The insulating layer 110 preferably has a stacked structure. The top layer of the insulating layer 110 is preferably made of a material that releases impurities that reduce the electrical resistance of the layer 108. As a result, the third region in contact with the top layer of the insulating layer 110 is conductive and functions as the other of the source and drain electrodes of the transistor 100. The first region in contact with the conductive layer 112 which functions as one of a source electrode and a drain electrode of the transistor 100 functions as one of a source region and a drain region.

[0065] The layer 208 is provided so as to cover the openings 241 and 243. The layer 208 is provided along the openings 241 and 243. The layer 208 has a region in contact with the top surface of the conductive layer 212a in the opening 241, a region in contact with the side surface of the insulating layer 110 in the opening 241, and a region in contact with the side surface of the conductive layer 212b in the opening 243. Furthermore, the layer 208 preferably has a region in contact with the top surface of the conductive layer 212b. The layer 208 has a shape that follows the shapes of the top surface and side surface of the conductive layer 212b, the side surface of the insulating layer 110, and the top surface of the conductive layer 212a.

[0066] A region of the layer 208 in contact with the conductive layer 212a functions as one of the source and drain regions of the transistor 200, and a region of the layer 208 in contact with the conductive layer 212b functions as the other of the source and drain regions. Part of a region of the layer 208 in contact with the insulating layer 110 may also function as a source or drain region.

[0067] When the layer 208 is in contact with not only the side surface but also the top surface of the conductive layer 212b, the contact area between the layer 208 and the conductive layer 212b is increased, and the contact resistance between the layer 208 and the conductive layer 212b can be reduced. This can increase the on-state current of the transistor 200. Note that although FIG. 1B and other drawings illustrate a structure in which an end of the layer 208 is in contact with the top surface of the conductive layer 212b, one embodiment of the present invention is not limited to this structure. The end of the layer 208 can be aligned or approximately aligned with an end of the conductive layer 212b on the side that does not face the opening 243. Alternatively, the layer 208 can cover the end of the conductive layer 212b on the side that does not face the opening 243, and the end of the layer 208 can be in contact with the top surface of the insulating layer 110. Note that the layer 208 can also be in contact with only the side surface of the conductive layer 212b on the opening 243 side, without being in contact with the top surface of the conductive layer 212b.

[0068] The layer 208 can be formed in the same process as the layer 108. For example, the layers 108 and 208 can be formed by forming films that will become the layers 108 and 208 and processing the films. Note that the layers 108 and 208 can also be formed in different processes. By forming the layers 108 and 208 in different processes, different materials can be used for the layers 108 and 208, thereby widening the range of material options.

[0069] As shown in FIG. 1A and other figures, the top shapes of the openings 241 and 243 can be identical or approximately identical to each other. In this case, as shown in FIGS. 1B and 1C and other figures, it is preferable that the lower surface edge of the conductive layer 212b on the opening 243 side be identical or approximately identical to the upper surface edge of the insulating layer 110 on the opening 241 side. The lower surface of the conductive layer 212b refers to the surface on the insulating layer 110 side. The upper surface of the insulating layer 110 refers to the surface on the conductive layer 212b side. The top shapes of the openings 241 and 243 may also be configured to differ from each other. When the top shape of the opening 243 does not match the top shape of the opening 241, it is preferable that the opening 243 encompasses the opening 241 in a top view. By having the top shape of the opening 243 match the top shape of the opening 241 or having the opening 243 encompass the opening 241 in a top view, the coverage of the layer 208 can be improved.

[0070] In this specification and the like, the top surface shape of opening 141 refers to the shape of the top surface end portion on the opening 141 side of insulating layer 110. The top surface shape of opening 241 refers to the shape of the top surface end portion on the opening 241 side of insulating layer 110. The top surface shape of opening 243 refers to the shape of the bottom surface end portion on the opening 243 side of conductive layer 212b.

[0071] An insulating layer 106 is provided over the layer 108, the layer 208, the conductive layer 212b, and the insulating layer 110. The insulating layer 106 has a region in contact with the top surface and side surfaces of the layer 108, the layer 208, the conductive layer 212b, and the top surface of the insulating layer 110. Part of the insulating layer 106 functions as a gate insulating layer for the transistor 100, and the other part functions as a gate insulating layer for the transistor 200. The insulating layer 106 is provided to cover the openings 141, 241, and 243, and has a shape following the shapes of the top surface and side surfaces of the layer 108, the layer 208, the conductive layer 212b, and the top surface of the insulating layer 110.

[0072] The conductive layer 104 and the conductive layer 204 are provided over the insulating layer 106. The conductive layer 104 and the conductive layer 204 each have a region in contact with the insulating layer 106 and have shapes that follow the shapes of the top surface and side surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the layer 108 in the opening 141 with the insulating layer 106 interposed therebetween. It can also be said that the conductive layer 104 has a region that faces the layer 108 in the opening 141 with the insulating layer 106 interposed therebetween. The conductive layer 204 has a region that overlaps with the layer 208 in the opening 241 with the insulating layer 106 interposed therebetween. It can also be said that the conductive layer 204 has a region that faces the layer 208 in the opening 241 with the insulating layer 106 interposed therebetween. The conductive layer 104 is provided so as to cover the opening 141 and has a shape that follows the shapes of the top surface and side surface of the insulating layer 106 in the opening 141. The conductive layer 204 is provided to cover the openings 241 and 243, and has a shape that follows the shapes of the top surface and side surface of the insulating layer 106 in the openings 241 and 243. The conductive layer 204 can be formed in the same process as the conductive layer 104. For example, the conductive layer 104 and the conductive layer 204 can be formed by forming a film that will become the conductive layer 104 and the conductive layer 204 and processing the film. Note that the conductive layer 104 and the conductive layer 204 can also be formed in different processes. By forming the conductive layer 104 and the conductive layer 204 in different processes, different materials can be used for the conductive layer 104 and the conductive layer 204, thereby widening the range of material selection.

[0073] As described above, a region of the layer 108 in contact with the conductive layer 112 functions as one of the source and drain regions of the transistor 100, and a region of the layer 108 in contact with the top layer of the insulating layer 110 functions as the other of the source and drain electrodes of the transistor 100. A region of the layer 108 that overlaps with the conductive layer 104 between the region that functions as one of the source and drain regions and the region that functions as the other of the source and drain electrodes, with the insulating layer 106 interposed therebetween, functions as a channel formation region of the transistor 100. A region of the layer 208 in contact with the conductive layer 212a functions as one of the source and drain regions of the transistor 200, and a region of the layer 208 in contact with the conductive layer 212b functions as the other of the source and drain regions of the transistor 200. A region of the layer 208 that overlaps with the conductive layer 204 between the source and drain regions, with the insulating layer 106 interposed therebetween, functions as a channel formation region of the transistor 200.

[0074] In the transistor 100 and the transistor 200, the source electrode and the drain electrode are located at different heights relative to the surface of the substrate 102, which is the surface on which they are formed, and the drain current flows in a direction perpendicular or approximately perpendicular to the surface of the substrate 102. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction), and therefore the transistor 100 and the transistor 200 can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0075] The channel lengths of the transistors 100 and 200 can be controlled by the thickness of the insulating layer 110. Specifically, in the transistor 100, the channel length can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112 and the layer 108. In the transistor 200, the channel length can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 212a and the conductive layer 212b. Therefore, the transistors 100 and 200 having channel lengths shorter than the minimum exposure dimension of an exposure apparatus used to manufacture the transistors can be manufactured with high precision. Furthermore, the reduction in the characteristic variations of multiple transistors stabilizes the operation of the semiconductor device 10, thereby improving its reliability. Furthermore, the reduction in the characteristic variations of transistors increases the degree of freedom in circuit design, allowing the operating voltage of the semiconductor device 10 to be lowered. Therefore, the power consumption of the semiconductor device 10 can be reduced.

[0076] In the transistor 100 and the transistor 200, the source electrode, the layer having the channel formation region, and the drain electrode can be provided in an overlapping manner, and therefore the occupied area can be significantly reduced compared to a so-called planar transistor in which these are arranged in a plane. Therefore, a small-sized semiconductor device can be obtained.

[0077] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (for example, one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0078] An insulating layer 195 is provided to cover the transistor 100 and the transistor 200. The insulating layer 195 functions as a protective layer for the transistor 100 and the transistor 200. Note that the insulating layer 195 is omitted in the perspective views shown in FIGS.

[0079] The semiconductor material used for the layer 108 and the layer 208 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: oxide semiconductor). Note that these semiconductor materials may contain impurities as dopants.

[0080] The crystallinity of the semiconductor material used for the layer 108 and the layer 208 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. The use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0081] The layer 108 and the layer 208 can each be made of, for example, silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS). A transistor using amorphous silicon for its channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for its channel formation region has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for its channel formation region has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed. Note that a transistor using silicon for its channel formation region may be referred to as a Si transistor, and a transistor using LTPS for its channel formation region may be referred to as an LTPS transistor.

[0082] The layers 108 and 208 each preferably contain a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. When a metal oxide is used for the layers 108 and 208, the layers 108 and 208 can each be referred to as a metal oxide layer. The band gap of the metal oxide used for the layers 108 and 208 is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0083] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0084] The insulating layer 110 will now be described.

[0085] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0086] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0087] The insulating layer 110 has a region in contact with the layer 108 and a region in contact with the layer 208. When a metal oxide is used for the layer 108 and the layer 208, it is preferable that at least a part of the region of the insulating layer 110 in contact with the layer 108 and at least a part of the region of the insulating layer 110 in contact with the layer 208 contain oxygen in order to improve the interface characteristics between the layer 108 and the insulating layer 110 and between the layer 208 and the insulating layer 110. In particular, it is preferable that the portion of the insulating layer 110 in contact with the channel formation region of the layer 108 and the portion of the insulating layer 110 in contact with the channel formation region of the layer 208 contain oxygen. One or more of an oxide and an oxynitride can be suitably used in the portion in contact with the channel formation region of the insulating layer 110.

[0088] When a metal oxide is used for the layer 108 and the layer 208, it is preferable that at least a part of the region of the insulating layer 110 in contact with the layer 108 and at least a part of the region of the insulating layer 110 in contact with the layer 208 each release oxygen when heated. In particular, it is preferable that the part of the insulating layer 110 in contact with the channel formation region of the layer 108 and the part of the insulating layer 110 in contact with the channel formation region of the layer 208 each release oxygen when heated. As a result, oxygen is supplied from the insulating layer 110 to the layer 108 and the layer 208, and oxygen vacancies (V Ｏ : Oxygen Vacancy), and oxygen deficiency (V Ｏ ) into which hydrogen has entered (hereinafter referred to as V Ｏ H) can be reduced.

[0089] Here, V is added to the metal oxide. Ｏ As H increases, V ＯCarriers may be generated by H, increasing the carrier concentration. In particular, if the carrier concentration in the channel formation region is high, the threshold voltage of the transistor may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may increase. For example, in the case of an n-channel transistor, the threshold voltage may shift to the negative side, increasing the cutoff current. In addition, the reliability of the transistor may decrease. Oxygen vacancies (V Ｏ ) and V Ｏ By reducing H, it is possible to prevent the carrier concentration in the channel formation region from increasing. As a result, a shift in threshold voltage is prevented, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be obtained. In addition, a highly reliable transistor and semiconductor device can be obtained.

[0090] The insulating layer 110 preferably has a stacked structure. Figure 1B and other figures show an example in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110d on the insulating layer 110c. The insulating layers 110a, 110b, 110c, and 110d can each be made of the materials listed for the insulating layer 110.

[0091] 3A and 3B , the layer 108 has a region 108M in contact with the insulating layer 110b, and the layer 208 has a region 208M in contact with the insulating layer 110b. The region 108M functions as a channel formation region of the transistor 100, and the region 208M functions as a channel formation region of the transistor 200. It can also be said that the channel formation regions of the transistors 100 and 200 are provided along the side surfaces of the insulating layer 110. The conductive layer 104 has a portion that overlaps with the region 108M with the insulating layer 106 interposed therebetween, and the conductive layer 204 has a portion that overlaps with the region 208M with the insulating layer 106 interposed therebetween.

[0092] The insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. As a result, at least the region 108M in the layer 108 can function as a channel formation region of the transistor 100. Furthermore, at least the region 208M in the layer 208 can function as a channel formation region of the transistor 200. The insulating layer 110b preferably contains silicon and oxygen. For example, one or both of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 110b. Note that although two regions 108M are shown in cross-sectional views such as FIG. 3A , the regions 108M are connected to one another in top view. Similarly, although two regions 208M are shown in cross-sectional views such as FIG. 3B , the regions 208M are connected to one another in top view.

[0093] It is more preferable to use a material that releases oxygen when heat is applied to the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 10, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the layers 108 and 208. By supplying oxygen from the insulating layer 110b to the layers 108 and 208, particularly to the channel formation region, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, the transistor 100 and the transistor 200 can have favorable electrical characteristics and high reliability.

[0094] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by sputtering in an oxygen-containing atmosphere. Then, the film can be removed. Note that a method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 2.

[0095] The insulating layer 110b is preferably formed by a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, by forming the insulating layer 110b by a method that does not use a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) as a deposition gas, a film with an extremely low hydrogen content can be obtained. The sputtering method is particularly suitable for forming the insulating layer 110b. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100 and the transistor 200.

[0096] Here, by using a material with high conductivity for the layer 108 and the layer 208, the transistor 100 and the transistor 200 can have large on-state current. However, when a material with high conductivity is used, oxygen vacancies (V Ｏ ) is easily formed, and V Ｏ H may increase. Ｏ The increase in H may shift the threshold voltage of the transistor and increase the cutoff current. By providing the insulating layer 110b, oxygen is supplied to at least the region 108M and the region 208M, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. As a result, a shift in the threshold voltage can be suppressed, and the transistors 100 and 200 can have both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0097] As shown in Figure 3A, the layer 108 has a region 108P that contacts the top layer of the insulating layer 110 (here, the insulating layer 110d). The region 108P contacts at least the top surface and side surface of the insulating layer 110d. The region 108P functions as the other of the source electrode and drain electrode of the transistor 100. Note that although two regions 108P are shown in the cross-sectional views such as Figure 3A, the regions 108P are connected together in top view.

[0098] The insulating layer 110d in contact with the region 108P is preferably made of a material that releases impurities that increase the conductivity (or lower the electrical resistance) of the region 108P. When a metal oxide is used for the layer 108, the elements contained in the impurities (hereinafter also referred to as impurity elements) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. The impurity element is preferably one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon, with hydrogen being particularly preferred. For example, the insulating layer 110d is preferably made of a material that releases one or both of hydrogen and water. Note that in this specification and the like, hydrogen may be used as an example of the impurity.

[0099] The oxygen bonded to the metal atoms in the metal oxide reacts with hydrogen to form water, leaving oxygen vacancies (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ ) with hydrogen in it. Ｏ H functions as a donor, generating electrons as carriers. Furthermore, some of the hydrogen bonds with oxygen, which bonds with metal atoms, generating electrons as carriers. This allows the metal oxide to exhibit electrical conductivity and function as a conductor. A metal oxide that functions as a conductor can be called an oxide conductor (OC). Generally, metal oxides have a large band gap, allowing them to transmit visible light (or they can be said to be translucent to visible light). An oxide conductor is a metal oxide that has a donor level near the conduction band. Therefore, oxide conductors are less affected by absorption due to the donor level, and have the same level of translucency to visible light as metal oxides.

[0100] The impurities released from the insulating layer 110d diffuse into the region 108P, increasing the carrier concentration and conductivity of the region 108P. This allows the region 108P to function as a conductor, and the region 108P can function as the other of the source electrode and drain electrode in the transistor 100. The region 108P can be referred to as an oxide conductor (OC).

[0101] Since part of the layer 108 (here, the region 108P) functions as the other of the source electrode and the drain electrode, there is no need to separately provide a conductive layer that functions as the other of the source electrode and the drain electrode, and therefore the number of layers constituting the transistor 100 can be reduced.

[0102] When photolithography is used to fabricate a semiconductor device, each component of the semiconductor device is arranged according to a design rule. Examples of components formed using photolithography include the layers (here, the layer 108, the conductive layer 104, and the conductive layer 204) of the transistor 100 and the transistor 200. The openings 141, 241, and 243 are also arranged according to a design rule. When the semiconductor device has wiring formed using photolithography, the wiring is also arranged according to a design rule. Examples of design rules include the width of a layer (hereinafter also referred to as a line), the width of a wiring, and the spacing between layers in the same layer (hereinafter also referred to as a space), the spacing between a layer and a wiring, and the spacing between wirings. The size of the opening is also included in the design rule. Between different layers, the layers, openings, and wirings need to be arranged taking into account the alignment accuracy (hereinafter also referred to as alignment accuracy or overlay accuracy) of an exposure tool. Since the transistor 100 does not include a separate conductive layer that functions as the other of the source electrode and the drain electrode, there is no need to consider the space and overlay accuracy for the conductive layer. Therefore, the distance between the transistor 100 and an adjacent element (e.g., a transistor and a capacitor) or a wiring can be shortened, and the area occupied by the semiconductor device can be reduced. Note that the top surface shape of layers, openings, and wirings formed by photolithography, or the photoresist used to form them, may be referred to as a pattern.

[0103] The layer 208 is provided to cover the opening 241 in the insulating layer 110 and the opening 243 in the conductive layer 212b. Furthermore, as described above, the coverage of the layer 208 can be improved by having the top surface shape of the opening 243 match the top surface shape of the opening 241 or by having the opening 243 encompass the opening 241 in a top view. When forming the openings 241 and 243, it is preferable to use processing conditions such that the top surface shapes of these openings match or the opening 243 encompasses the opening 241. Meanwhile, the layer 108 is provided to cover the opening 141 in the insulating layer 110. Because the transistor 100 does not have a conductive layer corresponding to the conductive layer 212b, the difficulty of forming the opening 141 is lower than the difficulty of forming the openings 241 and 243. Therefore, even when the openings 141 and 241 are formed in the same process, the size of the opening 141 can be made smaller than that of the opening 241.

[0104] By reducing the number of layers constituting the transistor 100, unevenness caused by the transistor 100 can be reduced. Here, if the unevenness of the surface on which a layer is formed is large, defects such as discontinuities or voids due to reduced coverage of the layer, or etching residues when processing the layer, may occur. By reducing the unevenness caused by the transistor 100, defects (e.g., discontinuities, voids, and etching residues) in the formation of layers provided on the transistor 100 can be suppressed, and the manufacturing yield can be increased.

[0105] Compared with the layer 108 including the region 108P functioning as the other of the source and drain electrodes of the transistor 100 and the region 108M functioning as the channel formation region, the conductive layer 212b functioning as the other of the source and drain electrodes of the transistor 200 has a wider range of material options. Therefore, depending on the material used for the layer 108, the electrical resistance of the conductive layer 212b may be lower than that of the region 108P. When the other of the source and drain electrodes functions as a wiring, the wiring is long, and the wiring resistance required for the wiring is relatively low, the transistor 200 including the conductive layer 212b can be preferably used. By using the transistor 200, a semiconductor device that operates at high speed can be obtained. On the other hand, when the wiring is short and the wiring resistance required for the wiring is relatively high, the transistor 100 can be preferably used. By using the transistor 100, a semiconductor device with a small occupancy area can be obtained.

[0106] The layer 108 has a region in contact with the top surface and side surfaces of the insulating layer 110d. This increases the contact area between the layer 108 and the insulating layer 110d, increasing the amount of impurities supplied from the insulating layer 110d to the layer 108, and efficiently lowering the electrical resistance of the region 108P. This increases the on-current of the transistor 100.

[0107] The region 108P, the conductive layer 112, and the conductive layer 104 can each function as a wiring, and the transistor 100 can be provided in a region where these wirings overlap. Similarly, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each function as a wiring, and the transistor 200 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100, the transistor 200, and wirings, the area occupied by these can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained.

[0108] The electrical resistance of region 108P is preferably lower than the electrical resistance of region 108M. The sheet resistance (also referred to as surface resistivity or sheet resistivity) of region 108P is preferably 1000 Ω / □ (also written as Ω / sq) or less, more preferably 500 Ω / □ or less, even more preferably 300 Ω / □ or less, even more preferably 200 Ω / □ or less, and even more preferably 100 Ω / □ or less. Note that, since it is preferable that the electrical resistance of region 108P is low, there is no lower limit on the sheet resistance.

[0109] The region 108P contains an element (impurity element) contained in the impurities released from the insulating layer 110d. When a material that releases one or both of hydrogen and water from the insulating layer 110d is used, the region 108P contains hydrogen as an impurity element.

[0110] The region 108P functioning as the other of the source electrode and the drain electrode preferably has a portion having a higher impurity element concentration than the region 108M functioning as a channel formation region. For example, the region 108P preferably has a portion having a higher hydrogen concentration than the region 108M.

[0111] As described above, the insulating layer 110d in contact with the region 108P preferably contains impurities and uses a material that releases the impurities. The insulating layer 110d can use one or more of the above-mentioned oxides, oxynitrides, nitrides, and nitride oxides. The insulating layer 110d preferably contains nitrogen and uses one or more of the above-mentioned nitrides and nitride oxides. When hydrogen is used as the impurity, the insulating layer 110d preferably contains silicon, nitrogen, and hydrogen. For example, the insulating layer 110d can preferably use silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen.

[0112] The insulating layer 110d can be formed using a gas containing an impurity. When hydrogen is used as the impurity, the insulating layer 110d can be formed using a gas containing hydrogen elements. Examples of the gas containing hydrogen elements include silane (SiH ４ ), disilane (Si ２ H ６ ), trisilane (Si ３ H８ ), TEOS (Tetraethoxysilane, Si(OC ２ H ５ ) ４ ), hydrogen (H ２ ), and ammonia (NH ３ When a silicon nitride film is formed as the insulating layer 110d by using the PECVD method, silane (SiH ４ ), nitrogen (N ２ ) and ammonia (NH ３ ) can be used. At this time, the amount of hydrogen released from the insulating layer 110d can be adjusted by changing the ratio of the flow rate of ammonia gas to the total film formation gas (hereinafter also referred to as an ammonia flow rate ratio). For example, by increasing the ammonia flow rate ratio, the amount of hydrogen contained in the insulating layer 110d can be increased, and the amount of hydrogen released by heat applied to the insulating layer 110d can be increased.

[0113] The amount of impurities released from the insulating layer 110d can be adjusted by adjusting the thickness of the insulating layer 110d. Specifically, increasing the thickness of the insulating layer 110d increases the amount of impurities released from the insulating layer 110d, thereby reducing the electrical resistance of the region 108P. As shown in FIG. 4A , the thickness T110d of the insulating layer 110d can be defined as the shortest distance between the surface on which the insulating layer 110d is to be formed (here, the upper surface of the insulating layer 110c) and the upper surface of the insulating layer 110d in a cross-sectional view. The thickness T110d is preferably 10 nm to 500 nm, more preferably 20 nm to 400 nm, even more preferably 50 nm to 300 nm, even more preferably 70 nm to 200 nm, even more preferably 70 nm to 150 nm, and even more preferably 70 nm to 120 nm.

[0114] Here, impurities released from the insulating layer 110d may diffuse into the region 108M via the region 108P. If the impurities are hydrogen, the hydrogen released from the insulating layer 110d may diffuse into the region 108M via the region 108P. However, oxygen vacancies (V Ｏ) is reduced, so that even if hydrogen diffuses into the region 108M, V Ｏ In addition, the hydrogen diffused into the region 108M causes oxygen vacancies (V Ｏ ) and V Ｏ Even if H is generated, oxygen vacancies (V Ｏ ) and V Ｏ H is reduced. Therefore, at least the region 108M in the layer 108 functions as a channel formation region, and the transistor 100 exhibits favorable electrical characteristics and is highly reliable. Note that the diffusion coefficient of oxygen in the layer 108 is smaller than that of hydrogen, so the electrical resistance of the region 108P is unlikely to increase due to oxygen released from the insulating layer 110b. Therefore, the electrical resistance of the region 108P can be kept low.

[0115] However, if the thickness T110d is large and the amount of impurities diffusing from the insulating layer 110d to the region 108M via the region 108P becomes too large, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ On the other hand, if the thickness T110d is small, the amount of impurities diffused into the region 108P may be small, which may increase the electrical resistance of the region 108P. By setting the thickness T110d within the above range, the oxygen deficiency (V Ｏ ) and V Ｏ This can suppress an increase in H and reduce the electrical resistance of the region 108P.

[0116] The concentration of the impurity element in the insulating layer 110d is 1×10 ２１ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Preferably, it is equal to or less than 1×10 ２１ atoms / cm ３ 5x10 or more ２２ atoms / cm ３Preferably, it is less than 5×10 ２１ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ For example, the hydrogen concentration of the insulating layer 110d is preferably 1×10 ２１ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Preferably, it is equal to or less than 1×10 ２１ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ Preferably, it is less than 5×10 ２１ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ It is preferable that:

[0117] Note that the concentration of the impurity element may vary in the thickness direction of the layer (also referred to as having a concentration gradient). When analyzing the concentration of the impurity element in the thickness direction of the layer, it is preferable that the maximum value of the concentration in the layer be within the above-mentioned range.

[0118] If the concentration of the impurity element in the insulating layer 110d is high, the amount of impurities diffusing from the insulating layer 110d to the region 108M via the region 108P may become too large. By setting the concentration of the impurity element in the insulating layer 110d within the above range, the electrical resistance of the region 108P is reduced and oxygen deficiency (V Ｏ ) and V Ｏ The increase in H can be suppressed.

[0119] The insulating layer 110d has a region in contact with the conductive layer 212b. It is more preferable to use a material that releases impurities that lower the electrical resistance of the conductive layer 212b for the insulating layer 110d. For example, when a metal oxide is used for the conductive layer 212b, the electrical resistance of the conductive layer 212b can be lowered by using a material that releases hydrogen for the insulating layer 110d.

[0120] The concentrations of impurity elements in the layer 108, the layer 208, and the insulating layer 110 can be analyzed using, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS) or electron spectrometry for chemical analysis (ESCA). When using XPS analysis, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis. Note that in low-concentration regions, quantification may be difficult or the concentration may be below the detection limit.

[0121] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112 and the conductive layer 212a. The insulating layer 110c is provided between the insulating layer 110b and the insulating layer 110d. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., hydrogen and water). Furthermore, the insulating layer 110a and the insulating layer 110c preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layer 110a and the insulating layer 110c can also function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation regions of the layer 108 and the layer 208. Therefore, the transistor 100 and the transistor 200 can have excellent electrical characteristics and high reliability.

[0122] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0123] The insulating layer 110c functions as a barrier film, which can prevent impurities released from the insulating layer 110d from diffusing into the channel formation regions of the layer 108 and the layer 208 through the insulating layer 110c and the insulating layer 110b. Therefore, the transistor 100 and the transistor 200 can have favorable electrical characteristics and high reliability.

[0124] It is preferable that the insulating layer 110a and the insulating layer 110c are made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112 and the conductive layer 212a through the insulating layer 110a, and from diffusing to the region 108P and the conductive layer 212b through the insulating layer 110c and the insulating layer 110d. Here, when oxygen is supplied to the region 108P, oxygen vacancies (V Ｏ ) and V Ｏ The H may decrease, which may increase the electrical resistance of the region 108P. By providing the insulating layer 110c between the region 108P and the insulating layer 110b, oxygen diffusion into the region 108P is suppressed, and an increase in the electrical resistance of the region 108P may be suppressed. Furthermore, when oxygen is supplied to the conductive layer 112, the conductive layer 212a, and the conductive layer 212b, these may be oxidized, which may increase the electrical resistance. By providing the insulating layer 110a between the conductive layer 112 and the insulating layer 110b and the insulating layer 110c between the conductive layer 212b and the insulating layer 110b, oxygen diffusion into these conductive layers is suppressed, and an increase in the electrical resistance of these conductive layers may be suppressed. Therefore, the transistor 100 and the transistor 200 can have a large on-state current.

[0125] By sandwiching the insulating layer 110b between the insulating layer 110a and the insulating layer 110c, the oxygen contained in the insulating layer 110b is prevented from diffusing toward the insulating layer 110a and toward the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the region 108M and the region 208M, reducing the oxygen vacancy (V Ｏ ) and V ＯH can be reduced. Therefore, the transistor 100 and the transistor 200 can have favorable electrical characteristics and high reliability.

[0126] The insulating layer 110a and the insulating layer 110c, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layer 110a and the insulating layer 110c can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Note that the insulating layer 110a and the insulating layer 110c can be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can be made of different materials.

[0127] The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c each preferably contain a small amount of impurities. Furthermore, the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c each preferably release a small amount of impurities. In particular, it is preferable that the amount of impurities containing hydrogen elements (e.g., hydrogen and water) released is small. Furthermore, it is preferable that the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c each have as little impurities containing hydrogen elements as possible. This prevents oxygen deficiency (V Ｏ ) and V Ｏ The increase in H can be suppressed.

[0128] The insulating layer 110d preferably has a region having a higher concentration of impurity elements than the insulating layer 110c. For example, the insulating layer 110d preferably has a region having a higher concentration of hydrogen than the insulating layer 110c. The concentration of impurity elements in the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0129] The amount of released hydrogen can be adjusted by varying the deposition conditions between the insulating layer 110d and the insulating layer 110c. Specifically, the deposition conditions between the insulating layer 110d and the insulating layer 110c can be varied by varying one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode. For example, by making the deposition power density of the insulating layer 110d lower than the deposition power density of the insulating layer 110c, the hydrogen content in the insulating layer 110d can be made higher than the hydrogen content in the insulating layer 110c. This increases the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d.

[0130] The hydrogen content in the deposition gas used to form the insulating layer 110d is preferably higher than the hydrogen content in the deposition gas used to form the insulating layer 110c. When silicon nitride films or silicon nitride oxide films are formed as the insulating layer 110d and the insulating layer 110c by PECVD, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to form the insulating layer 110d (hereinafter also referred to as the ammonia flow ratio) is preferably higher than the ammonia flow rate of the deposition gas used to form the insulating layer 110c. By forming the insulating layer 110d under conditions with a high ammonia flow rate ratio, the hydrogen content in the insulating layer 110d can be increased. Furthermore, the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d can be increased. For example, the insulating layer 110d can be formed using ammonia gas, and the insulating layer 110c can be formed without using ammonia gas (the flow rate of ammonia gas can be said to be zero). In this case, the ammonia flow ratio of the deposition gas used to form insulating layer 110c can be said to be zero, and the ammonia flow ratio of the deposition gas used to form insulating layer 110d can be said to be higher than the ammonia flow ratio of the deposition gas used to form insulating layer 110c.

[0131] It is more preferable that the film density of the insulating layer 110c be higher than that of the insulating layer 110d. This can prevent impurities contained in the insulating layer 110d from diffusing into the channel formation regions of the layers 108 and 208 via the insulating layers 110c and 110b. The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a darker transmission electron (TE) image, whereas a low film density results in a lighter transmission electron (TE) image. Therefore, in a transmission electron (TE) image, the insulating layer 110c may appear darker than the insulating layer 110d. Even if the same material is used for the insulating layers 110d and 110c, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0132] By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b or the insulating film that will become the insulating layer 110b when the insulating layer 110c or the insulating film that will become the insulating layer 110c is formed. This allows the amount of oxygen supplied from the insulating layer 110b to the layer 108 and the layer 208 to be increased, and oxygen deficiency (V Ｏ ) and V Ｏ For example, an aluminum oxide film can be formed by sputtering using an aluminum target in an oxygen-containing atmosphere as the insulating layer 110c or the insulating film that will become the insulating layer 110c. This allows oxygen to be supplied to the insulating layer 110b or the insulating film that will become the insulating layer 110b while the aluminum oxide film is being formed.

[0133] The insulating layer 110b can also function as a barrier film. The above-described materials can be used as the barrier film. For example, silicon nitride can be suitably used as the insulating layer 110b. The insulating layer 110 can have a single-layer structure of a silicon nitride film. The insulating layer 110b functions as a barrier film, which can suppress diffusion of impurities into the channel formation regions of the layers 108 and 208, thereby enabling the transistors 100 and 200 to exhibit favorable electrical characteristics and high reliability. Note that depending on the material used for the insulating layer 110b, the amount of oxygen supplied from the insulating layer 110b to the layers 108 and 208 may be reduced. In this case, it is preferable that at least the portions of the insulating layer 106 in contact with the channel formation regions of the layers 108 and 208 contain oxygen. Furthermore, it is more preferable to use a material that releases oxygen when heat is applied to these portions. The insulating layer 106 releases oxygen due to heat applied during the manufacturing process of the semiconductor device 10, and oxygen can be supplied to the layers 108 and 208. By supplying oxygen from the insulating layer 106 to the layers 108 and 208, particularly to the channel formation region, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. For example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide can be suitably used for the portion of the insulating layer 106 in contact with the layer 108 and the portion in contact with the layer 208.

[0134] Note that although the insulating layer 110 has a four-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 preferably includes at least the insulating layer 110b and the insulating layer 110d. For example, the insulating layer 110a may not be provided. The insulating layer 110 may have a two-layer, three-layer, five or more-layer structure, or a single-layer structure.

[0135] 1B and other examples show that the layer 108, the insulating layer 106, and the conductive layer 104 cover the opening 141 in the transistor 100, and the layer 208, the insulating layer 106, and the conductive layer 204 cover the opening 241 and the opening 243 in the transistor 200, but one embodiment of the present invention is not limited to this. In the transistor 100, a step can be formed between the insulating layer 110 and the conductive layer 112, and the layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step. Similarly, in the transistor 200, a step can be formed between the insulating layer 110, the conductive layer 212b, and the conductive layer 212a, and the layer 208, the insulating layer 106, and the conductive layer 204 are provided along the step.

[0136] [Layer 108, Layer 208] Metal oxides that can be used for layer 108 and layer 208 will be specifically described. Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0137] The layer 108 and the layer 208 may be made of, for example, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide), or the like. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, examples of usable materials include indium tin oxide containing silicon (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0138] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0139] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0140] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0141] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0142] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, resulting in a normally-off transistor. Furthermore, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, resulting in improved reliability.

[0143] The electrical characteristics and reliability of the transistor 100 and the transistor 200 vary depending on the composition of the metal oxide used in the layer 108 and the layer 208. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0144] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0145] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0146] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0147] By using a material with a high indium content for the layers 108 and 208, the on-state current or the field-effect mobility of the transistors 100 and 200 can be increased. Furthermore, by containing the element M, oxygen vacancies (V Ｏ ) can be suppressed. The content of element M in the metal oxide of layer 108 and layer 208 is preferably 0.1% to 25% inclusive, more preferably 0.1% to 20% inclusive, even more preferably 0.1% to 10% inclusive, even more preferably 0.1% to 8% inclusive, even more preferably 0.1% to 6% inclusive, and even more preferably 0.1% to 4% inclusive. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide of In:M:Zn=40:1:10 or a metal oxide in the vicinity thereof. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides of In:Sn:Zn=40:1:10 or a metal oxide in the vicinity thereof can be preferably used. Alternatively, metal oxides of In:Al:Zn=40:1:10 or a metal oxide in the vicinity thereof can be preferably used.

[0148] Here, if a polycrystalline metal oxide is used for the layers 108 and 208, the crystal grain boundaries may become recombination centers, trapping carriers and reducing the on-state current of the transistor. Furthermore, if a polycrystalline metal oxide is used for the layers 108 and 208, the surface irregularities of the layers 108 and 208 may become large. This may increase the step on the surface where a layer (e.g., the insulating layer 106) formed on the layers 108 and 208 is formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily forms a polycrystalline structure is used for the layers 108 and 208, it is preferable to include an element that inhibits crystallization. This prevents the layers 108 and 208 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the layers 108 and 208 can be improved, preventing defects such as discontinuities or voids in the layer.

[0149] For example, compared with indium tin oxide (ITO), indium tin oxide containing silicon (ITSO) is less likely to form a polycrystalline structure and is therefore suitable for use in layers 108 and 208. When ITSO is used, the silicon content is preferably 1% to 20%, more preferably 3% to 20%, even more preferably 3% to 15%, and even more preferably 5% to 15%. As the atomic ratio of metal elements, for example, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide containing silicon (ITSO) is used for layers 108 and 208, it is preferable that ITSO have crystallinity. Note that layer 108 may have an amorphous region or may be amorphous.

[0150] A metal oxide that does not contain element M can be applied to layer 108 and layer 208. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions close to these can be mentioned. Furthermore, the atomic ratio of In is more preferably equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0151] The compositions of the layers 108 and 208 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks in the spectra obtained by the analysis and identify and quantify the elements. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.

[0152] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). Thermal ALD or PEALD can be used as the ALD. When forming a metal oxide by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may be reduced to about 50% of that of the sputtering target. Alternatively, the PECVD method can be used to form the metal oxide.

[0153] Crystalline metal oxide is preferably used for the layer 108 and the layer 208. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the layer 108 and the layer 208 can be reduced, and a highly reliable semiconductor device can be realized.

[0154] The layers 108 and 208 are preferably formed using a CAAC-OS or an nc-OS.

[0155] The CAAC-OS has multiple layered crystals. The c-axes of the crystals are aligned in the normal direction to the surface where the layer 108 and the layer 208 are formed. The layer 108 and the layer 208 preferably have layered crystals parallel or approximately parallel to the surface where the layer 108 is formed. For example, the layer 108 preferably has layered crystals parallel or approximately parallel to the top surface of the conductive layer 112 in a region in contact with the top surface of the conductive layer 112. In particular, the layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface where the layer 108 is formed, in the opening 141. With this structure, the layered crystals of the layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current. Similarly, the layered crystals of the layer 208 are formed parallel or approximately parallel to the channel length direction of the transistor 200, thereby enabling the transistor to have a large on-state current.

[0156] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0157] The higher the substrate temperature during metal oxide formation, the higher the crystallinity of the resulting metal oxide. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Furthermore, the higher the ratio of the flow rate of oxygen gas to the total flow rate of film formation gas (hereinafter also referred to as oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide.

[0158] The crystallinity of the layer 108 and the layer 208 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0159] When a metal oxide is used for the layers 108 and 208, the V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which impurities such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0160] When a metal oxide is used for the layer 108 and the layer 208, the carrier concentration of each of the regions 108M and 208M that function as channel formation regions is 1×10 １８ cm−３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0161] As described above, the region of the layer 108 in contact with the conductive layer 112 functions as one of the source and drain regions of the transistor 100, and the region 108P functions as the other of the source and drain electrodes. The region of the layer 208 in contact with the conductive layer 212a functions as one of the source and drain regions of the transistor 200, and the region in contact with the conductive layer 212b functions as the other of the source and drain regions. The region 108P, the source and drain regions, have lower electrical resistance than the channel formation region. The region 108P, the source and drain regions can also be said to have a higher carrier concentration and a higher oxygen defect density than the channel formation region.

[0162] At least one of the region of the layer 108 in contact with the insulating layer 110a and the region of the layer 108 in contact with the insulating layer 110c can be a region having lower electrical resistance than the channel formation region (hereinafter also referred to as a low-resistance region). This region can also be referred to as a region having a higher carrier concentration or a higher oxygen defect density than the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) for the insulating layer 110a, the region of the layer 108 in contact with the insulating layer 110a can be a low-resistance region. The layer 108 can have a low-resistance region between one of the source and drain regions and the region 108M that functions as a channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110c, the region of the layer 108 in contact with the insulating layer 110c can be a low-resistance region. The layer 108 can have a low-resistance region between the region 108P that functions as the other of the source and drain electrodes and the region 108M that functions as a channel formation region. The low-resistance region can function as a buffer region for alleviating the drain electric field. Note that the low-resistance region can also function as a source region or a drain region. The same applies to the layer 208.

[0163] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0164] The layer 108 and the layer 208 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0165] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0166] Each of the layers 108 and 208 can have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the layers 108 and 208 can be the same or substantially the same. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the compositions of the two or more metal oxide layers included in the layers 108 and 208 are the same or substantially the same, the boundary (interface) between these metal oxide layers may not be clearly identified.

[0167] When the layers 108 and 208 each have a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, the surface on which the second metal oxide layer is formed is the surface of the first metal oxide layer, and the crystallinity of the second metal oxide layer may be increased. Furthermore, by performing heat treatment after forming the second metal oxide layer, the crystallinity of the first metal oxide layer can be increased. This heat treatment can also be called a crystallization treatment.

[0168] A first metal oxide layer is formed, and then a second metal oxide layer having higher crystallinity than the first layer is formed. For example, ALD can be suitably used to form the first metal oxide layer, and sputtering can be suitably used to form the second metal oxide layer. By performing heat treatment after the formation of the second metal oxide layer, the crystallinity of the first metal oxide layer and the second metal oxide layer can be further increased. In this case, the crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer may not be clearly identified. It is particularly preferable that the second metal oxide layer has a CAAC structure. This allows the crystals having the CAAC structure of the second metal oxide layer to serve as nuclei or seeds to increase the crystallinity of the first metal oxide layer.

[0169] A three-layer structure having a third metal oxide layer on the second metal oxide layer can be formed. For example, the first metal oxide layer and the third metal oxide layer can be formed by an ALD method, and the second metal oxide layer can be formed by a sputtering method. Heat treatment after the formation of the third metal oxide layer can increase the crystallinity of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer. In this case, crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer and the third metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer and the boundary between the second metal oxide layer and the third metal oxide layer may not be clearly identified. When the second metal oxide layer has a CAAC structure, the crystals having the CAAC structure of the second metal oxide layer can be used as nuclei or seeds to increase the crystallinity of the first metal oxide layer and the third metal oxide layer.

[0170] By stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the metal oxide layer. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the metal oxide layer. This allows for the realization of a highly reliable transistor. The thickness direction refers to a direction perpendicular or approximately perpendicular to the surface on which the metal oxide layer is formed. A metal oxide layer with such increased crystallinity can be called an axial growth CAAC (AG CAAC). In addition to the crystal growth occurring in the thickness direction, crystal growth may also occur in a direction parallel or approximately parallel to the surface on which the metal oxide layer is formed.

[0171] The temperature of the heat treatment can be 100°C or higher and lower than the strain point of the substrate. The temperature of the heat treatment is preferably 100°C or higher and 800°C or lower, more preferably 250°C or higher and 650°C or lower, and even more preferably 350°C or higher and 550°C or lower. The heat treatment time is, for example, preferably 1 minute to 1 hour, more preferably 10 minutes to 30 minutes, at a temperature of 350°C to 550°C or lower. The heating device used for the heat treatment is not particularly limited, and a device that heats the workpiece by heat conduction or heat radiation from a heating element (e.g., a resistance heating element) can be used. For the heat treatment, for example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats a workpiece by radiating light (electromagnetic waves) emitted from a lamp (e.g., a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp). The GRTA apparatus is an apparatus that heats a workpiece by using a high-temperature gas.

[0172] [Insulating Layer 110] As described above, the insulating layer 110 preferably has a stacked structure. The insulating layer 110b has a function of supplying oxygen to the channel formation regions (here, the regions 108M and 208M) of the layer 108 and the layer 208. The insulating layers 110a and 110c function as barrier films. The insulating layer 110d has a function of supplying an impurity element to the region 108P.

[0173] If the thickness T110c of the insulating layer 110c is small, impurities contained in the insulating layer 110d may diffuse into the region 108M and the region 208M via the insulating layer 110c and the insulating layer 110b. If the thickness T110a and the thickness T110c of the insulating layer 110a are small, oxygen contained in the insulating layer 110b may diffuse toward the conductive layer 112 and the conductive layer 212a via the insulating layer 110a, and toward the region 108P and the conductive layer 212b via the insulating layer 110c. This may reduce the amount of oxygen supplied to the channel formation regions of the layers 108 and 208 and increase the electrical resistance of the region 108P, the conductive layer 112, the conductive layer 212a, and the conductive layer 212b. On the other hand, if the thickness T110a and the thickness T110c are large, the amount of impurities released from the insulating layer 110a and the insulating layer 110c may increase, resulting in an increase in the amount of impurities diffusing into the channel formation region. 4B , thickness T110a can be the shortest distance between the surface on which insulating layer 110a is to be formed (here, the upper surface of conductive layer 112 or conductive layer 212a) and the upper surface of insulating layer 110a in a cross-sectional view. Thickness T110c can be the shortest distance between the surface on which insulating layer 110c is to be formed (here, the upper surface of insulating layer 110b) and the upper surface of insulating layer 110c in a cross-sectional view.

[0174] The thickness T110c is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, even more preferably 3 nm or more and 50 nm or less, even more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 3 nm or more and 10 nm or less, and even more preferably 5 nm or more and 10 nm or less.

[0175] The thickness T110a can be greater than the thickness T110c of the insulating layer 110c. If the region of the layer 108 in contact with the insulating layer 110a functions as the source or drain region of the transistor 100, increasing the thickness T110a can make the distance from the source or drain region to the gate electrode more uniform. Similarly, if the region of the layer 208 in contact with the insulating layer 110a functions as the source or drain region of the transistor 200, increasing the thickness T110a can make the distance from the source or drain region to the gate electrode more uniform. This can make the electric field of the gate electrode applied to the channel formation region more uniform. The thickness T110a of the insulating layer 110a is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, even more preferably 10 nm or more and 300 nm or less, even more preferably 20 nm or more and 300 nm or less, even more preferably 50 nm or more and 300 nm or less, even more preferably 100 nm or more and 300 nm or less, even more preferably 100 nm or more and 250 nm or less, even more preferably 150 nm or more and 250 nm or less.

[0176] By setting the thickness T110c within the above range, it is possible to suppress the diffusion of impurities contained in the insulating layer 110d into the channel formation regions of the layers 108 and 208. By setting the thickness T110a and the thickness T110c within the above range, it is possible to increase the amount of oxygen supplied to the channel formation regions of the layers 108 and 208, thereby reducing oxygen deficiency (V Ｏ ) and V Ｏ The thickness T110a and the thickness T110c are not limited to the above ranges.

[0177] Note that impurities released from the insulating layer 110a may diffuse into the channel formation region via the insulating layer 110b or via one of the source region and drain region of the layer 108. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region via the insulating layer 110b or via the other of the source region and drain region of the layer 108. When the impurity is hydrogen, hydrogen released from the insulating layer 110a or the insulating layer 110c may diffuse into the channel formation region. However, since oxygen is supplied from the insulating layer 110b to at least the region of the layer 108 that is in contact with the insulating layer 110b, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. The same applies to the layer 208. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0178] However, if the amount of impurities released from the insulating layer 110a and the insulating layer 110c becomes too large, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. Even when a material that releases impurities is used for the insulating layer 110a and the insulating layer 110c, it is more preferable that the amount of released impurities is small.

[0179] One or more of the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, and the insulating layer 110d can have a stacked structure.

[0180] When the insulating layer 110c has a stacked structure, the layers constituting the insulating layer 110c can be made of the materials listed for the insulating layer 110c. An oxide or an oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using an oxide or an oxynitride for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) during the formation of the layer (or the film that will become the layer), which is preferable. The insulating layer 110c can have, for example, a stacked structure of a first film containing an oxide or oxynitride and a second film containing a nitride or nitride oxide on the first film. More specifically, the insulating layer 110c can have, for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0181] [Opening 141, Opening 241, Opening 243] The top surface shapes of openings 141, 241, and 243 are not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or shapes with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1A and other figures, the top surface shapes of openings 141, 241, and 243 are preferably circular. By forming the top surface shapes of the openings circular, processing accuracy during formation of the openings can be improved, allowing for the formation of openings of finer sizes. When the top surface shapes of openings 241 and 243 are circular, openings 241 and 243 may or may not be concentric. Furthermore, in this specification and other figures, a circle is not limited to a perfect circle.

[0182] The channel lengths and channel widths of the transistors 100 and 200 will be described with reference to FIGS. 4A to 4C.

[0183] In FIG. 4B , the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100 corresponds to the length of the side surface of the insulating layer 110b on the opening 141 side in a cross-sectional view. In other words, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ100 between the side surface of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the top surface of the insulating layer 110a). In FIG. 4C , the channel length L200 of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L200 of the transistor 200 corresponds to the length of the side surface of the insulating layer 110b on the opening 241 side in a cross-sectional view. That is, the channel length L200 is determined by the thickness T110b of the insulating layer 110b and the angle θ200 between the side surface of the insulating layer 110b on the opening 241 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel lengths L100 and L200 can be set to values ​​smaller than the minimum exposure dimension of the exposure tool, enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized with conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is also possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0184] The channel length L100 and the channel length L200 may each be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0185] By shortening the channel lengths L100 and L200, the on-state current of the transistor 100 and the transistor 200 can be increased. By using the transistor 100 and the transistor 200, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0186] The channel length L100 can be controlled by adjusting the thickness T110b and the angle θ100. Similarly, the channel length L200 can be controlled by adjusting the thickness T110b and the angle θ200.

[0187] The thickness T110b may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. The thickness T110b may be appropriately set to obtain a desired channel length L100. As shown in FIG. 4B , the thickness T110b may be the shortest distance between the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a) and the upper surface of the insulating layer 110b in a cross-sectional view.

[0188] Preferably, the angles θ100 and θ200 are each 90 degrees or less. By reducing the angles θ100 and θ200, the coverage of layers (e.g., layers 108 and 208) formed on the insulating layer 110 can be improved. Furthermore, when the angle θ100 is 90 degrees or less, the smaller the angle θ100, the longer the channel length L100 can be, and the larger the angle θ100, the shorter the channel length L100 can be. The same applies to the angle θ200 and the channel length L200.

[0189] 4B and other figures, the angles θ100 and θ200 are each shown as being less than 90 degrees, but this is not a limitation of one embodiment of the present invention. The angles θ100 and θ200 can each be set to 90 degrees or approximately 90 degrees. This allows the channel lengths L100 and L200 to be shortened.

[0190] The angles θ100 and θ200 can each be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and can be 90 degrees or less, 85 degrees or less, or 80 degrees or less. The angles θ100 and θ200 can also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less. The angles θ100 and θ200 can each be set appropriately to obtain the desired channel length L100.

[0191] By making the angle θ200 the same as or approximately the same as the angle θ100, the channel length L200 becomes the same as or approximately the same as the channel length L100. For example, by forming the opening 141 and the opening 241 in the same process, the angles θ100 and θ200 can be made the same as or approximately the same. Alternatively, the angles θ100 and θ200 can be made different from each other. For example, by forming the opening 141 and the opening 241 in different processes and making the angles θ100 and θ200 different from each other, the channel lengths L100 and L200 can be made different from each other. For example, when the angle θ200 is 90 degrees or less, by making the angle θ200 smaller, the channel length L200 becomes longer, and the saturation of the transistor 200 can be improved.

[0192] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0193] When the angles θ100 and θ200 are large, it is preferable to use a film formation method with higher coverage for forming the layers provided in the openings 141, 241, and 243. For example, when the angles θ100 and θ200 are 85 degrees or greater and 90 degrees or less, the ALD method can be suitably used for forming the insulating layer 106, the layer 108, and the layer 208. On the other hand, when the angles θ100 and θ200 are small, a film formation method with higher productivity can be suitably used. For example, when the angles θ100 and θ200 are less than 85 degrees, the PECVD method can be suitably used for forming the insulating layer 106, and sputtering can be suitably used for forming the layer 108 and the layer 208.

[0194] The thickness of the region 108P of the layer 108 provided along the top surface of the insulating layer 110 may be thicker than the thickness of the region 108M provided along the side surface of the insulating layer 110. By increasing the thickness of the region 108P, the electrical resistance of the other of the source electrode and the drain electrode of the transistor 100 can be reduced.

[0195] 1B and the like show a cross-sectional view in which the shape of the side surface of the insulating layer 110 on the opening 141 side and the shape of the side surface of the opening 241 side are linear, but one embodiment of the present invention is not limited to this. In a cross-sectional view, the shape of the side surface of the insulating layer 110 on the opening 141 side and the shape of the side surface of the opening 241 side can be curved. Alternatively, a structure can be used in which the shape of the side surface includes both a linear region and a curved region.

[0196] Here, the conductive layer 212b is preferably not provided inside the opening 241. Specifically, the conductive layer 212b preferably does not have a region in contact with the side surface of the insulating layer 110 on the opening 241 side. If the conductive layer 212b is also provided inside the opening 241, the channel length L200 of the transistor 200 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L200. Therefore, it is preferable that the top shape of the opening 243 coincides with the top shape of the opening 241, or that the opening 243 encompasses the opening 241 in a top view.

[0197] In Figures 4A and 4B, the width D141 of the opening 141 is indicated by a double-headed, dashed arrow, and in Figures 4A and 4C, the width D241 of the opening 241 is indicated by a double-headed, dashed arrow. Figure 4A shows an example in which the top surface shapes of the openings 141 and 241 are each circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the perimeter of the circle. That is, the channel width W100 is π × D141. Similarly, when the top surface shape of the opening 241 is circular, the channel width W200 of the transistor 200 is π × D241. When the top surface shapes of the openings 141 and 241 are circular, the transistors 100 and 200 can be realized with smaller channel widths than those with other shapes.

[0198] The widths D141 and D241 may vary in the depth direction. For example, the widths D141 and D241 may be the average values ​​of the diameters at the highest and lowest points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view, and the diameters at the midpoints between these. Alternatively, the widths D141 and D241 may be any of the diameters at the highest and lowest points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view, or the diameters at the midpoints between these.

[0199] When the openings 141 and 241 are formed using photolithography, the widths D141 and D241 are equal to or greater than the minimum exposure dimension of the exposure device. The widths D141 and D241 may be, for example, equal to or greater than 20 nm, equal to or greater than 50 nm, equal to or greater than 100 nm, equal to or greater than 200 nm, equal to or greater than 300 nm, equal to or greater than 400 nm, or equal to or greater than 500 nm, and may be less than 5 μm, equal to or less than 4.5 μm, equal to or less than 4 μm, equal to or less than 3.5 μm, equal to or less than 3 μm, equal to or less than 2.5 μm, equal to or less than 2 μm, equal to or less than 1.5 μm, or equal to or less than 1 μm.

[0200] 4A and other figures show a configuration in which the width D141 and the width D241 are the same, but one embodiment of the present invention is not limited to this. The width D141 and the width D241 may be different. By making the width D141 and the width D241 different, the channel width W100 and the channel width W200 can be made different.

[0201] Note that although the example described here is one in which the region 108M serves as a channel formation region of the transistor 100 and the region 208M serves as a channel formation region of the transistor 200, one embodiment of the present invention is not limited to this. A region of the layer 108 in contact with the insulating layer 110a may also serve as a channel formation region. A region of the layer 108 in contact with the insulating layer 110c may also serve as a channel formation region. The same applies to the layer 208.

[0202] [Conductive Layer 112, Conductive Layer 104, Conductive Layer 212a, Conductive Layer 212b, Conductive Layer 204] The conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for these layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the above metals. The conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each be preferably made of a conductive material with low electrical resistivity, such as one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred because of its excellent mass productivity.

[0203] A conductive metal oxide (oxide conductor) can be used for each of the conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204. Examples of oxide conductors (OC) include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, oxide conductors containing indium are preferable because of their high conductivity.

[0204] Oxygen deficiency (V) in metal oxides with semiconducting properties Ｏ ) and the oxygen vacancy (V ＯWhen hydrogen is added to a metal oxide, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive. A metal oxide that has become electrically conductive can be called an oxide conductor.

[0205] The conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0206] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be applied to each of the conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0207] Note that the conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can be formed using the same material, or at least one of them can be formed using a different material.

[0208] The layer 108 is formed after the conductive layer 112 is formed, and the layer 208 is formed after the conductive layer 212a and the conductive layer 212b are formed. When the layers 108 and 208 contain oxygen or are formed in an atmosphere containing oxygen, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112, the conductive layer 212a, and the conductive layer 212b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112 and the layer 108, between the conductive layer 212a and the layer 208, and between the conductive layer 212b and the layer 208, which may hinder conduction therebetween. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor for the conductive layer 112, the conductive layer 212a, and the conductive layer 212b.

[0209] For the conductive layer 112, the conductive layer 212a, and the conductive layer 212b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112, the conductive layer 212a, or the conductive layer 212b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the layer 108 and the layer in contact with the layer 208.

[0210] The conductive layer 112, the conductive layer 212a, and the conductive layer 212b can each be formed using any of the above-described oxide conductors. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium can be used.

[0211] The conductive layer 112, the conductive layer 212a, and the conductive layer 212b may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may each be made of the nitride conductor.

[0212] 5A to 6B are cross-sectional views of a semiconductor device 10A according to one embodiment of the present invention. For a top view of the semiconductor device 10A, refer to FIG. 1A. 5A to 6B are cross-sectional views of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0213] The semiconductor device 10A includes a transistor 100A, a transistor 200A, and an insulating layer 110. The transistor 100A differs from the transistor 100 shown in FIG. 1B and the like mainly in that the conductive layer 112 has a stacked structure, and the transistor 200A differs from the transistor 200 mainly in that the conductive layer 212a has a stacked structure.

[0214] 5A and 5B show a configuration in which the conductive layer 112 has a two-layer structure of a conductive layer 112_1 and a conductive layer 112_2 over the conductive layer 112_1, and the conductive layer 212a has a two-layer structure of a conductive layer 212a_1 and a conductive layer 212a_2 over the conductive layer 212a_1.

[0215] For the conductive layer 112_2 having a region in contact with the layer 108, a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor is preferably used. For materials that can be used for the conductive layer 112_2, the description of the conductive layer 112 can be referred to.

[0216] The conductive layer 112_1 does not have a region in contact with the layer 108, and therefore, the material used is not particularly limited. For example, the conductive layer 112_1 is preferably made of a material having lower electrical resistivity than the conductive layer 112_2. This can reduce the electrical resistance of the conductive layer 112. For example, In—Sn—Si oxide (ITSO) can be preferably used for the conductive layer 112_2, and copper or tungsten can be preferably used for the conductive layer 112_1.

[0217] 5A, the edge of the conductive layer 112_2 can be aligned or approximately aligned with the edge of the conductive layer 112_1. For example, the conductive layer 112 can be formed by forming a first film to be the conductive layer 112_1 and a second film to be the conductive layer 112_2, and then processing the first film and the second film. By processing the first film and the second film in the same process, the manufacturing cost can be reduced.

[0218] The end of the conductive layer 112_2 may not be aligned with the end of the conductive layer 112_1. As shown in FIG. 5B , the conductive layer 112_2 may be formed so as to cover the conductive layer 112_1. The conductive layer 112_2 has a region in contact with the top surface and side surface of the conductive layer 112_1. It can also be said that the conductive layer 112_2 has a portion protruding beyond the end of the conductive layer 112_1. For example, the conductive layer 112_1 may be formed, a film to become the conductive layer 112_2 may be formed on the conductive layer 112_1, and the film may be processed to form the conductive layer 112_2. By making the conductive layer 112_2 protrude beyond the end of the conductive layer 112_1, the step on the formation surface of a layer (e.g., the insulating layer 110) formed on the conductive layer 112 is reduced, thereby improving the coverage of the layer. This can prevent defects such as discontinuities or voids in the layer.

[0219] 5A and 5B , some or all of the layers constituting the conductive layer 112 may have different thicknesses. The electrical resistance of the conductive layer 112 can be reduced by making the thickness of a layer using a material with low electrical resistivity thicker than the other layers. For example, a material with lower electrical resistivity than the conductive layer 112_2 can be used for the conductive layer 112_1, and the thickness of the conductive layer 112_1 can be made thicker than the thickness of the conductive layer 112_2. This reduces the electrical resistance of the conductive layer 112. The thicknesses of the layers constituting the conductive layer 112 can also be the same or approximately the same.

[0220] The conductive layer 212a_1 can be formed in the same process as the conductive layer 112_1, and the conductive layer 212a_2 can be formed in the same process as the conductive layer 112_2. For the conductive layers 212a_1 and 212a_2, the description of the conductive layers 112_1 and 112_2 can be referred to.

[0221] 6A and 6B show a configuration in which the conductive layer 112 has a three-layer structure of a conductive layer 112_3, a conductive layer 112_1 on the conductive layer 112_3, and a conductive layer 112_2 on the conductive layer 112_1, and the conductive layer 212a has a three-layer structure of a conductive layer 212a_3, a conductive layer 212a_1 on the conductive layer 212a_3, and a conductive layer 212a_2 on the conductive layer 212a_1.

[0222] As shown in FIG. 6A , the end of the conductive layer 112_1 can be in contact with the top surface of the conductive layer 112_3. The conductive layer 112_2 has regions in contact with the top and side surfaces of the conductive layer 112_1 and the top surface of the conductive layer 112_3. That is, it can be said that the conductive layers 112_2 and 112_3 each have portions that protrude beyond the end of the conductive layer 112_1. It can also be said that the top, side, and bottom surfaces of the conductive layer 112_1 are surrounded by the conductive layers 112_2 and 112_3. The conductive layer 112_3 is preferably made of a material that has high adhesion to the surface on which the conductive layer 112_3 is to be formed (here, the surface of the substrate 102). The end of the conductive layer 112_3 can be aligned or approximately aligned with the end of the conductive layer 112_2. For example, a first film to be the conductive layer 112_3 is formed, a conductive layer 112_1 is formed on the first film, and a second film to be the conductive layer 112_2 is formed on the first film and the conductive layer 112_1. Then, by processing the first film and the second film, the conductive layer 112 including the conductive layer 112_3, the conductive layer 112_1, and the conductive layer 112_2 can be formed. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

[0223] As described above, the conductive layer 112_1 is preferably made of a material with low electrical resistivity. However, depending on the material, adhesion between the conductive layer 112_1 and the surface on which the conductive layer 112_1 is to be formed (e.g., the surface of the substrate 102) may be low, which may result in a low manufacturing yield of the semiconductor device. By using a material for the conductive layer 112_3 that has higher adhesion to the surface on which the conductive layer 112_1 is to be formed than the conductive layer 112_1, the manufacturing yield of the semiconductor device can be increased. Note that the thickness of the conductive layer 112_3 is preferably a thickness that effectively enhances adhesion between the conductive layer 112 and the surface on which the conductive layer 112 is to be formed, and can be thinner than the thicknesses of the conductive layer 112_1 and the conductive layer 112_2. Reducing the thickness of the conductive layer 112_3 can reduce manufacturing costs.

[0224] For example, it is preferable to use In—Sn—Si oxide (ITSO) for the conductive layer 112_3, copper for the conductive layer 112_1, and In—Sn—Si oxide (ITSO) for the conductive layer 112_2. When a glass substrate is used as the substrate 102, adhesion between the glass substrate and an ITSO film is higher than adhesion between a glass substrate and a copper film. Furthermore, using the same material for the conductive layers 112_2 and 112_3 facilitates processing when the conductive layers 112_2 and 112_3 are formed in the same process, thereby increasing the manufacturing yield of the semiconductor device.

[0225] 6B , the edge of the conductive layer 112_3 can be aligned or substantially aligned with the edge of the conductive layer 112_1. For example, a first film to be the conductive layer 112_3 is formed, a second film to be the conductive layer 112_1 is formed on the first film, and the first and second films are processed to form the conductive layer 112_3 and the conductive layer 112_1. Then, the conductive layer 112 can be formed by forming the conductive layer 112_2 on the conductive layer 112_3 and the conductive layer 112_1. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

[0226] The conductive layer 212a_3 can be formed in the same process as the conductive layer 112_3. For the conductive layer 212a_3, the description of the conductive layer 112_3 can be referred to.

[0227] Although the conductive layer 112 and the conductive layer 212a each have a stacked structure of two or three layers in this example, one embodiment of the present invention is not limited to this. The conductive layer 112 and the conductive layer 212a may also have a stacked structure of four or more layers.

[0228] The structures of the conductive layer 112 and the conductive layer 212a shown in FIGS. 5A to 6B can also be applied to other structure examples.

[0229] [Insulating Layer 106] The insulating layer 106 is preferably formed by a method with high coverage because it is provided to cover the openings 141, 241, and 243. The insulating layer 106 is preferably formed by a sputtering method, a PECVD method, or an ALD method. As the ALD method, a thermal ALD method or a PEALD (Plasma Enhanced ALD) method can be used. The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it exhibits high coverage and allows low-temperature film formation.

[0230] The insulating layer 106 preferably includes one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as that used for the insulating layer 110.

[0231] The insulating layer 106 is provided over the layer 108, the layer 208, the conductive layer 212b, and the insulating layer 110. When a metal oxide is used for the layer 108 and the layer 208, any of the above-described oxides and oxynitrides is preferably used for at least a film in contact with the layer 108 and the layer 208 among the films constituting the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0232] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0233] 1B and the like, the insulating layer 106 has a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers.

[0234] 7 is a cross-sectional view of a semiconductor device 10B according to one embodiment of the present invention. For a top view of the semiconductor device 10B, see FIG. 1A. FIG. 7 is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0235] The semiconductor device 10B includes a transistor 100B, a transistor 200B, and an insulating layer 110. The transistors 100B and 200B are different from the transistors 100 and 200 shown in FIG. 1B and the like mainly in that the insulating layer 106 has a stacked-layer structure. FIG. 7 shows a configuration in which the insulating layer 106 has a two-layer structure including an insulating layer 106a and an insulating layer 106b over the insulating layer 106a.

[0236] In the case where the insulating layer 106 has a stacked-layer structure, the insulating layer (the insulating layer 106a here) on the layer 108 and the layer 208 side preferably contains oxide or oxynitride. For example, the insulating layer 106a can be preferably made of one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0237] It is preferable to provide a layer that functions as a barrier film in at least one of the layers that constitute the insulating layer 106. This can prevent metal components contained in the conductive layer 104 and the conductive layer 204 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100B and the transistor 200B from diffusing into the layer 108 and the layer 208 through the insulating layer 106. Furthermore, it can prevent oxygen contained in the layer 108 and the layer 208 from diffusing into the conductive layer 104 and the conductive layer 204 through the insulating layer 106. This can prevent oxygen deficiency (V Ｏ ) and V ＯThe increase in H can be suppressed. Furthermore, the conductive layer 104 and the conductive layer 204 can be prevented from being oxidized by oxygen contained in the layer 108 and the layer 208, and the increase in the electrical resistance of the conductive layer 104 and the conductive layer 204 can be suppressed. As a result, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics. The layer functioning as a barrier film preferably uses one or more of the above-described nitrides and nitride oxides. Alternatively, one or more of oxides and oxynitrides can also be used for the layer, and aluminum oxide can be preferably used, for example.

[0238] For example, silicon oxynitride can be used for the insulating layer 106a, and silicon nitride can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a, and aluminum oxide can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a, and silicon oxynitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a, and silicon nitride can be used for the insulating layer 106b.

[0239] Although the insulating layer 106 has a two-layer structure in this example, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a three-layer or more layer structure.

[0240] The configuration of the insulating layer 106 shown in FIG. 7 can also be applied to other configuration examples.

[0241] [Insulating Layer 195] The insulating layer 195, which functions as a protective layer for the transistors 100 and 200, is preferably made of a material through which impurities do not easily diffuse. By providing the insulating layer 195, diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.

[0242] The insulating layer 195 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of acrylic resin and polyimide resin can be used as the organic material. A photosensitive material can be used as the organic material. Two or more of the above insulating films can also be stacked. The insulating layer 195 can have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0243] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. Alternatively, a substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shapes of the semiconductor substrate and the insulating substrate are not particularly limited and may be circular or rectangular.

[0244] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0245] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same functions as the configuration example described above may be hatched with the same pattern and may not be assigned reference numerals.

[0246] 8A shows a cross-sectional view of a semiconductor device 10C according to one embodiment of the present invention. For a top view of the semiconductor device 10C, see FIG. 1A. FIG. 8A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0247] The semiconductor device 10C includes a transistor 100C, a transistor 200C, and an insulating layer 110. The semiconductor device 10C differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that the insulating layer 110 includes an insulating layer 110e.

[0248] FIG. 8B shows an enlarged view of the transistor 100C shown in FIG. 8A , and FIG. 8C shows an enlarged view of the transistor 200C. The insulating layer 110 includes an insulating layer 110e, an insulating layer 110a on the insulating layer 110e, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110d on the insulating layer 110c. The insulating layer 110e can be made of a material that can be used for the insulating layer 110d. For example, silicon nitride or silicon nitride oxide can be suitably used for the insulating layer 110e. Note that the insulating layer 110d and the insulating layer 110e can be made of the same material. Alternatively, different materials can be used for them. For the insulating layer 110e, the description of the insulating layer 110d can be referred to.

[0249] The insulating layer 110e is provided between the insulating layer 110a and the conductive layer 112 and between the insulating layer 110a and the conductive layer 212a and is provided so as to cover the conductive layer 112 and the conductive layer 212a. The insulating layer 110e has regions in contact with the top and side surfaces of the conductive layer 112, the top and side surfaces of the conductive layer 212a, the top surface of the substrate 102, the side surface of the layer 108, and the side surface of the layer 208.

[0250] The insulating layer 110e is preferably made of a material that releases impurities (e.g., water and hydrogen) that reduce the electrical resistance of the layer 108 and the layer 208. This allows the region of the layer 108 in contact with the insulating layer 110e and the region of the layer 208 in contact with the insulating layer 110e to be low-resistance regions. The layer 108 can have a low-resistance region between the region in contact with the conductive layer 112 (one of the source and drain regions of the transistor 100C) and the channel formation region. Similarly, the layer 208 can have a low-resistance region between the region in contact with the conductive layer 212a (one of the source and drain regions of the transistor 200C) and the channel formation region. These low-resistance regions can function as buffer regions for reducing the drain electric field. Note that these low-resistance regions may function as source or drain regions.

[0251] By providing a low-resistance region between the drain and the channel formation region, a high electric field is less likely to be generated near the drain, which suppresses the generation of hot carriers and thus reduces transistor degradation. For example, in the transistor 100C, when the conductive layer 112 functions as a drain electrode and the region 108P functions as a source electrode, by forming the region of the layer 108 in contact with the insulating layer 110e as a low-resistance region, a high electric field is less likely to be generated near the drain, which suppresses the generation of hot carriers and thus reduces transistor degradation. Similarly, in the transistor 200C, when the conductive layer 212a functions as a drain electrode and the conductive layer 212b functions as a source electrode, by forming the region of the layer 208 in contact with the insulating layer 110e as a low-resistance region, a high electric field is less likely to be generated near the drain, which suppresses the generation of hot carriers and thus reduces transistor degradation.

[0252] When the region of the layer 108 in contact with the insulating layer 110e functions as a source region or a drain region, the distance from the source region of the layer 108 to the gate electrode and the distance from the drain region to the gate electrode can be made more uniform. This makes it possible to make the electric field of the gate electrode applied to the channel formation region more uniform in the transistor 100. The same applies to the transistor 200.

[0253] It is preferable to provide the insulating layer 110a between the insulating layer 110e and the insulating layer 110b. By providing the insulating layer 110a functioning as a barrier film, impurities released from the insulating layer 110e can be prevented from diffusing into the channel formation regions of the layer 108 and the layer 208 through the insulating layers 110a and 110b. This enables a highly reliable transistor to exhibit favorable electrical characteristics.

[0254] The insulating layer 110e preferably has a region having a higher impurity element concentration than the insulating layer 110a. For example, the insulating layer 110e preferably has a region having a higher hydrogen concentration than the insulating layer 110a. The film density of the insulating layer 110a is more preferably higher than that of the insulating layer 110e. For the insulating layer 110e and the insulating layer 110a, the description of the insulating layer 110d and the insulating layer 110c can be referred to.

[0255] Although the insulating layer 110 has a five-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 can also have a two-layer, three-layer, four-layer, or six or more-layer structure. Alternatively, the insulating layer 110 can have a single-layer structure.

[0256] The configuration of the insulating layer 110 shown in Configuration Example 1-2 can also be applied to other configuration examples.

[0257] 9A shows a cross-sectional view of a semiconductor device 10D according to one embodiment of the present invention. For a top view of the semiconductor device 10D, see FIG. 1A. FIG. 9A is a cross-sectional view of the cut surface taken along dashed line A1-A2 in FIG. 1A.

[0258] The semiconductor device 10D includes a transistor 100D, a transistor 200D, an insulating layer 110, and an insulating layer 109. The semiconductor device 10D differs from the semiconductor device 10 shown in FIG.

[0259] An enlarged view of the transistor 100D shown in FIG. 9A is shown in FIG. 9B, and an enlarged view of the transistor 200D is shown in FIG. The insulating layer 109 is provided between the conductive layer 112 and the conductive layer 212a and the substrate 102. The insulating layer 109 is provided over the substrate 102, the conductive layer 112 and the conductive layer 212a are provided over the insulating layer 109, and the insulating layer 110 is provided over the conductive layer 112, the conductive layer 212a, and the insulating layer 109. The insulating layer 109 has regions in contact with the lower surface of the conductive layer 112, the lower surface of the conductive layer 212a, the lower surface of the insulating layer 110, and the upper surface of the substrate 102. The conductive layer 112 has regions in contact with the insulating layer 109 and the insulating layer 110 and sandwiched therebetween. The conductive layer 212a has regions in contact with the insulating layer 109 and the insulating layer 110 and sandwiched therebetween.

[0260] The insulating layer 109 is preferably made of a material that releases impurities (for example, water and hydrogen) that reduce the electrical resistance of the layer 108 and the layer 208. The insulating layer 109 can be made of a material that can be used for the insulating layer 110d. For example, silicon nitride or silicon nitride oxide can be suitably used for the insulating layer 109. For the insulating layer 109, the description of the insulating layer 110d can be referred to.

[0261] The impurities released from the insulating layer 109 diffuse into a region of the conductive layer 112 in contact with the insulating layer 109 and a region of the conductive layer 212a in contact with the insulating layer 109. The impurities diffused into the conductive layer 112 diffuse into a region of the layer 108 in contact with the conductive layer 112, and the impurities diffused into the conductive layer 212a diffuse into a region of the layer 208 in contact with the conductive layer 212a. This reduces the electrical resistance of the region of the layer 108 in contact with the conductive layer 112, i.e., one of the source and drain regions of the transistor 100. Similarly, the electrical resistance of the region of the layer 208 in contact with the conductive layer 212a, i.e., one of the source and drain regions of the transistor 200, can be reduced. Therefore, the transistors 100D and 200D can have large on-state currents, and a semiconductor device that operates at high speed can be obtained.

[0262] When a metal oxide is used for the layer 108 and the layer 208, the impurities released from the insulating layer 109 preferably include hydrogen. Hydrogen diffused from the insulating layer 109 to the layer 108 through the conductive layer 112 increases the carrier concentration in the region of the layer 108 in contact with the conductive layer 112, thereby reducing the electrical resistance of one of the source and drain regions of the transistor 100. Similarly, hydrogen diffused from the insulating layer 109 to the layer 208 through the conductive layer 212a increases the carrier concentration in the region of the layer 208 in contact with the conductive layer 212a, thereby reducing the electrical resistance of one of the source and drain regions of the transistor 200.

[0263] The insulating layer 109 is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112 and the conductive layer 212a. This can reduce the electrical resistance of the conductive layer 112 and the conductive layer 212a. For example, when a metal oxide is used for the conductive layer 112 and the conductive layer 212a, the impurities preferably contain hydrogen. This increases the carrier concentration of the conductive layer 112 and the conductive layer 212a, thereby reducing the electrical resistance. Furthermore, the conductive layer 112 and the conductive layer 212a can function as wirings, thereby providing a semiconductor device with low wiring resistance. Note that the impurities that reduce the electrical resistance of the conductive layer 112 and the conductive layer 212a may be the same as or different from the impurities that reduce the electrical resistance of the layer 108 and the layer 208.

[0264] The materials that can be used for the conductive layer 112 and the conductive layer 212a are as described above. Note that the conductive layer 112 and the conductive layer 212a preferably easily transmit impurities and more preferably do not easily adsorb impurities.

[0265] The insulating layer 110a has regions in contact with the top surface of the insulating layer 109, the top surface and side surfaces of the conductive layer 112, and the top surface and side surfaces of the conductive layer 212a. This can prevent impurities contained in the insulating layer 109, the conductive layer 112, and the conductive layer 212a from diffusing into the channel formation regions of the layer 108 and the layer 208 through the insulating layer 110a and the insulating layer 110b.

[0266] The insulating layer 109 preferably has a region where the concentration of impurity elements is higher than that of the insulating layer 110a. For example, the insulating layer 109 preferably has a region where the concentration of hydrogen is higher than that of the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. For the insulating layer 109 and the insulating layer 110a, the description of the insulating layer 110d and the insulating layer 110c can be referred to.

[0267] Note that impurities released from the insulating layer 109 may diffuse into the channel formation region of the layer 108 via the conductive layer 112 and one of the source region and drain region of the layer 108. Similarly, impurities released from the insulating layer 109 may diffuse into the channel formation region of the layer 208 via the conductive layer 212a and one of the source region and drain region of the layer 208. When the impurity is hydrogen, hydrogen released from the insulating layer 109 may diffuse into the channel formation regions of the layer 108 and the layer 208. However, since oxygen is supplied from the insulating layer 110b to at least the regions of the layer 108 and the layer 208 that are in contact with the insulating layer 110b, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. As a result, a shift in the threshold voltage can be suppressed, and the transistors 100 and 200 can have both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0268] 9A and other drawings show the insulating layer 110 having a four-layer structure of the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, and the insulating layer 110d, but one embodiment of the present invention is not limited to this. For example, the insulating layer 110 may have a five-layer structure of the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, the insulating layer 110d, and the insulating layer 110e.

[0269] The configuration of the insulating layer 109 shown in Configuration Example 1-3 can also be applied to other configuration examples.

[0270] 10A is a cross-sectional view of a semiconductor device 10E according to one embodiment of the present invention. For a top view of the semiconductor device 10E, see FIG. 1A. FIG. 10A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0271] The semiconductor device 10E includes a transistor 100E, a transistor 200E, and an insulating layer 110. The semiconductor device 10E differs mainly from the semiconductor device 10 shown in FIG. 1B and the like in that the layer 108 and the layer 208 each have a stacked structure.

[0272] An enlarged view of the transistor 100E shown in Fig. 10A is shown in Fig. 10B, and an enlarged view of the transistor 200E shown in Fig. 10C. Fig. 10A to Fig. 10C show a configuration in which the layer 108 has a three-layer structure of a layer 108a, a layer 108b on the layer 108a, and a layer 108c on the layer 108b, and the layer 208 has a three-layer structure of a layer 208a, a layer 208b on the layer 208a, and a layer 208c on the layer 208b.

[0273] The layers 108a, 108b, 108c, 208a, 208b, and 208c can be made of the materials listed for the layers 108 and 208, respectively. The layers 108a, 108b, 108c, 208a, 208b, and 208c each preferably contain a metal oxide exhibiting semiconductor properties. The layer 108a can be made of the same material as the layer 208a, the layer 108b can be made of the same material as the layer 208b, and the layer 108c can be made of the same material as the layer 208c.

[0274] For example, layers 108a and 208a can be formed in the same process. Layers 108b and 208b can be formed in the same process. Layers 108c and 208c can be formed in the same process. Layers 108 and 208 can be formed by forming a first film that will become layers 108a and 208a, forming a second film that will become layers 108b and 208b, and forming a third film that will become layers 108c and 208c, and then processing the first film, second film, and third film to form layers 108 and 208. Alternatively, layers included in layer 108 can be formed in a process different from that of layers included in layer 208.

[0275] The band gap of each of the first metal oxide in the layers 108a and 208a, the second metal oxide in the layers 108b and 208b, and the third metal oxide in the layers 108c and 208c is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0276] The band gap of the first metal oxide is preferably larger than the band gap of the second metal oxide. The band gap of the third metal oxide is preferably larger than the band gap of the second metal oxide. Layer 108b can be sandwiched between layers 108a and 108c, which have larger band gaps than layer 108b, to form a buried channel. This makes layer 108b the main current path in layer 108. Similarly, layer 208b is sandwiched between layers 208a and 208c to form a buried channel. This makes layer 208b the main current path in layer 208.

[0277] In the following description, the layer 108 including the layers 108a, 108b, and 108c will be taken as an example, and a description of the layer 208 may be omitted. Regarding the layer 208, descriptions of the layers 108a, 108b, and 108c can be interpreted as the layers 208a, 208b, and 208c.

[0278] The difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more. The difference between the band gap of the third metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more.

[0279] The conduction band minimum of the first metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably smaller than the electron affinity of the second metal oxide. The electron affinity of the third metal oxide is preferably smaller than the electron affinity of the second metal oxide.

[0280] The band gaps of the first metal oxide, the second metal oxide, and the third metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS or ESCA), or X-ray absorption fine structure (XAFS). Alternatively, analysis can be performed by combining a plurality of these techniques. The electron affinity or the conduction band minimum can be determined from the ionization potential, which is the energy difference between the vacuum level and the valence band maximum, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0281] Trap levels due to impurities or defects can be formed at and near the interface between the insulating layer 110 and the layer 108. Examples of such impurities include residual components of an etchant or etching gas used to form the opening 141 and components of the conductive layer 112 that adhere to the side surface of the insulating layer 110 when the opening 141 is formed. By providing the layer 108a between the layer 108b and the insulating layer 110, the layer 108b can be separated from the trap levels.

[0282] Damage may occur to the interface between the insulating layer 106 and the layer 108 and its vicinity when the insulating layer 106 is formed. As a result, trap states may be formed at the interface between the insulating layer 106 and the layer 108 and its vicinity. By providing the layer 108c between the layer 108b and the insulating layer 106, the layer 108b can be separated from the trap states.

[0283] By sandwiching the layer 108b, which is the main current path of the layer 108, between the layers 108a and 108c, it is possible to reduce trap levels at the interface of the layer 108b and in the vicinity of the interface. This allows a transistor with high on-state current and high reliability to be obtained. Therefore, a semiconductor device that achieves both high-speed operation and high reliability can be provided.

[0284] The composition of the first metal oxide is preferably different from the composition of the second metal oxide. The composition of the third metal oxide is preferably different from the composition of the second metal oxide. By varying the compositions of the metal oxides, the band gap can be adjusted. Specifically, the content of element M in the first metal oxide and the content of element M in the third metal oxide are preferably higher than the content of element M in the second metal oxide. This allows the band gap of the first metal oxide and the band gap of the third metal oxide to be larger than the band gap of the second metal oxide.

[0285] The indium content of the second metal oxide is preferably higher than the indium content of the first metal oxide and the indium content of the third metal oxide, thereby enabling a transistor with a large on-state current to be obtained.

[0286] For example, when the first metal oxide and the second metal oxide are In-M-Zn oxides, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 40:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:40 (atomic ratio) or thereabout. It is particularly preferable to use one or more of gallium, aluminum, and tin as the element M. The element M in the first metal oxide, the element M in the second metal oxide, and the element M in the third metal oxide can have the same structure. Alternatively, some or all of these elements can be different. Furthermore, when one or more of the first metal oxide, the second metal oxide, and the third metal oxide contain multiple elements M, each of the elements M may be the same as the element M contained in the other metal oxide, or some or all of the elements M may be different.

[0287] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, the second metal oxide may preferably have a composition of In:Sn:Zn=10:1:40 [atomic ratio] or a composition thereabout, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout.

[0288] The second metal oxide may be free of element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar ratio; the second metal oxide may have an atomic ratio of In:Zn=4:1 or a similar ratio; and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar ratio. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Zn=1:1 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Zn=1:4 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition.

[0289] FIG. 11A shows an enlarged view of the side surfaces of layer 108 and insulating layer 110 and their vicinity, while FIG. 11B shows an enlarged view of the side surfaces of layer 208 and insulating layer 110 and their vicinity. In FIG. 11A, the thickness T108a of layer 108a, the thickness T108b of layer 108b, and the thickness T108c of layer 108c are each indicated by solid arrows. In FIG. 11B, the thickness T208a of layer 208a, the thickness T208b of layer 208b, and the thickness T208c of layer 208c are each indicated by solid arrows. Here, the thickness of layer 108 is defined as the shortest distance between insulating layer 110b and insulating layer 106 in the region in contact with layer 108 in a cross-sectional view. The thickness of each layer of layer 108 can be, for example, the thickness of each layer of layer 108 at the midpoint between the height of the top surface and the height of the bottom surface of insulating layer 110. The same applies to layer 208.

[0290] As described above, layers 208a, 208b, and 208c can be formed in the same process as layers 108a, 108b, and 108c. Furthermore, when the angles θ100 and θ200 (see FIGS. 4B and 4C ) of insulating layer 110, on which layers 108 and 208 are formed, are the same or approximately the same, thicknesses T108a and T208a may be the same or approximately the same, thicknesses T108b and T208b may be the same or approximately the same, and thicknesses T108c and T208c may be the same or approximately the same. Note that thicknesses T108a and T208a may be different from each other. The same applies to thicknesses T108b and T208b, and thicknesses T108c and T208c.

[0291] The following description will be given taking as an example the thickness of each layer of the layer 108. Note that with regard to the layer 208, the descriptions relating to the thickness T108a, the thickness T108b, and the thickness T108c can be read as the thickness T208a, the thickness T208b, and the thickness T208c.

[0292] By increasing the thickness T108b of the layer 108b, which is the main current path of the layer 108, the transistor 100 can have a large on-state current. The thickness T108b is preferably greater than the thicknesses T108a and T108c. However, if the thickness T108b is too thick, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. The thickness T108b is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 15 nm or less.

[0293] The thickness T108c is preferably thicker than the thickness T108a. By increasing the thickness T108c, the layer 108b can be separated from trap levels that may be formed at the interface between the insulating layer 106 and the layer 108 and in the vicinity thereof. Furthermore, damage to the layer 108b during the formation of the insulating layer 106 can be suppressed. If the thickness T108c is too thick, the distance between the conductive layer 104, which functions as a gate electrode, and the layer 108b increases, which may result in a small on-state current. The thickness T108c is preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, even more preferably 1 nm or more and 10 nm or less, and even more preferably 2 nm or more and 10 nm or less.

[0294] Oxygen contained in the insulating layer 110 is supplied to the layer 108b via the layer 108a. Therefore, it is preferable that the layer 108a is easily permeable to oxygen. By making the thickness T108a thinner than the thickness T108c, the oxygen contained in the insulating layer 110 can be efficiently supplied to the layer 108b. This reduces the oxygen vacancy (V Ｏ ) and V Ｏ H can be reduced. If the thickness T108a is too thin, the distance between the layer 108b and the trap levels at or near the interface between the insulating layer 110 and the layer 108 becomes short, which may result in a small on-state current. Furthermore, reliability may be deteriorated. The thickness T108a is preferably 0.1 nm to 10 nm, more preferably 0.3 nm to 5 nm, even more preferably 0.5 nm to 5 nm, and even more preferably 0.5 nm to 3 nm.

[0295] It is more preferable that the layers 108a, 108b, and 108c each have crystallinity. When the layer 108a has crystallinity, the crystallinity of the layer 108b formed thereon can be increased. Similarly, when the layer 108b has crystallinity, the crystallinity of the layer 108c formed thereon can be increased.

[0296] The band gap of the first metal oxide and the band gap of the third metal oxide can be different. The band gap of the third metal oxide is preferably larger than the band gap of the first metal oxide. By using a material with a large band gap for the layer 108c located on the conductive layer 104 side functioning as a gate electrode, generation and induction of carriers in the layer 108c and at the interface between the layer 108c and the gate insulating layer (the insulating layer 106 here) can be suppressed, thereby making the transistor highly reliable. For example, generation and induction of carriers in the layer 108c and at the interface thereof due to light incident on the transistor can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor due to light.

[0297] Note that by making the band gap of the first metal oxide in the layer 208a smaller than the band gap of the third metal oxide in the layer 208c, the contact resistance between the layer 208a and the conductive layer 212a and the contact resistance between the layer 208a and the conductive layer 212b can be reduced. Therefore, the transistor 200 can have a large on-state current.

[0298] The difference between the band gap of the first metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the first metal oxide. In other words, the electron affinity of the third metal oxide is preferably smaller than the electron affinity of the first metal oxide.

[0299] The content of element M in the third metal oxide is preferably higher than the content of element M in the first metal oxide, thereby making it possible to make the band gap of the third metal oxide larger than the band gap of the first metal oxide.

[0300] When the first metal oxide, the second metal oxide, and the third metal oxide are In-M-Zn oxides, for example, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=40:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=10:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout.

[0301] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition.

[0302] The second metal oxide may be configured to not contain the element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=4:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=1:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout.

[0303] Although Figure 10A and other figures show an example in which the layer 108 and the layer 208 each have a three-layer structure, one embodiment of the present invention is not limited thereto. For example, the layer 108 may have a structure in which one or both of the layers 108a and 108c are absent, and the layer 208 may have a structure in which one or both of the layers 208a and 208c are absent. For example, as shown in Figure 12A, the layer 108 may have a two-layer structure of the layers 108b and 108c, and the layer 208 may have a two-layer structure of the layers 208b and 208c. Alternatively, as shown in Figure 12B, the layer 108 may have a two-layer structure of the layers 108a and 108b, and the layer 208 may have a two-layer structure of the layers 208a and 208b. Alternatively, the layer 108 and the layer 208 may each have a stacked structure of four or more layers.

[0304] The configurations of the layer 108 and the layer 208 shown in Configuration Example 1-4 can also be applied to other configuration examples.

[0305] 13A shows a top view of a semiconductor device 10F according to one embodiment of the present invention, FIG. 13B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 13A, and FIG. 13C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0306] The semiconductor device 10F includes a transistor 100F, a transistor 200F, and an insulating layer 110. The semiconductor device 10F differs from the semiconductor device 10 shown in FIG. 1B and the like mainly in that the transistor 100F includes a conductive layer 103, a layer 105, and an insulating layer 116, and the transistor 200F includes a conductive layer 203, a layer 205, and an insulating layer 216.

[0307] An enlarged view of transistor 100F shown in FIG. 13B is shown in FIG. 14A, and an enlarged view of transistor 200F is shown in FIG. 14B.

[0308] The transistor 100F includes a conductive layer 103 and a layer 105 between an insulating layer 110a and an insulating layer 110b. The conductive layer 103 is provided on the insulating layer 110a, and the layer 105 is provided on the top surface and side surface of the conductive layer 103. The insulating layer 110, the layer 105, and the conductive layer 103 have an opening 141 that reaches the conductive layer 112. The insulating layer 116 has a region in contact with the side surface of the insulating layer 110 and the side surface of the layer 105 in the opening 141. The insulating layer 116 is provided along the side surface of the insulating layer 110 and the side surface of the layer 105 in the opening 141, and therefore can be called a sidewall or sidewall insulating layer. The insulating layer 116 also has a region in contact with a part of the top surface of the conductive layer 112 in the opening 141. The layer 108 has a region in contact with a part of the top surface of the conductive layer 112 and the side surface of the insulating layer 116 in the opening 141. The insulating layer 116 is located between the conductive layers 103 and 105 and the layer 108 , and the conductive layers 103 and 108 are electrically insulated from each other by the insulating layer 116 .

[0309] In the transistor 100F, the layer 108 has a region that overlaps with the conductive layer 104 with the insulating layer 106 interposed therebetween and with the conductive layer 103 with the insulating layer 116 interposed therebetween. In other words, the layer 108 has a region sandwiched between the conductive layer 104 with the insulating layer 106 interposed therebetween and the conductive layer 103 with the insulating layer 116 interposed therebetween.

[0310] In the transistor 100F, the conductive layer 104 functions as a gate electrode (also referred to as a first gate electrode). Part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 103 functions as a back gate electrode (also referred to as a second gate electrode). The insulating layer 116 functions as a back gate insulating layer (also referred to as a second gate insulating layer).

[0311] By providing a back gate electrode in the transistor 100F, the potential of the back gate electrode side (back channel side) of the layer 108 is fixed, and the saturation of the Id-Vd characteristics can be improved. Furthermore, by fixing the potential of the back channel side of the layer 108, a shift in the threshold voltage can be suppressed. Therefore, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be provided.

[0312] The insulating layer 116 can be made of a material that can be used for the insulating layer 106. When a metal oxide is used for the layer 108, it is preferable to use any of the above-mentioned oxides and oxynitrides for at least a film that is in contact with the layer 108 among the films that constitute the insulating layer 116. The insulating layer 116 has a region that is in contact with the insulating layer 110. It is preferable that the insulating layer 116 has a region that is in contact with the insulating layer 110b in particular. Oxygen released from the insulating layer 110b by heat applied during the manufacturing process of the semiconductor device is supplied to the insulating layer 116. Furthermore, oxygen can be supplied to the layer 108 by releasing oxygen from the insulating layer 110b. Oxygen can be supplied to the layer 108 by supplying oxygen from the insulating layer 110b through the insulating layer 116 to the layer 108, particularly to the channel formation region, to prevent oxygen deficiency (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 100F can have favorable electrical characteristics and high reliability.

[0313] The layer 105 is located between the conductive layer 103 and the insulating layer 110 and between the conductive layer 103 and the insulating layer 116. The layer 105 has a region in contact with the top surface and side surface of the conductive layer 103. The conductivity of the layer 105 is not particularly limited. The layer 105 preferably functions as a barrier film. When the layer 105 functions as a barrier film, the conductive layer 103 can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance from increasing. Furthermore, an increase in the amount of oxygen supplied from the insulating layer 110b to the insulating layer 116 can increase the amount of oxygen supplied to the channel formation region of the layer 108. Therefore, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0314] The materials that can be used as the barrier film are as described above. The layer 105 preferably contains a component contained in the conductive layer 103. When an oxide is used for the layer 105, the layer 105 preferably contains an element contained in the conductive layer 103 and oxygen. When a nitride is used for the layer 105, the layer 105 preferably contains an element contained in the conductive layer 103 and nitrogen. When aluminum is used for the conductive layer 103, the layer 105 preferably contains aluminum and oxygen. For example, aluminum can be used for the conductive layer 103, and aluminum oxide can be used for the layer 105.

[0315] When an oxide is used for the layer 105, the layer 105 can be formed by oxidizing the conductive layer 103 or a film that will become the conductive layer 103. When a nitride is used for the layer 105, the layer 105 can be formed by nitriding the conductive layer 103 or a film that will become the conductive layer 103. Note that the boundary between the conductive layer 103 and the layer 105 may be unclear, and therefore, in Figure 14A and other figures, this boundary is indicated by a dashed line.

[0316] The treatment for oxidizing the conductive layer 103 (hereinafter also referred to as oxidation treatment) or nitriding the conductive layer 103 (hereinafter also referred to as nitriding treatment) can be, for example, plasma treatment. The atmosphere used for the oxidation treatment preferably contains oxygen. For example, the atmosphere may contain oxygen (O ２ ), nitrous oxide (N２ O), nitrogen dioxide (NO ２ An atmosphere containing one or more of nitrogen (N), carbon monoxide, and carbon dioxide can be suitably used. The atmosphere used in the nitriding treatment preferably contains nitrogen. ２ ) can be suitably used.

[0317] For example, after forming the layer that will become the conductive layer 103 and before forming the film that will become the insulating layer 110b, the conductive layer 103 is subjected to oxidation treatment or nitriding treatment to form an oxide or nitride on the surface of the layer that will become the conductive layer 103. Furthermore, after forming the opening 141 and before forming the insulating layer 116, the conductive layer 103 is subjected to oxidation treatment or nitriding treatment to form an oxide or nitride on the surface of the conductive layer 103 that faces the opening 141. This allows the layer 105 to be formed on the top surface and side surface of the conductive layer 103.

[0318] 14A , the channel length L100 of the transistor 100F is indicated by a dashed double-headed arrow. The channel length L100 corresponds to the length of the region where the insulating layer 116 and the layer 108 are in contact with each other in a cross-sectional view. When the insulating layer 116 is provided on the side surfaces of the conductive layer 103, the layer 105, and the insulating layer 110, the channel length L100 is determined by the sum of the thicknesses of the conductive layer 103, the layer 105, and the insulating layer 110, and the angle θ100 between the side surface of the insulating layer 110 on the opening 141 side and the surface where the insulating layer 110 is to be formed (here, the top surface of the conductive layer 112). Therefore, the transistor 100F can have a channel length shorter than the minimum exposure dimension of an exposure apparatus used to fabricate the transistor.

[0319] The conductive layer 103 can be electrically connected to the conductive layer 112. For example, an opening can be formed in a region of the insulating layer 110a that overlaps with the conductive layer 112, and the conductive layer 103 can be provided to cover the opening, thereby making the conductive layer 103 and the conductive layer 112 in contact with each other. The conductive layer 112 that functions as a source or drain electrode and the conductive layer 103 that functions as a back gate electrode are electrically connected to each other, so that the source or drain electrode and the back gate electrode can have the same potential. For example, when the conductive layer 112 functions as a source electrode, a shift in the threshold voltage of the transistor 100F can be suppressed. Furthermore, the reliability of the transistor 100F can be improved. Note that the conductive layer 103 can also be formed in contact with the top surface of the conductive layer 112 without providing the insulating layer 110a.

[0320] The conductive layer 103 can be electrically connected to the conductive layer 104. For example, openings are provided in regions of the insulating layers 110b, 110c, 110d, and 106 that overlap with the conductive layer 103, and the conductive layer 104 is provided to cover the openings, thereby making it possible to have a structure in which the conductive layer 103 and the conductive layer 104 are in contact with each other. By electrically connecting the conductive layer 104 that functions as a gate electrode to the conductive layer 103 that functions as a back gate electrode, the back gate electrode and the gate electrode can have the same potential, and the on-state current of the transistor 100F can be increased.

[0321] The transistor 200F includes a conductive layer 203 and a layer 205 between an insulating layer 110a and an insulating layer 110b. The conductive layer 203 is provided over the insulating layer 110a, and the layer 205 is provided on the top surface and side surface of the conductive layer 203. The insulating layer 110, the layer 205, and the conductive layer 203 have an opening 141 that reaches the conductive layer 212a. The insulating layer 216 has a region in contact with the side surface of the insulating layer 110 and the side surface of the layer 205 in the opening 241, and a region in contact with the side surface of the conductive layer 212b in the opening 243. The conductive layer 203 can be formed in the same process as the conductive layer 103. The layer 205 can be formed in the same process as the layer 105. The insulating layer 216 can be formed in the same process as the insulating layer 116. The conductive layer 203, the layer 205, and the insulating layer 216 can be described in detail in the description of the conductive layer 103, the layer 105, and the insulating layer 116, and therefore detailed description thereof will be omitted.

[0322] In the transistor 200F, the conductive layer 204 functions as a gate electrode (also referred to as a first gate electrode). Part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 203 functions as a back gate electrode (also referred to as a second gate electrode). The insulating layer 216 functions as a back gate insulating layer (also referred to as a second gate insulating layer). By providing the back gate electrode in the transistor 200F, the saturation of the Id-Vd characteristics can be improved. Furthermore, a shift in the threshold voltage can be suppressed. Therefore, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be obtained.

[0323] 13B and the like show a structure in which the transistor 100F and the transistor 200F each have a backgate electrode, but one embodiment of the present invention is not limited to this. A semiconductor device may have a structure including a transistor having a backgate electrode and a transistor not having a backgate electrode. For example, the transistor 100F may have the conductive layer 103 and the layer 105, and the transistor 200F may have the conductive layer 203 and the layer 205. In this case, the transistor 200F may have an insulating layer 216. Alternatively, the insulating layer 216 may not be provided, and the layer 208 may have a region in contact with a side surface of the insulating layer 110.

[0324] 14A, the height of the top surface of the insulating layer 116 can be the same as or approximately the same as the height of the top surface of the insulating layer 110. As shown in FIG. 14B, the height of the top surface of the insulating layer 216 can be the same as or approximately the same as the height of the top surface of the conductive layer 212b. For example, the insulating layer 116 and the insulating layer 216 can be formed by providing a film to cover the openings 141, 241, and 243, and then removing part of the film to expose the top surfaces of the insulating layer 110, the conductive layer 112, the conductive layer 212a, and the conductive layer 212b. For example, anisotropic etching can be suitably used to form the insulating layer 116 and the insulating layer 216.

[0325] 15A to 15C show configurations in which the height of the top surface of insulating layer 116 is different from the height of the top surface of insulating layer 110. FIG. 15A shows a configuration in which the height of the top surface of insulating layer 116 is lower than the height of the top surface of insulating layer 110d but higher than the height of the top surface of insulating layer 110c. FIG. 15B shows a configuration in which the height of the top surface of insulating layer 116 is lower than the height of the top surface of insulating layer 110c but higher than the height of the top surface of insulating layer 110b. As shown in FIGS. 15A and 15B, by configuring layer 108 to contact the side surface of insulating layer 110d, the contact area between layer 108 and insulating layer 110d is increased, thereby efficiently reducing the electrical resistance of region 108P (see FIG. 3A). Alternatively, as shown in FIG. 15C, the height of the top surface of insulating layer 116 may be lower than the height of the top surface of insulating layer 110b but higher than the height of the top surface of layer 105. The insulating layer 116 preferably contacts at least the entire side surface of the layer 105 on the opening 141 side.

[0326] 15D to 15G show configurations in which the height of the top surface of the insulating layer 216 is different from the height of the top surface of the conductive layer 212b. FIG. 15D shows a configuration in which the height of the top surface of the insulating layer 216 is lower than the height of the top surface of the conductive layer 212b and higher than the height of the top surface of the insulating layer 110d. FIG. 15E shows a configuration in which the height of the top surface of the insulating layer 216 is lower than the height of the top surface of the insulating layer 110d and higher than the height of the top surface of the insulating layer 110c. As shown in FIGS. 15D and 15E, by configuring the layer 208 to be in contact with the side surface of the conductive layer 212b, the contact area between the layer 208 and the conductive layer 212b is increased, thereby efficiently reducing the electrical resistance of the other of the source and drain regions of the transistor 200F. FIG. 15F also shows a configuration in which the height of the top surface of the insulating layer 216 is lower than the height of the top surface of the insulating layer 110c and higher than the height of the top surface of the insulating layer 110b. 15G, the height of the upper surface of insulating layer 216 may be lower than the height of the upper surface of insulating layer 110b and higher than the height of the upper surface of layer 205. It is preferable that insulating layer 216 contacts at least the entire side surface of layer 205.

[0327] 16A and 16B show examples of structures different from the transistors 100F and 200F shown in FIGS. 14A and 14B. A transistor 100G shown in FIG. 16A differs from the transistor 100F mainly in that an insulating layer 110a is also provided between the conductive layer 112 and the insulating layer 116. A transistor 200G shown in FIG. 16B differs from the transistor 100F mainly in that an insulating layer 110a is also provided between the conductive layer 212a and the insulating layer 216.

[0328] By providing the insulating layer 110a between the insulating layer 116 and the conductive layer 112, the insulating layer 116 and the conductive layer 112 are not in contact with each other, and therefore, it is possible to prevent oxygen from being supplied from the insulating layer 116 to the conductive layer 112, which would cause the conductive layer 112 to be oxidized and the electrical resistance of the conductive layer 112 to increase. Similarly, by providing the insulating layer 110a between the insulating layer 216 and the conductive layer 212a, the insulating layer 216 and the conductive layer 212a are not in contact with each other, and therefore, it is possible to prevent oxygen from being supplied from the insulating layer 216 to the conductive layer 212a, which would cause the conductive layer 212a to be oxidized and the electrical resistance of the conductive layer 212a to increase.

[0329] For example, a first insulating film that will become insulating layer 110a and a layer that will become conductive layer 103 are formed on the conductive layer 112. Then, a layer that will become layer 105 is formed on the surface of the layer that will become conductive layer 103, and a second insulating film that will become insulating layer 110b, a third insulating film that will become insulating layer 110c, and a fourth insulating film that will become insulating layer 110d are formed. Then, parts of the layer that will become conductive layer 103, the layer that will become layer 105, the second insulating film, the third insulating film, and the fourth insulating film are removed to form an opening that will become opening 141, thereby forming the conductive layer 103, insulating layer 110b, insulating layer 110c, and insulating layer 110d. Then, layer 105 is also formed on the surface of the conductive layer 103 that faces the opening. Then, a fifth insulating layer that will become insulating layer 116 is formed so as to cover the opening that will become opening 141. Then, a portion of the fifth insulating layer and a portion of the first insulating film are removed to expose the upper surface of insulating layer 110d and the upper surface of conductive layer 112, thereby forming opening 141 and insulating layer 116. Conductive layer 203, layer 205, and opening 241 can be formed in the same manner. Here, when forming the opening that will become opening 141, the thickness of the first insulating film at the opening may be reduced. As a result, as shown in FIG. 16A , the thickness of the region of insulating layer 110a that contacts insulating layer 116 may be thinner than the thickness of the region of insulating layer 110a that contacts conductive layer 103. Similarly, as shown in FIG. 16B , the thickness of the region of insulating layer 110a that contacts insulating layer 216 may be thinner than the thickness of the region of insulating layer 110a that contacts conductive layer 203.

[0330] The structures of the conductive layer 103, the insulating layer 116, the conductive layer 203, and the insulating layer 216 shown in Structural Example 1-5 can also be applied to other structural examples. In addition, the structures of the conductive layer 103, the layer 105, the insulating layer 116, the conductive layer 203, the layer 205, and the insulating layer 216 can also be applied to other structural examples.

[0331] 17A to 17E show circuit diagrams of a semiconductor device of one embodiment of the present invention. 18A to 20B show top views and cross-sectional views of the semiconductor device of one embodiment of the present invention. In the following, transistors 100 and 200 will be mainly used as examples of transistors included in the semiconductor device of one embodiment of the present invention. The semiconductor device of one embodiment of the present invention is not limited thereto, and can have a structure including one or more of the above-described transistors 100 to 100G and transistors 200 to 200G.

[0332] A semiconductor device according to one embodiment of the present invention includes at least two transistors, and one of the transistors has a gate, a source, or a drain electrically connected to the other of the transistors. Alternatively, the semiconductor device according to one embodiment of the present invention includes a transistor and a capacitor, and one of the transistors has a gate, a source, or a drain electrically connected to one terminal of the capacitor.

[0333] The semiconductor device of one embodiment of the present invention can be applied to a display device. The display device includes a transistor and a display element, and a source or a drain of the transistor is electrically connected to a pixel electrode of the display element.

[0334] [Configuration Example 2-1] FIG. 17A shows a circuit diagram of a semiconductor device 20 according to one embodiment of the present invention. FIG. 18A shows a top view of the semiconductor device 20 according to one embodiment of the present invention. FIG. 18B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 18A. FIG. 1C can be referred to for cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG. 18A. Furthermore, the cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG. 1C can be referred to for a cross-sectional view of the cut surface taken along dashed dotted line B5-B6 in FIG. 18A, and the cross-sectional view of the cut surface taken along dashed dotted line B3-B4 in FIG. 1C can be referred to for a cross-sectional view of the cut surface taken along dashed dotted line B7-B8.

[0335] The semiconductor device 20 includes a transistor 100, a transistor 100s, a transistor 200, a transistor 200s, and an insulating layer 110. The semiconductor device 20 is provided over a substrate 102. The above description of the transistor 100 and the transistor 200 can be referred to.

[0336] The transistor 100s includes a conductive layer 104A, an insulating layer 106, a layer 108, and a conductive layer 112A. The transistor 100s has a similar structure to that of the transistor 100. The conductive layer 104A corresponds to the conductive layer 104, and the conductive layer 112A corresponds to the conductive layer 112. The layer 108 is shared by the transistor 100 and the transistor 100s.

[0337] In the transistor 100s, the conductive layer 104A functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. In the transistor 100s, the conductive layer 112A functions as one of a source electrode and a drain electrode, and the region 108P functions as the other of the source electrode and the drain electrode. In the transistor 100s, a region of the layer 108 in contact with the conductive layer 112A functions as one of a source region and a drain region, and a region in contact with the insulating layer 110b functions as a channel formation region.

[0338] The layer 108 includes a region 108P functioning as the other of the source and drain electrodes of the transistor 100 and the other of the source and drain electrodes of the transistor 100s, a channel formation region of the transistor 100, and a channel formation region of the transistor 100s. The transistors 100 and 100s share the region 108P, thereby electrically connecting the other of the source and drain electrodes of the transistor 100 to the other of the source and drain electrodes of the transistor 100s. In the semiconductor device 20, the region 108P electrically connects the transistors 100 and 100s. Furthermore, the area occupied by the semiconductor device 20 can be reduced by sharing the layer 108 between the transistors 100 and 100s.

[0339] The transistor 200s includes a conductive layer 204A, an insulating layer 106, a layer 208A, a conductive layer 212aA, and a conductive layer 212b. The transistor 200s has a similar structure to that of the transistor 200. The conductive layer 204A corresponds to the conductive layer 204, the layer 208A corresponds to the layer 208, and the conductive layer 212aA corresponds to the conductive layer 212a. The conductive layer 212b is shared by the transistor 200 and the transistor 200s.

[0340] In the transistor 200s, the conductive layer 204A functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. In the transistor 200s, the conductive layer 212aA functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other of the source electrode and the drain electrode. In the transistor 200s, a region of the layer 208A in contact with the conductive layer 212aA functions as one of a source region and a drain region, a region in contact with the conductive layer 212b functions as the other of the source region and the drain region, and a region in contact with the insulating layer 110b functions as a channel formation region.

[0341] The conductive layer 212b functions as the other of the source and drain electrodes of the transistor 200 and the other of the source and drain electrodes of the transistor 200s. The conductive layer 212b is shared by the transistors 200 and 200s, so that the other of the source and drain electrodes of the transistor 200 is electrically connected to the other of the source and drain electrodes of the transistor 200s. In the semiconductor device 20, the conductive layer 212b electrically connects the transistors 200 and 200s. Furthermore, the area occupied by the semiconductor device 20 can be reduced by sharing the conductive layer 212b between the transistors 200 and 200s.

[0342] As described above, depending on the material used for the layer 108, the electrical resistance of the conductive layer 212b may be lower than the electrical resistance of the region 108P. When the other of the source electrode and the drain electrode functions as a wiring, if the wiring is long and the wiring resistance required for the wiring is relatively low, the transistor 200 including the conductive layer 212b can be preferably used. By using the transistor 200, a semiconductor device that operates at high speed can be obtained. On the other hand, if the wiring is short and the wiring resistance required for the wiring is relatively high, the transistor 100 can be preferably used. By using the transistor 100, a semiconductor device with a small occupation area can be obtained.

[0343] 18A and 18B , the distance between the transistor 200 and the transistor 200s can be longer than the distance between the transistor 100 and the transistor 100s. Note that one embodiment of the present invention is not limited thereto, and the distance between the transistor 100 and the transistor 100s can be the same as or longer than the distance between the transistor 200 and the transistor 200s.

[0344] A conductive layer 112, a conductive layer 112A, a conductive layer 212a, and a conductive layer 212aA are provided over a substrate 102. The conductive layer 112, the conductive layer 112A, the conductive layer 212a, and the conductive layer 212aA can be formed in the same process. For example, the conductive layer 112, the conductive layer 112A, the conductive layer 212a, and the conductive layer 212aA can be formed by forming a film that will become the conductive layer 112, the conductive layer 112A, the conductive layer 212a, and the conductive layer 212aA, and then processing the film. Alternatively, some of these layers can be formed in different processes.

[0345] An insulating layer 110 is provided on the conductive layer 112, the conductive layer 112A, the conductive layer 212a, and the conductive layer 212aA. The insulating layer 110 has an opening 141 reaching the conductive layer 112, an opening 141A reaching the conductive layer 112A, an opening 241 reaching the conductive layer 212a, and an opening 241A reaching the conductive layer 212aA. The openings 141, 141A, 241, and 241A can be formed in the same process. Alternatively, some of these openings can be formed in different processes.

[0346] The conductive layer 212b is provided over the insulating layer 110. The conductive layer 212b has a region overlapping with the conductive layer 212a and a region overlapping with the conductive layer 212aA, with the insulating layer 110 interposed therebetween. It can also be said that the insulating layer 110 has a region sandwiched between the conductive layer 212a and the conductive layer 212b, and a region sandwiched between the conductive layer 212aA and the conductive layer 212b.

[0347] The conductive layer 212b has an opening 243 that reaches the conductive layer 212a and an opening 243A that reaches the conductive layer 212aA. The opening 243 is provided in a region overlapping with the opening 241, and the opening 243A is provided in a region overlapping with the opening 241A. The opening 243 and the opening 243A can be formed in the same process. Alternatively, some of these openings can be formed in different processes.

[0348] Layer 108 is provided to cover openings 141 and 141A, layer 208 is provided to cover openings 241 and 243, and layer 208A is provided to cover openings 241A and 243A. Layer 108, layer 208, and layer 208A can be formed in the same process. Alternatively, some of these layers can be formed in different processes.

[0349] The layer 108 has a region in contact with the top surface of the conductive layer 112 and a region in contact with the side surface of the insulating layer 110 in the opening 141. The layer 108 also has a region in contact with the top surface of the conductive layer 112A and a region in contact with the side surface of the insulating layer 110 in the opening 141A. The layer 208 has a region in contact with the top surface of the conductive layer 212a and a region in contact with the side surface of the insulating layer 110 in the opening 241, and a region in contact with the side surface of the conductive layer 212b in the opening 243. The layer 208A has a region in contact with the top surface of the conductive layer 212aA and a region in contact with the side surface of the insulating layer 110 in the opening 241A, and a region in contact with the side surface of the conductive layer 212b in the opening 243A.

[0350] Preferably, the layer 208 and the layer 208A each have a region in contact with the upper surface of the conductive layer 212b. By having the layer 208b in contact with not only the side surfaces but also the upper surface of the conductive layer 212b, the contact area between the layer 208b and the conductive layer 212b is increased, and the contact resistance between the layer 208b and the conductive layer 212b can be reduced. The same applies to the layer 208 and the conductive layer 212b.

[0351] The insulating layer 106 is provided over the layer 108 , the layer 208 , the layer 208A, the conductive layer 212B, and the insulating layer 110 .

[0352] On the insulating layer 106, a conductive layer 104, a conductive layer 104A, a conductive layer 204, and a conductive layer 204A are provided.

[0353] In the opening 141, the conductive layer 104 has a region overlapping with the layer 108 with the insulating layer 106 interposed therebetween. In the opening 141A, the conductive layer 104A has a region overlapping with the layer 108 with the insulating layer 106 interposed therebetween. In the opening 241A, the conductive layer 204 has a region overlapping with the layer 208 with the insulating layer 106 interposed therebetween. In the opening 241A, the conductive layer 204A has a region overlapping with the layer 208A with the insulating layer 106 interposed therebetween. The conductive layer 104, the conductive layer 104A, the conductive layer 204, and the conductive layer 204A can be formed in the same process. Alternatively, some of these layers can be formed in different processes.

[0354] Although electrical connections between the transistors 100 and 100s and the transistors 200 and 200s are not shown in FIGS. 17A, 18A, and 18B, they may be electrically connected.

[0355] Note that the configurations of the transistors 100 and 100s and the configurations of the transistors 200 and 200s shown in Configuration Example 2-1 can also be applied to other configuration examples.

[0356] The following describes a configuration example that has some configurations different from the above-described configuration example 2-1. Note that, below, descriptions of parts that overlap with the above-described configuration example 2-1 may be omitted. Also, in the drawings shown below, parts that have the same functions as the above-described configuration example 2-1 may be hatched with the same pattern and may not be assigned reference numerals.

[0357] [Configuration Example 2-2] FIG. 17B shows a circuit diagram of a semiconductor device 20A according to one embodiment of the present invention. FIG. 19A shows a top view of the semiconductor device 20A according to one embodiment of the present invention. FIG. 19B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 19A. FIG. 1C can be referred to for cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG. 19A.

[0358] The semiconductor device 20A includes a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 20A is provided over a substrate 102. The other of the source and drain of the transistor 100 is electrically connected to the other of the source and drain of the transistor 200.

[0359] The layer 108 included in the transistor 100 has a portion over the insulating layer 110 that is in contact with the conductive layer 212b included in the transistor 200. That is, the region 108P has a portion that is in contact with the conductive layer 212b. It can also be said that the region 108P is continuous with the conductive layer 212b, or that the region 108P is continuous with the conductive layer 212b. Furthermore, it is preferable that the layer 108 be in contact with not only the side surface but also the top surface of the conductive layer 212b. An end portion of part of the layer 108 is located over the conductive layer 212b.

[0360] The contact between the region 108P and the conductive layer 212b electrically connects the other of the source and drain of the transistor 100 to the other of the source and drain of the transistor 200. The contact between the region 108P and the conductive layer 212b eliminates the need to provide a separate conductive layer that electrically connects the region 108P and the conductive layer 212b, thereby reducing the area occupied by the semiconductor device 20A.

[0361] Note that the structures of the layer 108 and the conductive layer 212b shown in Structural example 2-2 can also be applied to other structural examples.

[0362] [Configuration Example 2-3] FIG. 20A shows a top view of a semiconductor device 20B according to one embodiment of the present invention. FIG. 20B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 20A. FIG. 1C can be referred to for cross-sectional views of cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG. 20A. FIG. 17B can be referred to for a circuit diagram of the semiconductor device 20B.

[0363] The semiconductor device 20B includes a transistor 100, a transistor 200, an insulating layer 110, and a conductive layer 193. The semiconductor device 20B is provided on a substrate .

[0364] The other of the source and the drain of the transistor 100 is electrically connected to the other of the source and the drain of the transistor 200 through a conductive layer 193. The conductive layer 193 functions as a wiring that electrically connects the transistor 100 and the transistor 200 together.

[0365] The insulating layer 106 has an opening 145 that reaches the region 108P and an opening 145A that reaches the conductive layer 212b. The conductive layer 104, the conductive layer 204, and the conductive layer 193 are provided on the insulating layer 106. The conductive layer 193 is provided so as to cover the opening 145 and the opening 145A. The conductive layer 193 has a region that contacts the region 108P in the opening 145 and a region that contacts the conductive layer 212b in the opening 145A. The conductive layer 193 is electrically connected to the region 108P in the opening 145 and is electrically connected to the conductive layer 212b in the opening 145A. In other words, the region 108P is electrically connected to the conductive layer 212b via the conductive layer 193.

[0366] The conductive layer 193 can be formed, for example, in the same process as the conductive layer 104 and the conductive layer 204. Note that the conductive layer 193 can also be formed in a process different from that for the conductive layer 104 and the conductive layer 204. For example, after the insulating layer 195 is formed over the conductive layer 104 and the conductive layer 204, the openings 145 and 145A can be formed in the insulating layer 106 and the insulating layer 195, and the conductive layer 193 can be formed so as to cover the openings 145 and 145A.

[0367] Here, when a metal or an alloy is used for the wiring, the electrical resistance of the wiring can be lower in some cases than when an oxide conductor (OC) is used. When the distance between the transistor 100 and the transistor 200 is long and the wiring resistance required for electrically connecting the transistor 100 and the transistor 200 is relatively low, a metal or an alloy can be suitably used for the conductive layer 193 that functions as the wiring.

[0368] 19B and other drawings, when the distance between the transistor 100 and the transistor 200 is short and the wiring resistance required for electrically connecting the transistor 100 and the transistor 200 is relatively high, the conductive layer 193 may not be provided. When the region 108P of the transistor 100 and the conductive layer 212b of the transistor 200 are in contact with each other, the other of the source and drain of the transistor 100 can be electrically connected to the other of the source and drain of the transistor 200.

[0369] The method for electrically connecting the transistor 100 and the transistor 200 can be determined depending on the material used for the layer 108 and the wiring resistance required for the wiring electrically connecting the transistor 100 and the transistor 200 .

[0370] Note that the structures of the layer 108, the conductive layer 212b, and the conductive layer 193 shown in Structural Example 2-3 can also be applied to other structural examples.

[0371] [Configuration Example 2-4] Fig. 17C shows a circuit diagram of a semiconductor device 20C according to one embodiment of the present invention. Fig. 21A shows a top view of the semiconductor device 20C. Fig. 21B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Fig. 21A, and Fig. 21C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0372] The semiconductor device 20C includes a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 20C is provided over a substrate 102. One of the source and the drain of the transistor 100 is electrically connected to one of the source and the drain of the transistor 200.

[0373] 21A to 21C includes a conductive layer 112 instead of the conductive layer 212a shown in FIG.

[0374] The conductive layer 112 functions as one of a source electrode and a drain electrode of the transistor 100 and one of a source electrode and a drain electrode of the transistor 200. The conductive layer 112 is shared by the transistors 100 and 200, so that one of the source electrode and the drain electrode of the transistor 100 is electrically connected to one of the source electrode and the drain electrode of the transistor 200. In the semiconductor device 20C, the conductive layer 112 electrically connects the transistors 100 and 200. Furthermore, the conductive layer 112 is shared by the transistors 100 and 200, so that the area occupied by the semiconductor device 20C can be reduced.

[0375] The structure of the conductive layer 112 shown in Structural example 2-4 can also be applied to other structural examples.

[0376] [Configuration Example 2-5] FIG. 17D shows a circuit diagram of a semiconductor device 20D according to one embodiment of the present invention. FIG. 22A shows a top view of the semiconductor device 20D. FIG. 22B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 22A. FIG. 1C can be referred to for cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG. 22A.

[0377] The semiconductor device 20D includes a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 20D is provided on a substrate .

[0378] The insulating layer 106 has an opening 145B that reaches the region 108P. The conductive layer 204 is provided to cover the opening 145B. The conductive layer 204 has a region that contacts the region 108P in the opening 145B. The conductive layer 204 is electrically connected to the region 108P in the opening 145B.

[0379] By contacting the region 108P and the conductive layer 204, there is no need to provide a separate conductive layer that electrically connects the region 108P and the conductive layer 204, and therefore the area occupied by the semiconductor device 20D can be reduced.

[0380] Here, the structure in which the other of the source electrode and the drain electrode of the transistor 100 is electrically connected to the gate electrode of the transistor 200 is shown; however, one embodiment of the present invention is not limited to this. As shown in Figure 17E, the other of the source electrode and the drain electrode of the transistor 200 can be electrically connected to the gate electrode of the transistor 100. For example, an opening reaching the conductive layer 212b can be provided in the insulating layer 106, and the conductive layer 104 can be formed to cover the opening. The conductive layer 212b and the conductive layer 104 can be electrically connected to each other by being in contact with each other in the opening.

[0381] Note that the structures of the layer 108 and the conductive layer 204 shown in Structural Example 2-5 can also be applied to other structural examples.

[0382] Although the structure of a semiconductor device including a plurality of transistors has been described here, one embodiment of the present invention is not limited thereto. The semiconductor device according to one embodiment of the present invention can be suitably used for a display device. In the display device according to one embodiment of the present invention, the region 108P of the transistor can be in contact with a pixel electrode of a display element. The structure of the display device will be described in detail in Embodiment 3.

[0383] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0384] 23A to 25D , a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts similar to those described in Embodiment 1 may be omitted.

[0385] Thin films (e.g., insulating films and conductive films) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, or the like. CVD methods include a PECVD method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0386] Thin films (e.g., insulating films and conductive films) that constitute semiconductor devices can be formed by wet film-forming methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0387] When processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0388] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0389] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0390] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0391] Here, an example of a method for manufacturing the semiconductor device 10D shown in Fig. 9A to Fig. 9C will be described with reference to Fig. 23A to Fig. 25D. Fig. 23A to Fig. 25D show cross-sectional views taken along dashed line A1-A2 shown in Fig. 9A.

[0392] First, the insulating layer 109 is formed over the substrate 102. The insulating layer 109 can be formed by a sputtering method or a PECVD method.

[0393] Next, a conductive film is formed over the insulating layer 109 and processed to form the conductive layer 112 and the conductive layer 212a (FIG. 23A). The conductive film can be formed by a sputtering method.

[0394] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112 and the conductive layer 212a (FIG. 23B).

[0395] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110af, it is preferable to form the insulating film 110bf continuously using the same device.

[0396] The substrate temperature during the formation of the insulating films 110af and 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature within the above-described range during the formation of the insulating films 110af and 110bf, the amount of impurities (e.g., water and hydrogen) released from the insulating films can be reduced, and the diffusion of impurities into the layers 108 and 208 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0397] Since the insulating films 110af and 110bf are formed before the layers 108 and 208, there is no need to worry about oxygen being desorbed from the layers 108 and 208 due to heat applied during the formation of the insulating films 110af and 110bf.

[0398] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0399] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. For example, ion implantation or plasma treatment can be used as a method for supplying oxygen. Oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied by ion implantation or plasma treatment to the insulating film 110bf. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The ion implantation or plasma treatment is preferably performed in an atmosphere containing oxygen. For example, the atmosphere can be oxygen (O ２ ), nitrous oxide (N ２ O), nitrogen dioxide (NO ２ An atmosphere containing one or more of carbon monoxide, carbon dioxide, and / or nitric acid can be preferably used. Alternatively, oxygen can be supplied by generating oxygen plasma by irradiating high-frequency electromagnetic waves in an oxygen-containing atmosphere. For example, oxygen can be supplied by performing microwave treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating film 110bf through a film that suppresses oxygen desorption formed on the insulating film 110bf. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0400] In this specification, microwaves refer to electromagnetic waves with a frequency of 300 MHz or more and 300 GHz or less. A typical example of microwaves is electromagnetic waves with a frequency of 2.45 GHz. Microwave processing refers to processing using a device with a power source that generates high-density plasma using microwaves. Microwave processing can also be called microwave-excited high-density plasma processing.

[0401] After the insulating film 110bf is formed, oxygen can be supplied by performing a plasma treatment without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0402] A film 137 is preferably formed on the insulating film 110bf (FIG. 23C). The film 137 preferably contains oxygen. By forming the film 137, oxygen can be supplied to the insulating film 110bf.

[0403] The conductivity of the film 137 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 137. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 137.

[0404] The film 137 is preferably made of an oxide material containing one or more of the same elements as those of the layers 108 and 208. In particular, it is preferable to use a metal oxide applicable to the layers 108 and 208. Furthermore, by using the same material as those of the layers 108 and 208 for the film 137, a common device can be used to form the film 137 and the films that will become the layers 108 and 208, thereby increasing productivity and reducing manufacturing costs.

[0405] When forming the film 137, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the film formation gas introduced into the treatment chamber of the film formation apparatus or the oxygen partial pressure in the treatment chamber. The oxygen flow rate or oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0406] By forming the film 137 in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the film 137, and oxygen can be prevented from being released from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the layer 108 and the layer 208 by subsequent heat treatment. As a result, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0407] Heat treatment can be performed after the film 137 is formed. By performing heat treatment after the film 137 is formed, oxygen can be effectively supplied from the film 137 to the insulating film 110bf.

[0408] The temperature of the heat treatment is preferably 150° C. or higher, 200° C. or higher, 230° C. or higher, or 250° C. or higher, but lower than the strain point of the substrate, i.e., 450° C. or lower, 400° C. or lower, 350° C. or lower, or 300° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere with as low a content of hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating films 110af and 110bf as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) apparatus, or the like. By using an RTA device, the heat treatment time can be shortened.

[0409] After the film 137 is formed or after the above-described heat treatment, oxygen may be supplied to the insulating film 110bf through the film 137. The above description can be referred to for the method of supplying oxygen, and therefore detailed description thereof will be omitted.

[0410] Next, the film 137 is removed. There is no particular limitation on the method for removing the film 137, but wet etching can be suitably used. By using wet etching, etching of the insulating film 110bf can be suppressed when removing the film 137. This can suppress the thickness of the insulating film 110bf from becoming thin, and can make the thickness of the insulating layer 110b uniform.

[0411] After removing the film 137, oxygen can be further supplied to the insulating film 110bf. The above description can be referred to for the method of supplying oxygen. For example, as shown in FIG. 23D , a film 139 can be formed on the insulating film 110bf, and oxygen can be supplied to the insulating film 110bf through the film 139. For this treatment, plasma treatment in an atmosphere containing oxygen can be used. In FIG. 23D , arrows are used to schematically show how oxygen is supplied to the insulating film 110bf.

[0412] A conductive film or a semiconductor film is preferably used for the film 139. A metal oxide film, a metal film, or an alloy film can be used for the film 139. When a metal oxide film is used for the film 139 and the film 139 is formed by a sputtering method or the like in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf even during the formation of the film 139.

[0413] Because oxygen is supplied to the insulating film 110bf through the film 139, the thickness of the film 139 is preferably small. Specifically, the thickness of the film 139 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm. Typically, the thickness can be about 5 nm.

[0414] The substrate temperature during the formation of the film 139 is preferably 350° C. or less, more preferably 340° C. or less, further preferably 330° C. or less, and further preferably 300° C. or less, thereby increasing the amount of oxygen supplied to the insulating film 110bf.

[0415] By providing the film 139, when a bias voltage is applied between the pair of electrodes when oxygen is supplied, the film 139 tends to attract ionized oxygen, thereby increasing the amount of oxygen supplied to the insulating film 110bf.

[0416] A dry etching apparatus, an ashing apparatus, or a PECVD apparatus can be suitably used as the processing apparatus for supplying oxygen. In particular, it is preferable to use an ashing apparatus. When a bias voltage is applied between a pair of electrodes of the processing apparatus, the bias voltage can be set to, for example, 10 V or more and 1 kV or less. Alternatively, the bias power density can be set to, for example, 1 W / cm. ２ More than 5W / cm ２ It can be as follows:

[0417] Next, the film 139 is removed (FIG. 23E). The film 139 can be preferably removed by wet etching.

[0418] By supplying oxygen to the insulating film 110bf that becomes the insulating layer 110b, the amount of oxygen contained in the insulating layer 110b increases, and the amount of oxygen supplied from the insulating layer 110b to the layer 108 and the layer 208 can be increased, so that even the transistors 100 and 200 with short channel lengths can exhibit good electrical characteristics.

[0419] Next, an insulating film 110cf that will become the insulating layer 110c and an insulating film 110df that will become the insulating layer 110d are formed on the insulating film 110bf ( FIG. 24A ). The formation of the insulating film 110cf and the insulating film 110df can be performed by referring to the description of the formation of the insulating film 110af and the insulating layer 109, and therefore detailed description thereof will be omitted.

[0420] Next, a conductive film 212f that will become the conductive layer 212b is formed over the insulating film 110df (FIG. 24B). The conductive film 212f can be preferably formed by sputtering.

[0421] Next, the conductive film 212f is processed to form a conductive layer 212B (FIG. 24C). The conductive layer 212B will later become the conductive layer 212b. The conductive layer 212B can be preferably formed by, for example, wet etching.

[0422] Subsequently, a part of the conductive layer 212B is removed to form a conductive layer 212b having an opening 243. The conductive layer 212b can be preferably formed by wet etching. The opening 243 is provided in a region overlapping with the conductive layer 212a.

[0423] Next, parts of the insulating films 110af, 110bf, 110cf, and 110df are removed to form the insulating layer 110 having openings 141 and 241 ( FIG. 24D ). The openings 141 are provided in regions overlapping with the conductive layer 112. The conductive layer 112 is exposed by forming the openings 141. The openings 241 are provided in regions overlapping with the openings 243. The conductive layer 212a is exposed by forming the openings 241. Dry etching can be suitably used to form the insulating layer 110.

[0424] The openings 141 and 241 can be formed using, for example, the resist mask used to form the opening 243. Specifically, a resist mask is formed over the insulating film 110df and the conductive layer 212B, a part of the conductive layer 212B is removed using the resist mask to form the opening 243, and the openings 141 and 241 can be formed by removing parts of the insulating films 110af, 110bf, 110cf, and 110df using the resist mask. Using the same resist mask can improve productivity. Note that the openings 141 and 241 can also be formed using a resist mask different from the resist mask used to form the opening 243.

[0425] Next, a film 108f that will become the layer 108 and the layer 208 is formed so as to cover the openings 141, 241, and 243 ( FIG. 25A ). The film 108f is provided in contact with the top surface and side surfaces of the insulating layer 110, the top surface of the conductive layer 112, the top surface of the conductive layer 212a, and the top surface and side surfaces of the conductive layer 212b.

[0426] The film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the film 108f is preferably formed by an ALD method. Because the ALD method has high coverage, it can be suitably used to form the film 108f that covers the openings 141, 241, and 243. By using the ALD method, the film 108f can be formed with high coverage on the side surfaces of the insulating layer 110. Furthermore, the ALD method makes it easy to control the film formation rate, so a thin film can be formed with a high yield. Therefore, the ALD method can be suitably used when the film 108f is thin. Thermal ALD or PEALD can be used as the ALD method. PECVD can also be used to form the film 108f. When a metal oxide is used for the film 108f, the film 108f can be referred to as a metal oxide film.

[0427] The film 108f is preferably a dense film with as few defects as possible. Furthermore, the film 108f is preferably a high-purity film in which impurities including hydrogen elements are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the film 108f.

[0428] When the metal oxide film is formed, oxygen gas is preferably used. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0429] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the layers 108 and 208 in a later process, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0430] A mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used to form a metal oxide film. Note that the higher the oxygen flow rate or oxygen partial pressure when forming the metal oxide film, the higher the crystallinity of the metal oxide film, resulting in a highly reliable transistor. On the other hand, the lower the oxygen flow rate or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, resulting in a transistor with a large on-state current.

[0431] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the grain boundaries become recombination centers, and carriers are captured, which may reduce the on-current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline varies depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure depending on the composition of the metal oxide film.

[0432] The higher the substrate temperature during formation of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which leads to a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film, which leads to a transistor with a large on-state current.

[0433] The substrate temperature during the formation of the metal oxide film is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to 140° C. is preferable because it increases productivity. Furthermore, by forming the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0434] If the substrate temperature is too high, the metal oxide film may have a polycrystalline structure, so it is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film.

[0435] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0436] For example, when forming an In—Ga—Zn oxide, three precursors, namely, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, namely, a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0437] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0438] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0439] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0440] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0441] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0442] Oxidizing agents include, for example, ozone, oxygen, and water.

[0443] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the flow time of the source gases, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film can be controlled. Furthermore, by adjusting these, it is also possible to form a metal oxide film whose composition changes continuously.

[0444] Before forming the metal oxide film, it is preferable to perform at least one of a treatment for removing impurities (for example, water, hydrogen, and organic substances) adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110. By performing plasma treatment containing nitrous oxide gas, oxygen can be supplied while suitably removing organic substances on the surface of the insulating layer 110. After such treatment, it is preferable to form a metal oxide film successively without exposing the surface of the insulating layer 110 to the air.

[0445] When the layer 108 and the layer 208 have a stacked structure, it is preferable that after a metal oxide film is formed first, the next metal oxide film is formed successively without exposing the surface of the first metal oxide film to the air.

[0446] When the layers 108 and 208 each have a stacked structure, all of the layers constituting the layers 108 and 208 can be formed by the same deposition method (e.g., sputtering or ALD). Alternatively, different deposition methods can be used for each layer. For example, when the layers 108 and 208 each have a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, the first metal oxide layer can be deposited by sputtering, and the second metal oxide layer can be deposited by ALD.

[0447] Subsequently, the film 108f is processed into an island shape to form the layer 108 and the layer 208 (FIG. 25B).

[0448] The layers 108 and 208 can be preferably formed by wet etching. At this time, a portion of the conductive layer 212b in a region that does not overlap with the layer 208 may be etched and thinned. Similarly, a portion of the insulating layer 110 in a region that does not overlap with any of the layers 108, 208, and 212b may be etched and thinned. For example, a portion of the insulating layer 110d in the insulating layer 110 may be removed by etching, exposing a portion of the surface of the insulating layer 110c. Note that, in etching the film 108f, using a material with a high selectivity for the insulating layer 110d can prevent the insulating layer 110d from becoming thin.

[0449] Heat treatment is preferably performed after the film 108f is formed or after the film 108f is processed into the layer 108 and the layer 208. The heat treatment can remove impurities (e.g., hydrogen and water) contained in or adsorbed to the surface of the film 108f or the layer 108 and the layer 208. The heat treatment may also improve the film quality of the film 108f or the layer 108 and the layer 208 (e.g., reduce defects or increase crystallinity).

[0450] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the film 108f or the layer 108 and the layer 208. In this case, it is more preferable to perform the heat treatment before processing into the layer 108 and the layer 208. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0451] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a later step in which heat is applied (e.g., a film formation step) may also serve as this heat treatment.

[0452] After the film 108f is formed or after the film 108f is processed into the layer 108 and the layer 208, oxygen can be supplied to the film 108f or the layer 108 and the layer 208. This can eliminate oxygen vacancies (V Ｏ ) and V ＯH can be reduced. The above description can be referred to for the method of supplying oxygen. For example, microwave treatment can be performed in an oxygen-containing atmosphere. Furthermore, by supplying oxygen while heating the substrate, the crystallinity of the film 108f or the layer 108 and the layer 208 can be improved, and impurities (e.g., hydrogen and water) contained in or adsorbed on the surface of the film 108f or the layer 108 and the layer 208 can be removed. The substrate temperature during heating is preferably higher than room temperature (e.g., 25°C) and not higher than 600°C, more preferably 100°C to 600°C, and even more preferably 300°C to 450°C. The substrate temperature is preferably 100°C to 700°C, and even more preferably 300°C to 450°C. This can further improve the crystallinity of the film 108f or the layer 108 and the layer 208. When the substrate temperature increases with the oxygen supply treatment, the treatment can sometimes improve the crystallinity and remove impurities.

[0453] Subsequently, the insulating layer 106 is formed to cover the layer 108, the layer 208, the conductive layer 212b, and the insulating layer 110 (FIG. 25C). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0454] When an oxide semiconductor is used for the layer 108 and the layer 208, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 suppresses oxygen diffusion, thereby suppressing oxygen desorption from the layer 108 and the layer 208, and oxygen vacancies (V Ｏ In addition, oxygen contained in the layers 108 and 208 is prevented from diffusing into the conductive layers 104 and 204 through the insulating layer 106, thereby preventing the conductive layers 104 and 204 from being oxidized. As a result, a highly reliable transistor can be obtained, which exhibits favorable electrical characteristics.

[0455] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the layers 108 and 208, causing oxygen vacancies (VＯ ) and V Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the layer 108 and the layer 208. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0456] Before forming the insulating layer 106, plasma treatment can be performed on the surfaces of the layers 108 and 208. The plasma treatment can reduce impurities such as water adsorbed to the surfaces of the layers 108 and 208. Therefore, impurities at the interfaces between the layers 108 and 208 and the insulating layer 106 can be reduced, resulting in a highly reliable transistor. This is particularly suitable for the case where the surfaces of the layers 108 and 208 are exposed to the air between the formation of the layers 108 and 208 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere containing, for example, oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. Furthermore, the plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0457] After the insulating layer 106 is formed, oxygen can be supplied to the insulating layer 106. The above description can be referred to for the method of supplying oxygen. For example, microwave treatment can be performed in an atmosphere containing oxygen. The oxygen supplied to the insulating layer 106 is further supplied to the layer 108 and the layer 208, and oxygen vacancies (V Ｏ ) and V ＯH can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained. Furthermore, by supplying oxygen while heating the substrate, impurities (e.g., hydrogen and water) contained in or adsorbed to the surface of the insulating layer 106 can be removed and defects in the insulating layer 106 can be reduced. By reducing defects in the insulating layer 106, which functions as a gate insulating layer for the transistors 100 and 200, the transistors 100 and 200 can be made to have good electrical characteristics. For the substrate temperature during heating, the description of the heat treatment described above can be referred to. Note that when the substrate temperature increases due to the treatment of supplying oxygen, the treatment can sometimes remove impurities and reduce defects.

[0458] Subsequently, a conductive film is formed over the insulating layer 106 and processed to form the conductive layers 104 and 204 ( FIG. 25D ). The conductive film can be formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0459] Next, an insulating layer 195 is formed (FIG. 9A). The insulating layer 195 can be preferably formed by PECVD.

[0460] Through the above steps, the semiconductor device 10D of one embodiment of the present invention can be manufactured.

[0461] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0462] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0463] The display device of the present embodiment can be a high-definition display device, and therefore can be used, for example, as a display unit of a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit of a wearable device that can be worn on the head, such as a VR device such as a head-mounted display (HMD) or an AR device such as a glasses-type device.

[0464] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0465] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0466] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0467] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0468] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel has a configuration in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element (also called a display device) and an opposing substrate.

[0469] <Configuration Example 1 of Display Device> FIG. 26A shows a perspective view of a display device 50A.

[0470] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 26A, the substrate 152 is indicated by a dashed line.

[0471] The display device 50A has a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Fig. 26A shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 26A can also be said to be a display module having the display device 50A, an IC, and an FPC.

[0472] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 26A shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0473] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0474] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0475] 26A shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. The IC 173 may be, for example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method, or the like.

[0476] The semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 162 and the circuit portion 164 of the display device 50A, for example.

[0477] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0478] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 210. Fig. 26A shows an enlarged view of one pixel 210.

[0479] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0480] The pixel 210 shown in FIG. 26A includes a pixel 230R that emits red light, a pixel 230G that emits green light, and a pixel 230B that emits blue light. A full-color display can be achieved by configuring one pixel 210 with the pixels 230R, 230G, and 230B. The pixels 230R, 230G, and 230B each function as subpixels. The display device 50A shown in FIG. 26A also illustrates an example in which the pixels 230 functioning as subpixels are arranged in a stripe array. The number of subpixels constituting one pixel 210 is not limited to three and may be four or more. For example, the pixel 210 may have four subpixels that emit R, G, B, and white (W) light. Alternatively, the pixel 210 may have four subpixels that emit R, G, B, and Y light.

[0481] Each of the pixel 230R, the pixel 230G, and the pixel 230B includes a display element and a circuit that controls the driving of the display element.

[0482] Various elements can be used as the display element, including, for example, a liquid crystal element (also called a liquid crystal device) and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements using microcapsules, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods, etc. Furthermore, a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials may also be used.

[0483] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0484] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0485] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0486] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0487] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0488] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0489] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0490] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0491] 26B is a block diagram illustrating a display device 50A. The display device 50A has a display unit 162 and a circuit unit 164. The display unit 162 has a plurality of periodically arranged pixels 230 (pixels 230[1,1] to 230[m,n], where m and n are each independently an integer of 2 or greater). The circuit unit 164 has a first drive circuit unit 231 and a second drive circuit unit 232.

[0492] The circuit included in the first drive circuit unit 231 functions as, for example, a scanning line drive circuit. The circuit included in the second drive circuit unit 232 functions as, for example, a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 231 across the display unit 162. Some kind of circuit may be provided at a position facing the second drive circuit unit 232 across the display unit 162.

[0493] The circuit portion 164 can include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit. A transistor, a capacitor, or the like can be used for the circuit portion 164. The transistors included in the circuit portion 164 may be formed in the same process as the transistors included in the pixel 230.

[0494] The display device 50A has wirings 236 that are arranged parallel or approximately parallel to each other and whose potentials are controlled by a circuit included in a first drive circuit unit 231, and wirings 238 that are arranged parallel or approximately parallel to each other and whose potentials are controlled by a circuit included in a second drive circuit unit 232. Note that Fig. 26B shows an example in which wirings 236 and 238 are connected to pixel 230. However, wirings 236 and 238 are just an example, and wirings connected to pixel 230 are not limited to wirings 236 and 238.

[0495] The semiconductor device of one embodiment of the present invention includes a vertical transistor (VFET) having a submicron channel length and a large on-state current. An oxide semiconductor (OS) can be preferably used for a channel formation region of the transistor, thereby enabling the transistor to have a small off-state current. The semiconductor device of one embodiment of the present invention can be preferably used for one or both of the display portion 162 and the circuit portion 164. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all the transistors included in the display device can be OS transistors. By using OS transistors for all the transistors included in the display device, it is possible to reduce manufacturing costs.

[0496] 27A shows an example of the configuration of the pixel 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61.

[0497] The pixel circuit 51 includes a transistor 52A, a transistor 52B, and a capacitor 53. The pixel circuit 51 is a 2Tr1C pixel circuit including two transistors and one capacitor. Note that there is no particular limitation on the pixel circuit that can be applied to the display device of one embodiment of the present invention.

[0498] The anode of the light-emitting device 61 is electrically connected to one of the source and drain of the transistor 52B and one electrode of the capacitor 53. The other of the source and drain of the transistor 52B is electrically connected to a wiring ANO. The gate of the transistor 52B is electrically connected to one of the source and drain of the transistor 52A and the other electrode of the capacitor 53. The other of the source and drain of the transistor 52A is electrically connected to a wiring SL. The gate of the transistor 52A is electrically connected to a wiring GL. The cathode of the light-emitting device 61 is electrically connected to a wiring VCOM.

[0499] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring that applies a potential for supplying a current to the light-emitting device 61. The transistor 52A has a function of controlling the conduction or non-conduction state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0500] The transistor 52A functions as a selection transistor for controlling the selection state of the pixel 230. The transistor 52B functions as a drive transistor for controlling the amount of current flowing through the light-emitting device 61. The capacitance element 53 has a function of maintaining the gate potential of the transistor 52B. The intensity of light emitted by the light-emitting device 61 is controlled in accordance with an image signal supplied to the gate of the transistor 52B.

[0501] The above-described semiconductor device can be used for the pixel circuit 51. This allows the area occupied by the pixel circuit 51 to be reduced, resulting in a high-resolution display device. Furthermore, when the distance between a transistor and an element (e.g., a transistor and a capacitor) or a wiring electrically connected to the transistor is short, one of the transistors 100 to 100G can be preferably used as the transistor. This can further improve the resolution. On the other hand, when the distance between a transistor and an element or wiring electrically connected to the transistor is long, one of the transistors 200 to 200G can be preferably used as the transistor. This allows a display device that operates at high speed.

[0502] A display device with high luminance can be obtained by using any of the transistors 100 to 100G and the transistors 200 to 200G, which have a short channel length and a large on-state current, as the transistor 52A functioning as a selection transistor. The transistor 52B functioning as a driving transistor preferably has high saturation. For example, any of the transistors 100F, 100G, 200F, and 200G, which have a back gate electrode, can be suitably used as the transistor 52B. Note that a transistor without a back gate electrode can also be used as the transistor 52B.

[0503] By using a plurality of transistors and capacitors in a pixel circuit, a high-performance display device can be provided. By applying the semiconductor device of one embodiment of the present invention, the occupied area can be reduced even when the number of transistors and capacitors is increased, and a high-performance and high-resolution display device can be provided. For example, a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be provided.

[0504] Since the semiconductor device according to one embodiment of the present invention can occupy a small area, the aperture ratio of a pixel in a bottom-emission display device can be increased. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0505] In this specification and the like, the aperture ratio refers to the ratio of the area of ​​the region through which light is emitted to the area of ​​the pixel.

[0506] 27B shows an example of a configuration different from that of the pixel 230 shown in FIG. 27A. The pixel 230 has a pixel circuit 51A and a light-emitting device 61.

[0507] 27A in that the pixel circuit 51A includes a transistor 52C. The pixel circuit 51A includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The pixel circuit 51A is a 3Tr1C type pixel circuit including three transistors and one capacitor.

[0508] One of the source and drain of the transistor 52C is electrically connected to one of the source and drain of the transistor 52B. The other of the source and drain of the transistor 52C is electrically connected to a wiring V0. For example, a reference potential is supplied to the wiring V0. The gate of the transistor 52C is electrically connected to a wiring GL.

[0509] The transistor 52C has a function of controlling conduction or non-conduction between the wiring V0 and one of the source electrode and the drain electrode of the transistor 52B based on the potential of the wiring GL. The reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source potential of the transistor 52B.

[0510] The wiring V0 can be used to obtain a current value that can be used to set pixel parameters. Specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter and output to the outside.

[0511] A backgate can be provided in some or all of the transistors included in the pixel circuit 51. A pixel circuit 51B shown in FIG. 27C illustrates a configuration in which the transistor 52B in the pixel circuit 51 shown in FIG. 27A has a backgate, which is electrically connected to one of the source and drain of the transistor 52B. A pixel circuit 51C shown in FIG. 27D illustrates a configuration in which the transistor 52B in the pixel circuit 51A shown in FIG. 27B has a backgate, which is electrically connected to one of the source and drain of the transistor 52B. This can improve reliability. Note that the backgate of the transistor 52B can also be electrically connected to the gate of the transistor 52B. This can increase the on-state current of the transistor 52B.

[0512] 28A shows an example of a configuration different from the above-described pixel 230. The pixel 230 has a pixel circuit 51D and a light-emitting device 61.

[0513] The pixel circuit 51D includes a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, a capacitor C11, and a capacitor C12. The pixel circuit 51D is a 6Tr2C type pixel circuit including six transistors and two capacitors.

[0514] The anode of the light-emitting device 61 is electrically connected to one of the source and drain of the transistor M15. The cathode of the light-emitting device 61 is electrically connected to the wiring VCOM. The other of the source and drain of the transistor M15 is electrically connected to one of the source and drain of the transistor M12, one of the source and drain of the transistor M13, one of the source and drain of the transistor M16, one electrode of the capacitor C11, and one electrode of the capacitor C12. The gate of the transistor M12 is electrically connected to one of the source and drain of the transistor M11, the other of the source and drain of the transistor M13, and the other electrode of the capacitor C11. The backgate of the transistor M12 is electrically connected to one of the source and drain of the transistor M14 and the other electrode of the capacitor C12.

[0515] The other of the source and drain of transistor M11 is electrically connected to a wiring SL. The other of the source and drain of transistor M12 is electrically connected to a wiring ANO. The other of the source and drain of transistor M14 is electrically connected to a wiring V0. The other of the source and drain of transistor M16 is electrically connected to a wiring V1. For example, a constant potential is supplied to the wiring V1. The gates of transistors M11 and M16 are electrically connected to a wiring GL1. The gates of transistors M13 and M14 are electrically connected to a wiring GL2. The gate of transistor M15 is electrically connected to a wiring GL3.

[0516] The transistor M11 functions as a selection transistor that controls the conductive state or non-conductive state between the gate of the transistor M12 and the wiring SL. The transistor M12 functions as a drive transistor that controls the current flowing through the light-emitting device 61. The transistor M14 supplies the potential of the wiring V0 to the back gate of the transistor M12. The threshold voltage of the transistor M12 can be controlled by supplying a constant potential to the back gate of the transistor M12. The capacitor C11 maintains the gate potential of the transistor M12. The capacitor C12 maintains the back gate potential of the transistor M12. The pixel circuit 51D has a so-called internal threshold voltage correction function that corrects the threshold voltage of the transistor M12 using the back gate. Specifically, the capacitor C12 maintains a back gate potential such that the threshold voltage of the transistor M12 is 0 V. This makes it possible to correct the threshold voltage of the transistor M12 to a constant value of 0 V or near 0 V, regardless of variations in the threshold voltage of the transistor or deterioration over time.

[0517] 28B shows an example of a configuration different from the above-described pixel 230. The pixel 230 includes a pixel circuit 51E and a liquid crystal device 62.

[0518] The pixel circuit 51E includes a transistor 52A and a capacitor 53. One of the source and drain of the transistor 52A is electrically connected to a wiring SL, and the gate of the transistor 52A is electrically connected to a wiring GL. The other of the source and drain of the transistor 52A is electrically connected to one terminal of the capacitor 53 and the liquid crystal device 62. The other terminal of the capacitor 53 is electrically connected to a wiring VCOM.

[0519] 28C, a pixel circuit 51F may have a back gate in the transistor 52A, in which the back gate of the transistor 52A is electrically connected to the gate.

[0520] Figure 29A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0521] 29A includes a transistor 207D, a transistor 205R, a transistor 205G, a transistor 207G, a transistor 207B, a light-emitting element 130R, a light-emitting element 130G, a light-emitti...

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