Display device

Abstract

A display device according to the present disclosure comprises: a plurality of row scanning lines; a plurality of column data lines arranged so as to intersect the plurality of row scanning lines; and a plurality of pixels arranged at the intersections between the plurality of row scanning lines and the plurality of column data lines. Each pixel has a pixel electrode and a pixel circuit for applying a voltage to the pixel electrode. The pixel circuit has a plurality of storage elements and a plurality of transistors.

Description

display device

[0001] The present disclosure relates to a display device.

[0002] Patent Document 1 proposes a method of configuring a digitally driven pixel circuit from a data holding section made up of three transistors and a data output section made up of three transistors.

[0003] JP 2013-101285 A

[0004] In the technology described in Patent Document 1, data is held by a single inverter, making it difficult to stably hold data. Also, the number of transistors is large, making miniaturization difficult.

[0005] Therefore, it is desirable to provide a display device that can stably hold data in pixel circuits and that can be easily miniaturized.

[0006] A display device according to one embodiment of the present disclosure comprises a plurality of row scanning lines, a plurality of column data lines arranged to intersect with the plurality of row scanning lines, and a plurality of pixels arranged at the intersections of the plurality of row scanning lines and the plurality of column data lines, each pixel having a pixel electrode and a pixel circuit that applies a voltage to the pixel electrode, and the pixel circuit having a plurality of memory elements and a plurality of transistors.

[0007] In a display device according to an embodiment of the present disclosure, data can be held by a plurality of memory elements.

[0008] FIG. 1 is a circuit diagram schematically illustrating an example configuration of a display device according to a first embodiment of the present disclosure. FIG. 2 is a circuit diagram illustrating an example configuration of a pixel circuit in the display device according to the first embodiment. FIG. 3 is a timing chart illustrating an example operation of a pixel circuit in the display device according to the first embodiment. FIG. 4 is a timing chart illustrating an example operation of a pixel circuit in the display device according to the first embodiment. FIG. 5 is a circuit diagram illustrating an example configuration of a pixel circuit in a display device according to a second embodiment. FIG. 6 is a timing chart illustrating an example operation of a pixel circuit in the display device according to the second embodiment. FIG. 7 is a timing chart illustrating an example operation of a pixel circuit in the display device according to the second embodiment. FIG. 8 is a circuit diagram illustrating an example configuration of a pixel circuit in a display device according to a third embodiment. FIG. 9 is a timing chart illustrating an example operation of a pixel circuit in the display device according to the third embodiment. FIG. 10 is a timing chart illustrating an example operation of a pixel circuit in the display device according to the third embodiment.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 0. Comparative Example 1. First Embodiment (FIGS. 1 to 4) 1.1 Configuration 1.2 Operation 1.3 Effects 2. Second Embodiment (FIGS. 5 to 7) 2.1 Configuration 2.2 Operation 2.3 Effects 3. Third Embodiment (FIGS. 8 to 10) 3.1 Configuration 3.2 Operation 3.3 Effects 4. Other Embodiments

[0010] <0. Comparative Example> (Overview and Problems of a Display Device According to a Comparative Example) A display device according to an embodiment of the present disclosure is applicable to semiconductor display devices and spatial light modulation devices, and is particularly suitable for digitally driven liquid crystal display devices used in reflective liquid crystal display devices that perform display based on digital gradation signals.

[0011] In recent years, LCOS (Liquid Crystal on Silicon) liquid crystal display devices have become increasingly popular as the core components of projectors and spatial modulation devices that generate desired images by modulating the phase and intensity of light. LCOS display methods include analog drive, in which analog signals are applied directly to the liquid crystal as voltage, and digital drive, in which digital pulse-width-modulated (PWM) video signals are applied to pixel electrodes. Analog drive pixels require switching elements, such as semiconductor transistors such as CMOS (Complementary Metal Oxide Semiconductor), and storage capacitors to maintain voltage. Analog drive requires transistors with high voltage resistance and low leakage characteristics, making high-resolution and high-speed operation difficult. Incidentally, phase modulation devices that generate desired images by modulating the phase of a spatial light modulator require pixel miniaturization because the diffraction angle is determined by pixel size. Digital drive does not require high-voltage transistors, allowing for smaller transistor sizes than analog drive circuits. However, a typical digital driving circuit requires a latch circuit such as a flip-flop, and therefore the number of transistors is extremely large, at around 10, making further miniaturization difficult.

[0012] Meanwhile, Patent Document 1 (JP 2013-101285 A) proposes a method of configuring a digitally driven pixel circuit with a data retention section made up of three transistors and a data output section made up of three transistors. By using this solution, it is possible to reduce the number of transistors in the digital drive circuit from 10 to 6.

[0013] However, in the technology described in Patent Document 1, data is held by an inverter. Generally, data can be held stably by configuring a latch circuit such as a flip-flop. Therefore, it is difficult to hold data stably with a single inverter. Furthermore, the number of transistors cannot be reduced sufficiently, making miniaturization difficult.

[0014] Therefore, there is a demand for the development of a display device that is capable of stably holding data in pixel circuits, further reducing the number of transistors, and facilitating miniaturization.

[0015] 1. First Embodiment [1.1 Configuration] FIG. 1 is a circuit diagram that schematically illustrates an example configuration of a display device 10 according to a first embodiment of the present disclosure.

[0016] The display device 10 according to the first embodiment includes a display area 10a having a plurality of pixels P, a scanning line driving circuit 110 and a signal line driving circuit 120 arranged around the periphery of the display area 10a, a plurality of row scanning lines WWL and a plurality of column data lines DL. In addition, a timing controller (not shown) and a video signal processing unit (not shown) for performing various signal processing may also be provided.

[0017] The plurality of row scanning lines WWL and the plurality of column data lines DL are arranged so as to intersect with each other. The plurality of row scanning lines WWL are arranged in parallel, for example, along the vertical direction. The plurality of column data lines DL are arranged in parallel, for example, along the horizontal direction. The signal line driving circuit 120 supplies voltages based on video signals to the plurality of pixels P sequentially in the horizontal direction via the plurality of column data lines DL. The scanning line driving circuit 110 supplies gate signals (scanning signals) to the plurality of pixels P sequentially in the vertical direction via the plurality of row scanning lines WWL.

[0018] The pixels P are arranged at positions corresponding to the intersections of the row scanning lines WWL and the column data lines DL, and are arranged two-dimensionally in a matrix as a whole. Each pixel P has a pixel circuit.

[0019] In this display device 10, the pixels P are selected line-sequentially by the scanning line driving circuit 110 based on an externally input video signal, and a voltage corresponding to the video signal is supplied to each pixel P by the signal line driving circuit 120. In this way, the pixels P are driven to display an image.

[0020] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel circuit in the display device 10 according to the first embodiment.

[0021] 2 shows an example of the configuration of a pixel circuit when the display device 10 is a liquid crystal display device. Each pixel P has a liquid crystal LC, and a pixel electrode 31 and a common electrode 41 arranged opposite each other to apply a voltage to the liquid crystal LC. A common voltage common to each pixel P is applied to the common electrode 41 via a common voltage line VCOM. A voltage corresponding to a video signal is applied to the pixel electrode 31 via the pixel circuit.

[0022] The pixel circuit in the first embodiment is a digital driving circuit and includes a plurality of memory elements and a plurality of transistors. The pixel circuit in the first embodiment includes a first memory element r0 and a second memory element r1 as the plurality of memory elements. The pixel circuit in the first embodiment includes a first transistor nt1 and a second transistor nt2 as the plurality of transistors.

[0023] The first memory element r0 and the second memory element r1 are each a nonvolatile variable resistance element. Here, the variable resistance element may be, for example, a memory element constituting a resistive random access memory (ReRAM) or a memory element constituting a phase change memory (PCM). For example, the variable resistance element may be a magnetic tunnel junction (MTJ) element, which is a component of a magnetoresistive random access memory (MRAM).

[0024] The first transistor nt1 and the second transistor nt2 each have a gate electrode, a first terminal, and a second terminal. The first terminal may be a source terminal or a drain terminal. The second terminal may be a drain terminal if the first terminal is a source terminal, or may be a source terminal if the first terminal is a drain terminal. The first transistor nt1 and the second transistor nt2 may each be an N-channel MOS transistor (NMOS transistor) or a P-channel MOS transistor (PMOS transistor).

[0025] The first memory element r0 and the second memory element r1 each have a first terminal and a second terminal. Each column data line DL shown in FIG. 1 has a bit line and a source line SL. The bit lines include a first bit line BL and a second bit line xBL.

[0026] A first terminal of the first transistor nt1 is connected to the source line SL. A second terminal of the first transistor nt1 is connected to the second terminal of the first memory element r0, the second terminal of the second memory element r1, and the gate electrode of the second transistor nt2. A gate electrode of the first transistor nt1 is connected to the row scanning line WWL.

[0027] A first terminal of the first memory element r0 is connected to the first bit line BL, and a first terminal of the second memory element r1 is connected to the second bit line xBL.

[0028] A first terminal of the second transistor nt2 is connected to the voltage line VDD. A second terminal of the second transistor nt2 is connected to the pixel electrode 31. A gate electrode of the second transistor nt2 is connected to the second terminal of the first transistor nt1 and the second terminals of the first memory element r0 and the second memory element r1.

[0029] [1.2 Operation] Figures 3 and 4 are timing charts showing an example of the operation of the pixel circuit in the display device 10 according to the first embodiment. Figure 3 shows a timing chart when a voltage L (low) is applied to the pixel electrode 31. Figure 4 shows a timing chart when a voltage H (high) is applied to the pixel electrode 31. In Figures 3 and 4, (A) shows the source line SL, (B) the row scanning line WWL, (C) the first bit line BL, (D) the second bit line xBL, (E) the voltage line VDD, (F) the node n0, and (G) the voltage of the liquid crystal LC (pixel electrode 31).

[0030] In the pixel circuit according to the first embodiment, data is written to the first memory element r0 and the second memory element r1 at the timing when the first transistor nt1 operates, and a voltage corresponding to the written data is applied from the second transistor nt2 to the pixel electrode 31. Data of mutually opposite values ​​is written to the first memory element r0 and the second memory element r1.

[0031] In the pixel circuit according to the first embodiment, first, a digital signal from the source line SL (FIGS. 3 and 4A) is received by the first transistor nt1 by activating the row scanning line WWL (FIGS. 3 and 4B), and the digital signal is written to the first memory element r0 and the second memory element r1. At this time, since the first bit line BL and the second bit line xBL are at opposite voltages (FIGS. 3 and 4C and 4D), data of opposite values ​​is written to the first memory element r0 and the second memory element r1.

[0032] Then, a voltage corresponding to the written data is applied from the second transistor nt2 to the pixel electrode 31. For example, when applying a voltage H to the pixel electrode 31, the row scanning line WWL is deactivated (FIG. 4B), the first transistor nt1 is deactivated, and the first bit line BL connected to the first memory element r0 is activated (FIG. 4C). At this time, the second bit line xBL has a voltage opposite to that of the first bit line BL (FIG. 4D). At this time, the voltage at node n0 between the first memory element r0 and the second memory element r1 (FIG. 4F) is applied to the gate electrode of the second transistor nt2. As a result, a voltage corresponding to the voltage at node n0 is applied to the liquid crystal LC (pixel electrode 31) via the second transistor nt2 (FIG. 4G).

[0033] [1.3 Effects] As described above, according to the display device 10 according to the first embodiment, data can be held by the first memory element r0 and the second memory element r1. This makes it possible to provide the display device 10 that can stably hold data in the pixel circuit and facilitates miniaturization.

[0034] According to the display device 10 of the first embodiment, a pixel circuit can be configured with two transistors and two memory elements, which enables miniaturization of the pixel P. Furthermore, by using two memory elements, a storage capacitor with a large area penalty or a latch circuit such as a flip-flop is not required. Furthermore, by using resistance change elements as multiple memory elements, data can be stably stored.

[0035] The effects described in this specification are merely examples and are not limiting, and other effects may also be achieved. The same applies to the effects of other embodiments described below.

[0036] 2. Second embodiment Next, a display device 10 according to a second embodiment of the present disclosure will be described. Note that, hereinafter, parts that are substantially the same as the components of the display device 10 according to the first embodiment described above will be assigned the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0037] 5 is a circuit diagram showing an example of the configuration of a pixel circuit in the display device 10 according to the second embodiment. The overall configuration of the display device 10 according to the second embodiment may be the same as that shown in FIG.

[0038] 5 shows an example of the configuration of a pixel circuit when the display device 10 is a liquid crystal display device. Each pixel P has a liquid crystal LC, and a pixel electrode 31 and a common electrode 41 arranged opposite each other to apply a voltage to the liquid crystal LC. A common voltage common to each pixel P is applied to the common electrode 41 via a common voltage line VCOM. A voltage corresponding to a video signal is applied to the pixel electrode 31 via the pixel circuit.

[0039] The pixel circuit in the second embodiment is a digital driving circuit and includes a plurality of memory elements and a plurality of transistors. The pixel circuit in the second embodiment includes a first memory element r0 and a second memory element r1 as the plurality of memory elements. The pixel circuit in the second embodiment includes a first transistor nt1, a second transistor nt2, and a third transistor nt3 as the plurality of transistors.

[0040] The first memory element r0 and the second memory element r1 are each a nonvolatile variable resistance element. Here, the variable resistance element may be, for example, a memory element constituting a ReRAM or a memory element constituting a PCM. For example, it may be an MTJ element, which is a component of an MRAM.

[0041] The first transistor nt1, the second transistor nt2, and the third transistor nt3 each have a gate electrode, a first terminal, and a second terminal. The first terminal may be a source terminal or a drain terminal. The second terminal may be a drain terminal if the first terminal is a source terminal, or may be a source terminal if the first terminal is a drain terminal. The first transistor nt1, the second transistor nt2, and the third transistor nt3 may each be an N-channel MOS transistor (NMOS transistor) or a P-channel MOS transistor (PMOS transistor).

[0042] The first memory element r0 and the second memory element r1 each have a first terminal and a second terminal. Each column data line DL shown in FIG. 1 has a bit line and a source line SL. The bit lines include a first bit line BL and a second bit line xBL.

[0043] A first terminal of the first transistor nt1 is connected to the source line SL. A second terminal of the first transistor nt1 is connected to the second terminal of the first memory element r0, the second terminal of the second memory element r1, and the first terminal of the third transistor nt3. A gate electrode of the first transistor nt1 is connected to the row scanning line WWL.

[0044] A first terminal of the first memory element r0 is connected to the first bit line BL, and a first terminal of the second memory element r1 is connected to the second bit line xBL.

[0045] The first terminal of the third transistor nt3 is connected to the second terminal of the first transistor nt1, the second terminal of the first memory element r0, and the second terminal of the second memory element r1. The second terminal of the third transistor nt3 is connected to the gate electrode of the second transistor nt2. The gate electrode of the third transistor nt3 is connected to the signal line TGW. The third transistor nt3 is activated or deactivated according to the voltage of the signal line TGW.

[0046] A first terminal of the second transistor nt2 is connected to the voltage line VDD. A second terminal of the second transistor nt2 is connected to the pixel electrode 31. A gate electrode of the second transistor nt2 is connected to a second terminal of the third transistor nt3.

[0047] [2.2 Operation] Figures 6 and 7 are timing charts showing an example of the operation of the pixel circuit in the display device 10 according to the second embodiment. Figure 6 shows a timing chart when a voltage L (low) is applied to the pixel electrode 31. Figure 7 shows a timing chart when a voltage H (high) is applied to the pixel electrode 31. In Figures 6 and 7, (A) shows the source line SL, (B) the row scanning line WWL, (C) the first bit line BL, (D) the second bit line xBL, (E) the voltage line VDD, (F) the signal line TGW, (G) the node n0, and (H) the voltage of the liquid crystal LC (pixel electrode 31).

[0048] In the pixel circuit according to the second embodiment, data is written to the first memory element r0 and the second memory element r1 at the timing when the first transistor nt1 operates. Next, a voltage corresponding to the data written to the first memory element r0 and the second memory element r1 is applied to the gate electrode of the second transistor nt2 at the timing when the third transistor nt3 operates, thereby applying a voltage corresponding to the data from the second transistor nt2 to the pixel electrode 31. The third transistor nt3 operates at a timing based on a timing signal applied to the gate electrode of the third transistor nt3 from the signal line TGW. Data of mutually opposite values ​​is written to the first memory element r0 and the second memory element r1.

[0049] In the pixel circuit according to the second embodiment, first, a digital signal from the source line SL (FIGS. 6 and 7A) is received by the first transistor nt1 by activating the row scanning line WWL (FIGS. 6 and 7B), and the digital signal is written to the first memory element r0 and the second memory element r1. At this time, the first bit line BL and the second bit line xBL are at opposite voltages (FIGS. 6 and 7C and 7D), so that data of opposite values ​​is written to the first memory element r0 and the second memory element r1. Furthermore, at the timing when data is written to the first memory element r0 and the second memory element r1, the row scanning line WWL is activated, but the signal line TGW is not activated (FIGS. 6 and 7F), and the third transistor nt3 is in an off state.

[0050] Next, the row scanning line WWL is deactivated, the first transistor nt1 is deactivated, and then the data written to the first memory element r0 and the second memory element r1 is read. For example, when applying a voltage H to the pixel electrode 31, the first bit line BL connected to the first memory element r0 is activated (FIG. 7C). At this time, the second bit line xBL is deactivated (FIG. 7D). The voltage at node n0 between the first memory element r0 and the second memory element r1 (FIG. 7G) is applied from the third transistor nt3 to the gate electrode of the second transistor nt2 when the signal line TGW is activated (FIG. 7F). As a result, a voltage corresponding to the voltage at node n0 is applied to the liquid crystal LC (pixel electrode 31) via the third transistor nt3 and the second transistor nt2 (FIG. 7H).

[0051] [2.3 Effects] In the pixel circuit of the second embodiment, it is possible to apply a voltage to the pixel electrode 31 at the timing when the signal line TGW is activated, making it possible to realize a digital driving circuit capable of surface-wide driving. This enables digital surface-wide driving in the display device 10, improving the phase stability of the phase modulation device. This allows the display device 10 to obtain, for example, high-quality images or holographic images. Furthermore, in the pixel circuit of the second embodiment, the pixel circuit can be configured with three transistors and two memory elements, making it easy to miniaturize the pixel P.

[0052] Other configurations, operations, and effects may be substantially the same as those of the display device 10 according to the first embodiment.

[0053] 3. Third Embodiment Next, a display device 10 according to a third embodiment of the present disclosure will be described. Note that, hereinafter, parts that are substantially the same as the components of the display device 10 according to the first or second embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0054] 8 is a circuit diagram showing an example of the configuration of a pixel circuit in the display device 10 according to the third embodiment. The overall configuration of the display device 10 according to the third embodiment may be the same as that shown in FIG.

[0055] 8 shows an example of the configuration of a pixel circuit when the display device 10 is a liquid crystal display device. Each pixel P has a liquid crystal LC, and a pixel electrode 31 and a common electrode 41 arranged opposite each other to apply a voltage to the liquid crystal LC. A common voltage common to each pixel P is applied to the common electrode 41 via a common voltage line VCOM. A voltage corresponding to a video signal is applied to the pixel electrode 31 via the pixel circuit.

[0056] The pixel circuit in the third embodiment is a digitally driven drive circuit and includes a plurality of memory elements and a plurality of transistors. The pixel circuit in the third embodiment includes a first memory element r0 and a second memory element r1 as the plurality of memory elements. The pixel circuit in the third embodiment includes a first transistor nt1, a second transistor nt2, a third transistor nt3, and a fourth transistor pt1 as the plurality of transistors. The second transistor nt2 and the fourth transistor pt1 configure an inverter circuit INV1.

[0057] The first memory element r0 and the second memory element r1 are each a nonvolatile variable resistance element. Here, the variable resistance element may be, for example, a memory element constituting a ReRAM or a memory element constituting a PCM. For example, it may be an MTJ element, which is a component of an MRAM.

[0058] The first transistor nt1, the second transistor nt2, the third transistor nt3, and the fourth transistor pt1 each have a gate electrode, a first terminal, and a second terminal. The first terminal may be a source terminal or a drain terminal. The second terminal may be a drain terminal if the first terminal is a source terminal, or may be a source terminal if the first terminal is a drain terminal. The first transistor nt1 and the third transistor nt3 may each be an N-channel MOS transistor (NMOS transistor) or a P-channel MOS transistor (PMOS transistor). The second transistor nt2 may be an N-channel MOS transistor (NMOS transistor). The fourth transistor pt1 may be a P-channel MOS transistor (PMOS transistor).

[0059] The first memory element r0 and the second memory element r1 each have a first terminal and a second terminal. Each column data line DL shown in FIG. 1 has a bit line and a source line SL. The bit lines include a first bit line BL and a second bit line xBL.

[0060] A first terminal of the first transistor nt1 is connected to the source line SL. A second terminal of the first transistor nt1 is connected to the second terminal of the first memory element r0, the second terminal of the second memory element r1, the gate electrode of the second transistor nt2, and the gate electrode of the fourth transistor pt1. A gate electrode of the first transistor nt1 is connected to the row scanning line WWL.

[0061] A first terminal of the first memory element r0 is connected to the first bit line BL, and a first terminal of the second memory element r1 is connected to the second bit line xBL.

[0062] The first terminal of the second transistor nt2 is connected to the voltage line VCC. The first terminal of the fourth transistor pt1 is connected to the voltage line VDD. The gate electrodes of the second transistor nt2 and the fourth transistor pt1 are connected to each other. The second terminal of the second transistor nt2 and the second terminal of the fourth transistor pt1 are connected to each other. As a result, the second transistor nt2 and the fourth transistor pt1 form an inverter circuit INV1. The input terminal in1 of the inverter circuit INV1 is connected to the second terminal of the first transistor nt1 and the second terminals of the first memory element r0 and the second memory element r1. The output terminal out1 of the inverter circuit INV1 is connected to the first terminal of the third transistor nt3.

[0063] The gate electrode of the third transistor nt3 is connected to the signal line TGW. The third transistor nt3 is activated or deactivated according to the voltage of the signal line TGW. The second terminal of the third transistor nt3 is connected to the pixel electrode 31.

[0064] 9 and 10 are timing charts showing an example of the operation of the pixel circuit in the display device 10 according to the third embodiment. FIG. 9 shows a timing chart when a voltage L (low) is applied to the pixel electrode 31. FIG. 10 shows a timing chart when a voltage H (high) is applied to the pixel electrode 31. In FIGS. 9 and 10, (A) shows the source line SL, (B) the row scanning line WWL, (C) the first bit line BL, (D) the second bit line xBL, (E) the voltage line VDD, (F) the signal line TGW, (G) the node n0, and (H) the voltage of the liquid crystal LC (pixel electrode 31).

[0065] In the pixel circuit of the third embodiment, data is written to the first memory element r0 and the second memory element r1 at the timing when the first transistor nt1 operates, and then a voltage corresponding to the written data is applied to the inverter circuit INV1. Furthermore, at the timing when the third transistor nt3 operates, a voltage corresponding to the output of the inverter circuit INV1 is applied to the pixel electrode 31 via the third transistor nt3. The third transistor nt3 operates at a timing based on a timing signal applied to the gate electrode of the third transistor nt3. Data of mutually opposite values ​​is written to the first memory element r0 and the second memory element r1.

[0066] In the pixel circuit according to the third embodiment, first, a digital signal from the source line SL ((A) in FIGS. 9 and 10 ) is received by the first transistor nt1 by activating the row scanning line WWL ((B) in FIGS. 9 and 10 ), and the digital signal is written to the first memory element r0 and the second memory element r1. At this time, the first bit line BL and the second bit line xBL are at opposite voltages ((C) and (D) in FIGS. 9 and 10 ), so that data with opposite values ​​is written to the first memory element r0 and the second memory element r1. Furthermore, at the timing when data is written to the first memory element r0 and the second memory element r1, the row scanning line WWL is activated, but the signal line TGW is not activated ((F) in FIGS. 9 and 10 ), and the third transistor nt3 is in an off state.

[0067] Next, the row scanning line WWL is deactivated, the first transistor nt1 is deactivated, and then the data written to the first memory element r0 and the second memory element r1 is read. For example, when applying a voltage H to the pixel electrode 31, the first bit line BL connected to the first memory element r0 is activated (FIG. 10(C)). At this time, the second bit line xBL is deactivated (FIG. 10(D)). At this time, the voltage at the node n0 between the first memory element r0 and the second memory element r1 (FIG. 10(G)) is applied to the inverter circuit INV1. The voltage applied to the inverter circuit INV1 is amplified by the inverter circuit INV1 and then applied to the pixel electrode 31 via the third transistor nt3 when the signal line TGW is activated (FIG. 10(F)). As a result, a voltage corresponding to the voltage at the node n0 is amplified and applied to the liquid crystal LC (pixel electrode 31) via the inverter circuit INV1 and the third transistor nt3 ((H) in FIG. 10).

[0068] [3.3 Effects] In the pixel circuit of the display device 10 according to the third embodiment, the inverter circuit INV1 amplifies the digital signals written to the first memory element r0 and the second memory element r1. Then, the third transistor nt3 applies the output of the inverter circuit INV1 to the pixel electrode 31 in accordance with the activation timing of the signal line TGW, thereby realizing a digital driving circuit capable of full-area driving. This enables the display device 10 to achieve digital full-area driving, thereby improving the phase stability of the phase modulation device. This allows the display device 10 to produce, for example, high-quality images or holographic images. Furthermore, the pixel circuit according to the third embodiment can be configured with four transistors and two memory elements, facilitating miniaturization of the pixel P. Furthermore, signal amplification by the inverter circuit INV1 allows a sufficient voltage to be applied to the pixel electrode 31.

[0069] Other configurations, operations, and effects may be substantially the same as those of the display device 10 according to the first embodiment.

[0070] 4. Other Embodiments The technology according to the present disclosure is not limited to the above-described embodiments, and various modifications are possible.

[0071] For example, the present technology can be configured as follows. According to the present technology configured as follows, data can be held by a plurality of memory elements. This makes it possible to provide a display device that can stably hold data in a pixel circuit and facilitates miniaturization.

[0072] (1) A display device comprising: a plurality of row scanning lines; a plurality of column data lines arranged to intersect with the plurality of row scanning lines; and a plurality of pixels arranged at intersections of the plurality of row scanning lines and the plurality of column data lines, each of the pixels having a pixel electrode and a pixel circuit that applies a voltage to the pixel electrode, and the pixel circuit having a plurality of memory elements and a plurality of transistors. (2) The display device according to (1), wherein the pixel circuit includes a first transistor and a second transistor as the plurality of transistors, the first transistor and the second transistor each having a gate electrode, a first terminal, and a second terminal, the plurality of memory elements each having a first terminal and a second terminal, each of the column data lines having a bit line and a source line, the source line being connected to the first terminal of the first transistor, the bit line being connected to the first terminals of the plurality of memory elements, the gate electrode of the second transistor being connected to the second terminal of the first transistor and the second terminals of the plurality of memory elements, and the second terminal of the second transistor being connected to the pixel electrode. (3) The display device according to (2), wherein data is written to the plurality of memory elements at a timing when the first transistor operates, and a voltage according to the written data is applied from the second transistor to the pixel electrode. (4) The display device according to (2) or (3), wherein data having mutually opposite values ​​is written to the plurality of memory elements.(5) The display device according to (1), wherein the pixel circuit has first to third transistors as the plurality of transistors, the first to third transistors each having a gate electrode, a first terminal, and a second terminal, the plurality of memory elements each having a first terminal and a second terminal, each of the column data lines having a bit line and a source line, the source line being connected to the first terminal of the first transistor, the bit line being connected to the first terminals of the plurality of memory elements, the first terminal of the third transistor being connected to the second terminal of the first transistor and the second terminals of the plurality of memory elements, the second terminal of the third transistor being connected to the gate electrode of the second transistor, and the second terminal of the second transistor being connected to the pixel electrode. (6) The display device according to (5) above, wherein data is written to the plurality of memory elements at a timing when the first transistor operates, and a voltage according to the data written to the plurality of memory elements is applied to the gate electrode of the second transistor at a timing when the third transistor operates, thereby applying a voltage according to the data to the pixel electrode from the second transistor. (7) The display device according to (6) above, wherein the third transistor operates at a timing based on a timing signal applied to the gate electrode of the third transistor. (8) The display device according to any one of (5) to (7) above, wherein data having mutually opposite values ​​is written to the plurality of memory elements.(9) The display device according to (1), wherein the pixel circuit has first to fourth transistors as the plurality of transistors, the first to fourth transistors each having a gate electrode, a first terminal, and a second terminal, the plurality of memory elements each having a first terminal and a second terminal, each of the column data lines having a bit line and a source line, the source line being connected to the first terminal of the first transistor, the bit line being connected to the first terminal of the plurality of memory elements, the second terminal of the first transistor and the second terminals of the plurality of memory elements being connected to input terminals of an inverter circuit composed of the second transistor and the fourth transistor, an output terminal of the inverter circuit being connected to the first terminal of the third transistor, and the second terminal of the third transistor being connected to the pixel electrode. (10) The display device according to (9) above, wherein after writing data to the plurality of memory elements at a timing when the first transistor operates, a voltage according to the written data is applied to the inverter circuit, and at a timing when the third transistor operates, a voltage according to the output of the inverter circuit is applied to the pixel electrode via the third transistor. (11) The display device according to (10) above, wherein the third transistor operates at a timing based on a timing signal applied to the gate electrode of the third transistor. (12) The display device according to any one of (9) to (11) above, wherein data having mutually opposite values ​​is written to the plurality of memory elements. (13) The display device according to any one of (1) to (12) above, wherein each of the plurality of memory elements is a resistance change element.

[0073] This application claims priority based on Japanese Patent Application No. 2023-152229, filed on September 20, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0074] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A display device comprising: a plurality of row scanning lines; a plurality of column data lines arranged to intersect with the plurality of row scanning lines; and a plurality of pixels arranged at intersections of the plurality of row scanning lines and the plurality of column data lines, each of the pixels having a pixel electrode and a pixel circuit for applying a voltage to the pixel electrode, the pixel circuit having a plurality of memory elements and a plurality of transistors.

2. The display device of claim 1, wherein the pixel circuit has a first transistor and a second transistor as the plurality of transistors, the first transistor and the second transistor each having a gate electrode, a first terminal and a second terminal, the plurality of memory elements each having a first terminal and a second terminal, each of the column data lines having a bit line and a source line, the source line being connected to the first terminal of the first transistor, the bit line being connected to the first terminals of the plurality of memory elements, the gate electrode of the second transistor being connected to the second terminal of the first transistor and the second terminals of the plurality of memory elements, and the second terminal of the second transistor being connected to the pixel electrode.

3. The display device according to claim 2, wherein data is written to the plurality of memory elements at a timing when the first transistor operates, and a voltage according to the written data is applied from the second transistor to the pixel electrode.

4. The display device according to claim 2, wherein data having mutually opposite values ​​is written to the plurality of memory elements.

5. The display device according to claim 1, wherein the pixel circuit has first to third transistors as the plurality of transistors, the first to third transistors each having a gate electrode, a first terminal and a second terminal, the plurality of memory elements each having a first terminal and a second terminal, each of the column data lines has a bit line and a source line, the source line is connected to the first terminal of the first transistor, the bit line is connected to the first terminals of the plurality of memory elements, the first terminal of the third transistor is connected to the second terminal of the first transistor and the second terminals of the plurality of memory elements, the second terminal of the third transistor is connected to the gate electrode of the second transistor, and the second terminal of the second transistor is connected to the pixel electrode.

6. The display device according to claim 5, wherein data is written to the plurality of memory elements at a timing when the first transistor operates, and a voltage corresponding to the data written to the plurality of memory elements is applied to the gate electrode of the second transistor at a timing when the third transistor operates, thereby applying a voltage corresponding to the data from the second transistor to the pixel electrode.

7. The display device according to claim 6, wherein the third transistor operates at a timing based on a timing signal applied to the gate electrode of the third transistor.

8. The display device according to claim 5, wherein data having mutually opposite values ​​is written to the plurality of memory elements.

9. The display device according to claim 1, wherein the pixel circuit has first to fourth transistors as the plurality of transistors, the first to fourth transistors each having a gate electrode, a first terminal and a second terminal, the plurality of memory elements each having a first terminal and a second terminal, each of the column data lines has a bit line and a source line, the source line is connected to the first terminal of the first transistor, the bit line is connected to the first terminal of the plurality of memory elements, the second terminal of the first transistor and the second terminals of the plurality of memory elements are connected to input terminals of an inverter circuit composed of the second transistor and the fourth transistor, an output terminal of the inverter circuit is connected to the first terminal of the third transistor, and the second terminal of the third transistor is connected to the pixel electrode.

10. The display device according to claim 9, wherein after data is written to the plurality of memory elements at a timing when the first transistor operates, a voltage corresponding to the written data is applied to the inverter circuit, and at a timing when the third transistor operates, a voltage corresponding to an output of the inverter circuit is applied to the pixel electrode via the third transistor.

11. The display device according to claim 10, wherein the third transistor operates at a timing based on a timing signal applied to the gate electrode of the third transistor.

12. The display device according to claim 9, wherein data having mutually opposite values ​​is written to the plurality of memory elements.

13. The display device according to claim 1, wherein each of the plurality of memory elements is a resistance change element.

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