Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising a base (101), and a plurality of sub-pixels (Pxij), a driving circuit layer (102) and a pixel defining layer, which are arranged on the base, wherein, in a direction perpendicular to the plane where the display substrate is located, the driving circuit layer (102) is located between the base and the pixel defining layer; a plurality of pixel openings (80) are formed in the pixel defining layer, and each sub-pixel comprises at least one pixel opening; and the driving circuit layer may comprise a plurality of conductive layers. There is an overlap area between the orthographic projection of the pixel opening of at least one sub-pixel on the base and the orthographic projection of at least some signal lines in at least one conductive layer on the base; among the at least one sub-pixel, the overlap area corresponding to one sub-pixel is symmetrical with respect to the orthographic projection of at least one center line of the pixel opening of said sub-pixel on the base.

Description

Display substrate, display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, display devices using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of the present disclosure provide a display substrate comprising a substrate, and a plurality of sub-pixels, a driving circuit layer, and a pixel definition layer disposed on the substrate. The driving circuit layer is located between the substrate and the pixel definition layer in a direction perpendicular to a plane of the display substrate. The pixel definition layer has a plurality of pixel openings formed therein, with each sub-pixel including at least one pixel opening. The driving circuit layer includes a plurality of conductive layers.

[0006] There is an overlapping area between the pixel opening of at least one sub-pixel and the orthographic projection of at least part of the signal line in at least one conductive layer on the substrate; in the at least one sub-pixel, the overlapping area corresponding to one of the sub-pixels is symmetrical with respect to the orthographic projection of at least one center line of the pixel opening of the sub-pixel on the substrate.

[0007] In an exemplary embodiment, in a direction perpendicular to a plane of the display substrate, the at least a portion of the conductive layer includes a conductive layer in the driving circuit layer that is most adjacent to the pixel definition layer.

[0008] In an exemplary embodiment, the conductive layer of the driving circuit layer that is most adjacent to the pixel definition layer includes a first power line, the plurality of sub-pixels includes a plurality of sub-pixels, and the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel;

[0009] The areas of the overlapping regions between the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel and the orthographic projection of the first power line on the substrate are both larger than the areas of the overlapping regions between the pixel opening of the third sub-pixel and the orthographic projection of the first power line on the substrate.

[0010] In an exemplary embodiment, the conductive layer in the driving circuit layer that is closest to the pixel definition layer also includes a data signal line, and there is an overlapping area between the pixel opening of the second sub-pixel and the positive projection of two adjacent first power lines and one data signal line on the substrate. In a direction parallel to the plane of the display substrate, the first power line and the data signal line extend along a second direction, and in the first direction, the two first power lines are respectively located on both sides of the one data signal line, wherein the first direction intersects with the second direction.

[0011] In an exemplary embodiment, there are two first overlapping areas between the orthographic projections of the two adjacent first power lines and the corresponding pixel openings of the second sub-pixels on the substrate, and there is one second overlapping area between the orthographic projections of the one data signal line and the corresponding pixel opening of the second sub-pixel on the substrate. In the first direction, the two first overlapping areas are located on both sides of the one second overlapping area, and the two first overlapping areas are symmetrical with respect to the one second overlapping area.

[0012] In an exemplary embodiment, the conductive layer in the driving circuit layer that is closest to the pixel definition layer is the second source-drain metal layer, and the orthographic projection of the pixel opening of the first sub-pixel on the substrate and the orthographic projection of at least part of the signal line in the second source-drain metal layer on the substrate have a first overlapping area, the orthographic projection of the pixel opening of the second sub-pixel on the substrate and the orthographic projection of at least part of the signal line in the second source-drain metal layer on the substrate have a second overlapping area, and the orthographic projection of the pixel opening of the third sub-pixel on the substrate and the orthographic projection of at least part of the signal line in the second source-drain metal layer on the substrate have a third overlapping area, and the areas of the first overlapping area and the second overlapping area are both larger than the area of ​​the third overlapping area.

[0013] In an exemplary embodiment, the first overlapping area is symmetrical with respect to the orthographic projection of a midline of a pixel opening of the first sub-pixel extending along at least one of the first direction and the second direction on the substrate; the second overlapping area is symmetrical with respect to the orthographic projection of a midline of a pixel opening of the second sub-pixel extending along at least one of the first direction and the second direction on the substrate; and the third overlapping area is symmetrical with respect to the orthographic projection of a midline of a pixel opening of the third sub-pixel extending along at least one of the first direction and the second direction on the substrate.

[0014] In an exemplary embodiment, an orthographic projection of a pixel opening of the first sub-pixel on the substrate is located within a range of an orthographic projection of the first power line on the substrate.

[0015] In an exemplary embodiment, an area of ​​a pixel opening of the third sub-pixel is larger than an area of ​​a pixel opening of the first sub-pixel and smaller than an area of ​​a pixel opening of the second sub-pixel.

[0016] In an exemplary embodiment, the first sub-pixel is a sub-pixel that emits red light, the second sub-pixel is a sub-pixel that emits blue light, and the third sub-pixel is a sub-pixel that emits green light.

[0017] In an exemplary embodiment, the display substrate further includes an anode conductive layer, wherein the anode conductive layer is located between the driving circuit layer and the pixel definition layer in a direction perpendicular to the plane of the display substrate, the anode conductive layer includes a plurality of anodes, each anode including an anode main portion, and each sub-pixel includes at least one anode;

[0018] The orthographic projections of the pixel openings of the multiple sub-pixels on the substrate are respectively located within the range of the orthographic projections of the multiple anodes on the substrate, and the orthographic projection of the anode main body of at least one sub-pixel on the substrate has an overlapping area with the orthographic projection of at least part of the signal line in at least one conductive layer on the substrate; in the at least one sub-pixel, the overlapping area corresponding to one of the sub-pixels is symmetrical with respect to the orthographic projection of at least one midline of the anode main body of the sub-pixel on the substrate.

[0019] In an exemplary embodiment, the driving circuit layer includes a plurality of pixel driving circuits, at least some of the sub-pixels include the pixel driving circuits, and at least some of the pixel circuits include: at least one first type transistor and at least one second type transistor; the driving circuit layer includes at least a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer sequentially disposed on the substrate, wherein:

[0020] The first semiconductor layer includes at least: an active layer of a first type transistor in the pixel driving circuit; the first conductive layer includes at least: a gate of the first type transistor; the second conductive layer includes at least: a bottom gate of the second type transistor; the second semiconductor layer includes at least: an active layer of the second type transistor; and the third conductive layer includes at least: a top gate of the second type transistor.

[0021] In an exemplary embodiment, the first type of transistors includes at least first to seventh transistors and a ninth transistor, and the second type of transistors includes at least an eighth transistor;

[0022] In a direction parallel to the plane of the display substrate, in a first direction, the fourth transistor and the fifth transistor are located on the same side of the third transistor, the second transistor, the sixth transistor and the seventh transistor are located on the other side of the third transistor, and the eighth transistor is located between the second transistor and the fourth transistor; in a second direction, the fourth transistor and the fifth transistor are respectively located on both sides of the third transistor, the fifth to seventh transistors and the ninth transistor are located on the same side of the third transistor, the first transistor, the second transistor, the fourth transistor and the eighth transistor are located on the same side of the third transistor, and the first direction intersects with the second direction.

[0023] In an exemplary embodiment, the pixel driving circuits of the plurality of sub-pixels are arranged in an array, and in the pixel driving circuits of the sub-pixels in the same column, in the first direction, the first transistor in the i-1th row of sub-pixels is located between the seventh transistor and the ninth transistor in the i-1th row of sub-pixels, i=2, 3, ..., M+1, where M is an integer greater than or equal to 1.

[0024] In an exemplary embodiment, the first conductive layer further includes a first scan signal line extending along the first direction, and the first scan signal line in the i-th row is electrically connected to the first transistor in the i-th row and the seventh and ninth transistors in the i-1-th row.

[0025] In an exemplary embodiment, the first type of transistor is a low temperature polysilicon transistor, and the second type of transistor is an oxide transistor.

[0026] In an exemplary embodiment, the driving circuit layer further includes a fourth conductive layer, which is located on a side of the third conductive layer away from the substrate in a direction perpendicular to the plane of the display substrate, and includes a plurality of second initial signal lines and a plurality of rows of second initial signal connection lines.

[0027] The pixel driving circuits of the plurality of sub-pixels form a plurality of rows, the plurality of second initial signal lines are electrically connected to the plurality of rows of pixel driving circuits respectively, and the plurality of second initial signal lines extend along a first direction in a direction parallel to a plane of the display substrate and are arranged at intervals along a second direction, wherein the first direction intersects the second direction;

[0028] Each row of second initial signal connection lines includes a plurality of second initial signal connection lines extending along the second direction and arranged at intervals along the first direction. In the second direction, each row of second initial signal connection lines is located between two adjacent second initial signal lines, and both ends of the plurality of second initial signal connection lines in each row of second initial signal connection lines are respectively connected to the two adjacent second initial signal lines.

[0029] In an exemplary embodiment, the driving circuit layer further includes a fifth conductive layer, which is located on a side of the fourth conductive layer away from the substrate in a direction perpendicular to the plane of the display substrate, the fifth conductive layer includes a plurality of second power supply lines, and the second conductive layer further includes a plurality of second power connection lines;

[0030] In a direction parallel to the plane where the display substrate is located, the multiple second power lines extend along the second direction and are arranged at intervals along the first direction, the multiple second power connection lines extend along the first direction and are arranged at intervals along the second direction, and the multiple second power lines are electrically connected to the multiple second power connection lines through vias to form a grid structure.

[0031] In an exemplary embodiment, in a direction parallel to a plane where the display substrate is located, the display substrate includes a first display area, a second display area, and a connection area, the first display area and the second display area are connected via the connection area, the second display area at least partially surrounds the first display area, and pixel driving circuits of the plurality of sub-pixels are located in the first display area and the second display area, and form a plurality of columns;

[0032] The third conductive layer also includes a plurality of second data signal connection lines, and the fifth conductive layer also includes a plurality of first data signal lines and a plurality of second data signal lines; the plurality of first data signal lines are respectively electrically connected to the plurality of columns of pixel driving circuits located in the first display area, and the plurality of second data signal lines are electrically connected to the plurality of columns of pixel driving circuits located in the second display area; the plurality of second data signal connection lines are located in the second display area, and are respectively electrically connected to the plurality of columns of pixel driving circuits located in the second display area.

[0033] In an exemplary embodiment, the multiple sub-pixels form a plurality of pixel units, the multiple pixel units are arranged in an array, the pixel unit includes at least three adjacent sub-pixels, the second power line and the second initial signal connection line are arranged between two adjacent columns of pixel units, and the second power connection line and the second data signal connection line are located between two adjacent rows of pixel units.

[0034] In a second aspect, embodiments of the present disclosure further provide a display substrate, comprising a first display area, a second display area, a binding area, and a connection area, wherein the first display area and the second display area are connected via the connection area, the second display area at least partially surrounds the first display area, and the binding area is located on one side of the first display area in a direction parallel to a plane of the display substrate;

[0035] The second display area is provided with a plurality of second data signal lines and a plurality of second data signal connecting lines; one end of the plurality of second data signal connecting lines is electrically connected to the plurality of second data signal lines respectively, and the other end is electrically connected to the elements provided in the binding area.

[0036] In an exemplary embodiment, the second display area is provided with a plurality of pixel units, and the plurality of pixel units form a plurality of second pixel unit rows and a plurality of second pixel unit columns. The plurality of second pixel unit columns are arranged sequentially along a direction from the first display area to the second display area, and the distance between two adjacent second pixel unit rows increases sequentially from the first second pixel unit column to the last second pixel unit column.

[0037] In an exemplary embodiment, the first display area is circular in shape, and the second display area is strip-shaped that at least partially surrounds the first display area.

[0038] In an exemplary embodiment, in a direction parallel to the plane of the display substrate, the binding area and the connection are located on opposite sides of the first display area, the elements set in the binding area include a driving chip, and one end of the multiple second data signal connection lines is electrically connected to the driving chip.

[0039] In an exemplary embodiment, the display substrate further includes a first outer frame, the first outer frame being disposed around the first display area, the first outer frame including the connection area and the binding area, the first outer frame being provided with a plurality of second data signal patching lines, and the second data signal patching lines and the second data signal connection lines being located on different conductive layers;

[0040] The second data signal connection line extends from the second display area to the connection area, and the multiple second data signal adapter lines extend from the connection area along the first outer frame to the binding area, one end of which is electrically connected to the multiple second data signal connection lines located in the connection area, and the other end is electrically connected to the driving chip.

[0041] In an exemplary embodiment, the display substrate further includes a second outer frame area and a second inner frame area, and along a direction from the first display area to the second display area, the second inner frame area and the second outer frame area are located on both sides of the second display area.

[0042] In an exemplary embodiment, the second inner frame area is connected to the first outer frame area through the connection area, and the first outer frame area and the second inner frame area are provided with a second power signal supply line, and the second power signal supply line is electrically connected to the driving chip and extends through the first outer frame area to the second inner frame area.

[0043] In an exemplary embodiment, the display substrate further includes a cathode layer, the second display area includes a second power connection line electrically connected to a second power signal supply line in the second inner frame area, the second outer frame area includes a second power strapping line that overlaps with the cathode layer and the second power connection line, and the second power strapping line is electrically connected to the second power connection line and the cathode layer through a via.

[0044] In an exemplary embodiment, the second power signal supply line located in the first outer frame area overlaps with the cathode layer and is electrically connected to the cathode layer through a via hole.

[0045] In an exemplary embodiment, along a direction from the second display area to the second inner frame area, the second inner frame area sequentially includes: a first-type gate driving circuit and a first-type driving signal line electrically connected thereto, an initial signal line, a first power signal supply line, and a second power signal supply line;

[0046] Along the direction from the second display area to the second outer frame area, the second outer frame area includes in sequence: a second type gate drive circuit and a second type drive signal line electrically connected to it, and a second power supply jumper line, wherein the second type drive signal line is electrically connected to the drive chip via the second outer frame area, the second inner frame area, and the first outer frame area.

[0047] In an exemplary embodiment, the connection area is provided with an initial signal transfer electrode provided in a different layer from the initial signal line, a first power transfer electrode provided in a different layer from the first power signal supply line, a second power transfer electrode provided in a different layer or in the same layer as the second power signal supply line, and a drive signal transfer electrode provided in a different layer from the first type drive signal line;

[0048] Along the direction from the first display area to the first outer frame area, the first outer frame area sequentially includes: a first power signal supply line, an initial signal line, a first type driving signal line, and a second power signal supply line;

[0049] The first power signal supply line located in the first outer frame area is electrically connected to the first power signal supply line located in the second inner frame area through the first power conversion electrode; the initial signal line located in the first outer frame area is electrically connected to the initial signal line located in the second inner frame area through the initial signal conversion electrode; the first type of drive signal line located in the first outer frame area is electrically connected to the first type of drive signal line through the drive signal conversion electrode, and the second power signal supply line located in the first outer frame area is electrically connected to the second power signal supply line located in the second inner frame area through the second power conversion electrode.

[0050] In an exemplary embodiment, the second display area further includes a plurality of second-type scan signal lines, the output end of each second-type gate driving circuit is electrically connected to two corresponding second-type scan signal lines, and each second-type scan signal line is electrically connected to a plurality of sub-pixels in one of the second pixel unit rows.

[0051] In an exemplary embodiment, each second-type gate driving circuit has the same size as its two adjacent second pixel unit rows in the extending direction of the second outer frame;

[0052] Alternatively, each second-type gate driving circuit is divided into two connected circuit parts, and the two circuit parts are respectively consistent with the sizes of two adjacent second pixel unit rows in the extending direction of the second outer frame area;

[0053] Alternatively, two adjacent rows of second pixel units are regarded as a unit module, and in the extension direction of the second outer border area, the distance between the two adjacent unit modules is greater than the distance between the two second pixel units in the same unit module, and each second type of gate drive circuit is consistent with the size of an adjacent unit module in the extension direction of the second outer border area.

[0054] In an exemplary embodiment, along the direction from the first display area to the first outer frame area, the first outer frame area sequentially includes: a second power signal supply line, a first power signal supply line, an initial signal line, a gate driving circuit, and a driving signal line electrically connected thereto.

[0055] In a third aspect, an embodiment of the present disclosure further provides a display device comprising the display substrate described in any of the above embodiments.

[0056] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings are intended to provide a further understanding of the technical solutions of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0058] FIG1 is a schematic structural diagram of a display device;

[0059] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0060] FIG3 is a schematic diagram of a cross-sectional structure of a display in a display substrate;

[0061] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0062] FIG5 is a working timing diagram of a pixel driving circuit;

[0063] FIG6 is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0064] FIG7 is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0065] FIG8 is a schematic diagram showing an equivalent circuit of a pixel driving circuit provided by an exemplary embodiment of the present disclosure;

[0066] FIG9 a is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0067] FIG9 b is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0068] FIG9c is a partial enlarged schematic diagram of the position of M1 in FIG9a;

[0069] FIG9 d is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0070] FIG9e is a partial enlarged schematic diagram of the position of M1 in FIG9a;

[0071] FIG9f is a partial enlarged schematic diagram of the position of M2 in FIG9a;

[0072] FIG9g is a partial enlarged schematic diagram of the position of M2 in FIG9a;

[0073] FIG9h is a partial enlarged schematic diagram of the position of M2 in FIG9a;

[0074] FIG9i is a schematic structural diagram of an ERD watch assembled using the display substrate shown in FIG9a;

[0075] FIG10 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first semiconductor layer pattern is formed;

[0076] FIG11a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first conductive layer pattern is formed;

[0077] FIG11 b is a schematic diagram of a first conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0078] FIG12a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second conductive layer pattern is formed;

[0079] FIG12 b is a schematic diagram showing a second conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0080] FIG13a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second semiconductor layer pattern is formed;

[0081] FIG13 b is a schematic diagram showing a second semiconductor layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0082] FIG14a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third conductive layer pattern is formed;

[0083] FIG14 b is a schematic diagram showing a third conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0084] FIG15 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a sixth insulating layer pattern is formed;

[0085] FIG16a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0086] FIG16 b is a schematic diagram showing a fourth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0087] FIG17 is a schematic diagram showing a first planarization layer pattern formed according to an exemplary embodiment of the present disclosure;

[0088] FIG18a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fifth conductive layer pattern is formed;

[0089] FIG18 b is a schematic diagram showing a fifth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0090] FIG19 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second planarization layer pattern is formed;

[0091] FIG20 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after an anode conductive layer pattern is formed;

[0092] FIG20 b is a schematic diagram showing an anode conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0093] FIG21 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a pixel definition layer pattern is formed;

[0094] FIG21 b is a schematic diagram showing a pattern of a pixel definition layer of a display substrate provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0095] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0096] The scales of the figures in this disclosure are intended to serve as a reference for actual processes, but are not intended to be limiting. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted based on actual conditions. The figures described in this disclosure are merely schematic diagrams of the structures, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0097] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0098] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0099] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0100] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0101] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchangeable, and "source terminal" and "drain terminal" can be interchangeable. In the disclosed embodiments, the gate electrode can be referred to as the control electrode.

[0102] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0103] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0104] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0105] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0106] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0107] FIG1 is a schematic diagram of the structure of a display device. A display substrate may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array. The timing controller is connected to the data signal driver, the scan signal driver, and the light emitting signal driver, respectively. The data signal driver is connected to a plurality of data signal lines (D1 to Dn), the scan signal driver is connected to a plurality of scan signal lines (S1 to Sm), and the light emitting signal driver is connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data signal driver to the data signal driver, may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver to the scan signal driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specifications of the light emitting signal driver to the light emitting signal driver. The data signal driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data signal driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel row basis, where n can be a natural number. The scan signal driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan signal driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The emission signal driver can generate emission signals to be supplied to emission signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting signal driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate emission signals in a manner such that emission stop signals provided in the form of off-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal. o may be a natural number.

[0108] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel.

[0109] In an exemplary embodiment, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the sub-pixels in the pixel unit may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure.

[0110] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in this disclosure.

[0111] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include multiple transistors and storage capacitors that constitute the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the drive of the anode 301 and the cathode 303. The encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0112] In an exemplary embodiment, the organic light-emitting layer 302 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0113] In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG4 , the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C. The pixel driving circuit may be connected to seven signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light emitting signal line E, an initial signal line INIT, a first power line VDD, and a second power line VSS).

[0114] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively.

[0115] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0116] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initialization signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0117] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0118] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0119] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0120] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device to emit light.

[0121] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initialization signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0122] In an exemplary embodiment, the second electrode of the light-emitting device is connected to a second power line VSS. The signal on the second power line VSS is a low-level signal, while the signal on the first power line VDD is a continuously high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current display row is the same as the first scan signal line S1 in the pixel driving circuit of the previous display row. This can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0123] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0124] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line E, and the initial signal line INIT extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data signal line D extend in a vertical direction.

[0125] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0126] Figure 5 is an operating timing diagram of a pixel driving circuit. The following illustrates an exemplary embodiment using the operating process of the pixel driving circuit illustrated in Figure 4. The pixel driving circuit in Figure 4 includes seven transistors (first transistor T1 to seventh transistor T7), one storage capacitor C, and seven signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD, and second power line VSS). All seven transistors are P-type transistors.

[0127] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0128] The first phase A1, known as the reset phase, is characterized by a low-level signal on the second scan signal line S2, and a high-level signal on the first scan signal line S1 and the light-emitting signal line E. The low-level signal on the second scan signal line S2 turns on the first transistor T1, and the signal on the initialization signal line INIT is supplied to the second node N2, initializing the storage capacitor C and clearing the existing data voltage in the storage capacitor. The high-level signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the OLED does not emit light.

[0129] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signal on the first scan signal line S1 is a low-level signal, the signals on the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. During this phase, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (the second node N2) is Vd-|Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the initial voltage of the initialization signal line INIT is supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it, completing the initialization and ensuring that the OLED does not emit light. The signal of the second scanning signal line S2 is a high-level signal, turning off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0130] In the third phase A3, known as the light-emitting phase, the signal on the light-emitting signal line E is a low-level signal, while the signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0131] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0132] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0133] With advancements in display technology, flexible display devices are gradually evolving from two-dimensional to three-dimensional displays. For example, wearable displays in watches not only maximize the frontal display but also require side displays, achieving a surround-view sensory experience. Furthermore, improper signal routing within the display substrate can lead to significant color shift in the display panel, which can negatively impact the display quality.

[0134] An exemplary embodiment of the present disclosure provides a display substrate, which may include a substrate, and a plurality of sub-pixels, a driving circuit layer, and a pixel definition layer disposed on the substrate. In a direction perpendicular to a plane of the display substrate, the driving circuit layer is located between the substrate and the pixel definition layer. A plurality of pixel openings are formed in the pixel definition layer, and each sub-pixel includes at least one pixel opening. The driving circuit layer may include a plurality of conductive layers.

[0135] There is an overlapping area between the pixel opening of at least one sub-pixel and the orthographic projection of at least part of the signal line in at least one conductive layer on the substrate; in the at least one sub-pixel, the overlapping area corresponding to one of the sub-pixels is symmetrical with respect to the orthographic projection of at least one center line of the pixel opening of the sub-pixel on the substrate.

[0136] In a display substrate provided by an embodiment of the present disclosure, there is an overlapping area between the pixel opening of at least one sub-pixel in the display substrate and the orthographic projection of at least part of the signal line in at least one conductive layer on the substrate. In the at least one sub-pixel, the overlapping area corresponding to one of the sub-pixels is symmetrical with respect to the orthographic projection of at least one center line of the pixel opening of the sub-pixel on the substrate, which can solve the technical problem of large viewing angle color deviation of the display substrate.

[0137] As shown in FIG6 , the display substrate provided in an embodiment of the present disclosure may include a substrate and a plurality of sub-pixels Pxij, a driving circuit layer, and a pixel definition layer disposed on the substrate. In a direction perpendicular to the plane of the display substrate, the driving circuit layer is located between the substrate and the pixel definition layer. A plurality of pixel openings 80 are formed in the pixel definition layer. Each sub-pixel Pxij includes at least one pixel opening 80. The driving circuit layer may include a plurality of conductive layers.

[0138] There is an overlapping area between the pixel opening 80 of at least one sub-pixel Pxij and the orthographic projection of at least part of the signal line in at least one conductive layer on the substrate; in the at least one sub-pixel Pxij, the overlapping area corresponding to one of the sub-pixels Pxij is symmetrical with respect to the orthographic projection of at least one center line of the pixel opening 80 of the sub-pixel on the substrate.

[0139] In an exemplary embodiment, in a direction perpendicular to a plane where the display substrate is located, at least a portion of the conductive layer includes a conductive layer in the driving circuit layer that is most adjacent to the pixel definition layer.

[0140] In an exemplary embodiment, as shown in FIG6 , the conductive layer in the driving circuit layer that is most adjacent to the pixel definition layer may include a first power line 62 , and the plurality of sub-pixels Pxij may include a plurality of sub-pixels, the plurality of sub-pixels including a first sub-pixel P1 , a second sub-pixel P2 , and a third sub-pixel P3 ;

[0141] The areas of the orthographic overlapping regions of the pixel opening 801 of the first sub-pixel P1, the pixel opening 802 of the second sub-pixel P2 and the first power line 62 on the substrate are both larger than the areas of the orthographic overlapping regions of the pixel opening P3 of the third sub-pixel and the first power line 62 on the substrate.

[0142] In an exemplary embodiment, the overlapping areas between the pixel openings 80 of different sub-pixels and the first power line 62 are different, which can improve the flatness of the conductive layer in the driving circuit layer that is closest to the pixel definition layer at the position corresponding to the pixel opening 80, thereby improving color deviation.

[0143] In an exemplary embodiment, as shown in FIG6 , the conductive layer in the driving circuit layer that is closest to the pixel definition layer further includes a data signal line 61. The pixel opening 802 of the second sub-pixel P2 and the orthographic projections of the two adjacent first power lines 62 and one data signal line 61 on the substrate have an overlapping area. In a direction parallel to the plane of the display substrate, the first power line 62 and the data signal line 61 may extend along the second direction Y. In the first direction X, the two first power lines 62 are respectively located on both sides of the one data signal line 61, wherein the first direction X intersects with the second direction Y.

[0144] In an exemplary embodiment, there is an overlapping area between the pixel opening 802 of the second sub-pixel P2 and the orthographic projections of two adjacent first power lines 62 and one data signal line 61 on the substrate, which can improve the flatness of the conductive layer in the driving circuit layer that is closest to the pixel definition layer at the position of the pixel opening 802 of the second sub-pixel P2.

[0145] In an exemplary embodiment, as shown in FIG6 , two adjacent first power lines 62 and the pixel opening 802 of the corresponding second sub-pixel P2 have two first overlapping areas in their orthographic projections on the substrate, and one data signal line 61 and the pixel opening 802 of the corresponding second sub-pixel P2 have one second overlapping area in their orthographic projections on the substrate. In the first direction X, the two first overlapping areas are located on both sides of one second overlapping area, and the two first overlapping areas are symmetrical with respect to one second overlapping area, which can improve the defect of large viewing angle color deviation of the second sub-pixel P2.

[0146] In an exemplary embodiment, as shown in FIG6 , the conductive layer in the driving circuit layer that is most adjacent to the pixel definition layer is the second source-drain metal layer, and the orthographic projection of the pixel opening 801 of the first sub-pixel P1 on the substrate and the orthographic projection of at least part of the signal line in the second source-drain metal layer on the substrate have a first overlapping area, the orthographic projection of the pixel opening 802 of the second sub-pixel P2 on the substrate and the orthographic projection of at least part of the signal line in the second source-drain metal layer on the substrate have a second overlapping area, and the orthographic projection of the pixel opening 803 of the third sub-pixel P3 on the substrate and the orthographic projection of at least part of the signal line in the second source-drain metal layer on the substrate have a third overlapping area, and the areas of the first overlapping area and the second overlapping area are both larger than the area of ​​the third overlapping area.

[0147] In an exemplary embodiment, the first overlapping region may be symmetrical with respect to the orthographic projection of the midline of the pixel opening 801 of the first sub-pixel P1 extending along at least one of the first direction X and the second direction Y on the substrate; the second overlapping region may be symmetrical with respect to the orthographic projection of the midline of the pixel opening 802 of the second sub-pixel P2 extending along at least one of the first direction X and the second direction Y on the substrate; and the third overlapping region may be symmetrical with respect to the orthographic projection of the midline of the pixel opening 803 of the third sub-pixel P3 extending along at least one of the first direction X and the second direction Y on the substrate. In an exemplary embodiment, the overlapping region between the pixel opening and the orthographic projection of the second source / drain metal layer on the substrate is symmetrical with respect to the orthographic projection of the midline of the pixel opening extending along at least one of the first direction X and the second direction Y on the substrate, which can reduce color shift and thereby improve display quality.

[0148] In an exemplary embodiment, as shown in FIG6 , the orthographic projection position of the pixel opening 801 of the first sub-pixel P1 on the substrate can be within the range of the orthographic projection of the first power line 61 on the substrate, which can improve the flatness of the conductive layer in the driving circuit layer that is closest to the pixel definition layer at the position of the pixel opening 801 of the first sub-pixel P1.

[0149] In an exemplary embodiment, as shown in FIG. 6 , the area of ​​the pixel opening 803 of the third subpixel P3 may be larger than the area of ​​the pixel opening 801 of the first subpixel P1 and smaller than the area of ​​the pixel opening 802 of the second subpixel P2 .

[0150] In an exemplary embodiment, the first subpixel P1 may be a subpixel emitting red light, the second subpixel P2 may be a subpixel emitting blue light, and the third subpixel P3 may be a subpixel emitting green light.

[0151] In an exemplary embodiment, as shown in FIG6 , the display substrate may further include an anode conductive layer. In a direction perpendicular to the plane of the display substrate, the anode conductive layer may be located between the driving circuit layer and the pixel definition layer. The anode conductive layer may include a plurality of anodes 70 . The anode 70 may include an anode main body 701 . Each sub-pixel Pxij may include at least one anode 70 .

[0152] The orthographic projections of the pixel openings 80 of the multiple sub-pixels Pxij on the substrate are respectively located within the range of the orthographic projections of the multiple anodes 70 on the substrate. The orthographic projection of the anode main portion 701 of at least one sub-pixel Pxij on the substrate overlaps with the orthographic projection of at least a portion of the signal line in at least one conductive layer on the substrate. In the at least one sub-pixel, the overlapping region corresponding to one sub-pixel Pxij is symmetrical with respect to the orthographic projection of at least one midline of the anode main portion 701 of the sub-pixel on the substrate. As shown in FIG6 , each anode may include an anode main portion 701 and an anode connecting portion 702, the anode connecting portion 702 being electrically connected to the drive circuit layer. The orthographic projection of the pixel opening 80 on the substrate is located within the range of the orthographic projection of the corresponding anode main portion 701 on the substrate.

[0153] In an exemplary embodiment, as shown in FIG6 , the orthographic projection of the anode 71 of the first sub-pixel P1 on the substrate and the orthographic projection of at least part of the signal line in the second source-drain metal layer on the substrate have a first overlapping region, the orthographic projection of the anode 72 of the second sub-pixel P2 on the substrate and the orthographic projection of at least part of the signal line in the second source-drain metal layer on the substrate have a second overlapping region, and the orthographic projection of the anode 73 of the third sub-pixel P3 on the substrate and the orthographic projection of at least part of the signal line in the second source-drain metal layer on the substrate have a third overlapping region, and the areas of the first overlapping region and the second overlapping region are both larger than the area of ​​the third overlapping region.

[0154] In an exemplary embodiment, the first overlapping region may be symmetrical with respect to an orthographic projection of a centerline of the anode main portion of the first subpixel P1 extending along at least one of the first direction X and the second direction Y on the substrate; the second overlapping region may be symmetrical with respect to an orthographic projection of a centerline of the anode main portion of the second subpixel P2 extending along at least one of the first direction X and the second direction Y on the substrate; and the third overlapping region may be symmetrical with respect to an orthographic projection of a centerline of the anode main portion of the third subpixel P3 extending along at least one of the first direction X and the second direction Y on the substrate. In an exemplary embodiment, the overlapping region between the anode main portion and the second source / drain metal layer is symmetrical with respect to an orthographic projection of the centerline of the anode main portion extending along at least one of the first direction X and the second direction Y on the substrate, which can reduce color shift and thereby improve display quality.

[0155] In an exemplary embodiment, the driving circuit layer may include a plurality of pixel driving circuits, at least some of the sub-pixels may include the pixel driving circuits, and at least some of the pixel circuits may include: at least one first type transistor and at least one second type transistor; the driving circuit layer may include at least a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer sequentially disposed on a substrate, wherein:

[0156] The first semiconductor layer includes at least: an active layer of a first type transistor in a pixel driving circuit; the first conductive layer includes at least: a gate of the first type transistor; the second conductive layer includes at least: a bottom gate of a second type transistor; the second semiconductor layer includes at least: an active layer of the second type transistor; and the third conductive layer includes at least: a top gate of the second type transistor.

[0157] In an exemplary embodiment, as shown in FIG6 , the first type transistors may include at least first to seventh transistors T1 to T7 and a ninth transistor T9 , and the second type transistors include at least an eighth transistor T8 ;

[0158] In a direction parallel to the plane of the display substrate, in a first direction X, the fourth transistor T4 and the fifth transistor T5 are located on the same side of the third transistor T3, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are located on the other side of the third transistor T3, and the eighth transistor T8 is located between the second transistor T2 and the fourth transistor T4. In a second direction Y, the fourth transistor T4 and the fifth transistor T5 are respectively located on either side of the third transistor T3, the fifth transistor T5 to the seventh transistor T7, and the ninth transistor T9 are located on the same side of the third transistor T3, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the eighth transistor T8 are located on the same side of the third transistor T3. The first direction X intersects with the second direction Y.

[0159] In an exemplary embodiment, as shown in FIG6 , the pixel driving circuits of the plurality of sub-pixels are arranged in an array. In the same column of pixel driving circuits, in the first direction X, the first transistor T1 in the sub-pixel in the i-th row is located between the seventh transistor T7 and the ninth transistor T9 in the sub-pixel in the i-1-th row, where i=2, 3, …, M+1, and M is an integer greater than or equal to 1.

[0160] In an exemplary embodiment, the first conductive layer may further include a first scan signal line extending along the first direction X, and the first scan signal line located in the i-th row is electrically connected to the first transistor T1 located in the i-1th row, the seventh transistor T7 located in the i-1th row, and the ninth transistor T9 located in the i-1th row.

[0161] In example embodiments, the first type transistor may be a low temperature polysilicon transistor, and the second type transistor may be an oxide transistor.

[0162] In an exemplary embodiment, as shown in FIG7 , the driving circuit layer may further include a fourth conductive layer. In a direction perpendicular to the plane of the display substrate, the fourth conductive layer may be located on a side of the third conductive layer away from the substrate. The fourth conductive layer may include a plurality of second initial signal lines 59 and a plurality of rows of second initial signal connection lines 510.

[0163] The pixel driving circuits of the plurality of sub-pixels Pxij are formed into a plurality of rows, and the plurality of second initial signal lines 59 are electrically connected to the plurality of rows of pixel driving circuits, respectively. The plurality of second initial signal lines 59 extend along a first direction X in a direction parallel to the plane of the display substrate and are arranged at intervals along a second direction Y, where the first direction X intersects the second direction Y.

[0164] Each row of second initial signal connection lines includes a plurality of second initial signal connection lines 510 extending along the second direction Y and arranged at intervals along the first direction X. In the second direction Y, each row of second initial signal connection lines can be located between two adjacent second initial signal lines 59, and the two ends of the plurality of second initial signal connection lines 510 in each row of second initial signal connection lines 510 are respectively connected to the two adjacent second initial signal lines 59.

[0165] In an exemplary embodiment, each second initial signal line 59 is electrically connected to the seventh transistor T7 in one row of pixel driving circuits, and the multiple second initial signal lines 59 are connected as a whole through multiple second initial signal connecting lines 510, so that the multiple second initial signal connecting lines 510 and the multiple second initial signal lines 59 form an interconnected grid structure, so that the multiple second initial signal lines 59 have the same electric potential, and the electric potentials of the second initial signals written into the first electrodes of the seventh transistors T7 in different rows of pixel driving circuits are basically the same, which is beneficial to improving the display uniformity of the display panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0166] In an exemplary embodiment, as shown in FIG6 and FIG7 , the driving circuit layer further includes a fifth conductive layer. In a direction perpendicular to the plane of the display substrate, the fifth conductive layer is located on a side of the fourth conductive layer away from the substrate. The fifth conductive layer may include a plurality of second power supply lines 64, and the second conductive layer may further include a plurality of second power connection lines 32. The fifth conductive layer may be referred to as a second source-drain metal layer.

[0167] In a direction parallel to the plane of the display substrate, multiple second power lines 64 extend along the second direction Y and are arranged at intervals along the first direction X. Multiple second power connection lines 32 extend along the first direction X and are arranged at intervals along the second direction Y. The multiple second power lines 64 and the multiple second power connection lines 32 are electrically connected through vias to form a grid structure. This allows the second power lines 62 in the display substrate to have substantially the same potential, which is beneficial to improving the uniformity of the panel and ensuring the display effect of the display substrate.

[0168] In an exemplary embodiment, as shown in FIG8 , which is a schematic diagram of an equivalent circuit of a pixel driving circuit provided in an embodiment of the present disclosure, the difference from FIG4 is that an eighth transistor T8, a ninth transistor T9, a third scanning signal line S3, and a third initial signal line Vinit3 are newly added, wherein the eighth transistor T8 is an N-type transistor (oxide transistor) and the ninth transistor T9 is a P-type transistor (low-temperature polysilicon transistor); the first scanning signal line S1 is electrically connected to the control electrode of the first transistor T1, the control electrode of the seventh transistor T7, and the control electrode of the ninth transistor T9; the control electrode of the second transistor T2 and the control electrode of the fourth transistor T4 are electrically connected to the second scanning signal line S2; the first electrode of the eighth transistor T8 is connected to the second node N2, the second electrode of the eighth transistor T8 is connected to the fourth node N4, and the control electrode of the eighth transistor T8 is connected to the third scanning signal line S3; the second electrode of the first transistor T1 is connected to the fourth node N4; the first electrode of the ninth transistor T9 is connected to the third initial signal line Vinit3, the second electrode of the ninth transistor T2 is connected to the first node N1, and the control electrode of the ninth transistor T2 is connected to the first scanning signal line S1.

[0169] In an exemplary embodiment, as shown in FIG9a and FIG9b , in a direction parallel to the plane of the display substrate, the display substrate includes a first display area A1, a second display area A2, and a connection area B12. The first display area A1 and the second display area A2 are connected by the connection area B12. The second display area A2 at least partially surrounds the first display area A1. Pixel driving circuits for a plurality of sub-pixels are located in the first display area A1 and the second display area A2, forming a plurality of columns.

[0170] As shown in Figures 6, 7, and 9a, the third conductive layer may further include a plurality of second data signal connection lines 44, and the fifth conductive layer may further include a plurality of first data signal lines 611 and a plurality of second data signal lines 612 (i.e., the data signal lines 61 may include first data signal lines 611 and second data signal lines 612); the plurality of first data signal lines 611 are respectively electrically connected to the plurality of columns of pixel driving circuits located in the first display area A1, and the plurality of second data signal lines 612 are respectively electrically connected to the plurality of columns of pixel driving circuits located in the second display area A2; the plurality of second data signal connection lines 44 are located in the second display area A2 and are respectively electrically connected to the plurality of columns of pixel driving circuits located in the second display area A2. In an exemplary embodiment, the structures shown in Figures 6 and 7 are schematic diagrams of the structure of the two-row, six-column pixel driving circuit in the second display area A2. The difference between the pixel driving circuit in the first display area A1 and Figures 6 and 7 is that the second data signal connection lines 44 are not provided. That is, the pixel driving circuit structure in the first display area A1 is obtained by removing the second data signal connection lines 44 from Figures 6 and 7.

[0171] As shown in Figures 9a and 9b, the first display area A1 is provided with a first outer frame B1 on its periphery, and the second display area A2 may be provided with a second inner frame B21 and a second outer frame B22 on either side. Figure 9b illustrates two second data signal lines 612 in the second display area A2, but there may be more than two. The number of second data signal lines 612 provided in the second display area A2 may be, but is not limited to, 24, 48, or 72. As shown in Figure 9b, each second data signal connection line 44 may be electrically connected to a second data signal line 612 in the second display area A2 at one end, and the other end extends along the outer frame B1 of the first display area A1 to the binding area B10 and is electrically connected to the driver chip 90 located in the binding area B10. In an exemplary embodiment, the number of second data signal lines 612 matches the number of second data signal connection lines 44, and each second data signal line 612 is electrically connected to the driver chip 90 via a second data signal connection line 44.

[0172] In an exemplary embodiment, a plurality of sub-pixels Pxij form a plurality of pixel units P, the plurality of pixel units P are arranged in an array, the pixel unit includes at least three adjacent sub-pixels Pxij, the second power line 64 and the second initial signal connection line 510 are arranged between two adjacent columns of pixel units, and the second power connection line 32 and the second data signal connection line 44 are located between two adjacent rows of pixel units.

[0173] The present disclosure also provides a display substrate, as shown in FIG9a and FIG9b , which may include a first display area A1, a second display area A2, a binding area B10, and a connection area B12. The first display area A1 and the second display area A2 are connected via the connection area A12. The second display area A2 at least partially surrounds the first display area A1. In a direction parallel to the plane of the display substrate, the binding area B10 is located on one side of the first display area A1.

[0174] The second display area A2 is provided with multiple second data signal lines 612 and multiple second data signal connection lines 44. One end of the multiple second data signal connection lines 44 is electrically connected to the multiple second data signal lines 612 respectively, and the other end is electrically connected to the components set in the binding area B10.

[0175] In an exemplary embodiment, in a direction parallel to the plane of the display substrate, the binding area B10 and the connection B12 can be located on opposite sides of the first display area A1, and the elements set in the binding area B10 can include a driving chip 90, and one end of the plurality of second data signal connection lines 44 is electrically connected to the driving chip 90.

[0176] In an exemplary embodiment, as shown in Figure 9c, which is an enlarged schematic diagram of the position of M1 in Figure 9a, the second display area A2 is provided with a plurality of pixel units P, and the plurality of pixel units P form a plurality of second pixel unit rows and a plurality of second pixel unit columns. Along the direction from the first display area A1 to the second display area A2, the plurality of second pixel unit columns are arranged in sequence, and the distance between two adjacent second pixel unit rows increases in sequence from the first second pixel unit column to the last second pixel unit column.

[0177] In an exemplary embodiment, the first display area A1 may be provided with a plurality of pixel units, the plurality of pixel units forming a plurality of first pixel unit rows and a plurality of first pixel unit columns PL1, the plurality of first pixel unit columns PL1 being arranged along a first direction X, and the plurality of pixel units in each first pixel unit column being arranged along a second direction Y. In an exemplary embodiment, an arrangement direction of the plurality of pixel units in the first pixel unit column and an arrangement direction of the plurality of pixel units P in the second pixel unit column form a certain angle.

[0178] In an exemplary embodiment, one first pixel unit column may include three adjacent columns of sub-pixels, and one second pixel unit column may include three adjacent columns of sub-pixels.

[0179] In an exemplary embodiment, as shown in Figures 9b and 9c, the first display area A1 is provided with a plurality of first data signal lines 611, and the extension direction of the plurality of first data signal lines 611 is consistent with the arrangement direction of the plurality of pixel units P in the first pixel unit column PL1, and each first data signal line 611 is electrically connected to a plurality of sub-pixels Pxij in a sub-pixel column in a first pixel unit column PL1; the extension direction of the plurality of second data signal lines 612 in the second display area A2 is consistent with the arrangement direction of the plurality of pixel units in the second pixel unit column, and each second data signal line 612 is electrically connected to a plurality of sub-pixels Pxij in a sub-pixel column in a second pixel unit column.

[0180] In an exemplary embodiment, the first display area A1 is circular, and the second display area A2 is strip-shaped at least partially surrounding the first display area A1. As shown in Figures 9a and 9b, the strip-shaped second display area A2 may be arc-shaped.

[0181] In an exemplary embodiment, as shown in FIG9d , the display substrate may further include a first outer frame area B1, which is disposed around the first display area A1. The first outer frame area B1 includes a connection area A12 and a binding area B10. The first outer frame area B1 is provided with a plurality of second data signal transfer lines 440. The second data signal transfer lines 440 and the second data signal connection lines 44 are located on different conductive layers.

[0182] The second data signal connection line 44 extends from the second display area A2 to the connection area B12, and multiple second data signal adapter lines 440 extend from the connection area B12 along the first outer frame area B1 to the binding area B10, one end of which is electrically connected to the multiple second data signal connection lines 44 located in the connection area B12, and the other end is electrically connected to the driver chip 90.

[0183] In an exemplary embodiment, the second data signal transfer line 440 can be located in the fourth conductive layer (i.e., the first source and drain metal layer), the second data signal connection line 44 can be located in the third conductive layer (i.e., the third gate metal layer), and in the connection area B12, the second data signal transfer line 440 and the corresponding second data signal connection line 44 can be connected through a via.

[0184] In an exemplary embodiment, as shown in Figures 9a and 9b, the display substrate may further include a second outer frame area B22 and a second inner frame area B21, and along the direction from the first display area A1 to the second display area A2, the second inner frame area B21 and the second inner frame area B21 are located on both sides of the second display area A2.

[0185] In an exemplary embodiment, as shown in Figure 9c, the second inner frame area B21 is connected to the first outer frame area B1 through the connection area B12, and the first outer frame area B1 and the second inner frame area B21 are provided with a second power signal supply line VSS. The second power signal supply line VSS is electrically connected to the driving chip 90 and extends through the first outer frame area B1 to the second inner frame area B21.

[0186] In an exemplary embodiment, the display substrate may further include a cathode layer. The second display area A2 includes a second power connection line 32 (see Figures 6 and 7 ) electrically connected to the second power signal supply line VSS in the second inner frame area B21. The second outer frame area B22 includes a second power connection line VSS0 that overlaps with the cathode layer and the second power connection line 32. The second power connection line VSS0 is electrically connected to the second power connection line 32 and the cathode layer through a via. The second power connection line VSS0 receives the second power signal from the driver chip via the second power connection line 32 and the second power signal supply line VSS and supplies it to the cathode layer.

[0187] In an exemplary embodiment, the second power signal supply line VSS located in the first outer frame area B1 overlaps with the cathode layer and is electrically connected to the cathode layer through a via hole.

[0188] In an exemplary embodiment, the second power signal supply line VSS in the second inner frame area B21 has a smaller line width and is not electrically connected to the cathode layer, which can reduce the frame between the second display area A1 and the first display area A2.

[0189] In an exemplary embodiment, along the direction from the second display area A2 to the second inner frame area B21, the second inner frame area B21 sequentially includes: a first-type gate driving circuit GOA1 and a first-type driving signal line L1 electrically connected thereto, an initial signal line Vinit, a first power signal supply line VDD, and a second power signal supply line VSS;

[0190] Along the direction from the second display area A2 to the second outer frame area B22, the second outer frame area B22 includes in sequence: a second type gate drive circuit GOA2 and a second type drive signal line L2 electrically connected to it, and a second power supply jumper line VSS0, wherein the second type drive signal line L2 is electrically connected to the drive chip 90 via the second outer frame area V22, the second inner frame area B21, and the first outer frame area B1.

[0191] In an exemplary embodiment, the first type of gate drive circuit GOA1 may include a gate drive circuit that provides a scan signal to the second transistor T2 and the fourth transistor T4 (i.e., provides a scan signal to the second scan signal line S2), and the second type of gate drive circuit GOA2 may include a gate drive circuit that provides a first scan signal to the above-mentioned first scan signal line S1 (i.e., provides a first scan signal to the first transistor T1, the seventh transistor T7, and the ninth transistor T9), a gate drive circuit that provides a third scan signal to the third scan signal line S3 (i.e., provides a third scan signal line to the eighth transistor T8), and a gate drive circuit that provides a light-emitting control signal to the light-emitting control line E (i.e., provides a light-emitting control signal to the fifth transistor T5 and the sixth transistor T6).

[0192] In an exemplary embodiment, the connection area B12 is provided with an initial signal transfer electrode ZL1 provided at a different layer from the initial signal line Vinit, a first power transfer electrode ZL2 provided at a different layer from the first power signal supply line VDD, a second power transfer electrode ZL3 provided at a different layer or the same layer as the second power signal supply line VSS, and a drive signal transfer electrode ZL4 provided at a different layer from the first type drive signal line L1.

[0193] Along the direction from the first display area A1 to the first outer frame area B1, the first outer frame area B1 sequentially includes: a first power signal supply line VDD, an initial signal line Vinit, a first type driving signal line L1, and a second power signal supply line VSS;

[0194] The first power signal supply line VDD located in the first outer frame area B1 is electrically connected to the first power signal supply line VDD located in the second inner frame area B21 through the first power adapter electrode ZL2; the initial signal line Vinit located in the first outer frame area B1 is electrically connected to the initial signal line Vinit located in the second inner frame area B21 through the initial signal adapter electrode ZL1; the first type drive signal line L1 located in the first outer frame area B1 is electrically connected to the first type drive signal line L1 through the drive signal adapter electrode ZL4, and the second power signal supply line VSS located in the first outer frame area B1 is electrically connected to the second power signal supply line VSS located in the second inner frame area B21 through the second power adapter electrode ZL3.

[0195] In an exemplary embodiment, as shown in FIG9c , in the direction from the first display area A1 to the first outer frame area B1, the first outer frame area B1 is located between the initial signal line Vinit and the second power signal supply line VSS, and a first type of gate drive circuit GOA1 and a first type of drive signal line L1 electrically connected thereto, and a second type of gate drive circuit GOA2 and a second type of drive signal line L2 electrically connected thereto may also be provided.

[0196] In an exemplary embodiment, as shown in Figures 9c and 9e, the first type of drive signal lines and the second type of drive signal lines located in the first outer border area B1 each include two groups, wherein one group of the first type of drive signal lines L1 is configured to be electrically connected to the first type of gate drive circuit GOA1 that provides a scan signal to the first display area A1, and the other group of the first type of gate drive signal lines L1 is configured to be electrically connected to the first type of gate drive circuit GOA1 that provides a scan signal to the second display area A2 and is located in the second inner border area B21; wherein one group of the second type of drive signal lines L2 is configured to be electrically connected to the second type of gate drive circuit GOA2 that provides a scan signal to the first display area A1, and the other group of the second type of gate drive signal lines L2 is configured to be electrically connected to the second type of gate drive circuit GOA2 that provides a scan signal to the second display area A2 and is located in the second outer border area B22. The first type gate drive circuit GOA1 located in the first inner frame area B1 and the first type gate drive circuit GOA1 located in the second inner frame area B21 are connected to different first type drive signal lines L1, and the second type gate drive circuit GOA2 and the second type gate drive circuit GOA2 located in the second outer frame area B22 are connected to different second type drive signal lines L2. On the one hand, the first display area A1 and the second display area A2 can be driven separately and more flexibly. On the other hand, the load on the second type drive signal line L2 and the first type drive signal line L1 connected to the second type gate drive circuit GOA2 located in the second outer frame area B22 and the first type gate drive circuit GOA1 located in the second inner frame area B21 is reduced, which can control The brightness of the first display area A1 and the second display area A2 are as consistent as possible to avoid the situation where the second type of drive signal line L2 is connected to the second type of gate drive circuit GOA2 located in the first outer frame area B1 due to a large load, resulting in inconsistent potentials of the second type drive circuit GOA2 located in the first outer frame B22 and the second type of drive circuit GOA2 located in the first outer frame B1; and to avoid the situation where the first type of drive signal line L1 is connected to the first type of gate drive circuit GOA1 located in the first outer frame area B1 due to a large load, resulting in inconsistent potentials of the first type drive signal line L1 received by the first type drive circuit GOA1 located in the first inner frame B21 and the first type of drive circuit GOA1 located in the first outer frame B1.

[0197] In an exemplary embodiment, the initial signal line Vinit may include the first initial signal line Vinit1 connected to the first electrode of the first transistor T1, the second initial signal line Vinit2 connected to the first electrode of the seventh transistor T7, and the third initial signal line Vinit3 connected to the first electrode of the ninth transistor T9.

[0198] In an exemplary embodiment, as shown in Figure 9f, the second display area A2 may further include a plurality of second-type scanning signal lines SL2, the output end of each second-type gate drive circuit GOA2 is electrically connected to two corresponding second-type scanning signal lines SL2, and each second-type scanning signal line SL2 is electrically connected to a plurality of sub-pixels in one of the second pixel unit rows PH2.

[0199] In an exemplary embodiment, as shown in FIG9 f , each second-type gate driving circuit GOA2 has the same size as its two adjacent second pixel unit rows PH2 in the extending direction of the second outer frame area B22 ;

[0200] Alternatively, as shown in FIG9g , each second-type gate driving circuit GOA is divided into two connected circuit parts, and the two circuit parts are respectively consistent with the sizes of two adjacent second pixel unit rows in the extending direction of the second outer frame area;

[0201] Alternatively, as shown in Figure 9h, two adjacent second pixel unit rows are used as a unit module PC, and the distance between the two adjacent unit modules PC in the extension direction of the second outer frame area B22 is greater than the distance between the two second pixel units P in the same unit module, and each second type of gate driving circuit is consistent with the size of an adjacent unit module PC in the extension direction of the second outer frame area B22.

[0202] In the embodiment of the present disclosure, the first display area can be used as the main screen display area, and the second display area can be used as the secondary screen display area. In an exemplary embodiment, the main screen display area can be used as the secondary screen display area, and the secondary screen display area can be used as the main screen display area.

[0203] In an exemplary embodiment, an edge ring display (ERD) watch may include a primary display area and a secondary display area. First display area A1 may serve as the primary display area, while second display area A2 may serve as the secondary display area. In an exemplary embodiment, as shown in Figure 9i, which illustrates the structure of an ERD watch after assembly of the display substrate in Figure 9a, first display area A1 may be located on the front of the watch, while second display area A2 may be located on the side of the watch.

[0204] In an exemplary embodiment, the first direction X may be a row direction of the plurality of pixel units, and the second direction Y may be a column direction of the plurality of pixel units.

[0205] The following is an illustrative explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a layer of thin film made by deposition, coating or other processes on a substrate (or base substrate). If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0206] In an exemplary embodiment, taking 12 sub-pixels (2 sub-pixel rows and 6 sub-pixel columns) in a display area (AA) as an example, a process for preparing a display substrate may include the following operations.

[0207] (101) Prepare a substrate on a glass carrier. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the adhesive layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible material (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible material (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0208] (102) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the blocking layer pattern, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG10 , which is a plan view schematic diagram of the first semiconductor layer of twelve sub-pixels.

[0209] In an exemplary embodiment, the first semiconductor layer pattern of each sub-pixel may include the active layer 11 of the first transistor T1 to the active layer 17 of the seventh transistor T7, and the active layer 19 of the ninth transistor T9, and the active layer 11 of the first transistor T1 to the active layer 17 of the seventh transistor T7 are an integrated structure connected to each other.

[0210] In an exemplary embodiment, in the first direction X, the active layer 14 of the fourth transistor T4 and the active layer 15 of the fifth transistor T5 are located on the same side of the active layer 13 of the third transistor T3, and the active layer 12 of the second transistor T2, the active layer 16 of the sixth transistor T6, and the active layer 17 of the seventh transistor T7 are located on the other side of the active layer 13 of the third transistor T3; in the second direction Y, the active layer 14 of the fourth transistor T4 and the active layer 15 of the fifth transistor T5 are located on both sides of the active layer 13 of the third transistor T3, and the active layer 15 of the fifth transistor T5, the active layer 16 of the sixth transistor T6, the active layer 17 of the seventh transistor T7, and the active layer 19 of the ninth transistor T9 are located on the third transistor T3. 3, the active layer 14 of the fourth transistor T4, the active layer 12 of the second transistor T2, and the active layer 11 of the first transistor T1 are located on the same side of the active layer 13 of the third transistor T3, the active layer 17 of the seventh transistor T7 is located on a side of the active layer 16 of the sixth transistor T6 away from the active layer 12 of the second transistor T2, the active layer 11 of the first transistor T1 is located on a side of the active layer 12 of the second transistor T2 away from the active layer 16 of the sixth transistor T6, and the first region 11-1 of the active layer 11 of the first transistor T1 extends to the active layer of an adjacent row and is located between the active layer 19 of the ninth transistor T9 and the active layer 17 of the seventh transistor T7 in the adjacent row in the first direction X.

[0211] In an exemplary embodiment, the sub-pixel in the Mth row and the Nth column is used as an example for description: in the first direction X, the active layer 14 of the fourth transistor T4 and the active layer 15 of the fifth transistor T5 are located on the side of the active layer 13 of the third transistor T3 away from the sub-pixel in the N+1th column, and the active layer 12 of the second transistor T2, the active layer 16 of the sixth transistor T6, and the active layer 17 of the seventh transistor T7 are located on the side of the active layer 13 of the third transistor T3 away from the sub-pixel in the N-1th column; in the second direction Y, the active layer 11 of the first transistor T1, the active layer 12 of the second transistor T2, and the active layer 18 of the fourth transistor T4 are located on the side of the active layer 13 of the third transistor T3 away from the sub-pixel in the N-1th column. 14 is located on a side of the active layer 13 of the third transistor T3 away from the sub-pixels in the M+1th row, the active layer 15 of the fifth transistor T5, the active layer 16 of the sixth transistor T6, the active layer 17 of the seventh transistor T7, and the active layer 19 of the ninth transistor T9 are located on a side of the active layer 13 of the third transistor T3 away from the sub-pixels in the M-1th row, the active layer 17 of the seventh transistor T7 is located on a side of the active layer 16 of the sixth transistor T6 away from the active layer 13 of the third transistor T3, and the active layer 11 of the first transistor T1 is located on a side of the active layer 12 of the second transistor T2 away from the active layer 13 of the third transistor T3.

[0212] In an exemplary embodiment, the active layer 13 of the third transistor T3 may have a Z-shape, the active layer 11 of the first transistor T1, the active layer 12 of the second transistor T2, the active layer 14 of the fourth transistor T4, and the active layer 19 of the ninth transistor T9 may have an I-shape, the active layer 15 of the fifth transistor T5 may have a Z-shape, the active layer 16 of the sixth transistor T6 may have a zigzag shape extending along the second direction Y, and the active layer 17 of the seventh transistor T7 may have an L-shape.

[0213] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 13-1 of the active layer 13 of the third transistor T3 may serve as the second region 14-2 of the active layer 14 of the fourth transistor T4 and the second region 15-2 of the active layer 15 of the fifth transistor T5. The second region 13-2 of the active layer 13 of the third transistor T3 may serve as the second region 12-2 of the active layer 12 of the second transistor T2. The first region 16-1 of the active layer 16 of the sixth transistor T6 and the second region 16-2 of the active layer 16 of the sixth transistor T6 may serve as the active layer 16 of the seventh transistor T7. The second region 17-2 of the active layer 17, the second region 11-2 of the active layer 11 of the first transistor T1 can serve as the first region 12-1 of the active layer 12 of the second transistor T2, the first region 11-1 of the active layer 11 of the first transistor T1, the first region 14-1 of the active layer 14 of the fourth transistor T4, the first region 15-1 of the active layer 15 of the fifth transistor T5, the first region 17-1 of the active layer 17 of the seventh transistor T7, and the first region 19-1 and the second region 19-2 of the active layer 19 of the ninth transistor T9 can be set separately.

[0214] In an exemplary embodiment, the first region 11 - 1 of the active layer 11 of the first transistor T1 in the i-th row of sub-pixels may be disposed in the i−1-th row of sub-pixels, i=2, 3, . . . , M+1.

[0215] In exemplary embodiments, the shapes of active layers of the plurality of sub-pixels may be the same.

[0216] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning that the first transistor T1 to the seventh transistor T7 and the ninth transistor T9 may be LTPS thin-film transistors. In an exemplary embodiment, patterning the first semiconductor thin film through a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film, performing a dehydrogenation treatment on the amorphous silicon thin film, and then crystallizing the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, patterning the polycrystalline silicon thin film to form a first semiconductor layer pattern.

[0217] (103) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG11a and FIG11b , FIG11b being a planar schematic diagram of the first conductive layer in FIG11a . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0218] In an exemplary embodiment, the first conductive layer pattern may include at least: a first scan signal line 21, a second scan signal line 22, a first plate 23 of a storage capacitor, and a light-emitting control line 24. The main parts of the first scan signal line 21, the second scan signal line 22, and the light-emitting control line 24 may extend along the first direction X. In the same sub-pixel, the first scan signal line 21, the second scan signal line 22, the first plate 23 of the storage capacitor, and the light-emitting control line 24 may be arranged at intervals along the second direction Y.

[0219] In an exemplary embodiment, in the second direction Y, the second scan signal line 22 and the light emission control line 24 are located on both sides of the first plate 23 of the storage capacitor, the first scan signal line 21 is located on a side of the second scan signal line 22 away from the first plate 23 of the storage capacitor, and the third scan signal line 35 is located on a side of the light emission control line 24 away from the first plate 23 of the storage capacitor. For example, in the second direction Y, the second scan signal line 22, the first plate 23 of the storage capacitor, the light emission control line 24, and the first scan signal line 21 are arranged in sequence.

[0220] Take the M-th row and N-th column sub-pixel as an example: in the second direction Y, the second scanning signal line 22 can be located on the side of the first plate 23 of the storage capacitor in this sub-pixel close to the M-1-th row sub-pixel; the light-emitting control line 24 can be located on the side of the first plate 23 of the storage capacitor in this sub-pixel close to the M+1-th row sub-pixel; the first scanning signal line 21 can be located on the side of the light-emitting control line 24 away from the first plate 23 of the storage capacitor.

[0221] In an exemplary embodiment, the first electrode plate 23 may be located between the light-emitting control line 24 and the second scan signal line 22. The first electrode plate 23 may be rectangular, the corners of the rectangle may be chamfered, and the edges of the rectangle may be folded lines. The orthographic projection of the first electrode plate 23 on the substrate overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 23 may serve as both a plate of the storage capacitor and a control electrode of the third transistor T3.

[0222] In an exemplary embodiment, a region where the light emission control line 24 (i.e., the light emission signal line E in FIG8 ) overlaps with the active layer of the fifth transistor T5 may serve as the control electrode of the fifth transistor T5, a region where the light emission control line 24 overlaps with the active layer of the sixth transistor T6 may serve as the control electrode of the sixth transistor T6, a region where the first scan signal line 21 (i.e., the first scan signal line S1 in FIG8 ) overlaps with the active layer of the first transistor T1 may serve as the control electrode of the first transistor T1, a region where the first scan signal line 21 overlaps with the active layer of the seventh transistor T7 may serve as the control electrode of the seventh transistor T7, a region where the first scan signal line 21 overlaps with the active layer of the ninth transistor T9 may serve as the control electrode of the ninth transistor T9, a region where the second scan signal line 22 (i.e., the second scan signal line S2 in FIG8 ) overlaps with the active layer of the second transistor T2 may serve as the control electrode of the second transistor T2, and a region where the second scan signal line 22 overlaps with the active layer of the fourth transistor T4 may serve as the control electrode of the fourth transistor T4.

[0223] In an exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, and the light emitting control line 24 can be designed with equal width, or can be designed with unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0224] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7 and the ninth transistor T9, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first and second areas of the active layer 11 of the first transistor T1 to the active layer 17 of the seventh transistor T7 and the active layer 19 of the ninth transistor T9 are all conductorized.

[0225] (104) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in Figures 12a and 12b, where Figure 12a is a planar structural diagram of twelve sub-pixels, and Figure 12b is a planar schematic diagram of the second conductive layer in Figure 12a. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0226] In an exemplary embodiment, the second conductive layer pattern includes at least: a first shielding line 31, a second power connection line 32, and a second plate 33 of a storage capacitor. The main portions of the first shielding line 31 and the second power connection line 32 can extend along the first direction X. The second plate 33 of the storage capacitor can serve as another plate of the storage capacitor. In the second direction Y, the first shielding line 31 and the second power connection line 32 can be located on both sides of the second plate 33, respectively. For example, in the same sub-pixel, the first shielding line 31, the second plate 33 of the storage capacitor (i.e., the storage capacitor C in FIG8 ), and the second power connection line 32 can be arranged sequentially along the second direction Y.

[0227] In an exemplary embodiment, the first shielding line 31 is configured as a shielding layer for the eighth transistor T8, shielding the channel of the eighth transistor T8 to ensure the electrical performance of the oxide eighth transistor T8. In an exemplary embodiment, the first shielding line 31 and the subsequently formed third scan signal line can have the same signal. That is, the first shielding line 31 and the subsequently formed third scan signal line 41 are connected in parallel and are connected to the same signal source. This allows the first shielding line 31 to serve as the bottom gate electrode (i.e., bottom control electrode) of the eighth transistor T8, forming a dual-gate structure for the eighth transistor T8.

[0228] In an exemplary embodiment, the outline of the second electrode plate 33 can be rectangular, the corners of the rectangle can be chamfered, and the edges of the rectangle can be broken lines. The orthographic projection of the second electrode plate 33 on the substrate overlaps with the orthographic projection of the first electrode plate 33 on the substrate. The first electrode plate 23 and the second electrode plate 33 constitute the storage capacitor of the pixel driving circuit. The second electrode plate 33 is provided with an opening 34, which can be located in the middle of the second electrode plate 33. The opening 34 can be rectangular, so that the second electrode plate 33 forms an annular structure. The opening 34 exposes the third insulating layer covering the first electrode plate 23, and the orthographic projection of the first electrode plate 23 on the substrate includes the orthographic projection of the opening 34 on the substrate. In an exemplary embodiment, the opening 34 is configured to accommodate a twelfth via hole formed subsequently. The twelfth via hole is located within the opening 34 and exposes the first electrode plate 33, so that the first electrode of the eighth transistor T8 formed subsequently is connected to the first electrode plate 23.

[0229] (105) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG13a and FIG13b, where FIG13a is a planar structural diagram of twelve sub-pixels, and FIG13b is a planar schematic diagram of the second semiconductor layer in FIG13a.

[0230] In an exemplary embodiment, the second semiconductor layer pattern in each sub-pixel includes at least an active layer 18 of the eighth transistor T8 .

[0231] In an exemplary embodiment, the active layer 28 of the eighth transistor T8 may have an “L” shape, and the first region 18 - 1 and the second region 18 - 2 of the active layer 18 of the eighth transistor T8 may be separately provided.

[0232] In example embodiments, the shapes of the second semiconductor layers in a plurality of sub-pixel rows may be the same.

[0233] In an exemplary embodiment, within the plane of the display substrate, in the first direction X, the active layer 18 of the eighth transistor T8 may be located between the active layer 14 of the fourth transistor T4 and the active layer 12 of the second transistor T2; in the second direction Y, the active layer 18 of the eighth transistor T8 may be located on a side of the active layer 23 of the third transistor T3 away from the active layer 15 of the fifth transistor T5 and the active layer 16 of the sixth transistor T6.

[0234] In an exemplary embodiment, the sub-pixel in the Mth row and the Nth column is used as an example for description: in the first direction X, the active layer 11 of the first transistor T1, the active layer 12 of the second transistor T2, and the active layer 16 of the sixth transistor T6 are located on a side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N-1th column, the active layer 14 of the fourth transistor T4 and the active layer 15 of the fifth transistor T5 are located on a side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N+1th column, and the active layer 18 of the eighth transistor T8 is located between the active layer 14 of the fourth transistor T4 and the active layer 12 of the second transistor T2; in the second direction Y, the active layer 12 of the second transistor T2, the active layer 14 of the fourth transistor T4, and the active layer 18 of the eighth transistor T8 are located on a side of the active layer 13 of the third transistor T3 away from the sub-pixel in the M+1th row.

[0235] In an exemplary embodiment, the second semiconductor layer may be made of an oxide, i.e., the eighth transistor T8 is an oxide thin film transistor. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon. Since the leakage current of the IGZO TFT is relatively small, the eighth transistor T8 is an N-type transistor, which can prevent the first node N2 from leaking during the light-emitting stage.

[0236] (106) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fifth insulating film and a third conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG. 14a and FIG. 14b , FIG. 14a is a planar structural diagram of twelve sub-pixels, and FIG. 14b is a planar schematic diagram of the third conductive layer in FIG. 14a . In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0237] In an exemplary embodiment, the third conductive layer pattern includes at least: a third scanning signal line 41, a first initial signal line 42 (i.e., the first initial signal line Vinit1 in Figure 8), a third initial signal line 43, and a sub-screen data signal connection line 44. The main parts of the third scanning signal line 41, the first initial signal line 42, the third initial signal line 43, and the sub-screen data signal connection line 44 can extend along the first direction X. In the same sub-pixel row, the third scanning signal line 41, the first initial signal line 41, and the third initial signal line 43 can be arranged in sequence along the second direction Y.

[0238] In an exemplary embodiment, the sub-screen data signal connection line 44 may be disposed between two adjacent rows of sub-pixels.

[0239] In an exemplary embodiment, the region where the third scan signal line 41 (ie, the third scan signal line S3 in FIG. 8 ) overlaps with the active layer 18 of the eighth transistor T8 serves as a control electrode (also referred to as a top gate) of the eighth transistor T8 .

[0240] In an exemplary embodiment, the signals of the first blocking line 31 and the third scanning signal line 41 can be the same, that is, the two are connected in parallel and connected to the same signal source, so that the first blocking line 31 can serve as the bottom gate electrode (that is, the bottom control electrode) of the eighth transistor T8, forming the eighth transistor T8 with a dual-gate structure.

[0241] (107) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein a plurality of via holes are provided on the sixth insulating layer, as shown in FIG15 , which is a planar structural diagram of twelve sub-pixels.

[0242] In an exemplary embodiment, the multiple via holes in each sub-pixel include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10, an eleventh via hole V11, a twelfth via hole V12, a thirteenth via hole V13, a fourteenth via hole V14, a fifteenth via hole V15, a sixteenth via hole V16, a seventeenth via hole V17, and an eighteenth via hole V18.

[0243] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the orthographic projection of the active layer 11 of the first transistor T1 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away, exposing the surface of the first region 11-1 of the active layer 11 of the first transistor T1. The first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor T1 to the active layer 11 of the first transistor T1 through the via hole.

[0244] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the orthographic projection of the active layer 12 of the second transistor T2 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via hole V2 are etched away, exposing the surface of the second region 12-2 of the active layer 12 of the first transistor T1 (also the first region 12-1 of the active layer 12 of the second transistor T2). The second via hole V2 is configured to connect the second electrode of the subsequently formed first transistor T1 to the active layer 11 of the first transistor T1 through the via hole, and to connect the first electrode of the subsequently formed second transistor T2 to the active layer 12 of the second transistor T2 through the via hole.

[0245] In the exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the orthographic projection of the active layer 14 of the fourth transistor T4 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the first region 14-1 of the active layer 14 of the fourth transistor T4. The third via V3 is configured to connect the first electrode of the subsequently formed fourth transistor T4 to the active layer 14 of the fourth transistor T4 through the via.

[0246] In the exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the orthographic projection of the active layer 15 of the fifth transistor T5 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the first region 15-1 of the active layer 15 of the fifth transistor T5. The fourth via V4 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the active layer 15 of the fifth transistor T5 through the via.

[0247] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is within the orthographic projection of the active layer 15 of the fifth transistor T5 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via hole V5 are etched away, exposing the surface of the second region 15-2 of the active layer 15 of the fifth transistor T5 (also the first region 13-1 of the active layer 13 of the third transistor T3 and the second region 14-2 of the active layer 14 of the fourth transistor T4). The fifth via hole V5 is configured to connect the second electrode of a subsequently formed fifth transistor T5 to the active layer 15 of the fifth transistor T5 through the via hole, connect the first electrode of a subsequently formed third transistor T3 to the active layer 13 of the third transistor T3 through the via hole, and connect the second electrode of a subsequently formed fourth transistor T4 to the active layer 14 of the fourth transistor T4 through the via hole.

[0248] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the orthographic projection of the active layer 16 of the sixth transistor T6 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the second region 16-2 of the active layer 16 of the sixth transistor T6 (also the second region 17-2 of the active layer 17 of the seventh transistor T7). The sixth via V6 is configured to connect the second electrode of a subsequently formed sixth transistor T6 to the active layer 16 of the sixth transistor T6 through the via, and to connect the second electrode of a subsequently formed seventh transistor T7 to the active layer 17 of the seventh transistor T7 through the via.

[0249] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the orthographic projection of the active layer 17 of the seventh transistor T7 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the first region 17-1 of the active layer 17 of the seventh transistor T7. The seventh via V7 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the active layer 17 of the seventh transistor T7 through the via.

[0250] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the orthographic projection of the active layer 28 of the eighth transistor T8 on the substrate. The sixth insulating layer and the fifth insulating layer within the eighth via V8 are etched away, exposing the surface of the first region 18-1 of the active layer 28 of the eighth transistor T8. The eighth via V8 is configured to connect the first electrode of the subsequently formed eighth transistor T8 to the active layer 18 of the eighth transistor T8 through the via.

[0251] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the orthographic projection of the active layer 18 of the eighth transistor T8 on the substrate. The sixth and fifth insulating layers within the ninth via V9 are etched away, exposing the surface of the second region 18-2 of the active layer 18 of the eighth transistor T8. The ninth via V9 is configured to connect the second electrode of the subsequently formed eighth transistor T8 to the active layer 18 of the eighth transistor T8 through the ninth via V9.

[0252] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the orthographic projection of the active layer 19 of the ninth transistor T9 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the tenth via V10 are etched away, exposing the surface of the first region 19-1 of the active layer 19 of the ninth transistor T9. The tenth via V10 is configured to connect the first electrode of the subsequently formed ninth transistor T9 to the active layer 19 of the ninth transistor T9 through the via.

[0253] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the orthographic projection of the active layer 19 of the ninth transistor T9 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the eleventh via hole V11 are etched away, exposing the surface of the second region 19-2 of the active layer 19 of the ninth transistor T9. The eleventh via hole V11 is configured to connect the second electrode of the subsequently formed ninth transistor T9 to the active layer 19 of the ninth transistor T9 through the via hole.

[0254] In the exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the opening 34 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer within the twelfth via hole V12 are etched away, exposing the surface of the first electrode plate 23. The twelfth via hole V12 is configured to connect the first electrode of the subsequently formed eighth transistor T8 to the first electrode plate 23 through the via hole.

[0255] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second electrode plate 33 on the substrate. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the thirteenth via hole V13 are etched away, exposing the surface of the second electrode plate 33. The thirteenth via hole V13 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the second electrode plate 33 through the via hole. In an exemplary embodiment, a plurality of thirteenth via holes V13 serving as power via holes may be included, and the plurality of thirteenth via holes V13 may be arranged sequentially along the first direction X to increase the reliability of the connection between the first power connection line and the second electrode plate 33.

[0256] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the orthographic projection of the second electrode plate 33 on the substrate. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the fourteenth via V14 are etched away, exposing the surface of the second electrode plate 33. The fourteenth via V14 is configured to connect a subsequently formed fourth connection electrode or a first power adapter electrode to the second electrode plate 33 through this via. In an exemplary embodiment, a plurality of fourteenth vias V14 serving as power vias may be included, and the plurality of fourteenth vias V14 may be arranged sequentially along the second direction Y or the first direction X to increase the reliability of the connection between the first power connection line and the second electrode plate 33.

[0257] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the second power signal connection line 32 on the substrate. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the fifteenth via V15 are etched away, exposing the surface of the second power connection line 32. The fifteenth via V15 is configured to connect a subsequently formed second power signal line to the second power connection line 32 through the via.

[0258] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the first initial signal line 42 on the substrate. The sixth insulating layer within the sixteenth via hole V16 is etched away, exposing the surface of the first initial signal line 42. The sixteenth via hole V16 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first initial signal line 42 through the via hole.

[0259] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the third initial signal line 43 on the substrate. The sixth insulating layer within the seventeenth via hole V17 is etched away, exposing the surface of the third initial signal line 43. The seventeenth via hole V17 is configured to connect the first electrode of the subsequently formed ninth transistor T9 to the third initial signal line 43 through the via hole.

[0260] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the slave-screen data signal connection line 44 on the substrate. The sixth insulating layer within the eighteenth via hole V18 is etched away, exposing the surface of the slave-screen data signal connection line 44. The eighteenth via hole V18 is configured to allow a subsequently formed main-screen data signal line to be connected to the slave-screen data signal connection line 44 through the via hole.

[0261] (108) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 16a and FIG. 16b , where FIG. 16a is a planar structural diagram of twelve sub-pixels, and FIG. 16b is a planar schematic diagram of the fourth conductive layer in FIG. 16a . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0262] In an exemplary embodiment, the fourth conductive layer includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a sixth connecting electrode 56, a seventh connecting electrode 57, an eighth connecting electrode 58, a second initial signal line 59 (i.e., the second initial signal line Vinit2 in Figure 8), a second initial signal connecting line 510, a second power transfer electrode 511, and a first power transfer electrode 512.

[0263] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip with a main portion extending along the second direction Y. The first connection electrode 51 is connected to the first region 11-1 of the active layer 11 of the first transistor T1 through a first via hole V1, and is connected to the first initial signal line 42 in a sub-pixel row through a sixteenth via hole V16 in the row. In an exemplary embodiment, the first connection electrode 51 may serve as a first electrode of the first transistor T1 and is configured to be connected to the first initial signal line 42 and the active layer 21 of the first transistor T1.

[0264] In an exemplary embodiment, the main portion of the second connection electrode 52 extends along the first direction X. Its first end is connected to the second region 11-2 of the active layer 11 of the first transistor T1 (also the first region 12-1 of the active layer 12 of the second transistor T2) through a second via V2. Its second end is connected to the second region 18-2 of the active layer 18 of the eighth transistor T8 through a ninth via V9. This allows the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the second electrode of the eighth transistor T8 to have the same potential. In an exemplary embodiment, the second connection electrode 52 can serve as the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the second electrode of the eighth transistor T8.

[0265] In an exemplary embodiment, the third connection electrode 53 is connected to the first region 14-1 of the active layer 142 of the fourth transistor T4 via a third via hole V3. In an exemplary embodiment, the third connection electrode 53 may serve as the first electrode of the fourth transistor T4. In an exemplary embodiment, the third connection electrode 53 may also be connected to the secondary screen data signal connection line 44 via an eighteenth via hole V18. In an exemplary embodiment, not every third connection electrode 53 in the same sub-pixel row is connected to the secondary screen data signal connection line 44. For example, only one of the multiple third connection electrodes 53 in a sub-pixel row may be connected to the secondary screen data signal connection line 44.

[0266] In an exemplary embodiment, the fourth connection electrode 54 may be in the shape of a bar or a zigzag line extending along the second direction Y. One end of the fourth connection electrode 54 may be connected to the first region 15-1 of the active layer 15 of the fifth transistor T5 via a fourth via V4, and the other end may be connected to the second plate 33 of the capacitor via a thirteenth via V13. In an exemplary embodiment, the fourth connection electrode 54 may serve as the first electrode of the fifth transistor T5. In an exemplary embodiment, the fourth connection electrode 54 may be configured to be electrically connected to a subsequently formed first power line. Among the multiple fourth connection electrodes 54 in a subpixel row, not every fourth connection electrode 54 may be connected to a subsequently formed first power line. For example, if a pixel unit includes three subpixels, the fourth connection electrodes 54 in two subpixels in the pixel unit may be connected to a subsequently formed first power line, while the fourth connection electrode 54 in the remaining subpixel may not be connected to the subsequently formed first power line.

[0267] In an exemplary embodiment, the fifth connection electrode 55 may be in the shape of a bar extending along the second direction Y. The fifth connection electrode 55 is connected to the second region 15-2 of the active layer 15 of the fifth transistor T5 (also the second region 14-2 of the fourth transistor T4) via a fifth via hole V5. The fifth connection electrode 55 is connected to the second region 19-2 of the ninth transistor T9 via an eleventh via hole V11. In an exemplary embodiment, the fifth connection electrode 55 may serve as the second electrode of the fifth transistor T5, as well as the second electrode of the ninth transistor T9 and the second electrode of the fourth transistor T4.

[0268] In an exemplary embodiment, the sixth connection electrode 56 may be in a strip or zigzag shape extending along the second direction Y. The sixth connection electrode 56 is connected to the second region 16-2 of the active layer 26 of the sixth transistor T6 (also the second region 17-2 of the active layer 17 of the seventh transistor T7) through a sixth via hole V6. In an exemplary embodiment, the sixth connection electrode 56 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The sixth connection electrode 56 is configured to be connected to the anode connection electrode of a subsequently formed light-emitting element.

[0269] In an exemplary embodiment, the seventh connection electrode 57 may be in the shape of a bar or a zigzag line extending along the second direction Y. One end of the seventh connection electrode 57 is connected to the first region 18-1 of the active layer 18 of the eighth transistor T8 through an eighth via V8, and the other end is connected to the first electrode plate 23 through a twelfth via V12. In an exemplary embodiment, the seventh connection electrode 57 may serve as the first electrode of the eighth transistor T8.

[0270] In an exemplary embodiment, the eighth connection electrode 58 may be a zigzag shape extending along the second direction Y. One end of the eighth connection electrode 58 may be connected to the first region 19-1 of the active layer 19 of the ninth transistor T9 through a tenth via hole V10, and the other end may be connected to the third initial signal line 43 through a seventeenth via hole V16. In an exemplary embodiment, the eighth connection electrode 58 may serve as the first electrode of the ninth transistor T9.

[0271] In an exemplary embodiment, the second initial signal line 59 may be in the shape of a zigzag line with a main portion extending along the first direction X. The second initial signal line 59 connects to the first region 17-1 of the active layer 17 of the plurality of seventh transistors T7 in a subpixel row through a plurality of seventh via holes V7 in a subpixel row, thereby writing an initial voltage into the plurality of seventh transistors T7 in a subpixel row. In an exemplary embodiment, since the second initial signal line 59 is connected to the first region 17-1 of the active layer 27 of all the seventh transistors T7 in a subpixel row, the first electrodes of all the seventh transistors T7 in a subpixel row can be guaranteed to have the same potential, which helps improve the uniformity of the panel, prevent display defects on the display substrate, and ensure the display quality of the display substrate. In an exemplary embodiment, the second initial signal line 59 can serve as the first electrode of the seventh transistor T7. In an exemplary embodiment, in a subpixel row, the second initial signal line 59 can bend around the adjacent eighth connection electrode 58 along the second direction Y. For example, the second initial signal line 59 can bend around from one side of the eighth connection electrode 58 along the second direction Y.

[0272] In an exemplary embodiment, the second initial signal connection line 510 may be in the shape of a zigzag line or a strip, with its main portion extending along the second direction Y. Its ends are respectively connected to two adjacent second initial signal lines 59. In the second direction Y, the second initial signal connection line 510 is located between two adjacent second initial signal lines 59. In an exemplary embodiment, the second initial signal connection line 510 and the second initial signal lines 59 may be integrally formed. In an exemplary embodiment, the plurality of second initial signal lines 59 arranged along the second direction Y are connected into an integrated grid structure by the plurality of second initial signal connection lines 510, so that the plurality of second initial signal lines 59 have the same potential, which helps to improve the display uniformity of the display panel, avoid display defects on the display substrate, improve the quality of low grayscale images, and ensure the display effect of the display substrate. In an exemplary embodiment, a second initial signal connection line 510 can be set between two adjacent columns of sub-pixels or between two adjacent columns of pixel units (a pixel unit can include at least three sub-pixels arranged in sequence along the first direction X in a sub-pixel row). For example, as shown in Figure 16b, a pixel unit includes three sub-pixels arranged in sequence in a sub-pixel row, and multiple pixel units are arranged in an array. A second initial signal connection line 510 can be set between two adjacent pixel units, and a second initial signal connection line 510 can be set between the N+2th column and the N+3th column of sub-pixels. The spacing between two adjacent second initial signal connection lines 510 can be separated by three columns of sub-pixels.

[0273] In an exemplary embodiment, the second power transfer electrode 511 can be connected to the second power connection line 32 via the fifteenth via hole V15. The second power transfer electrode 511 can be configured to connect to a second power line formed subsequently. In an exemplary embodiment, the second power transfer electrode 511 is not provided in every sub-pixel. For example, in a row of sub-pixels, three sub-pixels arranged sequentially along the first direction X form a pixel unit, and a second power transfer electrode 511 can be provided in each pixel unit. In an exemplary embodiment, within a row of sub-pixels, the second initial signal line 59 can bend around adjacent second power transfer electrodes 511 along the second direction Y. For example, the second initial signal line 59 can bend around the side of the second power transfer electrode 511 opposite to the second direction Y.

[0274] In an exemplary embodiment, the first power transfer electrode 512 can be connected to the second electrode plate 33 through the fourteenth via hole V14. The first power transfer electrode 512 can be configured to be connected to a first power line formed subsequently. In an exemplary embodiment, the first power transfer electrode 512 is provided in some sub-pixels, and not every sub-pixel is provided with the first power transfer electrode 512; for example, in the Nth to N+5th columns of sub-pixels, the first power transfer electrode 512 is provided in the N+2nd and N+5th columns of sub-pixels, the first power transfer electrode 512 is not provided in the Nth, N+1th, N+3th, and N+4th columns of sub-pixels, the fourth connection electrode 54 in the Nth, N+1th, N+3th, and N+4th columns of sub-pixels is electrically connected to a first power line formed subsequently, and the fourth connection electrode 54 in the N+2nd and N+5th columns of sub-pixels is not electrically connected to the first power line formed subsequently.

[0275] In an exemplary embodiment, in the same row of sub-pixels, when the second initial signal line 59 is not provided between two adjacent columns of sub-pixels, one end of the fourth connection electrode 54 is connected to the active layer 15 and the second electrode plate 32 of the fifth transistor T5 in one of the columns of sub-pixels, and the other end extends into the adjacent column of sub-pixels and is electrically connected to a first power line formed subsequently; when the second initial signal line 59 is provided between two adjacent columns of sub-pixels, the fourth connection electrode 54 is connected to the active layer 15 and the second electrode plate 32 of the fifth transistor T5 in one of the columns of sub-pixels, and does not extend into the adjacent column of sub-pixels. The adjacent column of sub-pixels is electrically connected to the first power line formed subsequently through the first power adapter electrode 512.

[0276] In an exemplary embodiment, in the first direction X, the first power transfer electrode 512 is located on one side of the second initial signal line 59, and the fourth connection electrode 54 is located on the other side of the second initial signal line 59. In an exemplary embodiment, the fourth connection electrode 54 near the second initial signal line 59 may be in a stripe shape and is not electrically connected to a subsequently formed first power line, and the fourth connection electrode 54 not near the second initial signal line 59 may be in a zigzag shape. One end of the fourth connection electrode 54 is connected to the active layer 15 of the fifth transistor T5 in one column of sub-pixels, and the other end is located in an adjacent column of sub-pixels and is electrically connected to a subsequently formed first power line in the sub-pixels in that column.

[0277] (109) Forming a seventh insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the seventh insulating layer and the first planar layer pattern may include: first depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the seventh insulating film using a patterning process to form a seventh insulating layer covering the fourth conductive layer pattern and a first planar layer disposed on the seventh insulating layer, wherein a plurality of vias are disposed on the seventh insulating layer and the first planar layer, as shown in FIG17 , which is a planar structural diagram of twelve sub-pixels.

[0278] In an exemplary embodiment, the plurality of via holes in each sub-pixel may include at least a nineteenth via hole V19 , a twentieth via hole V20 , a twenty-first via hole V21 , a twenty-second via hole V22 , and a twenty-third via hole V23 .

[0279] In the exemplary embodiment, the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the third connection electrode 53 on the substrate. The first planar layer and the seventh insulating layer within the nineteenth via hole V19 are etched away, exposing the surface of the third connection electrode 53. The nineteenth via hole V19 is configured to connect a subsequently formed main screen data signal line to the third connection electrode 53 through the via hole.

[0280] In an exemplary embodiment, the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the sixth connection electrode 56 on the substrate. The first planar layer and the seventh insulating layer within the twentieth via hole V20 are etched away, exposing the surface of the sixth connection electrode 56. The twentieth via hole V20 is configured to electrically connect the anode connection electrode of a subsequently formed light-emitting element to the sixth connection electrode 56 through the via hole.

[0281] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the fourth connection electrode 54 on the substrate. The first planar layer and the seventh insulating layer within the twenty-first via hole V21 are etched away, exposing the surface of the fourth connection electrode 54. The twenty-first via hole V21 is configured to connect a subsequently formed first power line to the fourth connection electrode 54 through the via hole.

[0282] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is within the range of the orthographic projection of the second power transfer electrode 511 on the substrate. The first planar layer and the seventh insulating layer within the twenty-second via hole V22 are etched away, exposing the surface of the second power transfer electrode 511. The twenty-second via hole V22 is configured to connect a subsequently formed second power line to the second power transfer electrode 511 through the via hole.

[0283] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the first power transfer electrode 512 on the substrate. The first planar layer and the seventh insulating layer within the twenty-third via hole V23 are etched away, exposing the surface of the first power transfer electrode 512. The twenty-third via hole V23 is configured to connect a subsequently formed first power line to the first power transfer electrode 512 through the via hole.

[0284] (110) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG. 18a and FIG. 18b , where FIG. 18a is a planar structural diagram of twelve sub-pixels, and FIG. 18b is a planar schematic diagram of the fifth conductive layer in FIG. 18a . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0285] In an exemplary embodiment, the fifth conductive layer includes at least a data signal line 61 (i.e., a data signal line D in FIG8 ), a first power line 62 (i.e., a first power line VDD in FIG8 ), an anode connection electrode 63, and a second power line 64. In an exemplary embodiment, the anode connection electrode 63 is an anode connection electrode of the light-emitting element.

[0286] In an exemplary embodiment, the data signal line 61 is in the shape of a bar or a broken line, the main part of which extends along the second direction Y. The data signal line 61 is connected to the third connection electrode 53 through the nineteenth via V19. Since the third connection electrode 53 is connected to the first area 14-1 of the active layer 14 of the fourth transistor T4 through the via, the data signal line 61 is connected to the first electrode of the fourth transistor T4, and the data signal is written into the fourth transistor T4.

[0287] In the exemplary embodiment, the first power line 62 is in the shape of a zigzag line, with its main portion extending along the second direction Y. The first power line 62 is connected to the fourth connection electrode 54 or the first power adapter electrode 512 through a twenty-first via hole V21. Because the fourth connection electrode 54 and the first power adapter electrode 512 are connected to the second electrode plate 33 through the via hole, the first power line 62 is connected to the second electrode plate 33, allowing the power signal to be written to the second electrode plate 33. Because the fourth connection electrode 54 is connected to the first region 15-1 of the active layer 15 of the fifth transistor T5 through the via hole, the first power line 62 is connected to the first electrode of the fifth transistor T5, allowing the power signal to be written to the fifth transistor T5. In an exemplary embodiment, the first power line 62 may bend around adjacent anode connection electrodes 63 along the first direction X. For example, in a sub-pixel row, a pixel unit may include three sub-pixels arranged sequentially along the first direction X. In the same pixel unit, the first power line 62 in the first and second sub-pixels may bend around the anode connection electrode 63 on one side along the first direction X, and the first power line 62 in the third sub-pixel may bend around the anode connection electrode 63 on the opposite side of the first direction X. In an exemplary embodiment, in a sub-pixel, in the second direction Y, the dimension of the first power line 62 along the first direction X on the side of the anode connection electrode 63 closer to the storage capacitor (i.e., on the opposite side of the anode connection electrode 63 along the second direction Y) is greater than the dimension along the first direction X on the side of the anode connection electrode 63 farther from the storage capacitor (i.e., on the side of the anode connection electrode 63 along the second direction Y). For example, the first power line 62 may be provided with a plurality of bumps 621 , and the size of the bumps 621 on the first power line 62 along the first direction X is larger than the size of the bumps 621 on both sides of the bumps 621 along the first direction X in the second direction Y.

[0288] In an exemplary embodiment, multiple columns of first power lines 62 are electrically connected to multiple rows of sub-pixels' second plates 33 (multiple second plates 33 in the same row of sub-pixels are interconnected) to form a grid, which can enable the multiple first power lines 62 in the display substrate to have basically the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0289] In the exemplary embodiment, the anode connection electrode 63 is connected to the sixth connection electrode 56 through the twentieth via hole V20. Since the sixth connection electrode 56 is connected to the second region 16-2 of the active layer 16 of the sixth transistor T6 (also the second region 17-2 of the active layer 17 of the seventh transistor T7) through the via hole, the anode connection electrode 63 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0290] In an exemplary embodiment, the second power line 64 can be a bar with a main portion extending along the second direction Y. The second power line 64 can be provided with a connection structure 641. The connection structure 641 on the second power line 64 can be connected to the second power conversion electrode 511 through the twenty-second via V22. Since the second power conversion electrode 511 is connected to the second power connection line 32 through the via, the connection between the second power line 64 and the second power connection line 32 is realized. Multiple columns of second power lines 64 are electrically connected to multiple rows of second power connection lines 32 to form a grid shape, which can make the second power lines 64 in the display substrate have basically the same potential, which is beneficial to improving the uniformity of the panel and ensuring the display effect of the display substrate.

[0291] (111) Second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the second planar layer, as shown in FIG19 , which is a planar structural diagram of twelve sub-pixels corresponding to FIG18 a.

[0292] In an exemplary embodiment, the plurality of via holes may include at least a twenty-fourth via hole V24 .

[0293] In an exemplary embodiment, the via holes of each subpixel include at least a twenty-fourth via hole V24. The orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the orthographic projection of the anode connection electrode 63 on the substrate. The second planar layer within the twenty-fourth via hole V24 is removed, exposing the surface of the anode connection electrode 63. The twenty-fourth via hole V24 is configured to electrically connect a subsequently formed anode to the anode connection electrode 63 through the via hole. In an exemplary embodiment, the twenty-fourth via hole V24 can serve as an anode via hole.

[0294] At this point, the driving circuit layer is completed on the substrate. In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate.

[0295] In an exemplary embodiment, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, a first flat layer, and a second flat layer, the first insulating layer being arranged between the substrate and the first semiconductor layer, the second insulating layer being arranged between the first semiconductor layer and the first conductive layer, the third insulating layer being arranged between the first conductive layer and the second conductive layer, the fourth insulating layer being arranged between the second conductive layer and the second semiconductor layer, the fifth insulating layer being arranged between the second semiconductor layer and the third conductive layer, the sixth insulating layer being arranged between the third conductive layer and the fourth conductive layer, the seventh insulating layer and the first flat layer being arranged between the fourth conductive layer and the fifth conductive layer, and the second flat layer being arranged on the fifth conductive layer.

[0296] In an exemplary embodiment, after the driving circuit layer is prepared, a light-emitting structure layer is prepared on the driving circuit layer. The preparation process of the light-emitting structure layer may include the following operations: forming an anode pattern (i.e., an anode conductive layer), the anode is connected to the anode connection electrode through an anode via (i.e., the twenty-fourth via V24); forming a pixel definition layer, the pixel definition layer is provided with a pixel opening, and the pixel opening exposes the anode; forming an organic light-emitting layer by evaporation or inkjet printing, the organic light-emitting layer is connected to the anode through the pixel opening, and a cathode is formed on the organic light-emitting layer; forming an encapsulation layer, the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is provided between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer. The steps for forming the anode conductive layer and the pixel definition layer are as follows:

[0297] (112) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on the flat layer, as shown in FIG. 20 a and FIG. 20 b , where FIG. 20 a is a schematic plan view of a structure of twelve sub-pixels, and FIG. 20 b is a schematic plan view of the anode conductive layer in FIG. 20 a .

[0298] In an exemplary embodiment, the anode conductive layer pattern may include at least a plurality of anodes 70, and the plurality of anodes 70 may include: a first anode 71 of a red light-emitting unit, a second anode 72 of a blue light-emitting unit, and a third anode 73 of a green light-emitting unit. The area where the first anode 71 is located can form a red light-emitting unit that emits red light, the area where the second anode 72 is located can form a blue light-emitting unit that emits blue light, and the area where the third anode 73 is located can form a green light-emitting unit that emits green light.

[0299] In an exemplary embodiment, the first anode 71, the second anode 72, and the third anode 73 can be connected to the anode connection electrode 63 in the corresponding sub-pixel through the twenty-fourth via hole V24. Since the anode connection electrode 63 in the sub-pixel is electrically connected to the second electrode of the sixth transistor T6 (which is also the second electrode of the seventh transistor T7) through the via hole, the first anode 71, the second anode 72, and the third anode 73 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the anode connection electrode 63, respectively, thereby enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0300] In an exemplary embodiment, the anode 70 may include an anode main portion 701 and an anode connecting portion 702. The anode main portion 701 may have a rectangular structure. One end of the anode connecting portion 702 is connected to the anode main portion 701, and the other end is electrically connected to the anode connecting electrode 63 through the twenty-fourth via hole V24. The anode connecting portion 702 may have a strip-shaped structure and may be configured to compensate for differences in parasitic capacitance generated by signal routing between multiple sub-pixels. By providing the anode connecting portion 702, the parasitic capacitance of the multiple sub-pixels can be kept consistent, thereby improving the display uniformity of the display substrate.

[0301] (113) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: depositing a pixel definition layer thin film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition layer using a patterning process, and forming a pixel definition layer pattern disposed on the anode conductive layer, as shown in FIG. 21a and FIG. 21b , where FIG. 21a is a schematic diagram of a planar structure of twelve sub-pixels, and FIG. 21b is a schematic diagram of a planar structure of the pixel definition layer in FIG. 21a .

[0302] In an exemplary embodiment, the pixel definition layer pattern may include a plurality of pixel openings 80, wherein the pixel openings expose the anode 70. In an exemplary embodiment, the orthographic projections of the pixel openings 80 on the substrate are within the range of the orthographic projections of the anode 70 on the substrate. In an exemplary embodiment, the pixel openings 80 may include a pixel opening 801 for a first sub-pixel, a pixel opening 802 for a second sub-pixel, and a pixel opening 803 for a third sub-pixel. The orthographic projection of the pixel opening 801 for the first sub-pixel on the substrate overlaps with the orthographic projection of the first anode 71 on the substrate; the orthographic projection of the pixel opening 802 for the second sub-pixel on the substrate overlaps with the orthographic projection of the second anode 72 on the substrate; and the orthographic projection of the pixel opening 803 for the third sub-pixel on the substrate overlaps with the orthographic projection of the third anode 73 on the substrate.

[0303] In an exemplary embodiment, the pixel opening 802 and the second anode 72 of the second sub-pixel overlap with at least two portions of the signal line pattern in at least one conductive layer in the driving circuit layer, and at least two portions of the signal line pattern are distributed on both sides of the center of the pixel opening 802 of the second sub-pixel. This can make the anode flatness of each area in a second sub-pixel as consistent as possible, and can make the anode flatness of multiple second sub-pixels as consistent as possible, thereby improving the display uniformity of the display substrate.

[0304] In an exemplary embodiment, the main portions of the signal lines in the at least two portions of the signal line pattern extend along the column direction Y. As shown in FIG18b , the at least two portions of the signal line pattern of at least one conductive layer in the driving circuit layer may include a main screen data signal line 61. The main portion of the main screen data signal line 61 may extend along the column direction Y. In the column direction Y, the main screen data signal line 611 may be distributed on both sides of the center of the pixel opening 802 of the second sub-pixel (i.e., in the column direction Y, the area where the main screen data signal line 61 overlaps with the pixel opening 802 of the second sub-pixel may be symmetrical with respect to the midline of the pixel opening 802 of the second sub-pixel extending along the row direction X). In the row direction X, the main screen data signal line 61 may be distributed on both sides of the center of the pixel opening 802 of the second sub-pixel (i.e., in the row direction X, the area where the same main screen data signal line 61 overlaps with the pixel opening 802 of the second sub-pixel may be symmetrical with respect to the midline of the pixel opening 802 of the second sub-pixel extending along the column direction Y).

[0305] In an exemplary embodiment, as shown in FIG18b , at least two portions of the signal line pattern may further include a first power line 62. In the column direction Y, the two first power lines 62 may be distributed on both sides of the center of the pixel opening 802 of the second sub-pixel (i.e., in the column direction Y, the regions where the two first power lines 72 overlap with the pixel opening 802 of the second sub-pixel may be located on both sides of a center line of the pixel opening 802 of the second sub-pixel extending along the row direction X). In the row direction X, the first power line 72 may be distributed on both sides of the center of the pixel opening 802 of the second sub-pixel (i.e., in the row direction X, the regions where the same first power line 72 overlaps with the pixel opening 802 of the second sub-pixel may be located on both sides of a center line of the pixel opening 802 of the second sub-pixel extending along the column direction Y, and the regions where the first power line 62 overlaps with the pixel opening 802 of the second sub-pixel may be located on both sides of the main screen data signal line 61).

[0306] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as a buffer layer, which is used to improve the water and oxygen resistance of the substrate. The second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be referred to as a gate insulating (GI) layer. The sixth insulating layer may be referred to as an interlayer insulating (ILD) layer. The seventh insulating layer may be referred to as a passivation (PVX) layer.

[0307] The structure and preparation process shown above in the embodiment of the present disclosure are merely exemplary descriptions. In exemplary implementations, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The display substrate of the embodiment of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc., and the present disclosure does not limit this.

[0308] The present disclosure also provides a display device comprising the display substrate of any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a wearable device (e.g., a watch), a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0309] An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate including the first opening. The display device may further include a photosensitive element, and the orthographic projection of the photosensitive element on the base of the display substrate may be within the range of the orthographic projection of the first opening of the display substrate on the base.

[0310] In a display substrate provided by an embodiment of the present disclosure, there is an overlapping area between the pixel opening of at least one sub-pixel in the display substrate and the orthographic projection of at least part of the signal line in at least one conductive layer on the substrate. In the at least one sub-pixel, the overlapping area corresponding to one of the sub-pixels is symmetrical with respect to the orthographic projection of at least one center line of the pixel opening of the sub-pixel on the substrate, which can solve the technical problem of large viewing angle color deviation of the display substrate.

[0311] In the absence of conflict, the embodiments of the present disclosure, i.e., features in the embodiments, can be combined with each other to form new embodiments.

[0312] Although the embodiments disclosed in the present disclosure are as described above, the contents are only embodiments adopted to facilitate understanding of the embodiments of the present disclosure and are not intended to limit the embodiments of the present disclosure. Any person skilled in the art in the field to which the embodiments of the present disclosure belong may make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the embodiments of the present disclosure, but the scope of patent protection of the embodiments of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate includes a substrate, and a plurality of sub-pixels, a driving circuit layer, and a pixel defining layer disposed on the substrate. In a direction perpendicular to the plane of the display substrate, the driving circuit layer is located between the substrate and the pixel defining layer. A plurality of pixel openings are formed in the pixel defining layer, and each sub-pixel includes at least one pixel opening. The driving circuit layer includes a plurality of conductive layers; At least a part of the signal lines in at least one conductive layer overlaps with the pixel opening of at least one sub-pixel in the positive projection on the substrate; in the at least one sub-pixel, the overlapping region corresponding to one of the sub-pixels is symmetric with respect to at least one median line of the pixel opening of the sub-pixel in the positive projection on the substrate.

2. The display substrate according to claim 1, wherein, in a direction perpendicular to the plane of the display substrate, at least a part of the conductive layers includes the conductive layer closest to the pixel defining layer in the driving circuit layer.

3. The display substrate according to claim 2, wherein, the conductive layer closest to the pixel defining layer in the driving circuit layer includes a first power line. The plurality of sub-pixels includes multiple types of sub-pixels, and the multiple types of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel; The areas of the overlapping regions between the pixel openings of the first sub-pixel and the second sub-pixel and the first power line in the positive projection on the substrate are both larger than the area of the overlapping region between the pixel opening of the third sub-pixel and the first power line in the positive projection on the substrate.

4. The display substrate according to claim 3, wherein, the conductive layer closest to the pixel defining layer in the driving circuit layer further includes a data signal line. The pixel opening of the second sub-pixel has an overlapping region with two adjacent first power lines and a data signal line in the positive projection on the substrate. In a direction parallel to the plane of the display substrate, the first power line and the data signal line extend along a second direction. In a first direction, the two first power lines are respectively located on both sides of the data signal line, where the first direction intersects with the second direction.

5. The display substrate according to claim 4, wherein, the two adjacent first power lines and the pixel opening of the corresponding second sub-pixel have two first overlapping regions in the positive projection on the substrate, and the data signal line and the pixel opening of the corresponding second sub-pixel have a second overlapping region in the positive projection on the substrate. In the first direction, the two first overlapping regions are located on both sides of the second overlapping region, and the two first overlapping regions are symmetric with respect to the second overlapping region.

6. The display substrate according to claim 4, wherein, The conductive layer closest to the pixel definition layer in the driving circuit layer is the second source-drain metal layer. The positive projection of the pixel opening of the first sub-pixel on the substrate and the positive projection of at least part of the signal lines in the second source-drain metal layer on the substrate have a first overlapping area. The positive projection of the pixel opening of the second sub-pixel on the substrate and the positive projection of at least part of the signal lines in the second source-drain metal layer on the substrate have a second overlapping area. The positive projection of the pixel opening of the third sub-pixel on the substrate and the positive projection of at least part of the signal lines in the second source-drain metal layer on the substrate have a third overlapping area. The areas of the first overlapping area and the second overlapping area are both larger than the area of the third overlapping area.

7. The display substrate according to claim 6, wherein, the first overlapping area is symmetric with respect to the positive projection on the substrate of the midline extending in at least one of the first direction and the second direction of the pixel opening of the first sub-pixel; the second overlapping area is symmetric with respect to the positive projection on the substrate of the midline extending in at least one of the first direction and the second direction of the pixel opening of the second sub-pixel; the third overlapping area is symmetric with respect to the positive projection on the substrate of the midline extending in at least one of the first direction and the second direction of the pixel opening of the third sub-pixel.

8. The display substrate according to claim 3, wherein, the positive projection of the pixel opening of the first sub-pixel on the substrate is within the range of the positive projection of the first power supply line on the substrate.

9. The display substrate according to any one of claims 1 to 8 further includes an anode conductive layer. In the direction perpendicular to the plane where the display substrate is located, the anode conductive layer is located between the driving circuit layer and the pixel definition layer. The anode conductive layer includes a plurality of anodes. Each anode includes an anode main body. Each sub-pixel includes at least one anode; the positive projections of the pixel openings of the plurality of sub-pixels on the substrate are respectively within the ranges of the positive projections of the plurality of anodes on the substrate. The positive projection of the anode main body of at least one sub-pixel and the positive projection of at least part of the signal lines in at least one conductive layer on the substrate have an overlapping area; in the at least one sub-pixel, the overlapping area corresponding to one of the sub-pixels is symmetric with respect to the positive projection on the substrate of at least one midline of the anode main body of the sub-pixel.

10. The display substrate according to claim 1, wherein, the driving circuit layer includes a plurality of pixel driving circuits. At least part of the sub-pixels include the pixel driving circuits. At least part of the pixel circuits include: at least one transistor of the first type, at least one transistor of the second type; the driving circuit layer at least includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer sequentially disposed on the substrate, wherein: The first semiconductor layer at least includes: the active layer of the first type of transistor in the pixel driving circuit; the first conductive layer at least includes: the gate of the first type of transistor; the second conductive layer at least includes: the bottom gate of the second type of transistor; the second semiconductor layer at least includes: the active layer of the second type of transistor; the third conductive layer at least includes: the top gate of the second type of transistor.

11. The display substrate according to claim 10, wherein, the driving circuit layer further includes a fourth conductive layer. In a direction perpendicular to the plane of the display substrate, the fourth conductive layer is located on a side of the third conductive layer away from the substrate. The fourth conductive layer includes a plurality of second initial signal lines and a plurality of rows of second initial signal connection lines; The pixel driving circuits of the plurality of sub-pixels form a plurality of rows. The plurality of second initial signal lines are respectively electrically connected to the plurality of rows of pixel driving circuits. In a direction parallel to the plane of the display substrate, the plurality of second initial signal lines extend along a first direction and are arranged at intervals along a second direction, and the first direction intersects the second direction; Each row of second initial signal connection lines includes a plurality of second initial signal connection lines that extend along the second direction and are arranged at intervals along the first direction. In the second direction, each row of second initial signal connection lines is located between two adjacent second initial signal lines, and both ends of the plurality of second initial signal connection lines in each row of second initial signal connection lines are respectively connected to the two adjacent second initial signal lines.

12. The display substrate according to claim 11, wherein, the driving circuit layer further includes a fifth conductive layer. In a direction perpendicular to the plane of the display substrate, the fifth conductive layer is located on a side of the fourth conductive layer away from the substrate. The fifth conductive layer includes a plurality of second power supply lines, and the second conductive layer further includes a plurality of second power supply connection lines; In a direction parallel to the plane of the display substrate, the plurality of second power supply lines extend along the second direction and are arranged at intervals along the first direction, the plurality of second power supply connection lines extend along the first direction and are arranged at intervals along the second direction, and the plurality of second power supply lines and the plurality of second power supply connection lines are electrically connected through vias to form a grid-like structure.

13. The display substrate according to claim 12, wherein, In a direction parallel to the plane of the display substrate, the display substrate includes a first display area, a second display area, and a connection area. The first display area and the second display area are connected through the connection area. The second display area at least partially surrounds the first display area. The pixel driving circuits of the plurality of sub-pixels are located in the first display area and the second display area and form a plurality of columns; The third conductive layer further includes a plurality of second data signal connection lines, and the fifth conductive layer further includes a plurality of first data signal lines and a plurality of second data signal lines; the plurality of first data signal lines are respectively electrically connected to a plurality of columns of pixel driving circuits located in the first display area, and the plurality of second data signal lines are electrically connected to a plurality of columns of pixel driving circuits located in the second display area; the plurality of second data signal connection lines are located in the second display area and are respectively electrically connected to a plurality of columns of pixel driving circuits located in the second display area.

14. The display substrate according to claim 13, wherein, The plurality of sub-pixels form a plurality of pixel units, and the plurality of pixel units are arranged in an array. Each pixel unit includes at least three adjacent sub-pixels. The second power supply line and the second initial signal connection line are disposed between two adjacent columns of pixel units, and the second power supply connection line and the second data signal connection line are located between two adjacent rows of pixel units.

15. A display substrate, comprising a first display area, a second display area, a bonding area, and a connection area. The first display area is connected to the second display area through the connection area. The second display area at least partially surrounds the first display area. In a direction parallel to the plane of the display substrate, the bonding area is located on one side of the first display area; The second display area is provided with a plurality of second data signal lines and a plurality of second data signal connection lines; one ends of the plurality of second data signal connection lines are respectively electrically connected to the plurality of second data signal lines, and the other ends are electrically connected to components provided in the bonding area.

16. The display substrate according to claim 15, wherein, The second display area is provided with a plurality of pixel units. The plurality of pixel units form a plurality of second pixel unit rows and a plurality of second pixel unit columns. In a direction from the first display area to the second display area, the plurality of second pixel unit columns are arranged in sequence, and the distance between two adjacent second pixel unit rows increases sequentially from the first second pixel unit column to the last second pixel unit column.

17. The display substrate according to claim 16, wherein, The shape of the first display area is circular, and the shape of the second display area is a strip at least partially surrounding the first display area.

18. The display substrate according to claim 16, wherein, In a direction parallel to the plane of the display substrate, the bonding area and the connection area are located on opposite sides of the first display area. The components provided in the bonding area include a driving chip, and one end of the plurality of second data signal connection lines is electrically connected to the driving chip.

19. The display substrate according to claim 18 further includes a first outer frame. The first outer frame is disposed around the first display area. The first outer frame includes the connection area and the bonding area. The first outer frame is provided with a plurality of second data signal transfer lines, and the second data signal transfer lines and the second data signal connection lines are located in different conductive layers; The second data signal connection line extends from the second display area to the connection area, and the multiple second data signal transfer lines extend from the connection area along the first outer border to the bonding area, with one end electrically connected to the multiple second data signal connection lines located in the connection area and the other end electrically connected to the driving chip.

20. The display substrate according to claim 19, further comprising a second outer border area and a second inner border area. Along the direction from the first display area to the second display area, the second inner border area and the second outer border area are located on both sides of the second display area.

21. The display substrate according to claim 20, wherein, the second inner border area is connected to the first outer border area through the connection area, and second power signal supply lines are provided in the first outer border area and the second inner border area. The second power signal supply lines are electrically connected to the driving chip and extend to the second inner border area via the first outer border area.

22. The display substrate according to claim 21, further comprising a cathode layer. The second display area includes a second power connection line electrically connected to the second power signal supply line in the second inner border area. The second outer border area includes a second power connection line overlapping with the cathode layer and the second power connection line. The second power connection line is electrically connected to the second power connection line and the cathode layer through vias.

23. The display substrate according to claim 22, wherein, the second power signal supply line located in the first outer border area overlaps with the cathode layer and is electrically connected to the cathode layer through a via.

24. The display substrate according to claim 20, wherein, along the direction from the second display area to the second inner border area, the second inner border area sequentially includes: a first type of gate driving circuit and a first type of driving signal line, an initial signal line, a first power signal supply line, and a second power signal supply line electrically connected thereto; along the direction from the second display area to the second outer border area, the second outer border area sequentially includes: a second type of gate driving circuit and a second type of driving signal line, a second power connection line electrically connected thereto, wherein the second type of driving signal line is electrically connected to the driving chip via the second outer border area, the second inner border area, and the first outer border area.

25. The display substrate according to claim 24, wherein, the connection area is provided with an initial signal transfer electrode arranged in a different layer from the initial signal line, a first power transfer electrode arranged in a different layer from the first power signal supply line, a second power transfer electrode arranged in a different layer or the same layer as the second power signal supply line, and a driving signal transfer electrode arranged in a different layer from the first type of driving signal line; along the direction from the first display area to the first outer border area, the first outer border area sequentially includes: a first power signal supply line, an initial signal line, a first type of driving signal line, and a second power signal supply line. The first power signal supply line located in the first outer border area is electrically connected to the first power signal supply line located in the second inner border area through the first power transfer electrode; the initial signal line located in the first outer border area is electrically connected to the initial signal line located in the second inner border area through the initial signal transfer electrode; the first type of driving signal line located in the first outer border area is electrically connected to the first type of driving signal line through the driving signal transfer electrode, and the second power signal supply line located in the first outer border area is electrically connected to the second power signal supply line located in the second inner border area through the second power transfer electrode.

26. The display substrate according to claim 24, wherein, The second display area further includes a plurality of scan signal lines of a second type, the output end of each gate driving circuit of the second type is electrically connected to two corresponding scan signal lines of the second type, and each scan signal line of the second type is electrically connected to a plurality of sub-pixels in one row of the second pixel units.

27. The display substrate according to claim 26, wherein, The size of each gate driving circuit of the second type in the extending direction of the second outer border is the same as that of two adjacent rows of the second pixel units; or, each gate driving circuit of the second type is divided into two connected parts of circuits, and the sizes of the two parts of circuits in the extending direction of the second outer border area are respectively the same as those of two adjacent rows of the second pixel units; or, two adjacent rows of the second pixel units are used as a unit module, and in the extending direction of the second outer border area, the distance between two adjacent unit modules is greater than the distance between two second pixel units in the same unit module, and the size of each gate driving circuit of the second type in the extending direction of the second outer border area is the same as that of an adjacent unit module.

28. A display device, comprising the display substrate according to any one of claims 1 to 14, or comprising the display substrate according to any one of claims 15 to 27.

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