Chip packaging structure, manufacturing method therefor, and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors. Disclosed are a chip packaging structure, a manufacturing method therefor, and an electronic device. The main object is to solve the problem of chip packaging structure glass cores being prone to fracturing. In the present chip packaging structure, a glass core is provided with metallized vias. A first wiring layer is arranged on a first side of the glass core and is electrically connected to the metallized vias. A first chip is arranged on the side of the first wiring layer away from the glass core and is electrically connected to the first wiring layer. A first coating layer is arranged on a second side of the glass core and is provided with first conductive columns passing through said layer, and the first conductive columns are electrically connected to the first wiring layer by means of the metallized vias. A second chip is wrapped in the first coating layer and is electrically connected to the first wiring layer by means of the metallized vias. The first coating layer can increase the overall structural flexibility of the chip packaging structure, improve the mechanical strength of the chip packaging structure, relieve stress on the glass core, and reduce the risk of glass core fracturing.

Description

Chip packaging structure and manufacturing method thereof and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 26, 2023, with application number 202311257884.4 and application name “Chip packaging structure, manufacturing method thereof and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure, a manufacturing method thereof, and an electronic device. Background Art

[0003] Glass core board-based chip packaging technology uses a glass substrate as a core board, encapsulating the chip on or inside the glass core board to form a chip packaging structure. This chip packaging structure has the advantages of good electrical performance and low manufacturing cost. This is because the size of the metallized through-glass via (TGV) made on the glass core board and the size of the metal lines in the wiring layer made on both sides of the glass core board can be well adapted to the size of the metal lines on the PCB board, thus eliminating the need for an additional interconnect substrate between the chip packaging structure and the PCB.

[0004] However, glass core boards are prone to breakage, which limits the widespread application of chip packaging technology based on glass core boards.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a chip packaging structure, a method for manufacturing the chip packaging structure, and an electronic device including the chip packaging structure. The main purpose is to solve the problem that the glass core board is prone to breakage in the chip packaging structure based on the glass core board.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a chip packaging structure is provided, which includes: a glass core board, a first wiring layer, a first chip, a first cladding layer, and a second chip. The glass core board has a metallized via. The first wiring layer is arranged on the first side of the glass core board and is electrically connected to the metallized via. The first chip is arranged on the side of the first wiring layer away from the glass core board and is electrically connected to the first wiring layer. The first cladding layer is arranged on the second side of the glass core board and has a first conductive column arranged therethrough, and the first conductive column is electrically connected to the first wiring layer through the metallized via. The second chip is wrapped in the first cladding layer and is electrically connected to the first wiring layer through the metallized via.

[0009] As can be seen from the above, a first coating layer is provided on the back of the glass core board. On the one hand, since the first coating layer is composed of an organic material, it itself has good structural flexibility, thereby increasing the structural flexibility of the chip packaging structure as a whole, improving the mechanical strength of the chip packaging structure, and avoiding the problem of fracture caused by the small thickness of the glass core board. Moreover, when the chip packaging structure is installed on the PCB, the first coating layer can effectively relieve the stress on the glass core board, thereby avoiding the fracture of the glass core board due to excessive stress. On the other hand, by burying the second chip (or other components) and the first conductive column for electrical connection inside the first coating layer, the integration of the chip packaging structure is improved while avoiding the opening of a deep cavity on the glass core board, thereby avoiding damage to the overall structure of the glass core board and circumventing the process difficulty faced by opening a deep cavity on the glass core board.

[0010] In conjunction with the first aspect, in one possible implementation of the first aspect, the chip package structure further includes a second wiring layer, disposed on a side of the first cladding layer away from the glass core substrate and electrically connected to the first conductive pillars. In these embodiments, the second wiring layer may include one or more layers of metal wiring, with the metal wiring between different layers electrically interconnected. Optionally, the size of the metal wiring in the second wiring layer is larger than the size of the metal wiring in the first wiring layer; and the wiring density of the metal wiring in the second wiring layer is lower than the wiring density of the metal wiring in the first wiring layer. In this implementation, the second wiring layer is disposed on a side of the first cladding layer away from the glass core substrate. On the one hand, the presence of the second wiring layer can increase the metal wiring density and device integration of the chip package structure. On the other hand, in applications such as directly mounting the chip package structure on a PCB, since the size of the metal wiring in the second wiring layer is larger than the size of the metal wiring in the first wiring layer, the second wiring layer can serve as a transition between other wiring in the chip package structure and wiring on the PCB, improving the feasibility of direct mounting the chip package structure on a PCB and enabling the chip package structure to be compatible with a wider range of PCB specifications.

[0011] In combination with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes a packaging substrate, which is arranged on a side of the second wiring layer away from the first cladding layer; the first conductive column is electrically connected to the metal circuit in the packaging substrate through the second wiring layer. Optionally, the size of the metal circuit in the packaging substrate is larger than the size of the metal circuit in the second wiring layer, and the wiring density of the metal circuit in the packaging substrate is smaller than the wiring density of the metal circuit in the second wiring layer. In this implementation, a packaging substrate is further provided on the side of the second wiring layer away from the first cladding layer. Since the size of the metal circuit in the packaging substrate is larger than the size of the metal circuit in the second wiring layer, and the wiring density of the metal circuit in the packaging substrate is smaller than the wiring density of the metal circuit in the second wiring layer, it can serve as a transition between the chip packaging structure and the circuit on the PCB, thereby improving the feasibility of directly mounting the chip packaging structure on the PCB.

[0012] In conjunction with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes a packaging substrate, and the second wiring layer includes a layer of metal wiring. The presence of the packaging substrate can reduce the number of metal wiring layers in the second wiring layer.

[0013] In conjunction with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes, for example, a solder ball array or a copper pillar bump array, which may be disposed on a side of the second wiring layer away from the first cladding layer and electrically connected to the first conductive pillars via the second wiring layer. Where the aforementioned packaging substrate is not present in the chip packaging structure, the chip packaging structure may be electrically connected to a circuit external to the chip packaging structure via the solder ball array or the copper pillar bump array. Where the aforementioned packaging substrate is present in the chip packaging structure, the electrical connection between the second wiring layer and the packaging substrate may be achieved via the solder ball array or the copper pillar bump array.

[0014] In combination with the first aspect, in a possible implementation of the first aspect, when the above-mentioned packaging substrate exists in the chip packaging structure, a solder ball array and a copper pillar bump array are provided on the side of the packaging substrate away from the second wiring layer, which are used to realize the electrical connection between the chip packaging structure and the external circuit, for example, to realize the electrical connection between the chip packaging structure and the PCB board.

[0015] In conjunction with the first aspect, in one possible implementation of the first aspect, the chip packaging structure further includes a third wiring layer disposed between the first cladding layer and the glass core substrate; the third wiring layer is electrically connected to the first wiring layer via metallized vias, and the first conductive pillars are electrically connected to the metallized vias via the third wiring layer. The third wiring layer has solder balls on a surface adjacent to the first cladding layer, and the second chip is electrically connected to the solder balls.

[0016] In combination with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes an encapsulation layer composed of a plastic encapsulation material, which is arranged on the side of the first wiring layer away from the glass core board; the first chip can be completely or partially wrapped in the encapsulation layer. The situation where the first chip is partially wrapped in the encapsulation layer is, for example, that the front side (active side) of the chip is exposed outside the encapsulation layer, so as to facilitate the heat dissipation of the chip. In this implementation, on the one hand, the plastic encapsulation material wraps the first chip to protect the first chip from damage. On the other hand, the presence of the encapsulation layer can further improve the mechanical strength and fracture toughness of the chip packaging structure, further reduce the risk of fracture of the glass core board, and further reduce the thickness of the glass core board and the size of the TGV.

[0017] In conjunction with the first aspect, in one possible implementation of the first aspect, the chip packaging structure further includes a second cladding layer composed of an organic material, disposed between the glass core substrate and the first wiring layer, and having second conductive pillars extending therethrough; the metallized vias are electrically connected to the first wiring layer via the second conductive pillars. In this implementation, by disposing the second cladding layer between the glass core substrate and the first wiring layer, the mechanical strength and fracture toughness of the chip packaging structure can be further improved, the risk of glass core substrate fracture can be further reduced, the thickness of the glass core substrate can be further reduced, and the size of the TGV can be further reduced.

[0018] In conjunction with the first aspect, in one possible implementation of the first aspect, the chip packaging structure further includes a third chip, the third chip being encapsulated in the second cladding layer and electrically connected to the first wiring layer. By embedding the third chip in the second cladding layer, the integration of the chip packaging structure is further improved.

[0019] In conjunction with the first aspect, in one possible implementation of the first aspect, the glass core board has a first groove on a surface on a side adjacent to the first wiring layer; the chip package structure further includes a third chip disposed in the first groove and electrically connected to the first wiring layer. In this implementation, by providing a groove on the first side surface of the glass core board and mounting a chip or other device thereon, the chip package structure further improves its integration.

[0020] In combination with the first aspect, in a possible implementation of the first aspect, the third chip is an electrical interconnection structure, which is wrapped in the second cladding layer or located in a groove on the first side surface of the glass core board. There are multiple first chips, and different first chips are electrically connected through the electrical interconnection structure. In the case where the density of interconnection lines between different first chips is high, by burying the electrical interconnection structure in the second cladding layer, or setting the electrical interconnection structure in the groove on the first side surface of the glass core board, the requirements for the density of interconnection lines between different first chips can be met, and the signal quality between different first chips can be guaranteed. At the same time, the volume of the chip packaging structure is reduced, which is conducive to the integration of more chips and components.

[0021] In conjunction with the first aspect, in one possible implementation of the first aspect, the depth of the first groove on the first side of the glass core board is less than 150 μm. This, on the one hand, can avoid the risk of the glass core board breaking due to an excessively deep groove, and on the other hand, can reduce the difficulty of the groove forming process.

[0022] In combination with the first aspect, in a possible implementation of the first aspect, the electrical interconnection structure includes: a substrate and a wiring layer arranged on one side of the substrate. For example, the line width of the metal line in the wiring layer is usually less than or equal to 2μm, and the line spacing is usually less than or equal to 2μm. The line width and line spacing of the metal lines in a typical wiring layer are generally greater than 2um. In other words, the density of the metal lines in the electrical interconnection structure is much greater than the density of the metal lines in the wiring layer. Furthermore, the electrical interconnection structure can support the requirements for interconnection line density between different first chips, which is conducive to the miniaturization and high integration of the chip packaging structure.

[0023] In conjunction with the first aspect, in one possible implementation of the first aspect, the electrical interconnect structure further includes a through-silicon via (TSV) penetrating the substrate; the metallized via is electrically connected to the first wiring layer via the TSV. This shortens the length of the line between the metallized via and the first wiring layer, reducing signal loss. For example, this reduces current signal loss.

[0024] In combination with the first aspect, in a possible implementation of the first aspect, the thickness of the glass core board in the direction from the first wiring layer to the first cladding layer is 50um-2000um. For example, when the chip packaging structure includes a packaging substrate, the thickness of the glass core board can be 50um-200um. When the chip packaging structure does not include a packaging substrate and is used to be directly installed on a PCB board, the thickness of the glass core board can be 200um-2000um. This is because, when the chip packaging structure is installed on a PCB board, if the chip packaging structure includes a packaging substrate, then the packaging substrate can alleviate the stress on the glass core board, and then the thickness of the glass substrate can be further reduced to achieve a smaller TGV without increasing the risk of fracture of the glass core board. On the contrary, if the chip packaging structure does not include a packaging substrate, the thickness and fracture risk of the glass substrate need to be taken into account.

[0025] In the second aspect, an embodiment of the present application provides a method for manufacturing a chip packaging structure, the method comprising: preparing a metallized via on a glass core board; forming a first wiring layer on a first side of the glass core board, and installing a first chip on the first wiring layer; the first wiring layer is electrically connected to the metallized via; installing a second chip on a second side of the glass core board, and forming a first cladding layer; the first cladding layer wraps the second chip and has a first conductive column arranged therethrough, and the first conductive column is electrically connected to the first wiring layer through the metallized via.

[0026] In combination with the second aspect, in a possible implementation of the second aspect, the method further includes: forming a second wiring layer on a side of the first cladding layer away from the glass core board, the second wiring layer being electrically connected to the first conductive column.

[0027] In combination with the second aspect, in a possible implementation of the second aspect, before installing the second chip on the second side of the glass core board, it also includes: forming a third wiring layer on the second side of the glass core board, and forming a solder ball on the surface of the third wiring layer on one side close to the first cladding layer; the third wiring layer is electrically connected to the first wiring layer through the metallized via, and the first conductive column is electrically connected to the metallized via through the third wiring layer; installing the second chip on the second side of the glass core board specifically includes: soldering the second chip to the solder ball.

[0028] In combination with the second aspect, in a possible implementation of the second aspect, before forming the first wiring layer on the first side of the glass core board, it also includes: forming a second cladding layer on the first side of the glass core board, the second cladding layer having a second conductive column arranged therethrough; the metallized via is electrically connected to the first wiring layer through the second conductive column.

[0029] In combination with the second aspect, in a possible implementation of the second aspect, before forming the second cladding layer on the first side of the glass core board, it also includes: installing a third chip on the first side of the glass core board, and the second cladding layer wrapping the third chip; the third chip is electrically connected to the first wiring layer.

[0030] In combination with the second aspect, in a possible implementation of the second aspect, before forming the first wiring layer on the first side of the glass core board, the manufacturing method also includes: making a first groove on the first side surface of the glass core board; installing a third chip in the first groove; and electrically connecting the third chip to the first wiring layer.

[0031] In combination with the second aspect, in a possible implementation of the second aspect, there are multiple first chips; the third chip is an electrical interconnection structure, and different first chips are electrically connected through the electrical interconnection structure.

[0032] In a third aspect, an embodiment of the present application further provides an electronic device comprising: a mainboard and any one of the above-mentioned chip packaging structures, wherein the mainboard is arranged on a side of the glass core board in the chip packaging structure where the first coating layer is provided, and is electrically connected to the chip packaging structure.

[0033] Among them, the technical effects brought about by any design method in the second to third aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic structural diagram of a glass core board provided in an embodiment of the present application;

[0035] FIG2 is a perspective view of an electronic device according to an embodiment of the present application;

[0036] FIG3 is an exploded view of an electronic device according to an embodiment of the present application;

[0037] FIG4 is a schematic diagram of the structure of a chip packaging structure and a mainboard in an electronic device according to an embodiment of the present application;

[0038] FIG5 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0039] FIG6 is a schematic diagram of an interconnection bridge chip provided in an embodiment of the present application;

[0040] FIG7 is a schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0041] FIG8 is a schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0042] FIG9 is a schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0043] FIG10 is a schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0044] FIG11 is a schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0045] FIG12 is a partial exploded schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0046] FIG13 is a partially exploded schematic diagram of another chip packaging structure provided by an embodiment of the present application;

[0047] FIG14 is a schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0048] FIG15 is a flow chart of a method for manufacturing a chip packaging structure provided by an embodiment of the present application;

[0049] FIG16 is a schematic diagram of a manufacturing process of a chip packaging structure provided in an embodiment of the present application;

[0050] FIG17 is a schematic diagram of a manufacturing process of another chip packaging structure provided in an embodiment of the present application;

[0051] FIG18 is a schematic diagram of a manufacturing process of another chip packaging structure provided in an embodiment of the present application;

[0052] FIG19 is a schematic diagram of the manufacturing process of another chip packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0054] Hereinafter, the terms "first," "second," etc., are used solely for descriptive purposes to distinguish between identical or similar items with substantially the same function and effect, and are not to be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Therefore, a feature defined as "first," "second," etc., may explicitly or implicitly include one or more of such features.

[0055] Also, in the description of the present application, unless otherwise specified, “plurality” means two or more than two.

[0056] Furthermore, in this application, directional terms such as "upper," "lower," "left," "right," "horizontal," and "vertical" are defined relative to the orientation of components schematically shown in the accompanying drawings. It should be understood that these directional terms are relative concepts and are used for relative description and clarification, and may change accordingly based on changes in the orientation of components in the accompanying drawings. Unless otherwise expressly specified or limited, the term "connection" should be understood broadly. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium.

[0057] At the same time, in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0058] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0059] Glass core board-based chip packaging technology uses a glass substrate as a core board, encapsulating the chip on or inside the glass core board to form a chip packaging structure. This chip packaging structure has the advantages of good electrical performance and low manufacturing cost. This is because the size of the metallized through-glass via (TGV) made on the glass core board and the size of the metal lines in the wiring layer made on both sides of the glass core board can be well adapted to the size of the metal lines on the PCB board, thus eliminating the need for an additional interconnect substrate between the chip packaging structure and the PCB.

[0060] However, this glass core board-based chip packaging technology has obvious limitations.

[0061] First, to achieve a high electrical interconnect density, the TGVs within the glass core must be as small as possible. However, since thicker glass cores increase the difficulty of fabricating small TGVs, the thickness of the glass core must be reduced to achieve this. However, insufficient glass core thickness results in insufficient mechanical strength, making it prone to fracture under stress. This is particularly true when the glass core is large and directly assembled onto a PCB, where fracture presents a pressing technical challenge.

[0062] Secondly, as shown in Figure 1, due to the demand for integration and performance, it is also necessary to open a deep cavity on the back of the glass core board and bury chips or components. Among them, the back of the glass core board can be understood as the side of the glass core board where the chip is not installed, and the side where the chip is installed can be called the front. This process of burying chips or components inside the glass core board is very complicated, and the obtained cavity depth consistency is poor, which is not conducive to the subsequent installation of multiple chips or components of the same size. In addition, when multiple chips or components of different sizes need to be buried, it is difficult to make multiple cavities of different depths on the glass core board. At the same time, opening a deep cavity on the back of the glass core board destroys the structural integrity of the glass core board and further increases the risk of the glass core board breaking. The above two problems exist at the same time, which limits the widespread application of chip packaging technology based on glass core boards.

[0063] In view of this, embodiments of the present application provide a chip packaging structure and an electronic device including the chip packaging structure. In some application scenarios, the chip packaging structure can be a bare chip packaged into a chip, or a semiconductor structure obtained by packaging multiple chips, such as a multi-chip module (MCM) or SIP (System in a Package) package. This chip packaging structure has high mechanical strength while meeting the requirements of high electrical interconnection density and device integration, reducing the risk of glass core board fracture.

[0064] The above-mentioned electronic devices include, but are not limited to, electronic devices in the fields of information technology (IT) and communication technology (CT), such as supercomputing equipment, artificial intelligence equipment, servers, optical communication equipment, mobile phones, tablet personal computers, laptop computers, personal digital assistants (PDAs), cameras, personal computers, notebook computers, vehicle-mounted devices, wearable devices, augmented reality (AR) glasses, AR helmets, virtual reality (VR) glasses or VR helmets, etc., which require data processing / storage / transmission and reception. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic devices. For the sake of convenience of explanation, the following examples are all taken as examples of the electronic device being a mobile phone as shown in Figure 2.

[0065] Figure 2 is a perspective view of an electronic device provided in some embodiments of the present application, and Figure 3 is an exploded view of the electronic device shown in Figure 2 . Referring to Figures 2 and 3 , electronic device 1000 is a mobile phone. Electronic device 1000 may include a screen 100, a middle frame 200, a rear case 300, and a motherboard 400 secured to the middle frame 200, as shown in Figure 3 .

[0066] It should be understood that Figures 2 and 3 merely illustrate some components included in the electronic device 1000, and the actual shape, size, position, and configuration of these components are not limited by Figures 2 and 3. For example, in other examples, the electronic device 1000 may not include the screen 100. Alternatively, the electronic device 1000 may also include the camera 500 as shown in Figure 3.

[0067] In the embodiment of the present application, the electronic device 1000 further includes a chip packaging structure 600 as shown in FIG4 . The chip packaging structure mentioned in the embodiment of the present application may also be referred to as an integrated circuit. As shown in FIG4 , the chip packaging structure 600 is disposed on the mainboard 400 and is electrically connected to the mainboard 400. For example, the chip packaging structure 600 can be electrically connected to the mainboard 400 via a ball grid array (BGA) or a plurality of copper pillar bumps (CPB) arranged in an array, thereby enabling the chip packaging structure 600 to transmit signals to other devices or device stacking structures on the mainboard 400.

[0068] It should be noted that the mainboard 400 may be a printed circuit board (PCB). The number of chip packaging structures 600 on the mainboard 400 may be one, two, or more than two, which is not limited in this application.

[0069] To facilitate the following description, some of the figures illustrating the embodiments of this application illustrate a three-dimensional coordinate system, namely, an X, Y, and Z coordinate system. Referring to Figure 4 , the plane on which the motherboard 400 resides is the XY plane. Taking the rectangular motherboard 400 shown in Figure 4 as an example, the X-axis can be the length of the motherboard 400, the Y-axis can be the width of the motherboard 400, and the Z-axis can be perpendicular to, or approximately perpendicular to, the motherboard 400 within manufacturing tolerances. It is understood that the width of the motherboard 400 is smaller than its length.

[0070] It should be noted that Figures 2 to 4 are merely examples of application scenarios for the chip packaging structure provided in the embodiments of the present application, specifically illustrating the application of the chip packaging structure integrated into an electronic device. In fact, the chip packaging structure provided in the embodiments of the present application can also be used as an independent electronic device, and the specific implementation method will be described in detail below.

[0071] Please refer to Figure 5. The chip packaging structure 600 includes a glass core board 1, a first wiring layer 2, a first chip 3, a first cladding layer 4, a second chip 5, and a solder ball array 6 (or a copper column bump). The glass core board has a metallized via 101. The first wiring layer 2 is arranged on the first side of the glass core board 1 and is electrically connected to the metallized via 101. The first chip 3 is arranged on the side of the first wiring layer 2 away from the glass core board 1 and is electrically connected to the first wiring layer 2. The first cladding layer 4 is arranged on the second side of the glass core board 1 and has a first conductive column 401 arranged therethrough. The first conductive column 401 is electrically connected to the first wiring layer 2 through the metallized via 101. The second chip 5 is wrapped in the first cladding layer 4 and is electrically connected to the first wiring layer 2 through the metallized via 101. The solder ball array 6 is arranged on the side of the first cladding layer 4 away from the glass core board 1 and is electrically connected to the first conductive column 401.

[0072] In some embodiments, the chip package structure 600 may not include the solder ball array 6 .

[0073] In some embodiments, for ease of description, the first side of the glass core board 1 is also referred to as the front side of the glass core board 1 , and the second side of the glass core board 1 is also referred to as the back side of the glass core board 1 .

[0074] In the chip packaging structure 600 shown in FIG5 , a first cladding layer 4 is provided on the back of the glass core board 1. On the one hand, since the first cladding layer 4 is composed of an organic material, it has good structural flexibility, thereby increasing the overall structural flexibility of the chip packaging structure 600, improving the mechanical strength of the chip packaging structure 600, and avoiding the problem of fracture caused by the small thickness of the glass core board 1. Moreover, when the chip packaging structure 600 is installed on the PCB, the first cladding layer 4 can effectively relieve the stress on the glass core board 1, thereby avoiding the fracture of the glass core board 1 due to excessive stress. On the other hand, by burying the second chip 5 (or other components) and the first conductive column 401 for electrical connection inside the first cladding layer 4, the integration of the chip packaging structure 600 is improved while avoiding the opening of a deep cavity on the glass core board 1, thereby avoiding damage to the overall structure of the glass core board 1 and circumventing the process difficulty faced by opening a deep cavity on the glass core board 1.

[0075] In the embodiment of the present application, the above-mentioned chip (including the first chip 3 and the second chip 5) can be a processing chip with a data processing function, such as a central processing unit (CPU), a system on chip (SOC) or a graphics processing unit (GPU), etc., which can process data. The above-mentioned memory can be a random access memory (RAM) or a read-only memory (ROM). The chip can be a bare chip (i.e., a single die) or a chip stacking structure (i.e., multiple bare dies are stacked).

[0076] The present application does not limit the number of the first chip 3 and the second chip 5 in the chip packaging structure 600. The number of the first chip 3 and the second chip 5 in the chip packaging structure 600 can be one or more. However, for the MCM component, the number of chips is usually two or more. For example, a plurality of first chips 3 can be stacked in a direction perpendicular to the main board 400 / glass core board 1, or they can be arranged in parallel in a direction parallel to the main board 400 / glass core board 1, that is, they can be arranged on the first wiring layer 2 in the manner shown in Figure 5. At the same time, a plurality of second chips 5 can be stacked in a direction perpendicular to the main board 400 / glass core board 1, or they can be arranged in parallel in a direction parallel to the main board 400 / glass core board 1, that is, they can be arranged in the first cladding layer 4 in the manner shown in Figure 5.

[0077] In some embodiments, the glass core board 1 may be made of glass materials such as quartz glass or high-silica glass.

[0078] In some embodiments, the organic material may be an organic polymer material. The organic material encapsulates the second chip. The organic material may also be referred to as a molding compound, including but not limited to epoxy molding compound (EMC) and silicone resin. The epoxy molding compound (EMC), also known as epoxy resin molding compound or epoxy molding compound, is a powdered molding compound composed of an epoxy resin as a base resin, a high-performance phenolic resin as a curing agent, silica powder as a filler, and various additives.

[0079] In some embodiments, as shown in FIG5 , the second side surface of the glass core board 1 has at least one wiring layer. For ease of explanation and to distinguish it from the first wiring layer, the wiring layer is referred to as the second metal layer 7. In other embodiments, the wiring layer may also be referred to as the third wiring layer. The second metal layer 7 includes metal lines, BGA and / or CPB. The TGV in the glass core board 1 is electrically connected to the second metal layer 7 on the second side surface of the glass core board 1. Using chip packaging technology, the second chip 5 can be mechanically and electrically connected to the second metal layer 7 on the second side surface of the glass core board 1, and the first chip 3 can also be mechanically and electrically connected to the first wiring layer 2. Chip packaging technologies include wire bonding (WB), flip chip bonding (FC), etc.

[0080] In one possible implementation, the above-mentioned chip (including the first chip 3 and the second chip 5) can be the processing chip with data processing function mentioned above, or it can be a chip with electrical interconnection function (bridge die). In some examples of the present application, such a chip with electrical interconnection function can also be referred to as an electrical interconnection structure or an interconnection bridge chip. It should be understood that the interconnection bridge chip includes but is not limited to such a chip with electrical interconnection function.

[0081] FIG6 is an exemplary illustration of an interconnect bridge chip. As shown in A and B in FIG6 , the interconnect bridge chip generally includes a substrate (such as a wafer or silicon chip) and a circuit layer disposed on one side of the substrate. The circuit layer includes one or more layers of metal circuits, and the metal circuits between different layers achieve high-density interconnection. Through-silicon vias (TSVs) can be provided in the substrate and interconnected with the circuit layer, as shown in FIG6A . TSVs may also not be provided in the substrate, as shown in FIG6B . The line width of the metal circuits in the interconnect bridge chip is generally less than or equal to 2μm, and the line spacing is generally less than or equal to 2μm. The line width and line spacing of the metal circuits in a typical wiring layer are generally greater than 2μm. In other words, the density of the metal circuits in the electrical interconnect structure is much greater than the density of the metal circuits in the wiring layer. Since the interconnect bridge chip itself has a high wiring density, placing it in the chip packaging structure can meet the requirements for high interconnection density between different chips in the chip packaging structure, reduce the volume of the chip packaging structure, and facilitate the integration of more chips and components.

[0082] In some embodiments, as shown in FIG7 , the chip package structure 600 further includes a second wiring layer 8, which is disposed on a side of the first cladding layer 4 away from the glass core board 1. The second wiring layer 8 is electrically connected to the first conductive pillar 401. In these embodiments, the second wiring layer 8 can have one or more layers of metal wiring, with the metal wiring between different layers electrically interconnected. The solder ball array 6 is disposed on a side of the second wiring layer 8 away from the first cladding layer 4. The solder ball array 6 is electrically connected to the first conductive pillar 401 via the metal wiring in the second wiring layer 8.

[0083] In a possible implementation, the size of the metal lines in the second wiring layer 8 is larger than the size of the metal lines in the first wiring layer 2 and the second metal layer 7 .

[0084] In the chip package structure 600 shown in FIG7 , a second wiring layer 8 is provided on the side of the first cladding layer 4 away from the glass core board 1. On the one hand, the presence of the second wiring layer 8 can improve the metal circuit density and device integration of the chip package structure 600. On the other hand, in an application scenario where the chip package structure 600 is directly mounted on a PCB, because the size of the metal circuits in the second wiring layer 8 is larger than the size of the metal circuits in the first wiring layer 4 and the second metal layer 7, the second wiring layer 8 can serve as a transition between other circuits in the chip package structure 600 and the circuits on the PCB, improving the feasibility of directly mounting the chip package structure 600 on the PCB and making the chip package structure 600 adaptable to PCBs of a wider range of specifications. It should be noted that the phrase "directly mounting the chip package structure on the PCB" here means that no additional packaging substrate or wiring layer is provided between the chip package structure 600 and the PCB. The solder ball array 6 on the chip package structure 600 is directly soldered to the PCB, thereby electrically connecting it to the circuits on the PCB.

[0085] In some embodiments, as shown in FIG8 , the chip packaging structure 600 further includes an encapsulation layer 9 composed of a plastic encapsulation material, which is arranged on the side of the first wiring layer 2 away from the glass core board 1. As shown in FIG8 , the first chip 3 can be partially wrapped in the encapsulation layer 9, and the front side (active side) of the first chip 3 is exposed outside the encapsulation layer, which can facilitate the heat dissipation of the chip. On the one hand, the plastic encapsulation material wraps the first chip 3 to protect the first chip 3 from damage. On the other hand, the presence of the encapsulation layer 9 can further improve the mechanical strength and fracture toughness of the chip packaging structure 600, further reduce the risk of fracture of the glass core board 1, and further reduce the thickness of the glass core board 1, and further reduce the size of the TGV. In addition, the plastic encapsulation material can be used to fill the connection between the first chip 3 and the first wiring layer 2 to ensure the installation stability of the first chip 3 and the mechanical strength of the chip packaging structure, without adversely affecting the heat dissipation of the device.

[0086] In some embodiments, as shown in FIG9 , the chip packaging structure 600 further includes a second cladding layer 10 made of an organic material, the second cladding layer 10 being disposed between the glass core board 1 and the first wiring layer 2 and having a second conductive column 1001 extending therethrough. In these embodiments, the metallized via 101 is electrically connected to the first wiring layer 2 through the second conductive column 1001. Optionally, the first side surface of the glass core board 1 has at least one wiring layer, which is referred to as a first metal layer 11 for ease of description and to distinguish it from the first wiring layer, the second wiring layer, and the third wiring layer. In other embodiments, the wiring layer may also be referred to as a fourth wiring layer. The first metal layer 11 includes metal lines. The TGV in the glass core board 1 is electrically connected to the first metal layer 11 on the first side surface of the glass core board 1. The second cladding layer 10 is electrically connected to the TGV in the glass core board 1 through the first metal layer 11. In these embodiments, by arranging a second coating layer 10 between the glass core board 1 and the first wiring layer 2, the mechanical strength and fracture toughness of the chip packaging structure 600 can be further improved, the risk of fracture of the glass core board 1 can be further reduced, and the thickness of the glass core board 1 can be further reduced, and the size of the TGV can be further reduced.

[0087] In some embodiments, as shown in FIG. 9 , the chip package structure 600 further includes a third chip 12 . The third chip 12 is encapsulated in the second encapsulation layer 10 , and the third chip 12 is electrically connected to the first wiring layer 2 .

[0088] In some embodiments, the pin pitch of the first chip 3 is smaller than the pin pitch of the second chip 5, which means that the first chip 3 has higher requirements for interconnection line density than the second chip 5. For example, the first chip 3 can be a processor or a memory, and the second chip 5 can be a DTC chip, a passive component, etc.

[0089] Based on this, in a possible implementation, as shown in Figures 10 and 11, the above-mentioned third chip 12 is an interconnection bridge chip as shown in Figure 6, for example. The interconnection bridge chip is wrapped in the second cladding layer 10. High-density electrical interconnection is achieved between different first chips 3 on the first wiring layer 2 through the interconnection bridge chip. For example, the different first chips 3 on the first wiring layer 2 can be processors (such as CPU, GPU) and memories, respectively. In a more specific implementation, the first wiring layer 2 has a solder ball array on one side close to the second cladding layer 10, and the front side of the interconnection bridge chip (the side with high-density routing) is electrically connected to the metal lines in the first wiring layer through the solder balls in the solder ball array, thereby achieving high-density interconnection between different first chips 3 on the first wiring layer.

[0090] The above-mentioned third chip 12, that is, the interconnection bridge chip, may or may not have through-silicon vias. For example, continuing with Figures 10 and 11 as examples, the third chip 12 in Figure 10 is the interconnection bridge chip A as shown in Figure 6, that is, it does not have through-silicon vias. The front side of the third chip 12 is connected to the first wiring layer 2, and the back side of the third chip 12 is adhered to the first metal layer 11 through the adhesive layer 13 as shown in Figure 9. The third chip 12 in Figure 11 is the interconnection bridge chip B as shown in Figure 6, that is, it has through-silicon vias. The front side of the third chip 12 is welded to the first wiring layer 2, and the back side of the third chip 12 is welded to the second metal layer 11.

[0091] In one possible implementation, as shown in Figure 10 , the metallized vias in the glass core board 1 can be electrically connected to the first wiring layer via through-silicon vias in the interconnect bridge chip. This shortens the length of the line between the metallized vias and the first wiring layer, reducing signal loss. For example, this reduces current signal loss.

[0092] In other embodiments, as shown in FIG12 , a first groove 102 is provided on the first side surface of the glass core board 1 adjacent to the first wiring layer 2. The third chip 12 is disposed in the first groove 102 and is electrically connected to the first wiring layer 2. In these embodiments, by providing a groove on the first side surface of the glass core board 1 and mounting a chip or other device thereon, the integration of the chip packaging structure is further improved.

[0093] In one possible implementation, the depth of the first groove 102 on the first side of the glass core board is less than 150 μm, for example, 100 μm. This can, on the one hand, avoid the risk of the glass core board breaking due to an excessively deep groove, and on the other hand, reduce the difficulty of the groove forming process.

[0094] It should be noted that the specific implementation of the third chip 12 in Figure 12 can also be the interconnection bridge chip shown in Figure 6, which is used to achieve high-density interconnection between different first chips 3 on the first wiring layer. Similar to the implementation shown in Figures 11 and 10, the third chip 12 in Figure 12 can have silicon vias for achieving electrical connection between the metallized vias in the glass core board 1 and the first wiring layer, or it can be without silicon vias. For a detailed introduction to the implementation of Figure 12, please refer to the contents of the embodiments shown in Figures 11 and 10, and will not be repeated here.

[0095] In a possible implementation, the metallized via 101 in the glass core board 1 is opened in the first groove 102 , so that the metallized via 101 is electrically connected to the first wiring layer 2 through the third chip 12 .

[0096] In some embodiments, as shown in FIG13 , the chip packaging structure further includes a packaging substrate 14, which is disposed on a side of the second wiring layer 8 away from the first cladding layer 4. First conductive pillars 401 are soldered to the packaging substrate 14 via the solder ball array on the second wiring layer 8, thereby electrically connecting to the metal traces within the packaging substrate 14. Optionally, a plastic encapsulation compound is applied to the solder joints between the second wiring layer 8 and the packaging substrate 14 to ensure the stability of the connection. Optionally, the metal traces within the packaging substrate 14 are larger than those within the second wiring layer 8, and the wiring density of the metal traces within the packaging substrate 14 is lower than that within the second wiring layer 8. In this embodiment, the packaging substrate is further disposed on the side of the second wiring layer away from the first cladding layer. Because the metal traces within the packaging substrate are larger than those within the second wiring layer, and the wiring density of the metal traces within the packaging substrate is lower than that within the second wiring layer, the packaging substrate serves as a transition between the chip packaging structure and the circuits on the PCB, improving the feasibility of direct mounting the chip packaging structure on the PCB.

[0097] In the embodiment shown in Figure 13, the second wiring layer includes a layer of metal circuit. The presence of the package substrate can reduce the number of metal circuit layers in the second wiring layer.

[0098] In the above embodiment, the thickness of the glass core board in the direction from the first wiring layer to the first cladding layer is 50um-2000um. For example, when the chip packaging structure includes a packaging substrate, the thickness of the glass core board can be 50um-200um. When the chip packaging structure does not include a packaging substrate and is used to be directly installed on a PCB board, the thickness of the glass core board can be 200um-2000um. This is because, when the chip packaging structure is installed on a PCB board, if the chip packaging structure includes a packaging substrate, then the packaging substrate can alleviate the stress on the glass core board, and then the thickness of the glass substrate can be further reduced to achieve a smaller TGV without increasing the risk of fracture of the glass core board. On the contrary, if the chip packaging structure does not include a packaging substrate, the thickness and fracture risk of the glass substrate need to be taken into account.

[0099] In some embodiments, as shown in FIG14 , when the chip packaging structure is implemented as an independent electronic device, in the chip packaging structure 600, a heat sink 15 is further provided on the side of the packaging layer 9 away from the glass core board 1 for dissipating heat for the chip packaging structure. An electrical connector 16 is further provided on the side of the second wiring layer 10 away from the glass core board 1. One end of the electrical connector 16 is electrically connected to the second wiring layer 8, and the other end is used to connect to an external circuit, thereby realizing an electrical connection between the chip packaging structure and the external circuit, so that the chip packaging structure is realized as an independent electronic device. For example, the electrical connector 16 includes a power supply module for supplying power to the devices in the chip packaging structure, and may also include an interconnection module for realizing signal transmission between the chip packaging structure and the external circuit.

[0100] FIG15 shows a method for manufacturing a chip packaging structure provided in an embodiment of the present application. As shown in FIG15 , the manufacturing method may include the following steps.

[0101] S100, preparing metallized vias on the glass core board.

[0102] S200 , forming a first wiring layer on a first side of a glass core board, and mounting a first chip on the first wiring layer; the first wiring layer is electrically connected to the metallized vias.

[0103] S300 , mounting a second chip on the second side of the glass core board and forming a first cladding layer; the first cladding layer wraps the second chip and has a first conductive column provided therethrough, the first conductive column being electrically connected to the first wiring layer through a metallized via.

[0104] S400 , forming a solder ball array on a side of the first cladding layer away from the glass core board, wherein the solder ball array is electrically connected to the first wiring layer through metallized vias.

[0105] It should be noted that the manufacturing method flow shown in FIG15 does not constitute a limitation on the order in which the steps of the manufacturing method provided in the embodiments of the present application are to be executed. For example, S300 may be executed first, then S200, or S200 may be executed first, then S100, and so on. In addition, the further refinement of each step shown in FIG15 may be executed alternately. For example, the refinement of S100 may be executed alternately with the refinement of S200.

[0106] In some embodiments, the method for manufacturing the chip packaging structure further includes: S500, forming a second wiring layer on a side of the first cladding layer away from the glass core board, wherein the second wiring layer is electrically connected to the first conductive pillar.

[0107] In some embodiments, before executing S300, the manufacturing method of the chip packaging structure also includes: forming a third wiring layer on the second side of the glass core board and forming solder balls on the third wiring layer; in S300, installing a second chip on the second side of the glass core board, specifically including: soldering the second chip to the solder balls.

[0108] In some embodiments, before executing S200, the method for manufacturing a chip package structure further includes: S600, forming a second cladding layer on the first side of the glass core board, the second cladding layer having a second conductive pillar disposed therethrough. In these embodiments, the metallized via is electrically connected to the first wiring layer through the second conductive pillar.

[0109] In some embodiments, before executing S600, the chip packaging structure manufacturing method further includes: S700, mounting a third chip on the first side of the glass core board. In these embodiments, the second cladding layer wraps the third chip; and the third chip is electrically connected to the first wiring layer.

[0110] In some embodiments, before executing S600, the chip packaging structure manufacturing method further includes: S800, installing an electrical interconnection structure on the first side of the glass core board. In these embodiments, the second cladding layer wraps the electrical interconnection structure, and the metallized via is electrically connected to the first wiring layer through the electrical interconnection structure.

[0111] In some embodiments, before executing S200, the chip packaging structure manufacturing method further includes: S900, making a first groove on the first side surface of the glass core board; installing a third chip in the first groove; and electrically connecting the third chip to the first wiring layer.

[0112] In some embodiments, before executing S300, the method for manufacturing the chip packaging structure further includes: S1000, manufacturing a second groove on the second side surface of the glass core board; installing a third chip in the second groove; and electrically connecting the third chip to the first wiring layer.

[0113] The following describes in detail the manufacturing method of the chip packaging structure provided by the embodiments of the present application through a plurality of different embodiments. For ease of description, the first side surface of the glass core board is referred to as the front side, and the second side surface is referred to as the back side.

[0114] In one example, the chip packaging structure provided by the embodiment of the present application is manufactured according to the process shown in FIG16 :

[0115] S161. Etching through holes on the glass core board and metallizing the through holes to form metallized vias.

[0116] In a specific implementation, the metallization process may be depositing a metal layer, such as a copper layer.

[0117] S162, forming a first wiring layer on the front surface of the glass core board; electrically connecting the metallized vias in the glass core board to the circuits in the first wiring layer.

[0118] S163. Form a metal layer (i.e., the second metal layer mentioned in the above embodiment) on the back of the glass core board, and prepare a first conductive column on the metal layer; the metallized via in the glass core board is electrically connected to the first conductive column through the metal layer.

[0119] S164. Install a chip (ie, the second chip mentioned in the above embodiment) on the second metal layer on the back side of the glass core board.

[0120] S165. Use plastic packaging material to form a first cladding layer on the back of the glass core board, so that the first cladding layer wraps the first conductive column and the chip on the back, and the end of the first conductive column away from the glass core board is exposed to the outer surface of the first cladding layer.

[0121] S166. Form a second wiring layer on a surface of the first cladding layer away from the glass core board, wherein the second wiring layer is electrically connected to the first conductive column.

[0122] S167 . Install a chip (ie, the first chip mentioned in the above embodiment) on a side of the first wiring layer away from the glass core board.

[0123] S168 , forming a solder ball array on a surface of the second wiring layer on a side away from the first cladding layer.

[0124] Through the above steps S161 - S168 , a chip packaging structure as shown in FIG7 is manufactured.

[0125] In another example, the chip packaging structure provided by the embodiment of the present application is manufactured according to the process shown in FIG17 :

[0126] S171. Etching through holes on the glass core board and metallizing the through holes to form metallized vias.

[0127] In a specific implementation, the metallization process may be depositing a metal layer, such as a copper layer.

[0128] S172. Form a metal layer (i.e., the second metal layer mentioned in the above embodiment) on the back of the glass core board, and prepare a first conductive column on the metal layer; the metallized via in the glass core board is electrically connected to the first conductive column through the metal layer.

[0129] S173. Install a chip (i.e., the second chip mentioned in the above embodiment) on the second metal layer on the back side of the glass core board.

[0130] S174. Use plastic packaging material to form a first cladding layer on the back of the glass core board, so that the first cladding layer wraps the first conductive column and the chip on the back, and the end of the first conductive column away from the glass core board is exposed to the outer surface of the first cladding layer.

[0131] S175 , forming a second wiring layer on a surface of the first cladding layer away from the glass core board, wherein the second wiring layer is electrically connected to the first conductive column.

[0132] S176. Form a first wiring layer on the front surface of the glass core board; electrically connect the metallized vias in the glass core board to the circuits in the first wiring layer.

[0133] S177 , mounting a chip (ie, the first chip mentioned in the above embodiment) on a side of the first wiring layer away from the glass core board.

[0134] S178 , forming a solder ball array on a surface of the second wiring layer on a side away from the first cladding layer.

[0135] Through the above steps S171 - S178 , a chip packaging structure as shown in FIG7 is manufactured.

[0136] In another example, the chip packaging structure provided by the embodiment of the present application is manufactured according to the process shown in FIG18 :

[0137] S181. Etching blind holes on the glass core board in a direction from the front side to the back side of the glass core board, and metallizing the blind holes to form metallized blind holes.

[0138] In a specific implementation, the metallization process may be depositing a metal layer, such as a copper layer.

[0139] S182, forming a first wiring layer on the front surface of the glass core board; electrically connecting the metallized blind vias in the glass core board to the circuits in the first wiring layer.

[0140] Optionally, a carrier may be bonded to the side of the glass core board where the first wiring layer is formed, to facilitate subsequent operations.

[0141] S183. Grind and polish the back side of the glass core board until the metal layer of the inner hole of the glass core board is exposed, so that the metallized blind hole becomes a metallized through hole.

[0142] S184. Form a metal layer (i.e., the second metal layer mentioned in the above embodiment) on the back of the glass core board, and prepare a first conductive column on the metal layer; the metallized via in the glass core board is electrically connected to the first conductive column through the metal layer.

[0143] S185. Install a chip (ie, the second chip mentioned in the above embodiment) on the second metal layer on the back side of the glass core board.

[0144] S186. Use plastic packaging material to form a first cladding layer on the back of the glass core board, so that the first cladding layer wraps the first conductive column and the chip on the back, and the end of the first conductive column away from the glass core board is exposed to the outer surface of the first cladding layer.

[0145] S187. Form a second wiring layer on a surface of the first cladding layer away from the glass core board, wherein the second wiring layer is electrically connected to the first conductive column.

[0146] S188. Install a chip (ie, the first chip mentioned in the above embodiment) on a side of the first wiring layer away from the glass core board.

[0147] S189, forming a solder ball array on a surface of the second wiring layer away from the first cladding layer.

[0148] Through the above steps S181 - S189 , a chip packaging structure as shown in FIG7 is manufactured.

[0149] In another example, the chip packaging structure provided by the embodiment of the present application is manufactured according to the process shown in FIG19 :

[0150] S191. Etching blind holes on the glass core board in a direction from the back side to the front side of the glass core board, and metallizing the blind holes to form metallized blind holes.

[0151] S192. Form a metal layer (i.e., the second metal layer mentioned in the above embodiment) on the back of the glass core board, and prepare a first conductive column on the metal layer; the metallized blind hole in the glass core board is electrically connected to the first conductive column through the metal layer.

[0152] S193. Install a chip (ie, the second chip mentioned in the above embodiment) on the second metal layer on the back side of the glass core board.

[0153] S194. Use plastic packaging material to form a first cladding layer on the back of the glass core board, so that the first cladding layer wraps the first conductive column and the chip on the back, and the end of the first conductive column away from the glass core board is exposed to the outer surface of the first cladding layer.

[0154] S195 , forming a second wiring layer on a surface of the first cladding layer away from the glass core board, wherein the second wiring layer is electrically connected to the first conductive column.

[0155] S196. Grind and polish the front surface of the glass core board until the metal layer of the inner hole of the glass core board is exposed, so that the metallized blind hole becomes a metallized through hole.

[0156] S197. Form a first wiring layer on the front surface of the glass core board; electrically connect the metallized vias in the glass core board to the circuits in the first wiring layer.

[0157] S198. Install a chip (ie, the first chip mentioned in the above embodiment) on a side of the first wiring layer away from the glass core board.

[0158] S199, forming a solder ball array on a surface of the second wiring layer away from the first cladding layer.

[0159] Through the above steps S181 - S189 , a chip packaging structure as shown in FIG7 is manufactured.

[0160] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0161] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that: include: Glass core board with metallized vias; A first wiring layer, disposed on one side of the glass core board and electrically connected to the metallized via; A first chip is arranged on a side of the first wiring layer away from the glass core board and is electrically connected to the first wiring layer; A first cladding layer, made of an organic material, is disposed on the other side of the glass core board, and has a first conductive column disposed therethrough, wherein the first conductive column is electrically connected to the first wiring layer through the metallized via hole; The second chip is wrapped in the first covering layer and electrically connected to the first wiring layer through the metallized vias.

2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes: The second wiring layer is arranged on a side of the first cladding layer away from the glass core board and is electrically connected to the first conductive column.

3. The chip packaging structure according to claim 2, characterized in that: The chip packaging structure further includes: A packaging substrate, arranged on a side of the second wiring layer away from the first cladding layer; The first conductive column is electrically connected to a metal line in the packaging substrate through the second wiring layer.

4. The chip packaging structure according to claim 2 or 3, characterized in that: The second wiring layer includes a layer of metal lines.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The chip packaging structure further includes: A third wiring layer is arranged between the first cladding layer and the glass core board; the third wiring layer is electrically connected to the first wiring layer through the metallized vias, a solder ball is provided on a side of the third wiring layer close to the first cladding layer, and the second chip is electrically connected to the solder ball; The first conductive column is electrically connected to the metallized via through the third wiring layer.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The chip packaging structure further includes: The packaging layer is arranged on a side of the first wiring layer away from the glass core board; the first chip is located in the packaging layer.

7. The chip packaging structure according to claim 6, characterized in that: The packaging layer is made of a molding compound, and the first chip is completely or partially wrapped in the molding compound.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The chip packaging structure further includes: The second cladding layer is made of an organic material, is disposed between the glass core board and the first wiring layer, and has a second conductive column disposed therethrough; the metallized via is electrically connected to the first wiring layer through the second conductive column.

9. The chip packaging structure according to claim 8, characterized in that: The chip packaging structure further includes: The third chip is wrapped in the second covering layer and electrically connected to the first wiring layer.

10. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The glass core board has a first groove on its surface on one side close to the first wiring layer; the chip packaging structure further includes: A third chip is disposed in the first groove and is electrically connected to the first wiring layer.

11. The chip packaging structure according to claim 9 or 10, characterized in that: The number of the first chips is multiple; The third chip is an electrical interconnection structure, and different first chips are electrically connected via the electrical interconnection structure.

12. The chip packaging structure according to claim 11, characterized in that: The electrical interconnection structure includes: a substrate and a wiring layer arranged on one side of the substrate.

13. The chip packaging structure according to claim 11 or 12, characterized in that: The electrical interconnection structure further includes a through silicon via penetrating the substrate; the metallized via is electrically connected to the first wiring layer through the through silicon via and the wiring layer.

14. The chip packaging structure according to claim 10, characterized in that: The depth of the first groove is less than 150 um.

15. The chip packaging structure according to any one of claims 1 to 14, characterized in that: The thickness of the glass core board in the direction from the first wiring layer to the first cladding layer is 50um-2000um.

16. The chip packaging structure according to any one of claims 1 to 15, characterized in that: A solder ball array and a copper pillar bump array are arranged on a side of the second wiring layer away from the first cladding layer.

17. A method for manufacturing a chip packaging structure, characterized in that: The method comprises: Prepare metallized vias on the glass core board; forming a first wiring layer on a first side of the glass core board, and mounting a first chip on the first wiring layer; the first wiring layer is electrically connected to the metallized via; A second chip is mounted on the second side of the glass core board, and a first cladding layer is formed; the first cladding layer wraps the second chip and has a first conductive column arranged therethrough, and the first conductive column is electrically connected to the first wiring layer through the metallized via.

18. The manufacturing method according to claim 17, characterized in that: The method further comprises: A second wiring layer is formed on a side of the first cladding layer away from the glass core board, and the second wiring layer is electrically connected to the first conductive column.

19. The manufacturing method according to claim 18, characterized in that: Before the second chip is installed on the second side of the glass core board, the method further includes: A third wiring layer is formed on the second side of the glass core board, and a solder ball is formed on the surface of the third wiring layer on one side close to the first cladding layer; the third wiring layer is electrically connected to the first wiring layer through the metallized via hole, and the first conductive column is electrically connected to the metallized via hole through the third wiring layer; The step of installing a second chip on the second side of the glass core board comprises: The second chip is soldered to the solder balls.

20. The method according to any one of claims 17 to 19, characterized in that: Before forming the first wiring layer on the first side of the glass core board, the method further includes: A second cladding layer is formed on the first side of the glass core board, wherein the second cladding layer has a second conductive column disposed therethrough; and the metallized via is electrically connected to the first wiring layer through the second conductive column.

21. The manufacturing method according to claim 20, characterized in that: Before forming the second cladding layer on the first side of the glass core board, the method further comprises: A third chip is mounted on the first side of the glass core board, and the second cladding layer wraps the third chip; the third chip is electrically connected to the first wiring layer.

22. The method according to any one of claims 17 to 19, characterized in that: Before forming the first wiring layer on the first side of the glass core board, the manufacturing method further includes: Making a first groove on a first side surface of the glass core board; A third chip is mounted in the first groove; the third chip is electrically connected to the first wiring layer.

23. The method according to claim 21 or 22, characterized in that: The number of the first chips is multiple; The third chip is an electrical interconnection structure, and different first chips are electrically connected via the electrical interconnection structure.

24. An electronic device, characterized in that: include: Motherboard; According to the chip packaging structure as described in any one of claims 1-16, the main board is arranged on a side of the glass core board in the chip packaging structure where the first cladding layer is arranged, and is electrically connected to the chip packaging structure.

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