Semiconductor device, chip, electronic device and semiconductor device manufacturing method

Abstract

Provided in the embodiments of the present application are a semiconductor device, a chip, an electronic device and a semiconductor device manufacturing method, relating to the technical field of semiconductor bonding, and used for improving the electric connection effect between two semiconductor devices. The semiconductor device comprises a semiconductor structure and an interconnection layer, the interconnection layer being located on one side of the semiconductor structure, the interconnection layer comprising a plurality of bonding portions which are space apart, each bonding portion comprising a bonding pad and a metallic glass layer, the bonding pad being connected to the semiconductor structure, and the metallic glass layer covering the side of the bonding pad away from the semiconductor structure. The semiconductor device is used for chips.

Description

Semiconductor device, chip, electronic device and method for manufacturing semiconductor device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 28, 2023, with application number 202311290163.3 and application name “Semiconductor devices, chips, electronic devices and methods for preparing semiconductor devices”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor bonding technology, and in particular to a semiconductor device, a chip, an electronic device, and a method for preparing a semiconductor device. Background Art

[0003] With the development of semiconductor technology, the size of semiconductor devices has become smaller and smaller, and the size of the pads provided therein has also become smaller and smaller. In related technologies, hybrid bonding technology can be used to connect the pads of two semiconductor devices, thereby electrically connecting the two semiconductor devices. However, in related technologies, the bonding effect between the pads is poor, resulting in a poor electrical connection between the two semiconductor devices.

[0004] Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a semiconductor device, a chip, an electronic device and a method for manufacturing a semiconductor device, so as to improve the electrical connection effect between two semiconductor devices.

[0006] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] In one aspect, a semiconductor device is provided. The semiconductor device includes a semiconductor structure and an interconnect layer. The interconnect layer is located on one side of the semiconductor structure and includes a plurality of spaced bonding portions. The bonding portions include bonding pads and a metallic glass layer. The bonding pads are connected to the semiconductor structure, and the metallic glass layer covers a side of the bonding pads away from the semiconductor structure.

[0008] In the above-mentioned semiconductor device, the metallic glass layer can be electrically connected to the bonding pad, and the metallic glass layer can be electrically connected to the semiconductor structure through the bonding pad. The metallic glass layer of the semiconductor device can be hybrid-bonded with the metallic glass layer of another semiconductor device, and the metallic glass layers of the two semiconductor devices can form a bonding connection portion, and the bonding connection portion can be electrically connected to the semiconductor structure through the bonding pad. In this case, the semiconductor structures of the two semiconductor devices can be electrically connected through the bonding pad and the bonding connection portion. In the bonding process of the metallic glass layers of the bonding portions in the two semiconductor devices, the metallic glass layers of the bonding portions in the two semiconductor devices are aligned with high precision and hybrid-bonded, and then annealed. During the annealing process, when the temperature reaches the supercooled liquid phase region, the metallic glass layers of the two semiconductor devices can soften and form a liquid-like state, thereby producing an effect similar to liquid flow, thereby reducing the gap at the contact interface of the metallic glass layers of the two semiconductor devices, thereby improving the contact effect of the metallic glass layers of the two semiconductor devices, thereby improving the bonding effect of the two semiconductor devices, and further improving the electrical connection quality of the two semiconductor devices, thereby improving the subsequent electrical testing and reliability testing of the chip. In addition, before the metallic glass layers of the two semiconductor devices are bonded, an oxide layer may exist on the surface of the metallic glass layer. The metallic glass layer is an amorphous structure (i.e., no crystalline structure) at the microscopic level. Among them, the metal atoms in the metallic glass layer do not occupy the lowest energy site, so the metal atoms are in a higher energy state structurally. In this case, the metallic glass layer can activate the movement of its local metal atomic clusters through ultrasonic vibration at room temperature, and the movement of the atomic clusters can enable the atomic clusters to break through the oxide layer of the bonding interface of the metallic glass layer. At this time, the metallic glass layers in the two semiconductor devices can break through the surface oxide layer for bonding. Therefore, the bonding effect of the metallic glass layers in the two semiconductor devices is better. In addition, since, at room temperature, the movement of the atomic clusters in the metallic glass layer can break through the surface oxide layer, the metallic glass layers in the two semiconductor devices can be bonded under room temperature conditions. In addition, after the metallic glass layers of the two semiconductor devices are mixed and bonded, the movement of the metal atomic clusters will be more intense during the annealing process, which will be more conducive to the metal atomic clusters breaking through the oxide layer at the bonding interface of the metallic glass layer, thereby improving the bonding effect of the metallic glass layers in the two semiconductor devices.

[0009] In some embodiments, the interconnect layer further includes: a dielectric layer, the bonding portion is embedded in the dielectric layer, the dielectric layer exposes a first surface of the metallic glass layer, the first surface is a surface of the metallic glass layer facing away from the semiconductor structure; the dielectric layer includes a second surface facing away from the semiconductor structure; wherein the first surface is closer to the semiconductor structure than the second surface.

[0010] The first surface of the metallic glass layer can enclose an expansion space with the dielectric layer. During the bonding process of the metallic glass layer at the bonding portion of the two semiconductor devices, the metallic glass layers of the two semiconductor devices can expand, and at this time, the volume of the metallic glass layer can increase. By making the first surface of the metallic glass layer and the dielectric layer enclose an expansion space, the metallic glass layer can expand into the expansion space, thereby avoiding that after the metallic glass layer expands, the portion protruding too much from the second surface of the dielectric layer causes a gap between the metallic glass layers of the two semiconductor devices after bonding. In the embodiment of the present application, by making the first surface closer to the semiconductor structure than the second surface, the phenomenon of a gap between the two semiconductor devices after bonding due to the expansion of the metallic glass layer can be reduced.

[0011] In some embodiments, the distance between the first surface and the second surface in the first direction is greater than or equal to and less than or equal to The first direction is perpendicular to the first surface.

[0012] Wherein, by making the distance between the first surface and the second surface in the first direction greater than or equal to The metallic glass layer can have sufficient expansion space to avoid the metallic glass layer from protruding too much from the second surface after expansion due to lack of expansion space, resulting in a gap between the two semiconductor devices after the metallic glass layer is bonded, thereby affecting the bonding effect of the metallic glass layer in the two semiconductor devices. The phenomenon of a gap between two semiconductor devices after bonding the metallic glass layer can be reduced.

[0013] By making the distance between the first surface and the second surface in the first direction less than or equal to This can prevent the expansion space of the metallic glass layer from being too large, which would result in the metallic glass layer being unable to fill the expansion space after expansion. If the expansion space is too large, a gap would exist between the metallic glass layers of the two semiconductor devices after expansion, thereby affecting the contact effect of the metallic glass layers of the two semiconductor devices. Therefore, by making the distance between the first surface and the second surface in the first direction less than or equal to The influence of the excessive expansion space on the bonding effect of the metallic glass layers of the two semiconductor devices can be reduced.

[0014] In some embodiments, the dielectric layer includes a first isolation layer, an intermediate layer, and a second isolation layer sequentially stacked on the semiconductor structure; the bonding pad is embedded in the first isolation layer, the intermediate layer, and the second isolation layer, and the metallic glass layer is embedded in the second isolation layer.

[0015] The second surface of the dielectric layer is the surface of the second isolation layer facing away from the semiconductor structure. In this way, the first surface of the metallic glass layer can be lower than or flush with the second surface of the dielectric layer.

[0016] In some embodiments, a ratio of the thickness of the bonding pad to the thickness of the metallic glass layer is greater than or equal to 10.55 and less than or equal to 158.9.

[0017] Wherein, the ratio of the thickness of the bonding pad to the thickness of the metallic glass layer is greater than or equal to 10.55, thereby preventing the thickness of the metallic glass layer from being too large. If the thickness of the metallic glass layer is too large, it may cause the portion of the metallic glass layer to protrude too much from the second surface after expansion. At this time, after the metallic glass layers of the two semiconductor devices are bonded, a gap may exist between the two semiconductor devices. Therefore, by making the ratio of the thickness of the bonding pad to the thickness of the metallic glass layer greater than or equal to 10.55, the phenomenon of the presence of a gap between the two semiconductor devices due to the excessive thickness of the metallic glass layer can be reduced. In addition, the ratio of the thickness of the bonding pad to the thickness of the metallic glass layer is less than or equal to 158.9, thereby preventing the thickness of the metallic glass layer from being too small. If the thickness of the metallic glass layer is too small, it may cause a gap between the metallic glass layers of the two semiconductor devices after expansion, thereby causing the metallic glass layers of the two semiconductor devices to be insufficiently bonded. Therefore, by making the ratio of the thickness of the bonding pad to the thickness of the metallic glass layer less than or equal to 158.9, the phenomenon of insufficient bonding of the metallic glass layers of two semiconductor devices due to too small a thickness of the metallic glass layer can be reduced.

[0018] In some embodiments, the bonding pad includes a first portion and a second portion, wherein one end of the first portion is connected to the semiconductor structure, and the second portion is connected to the other end of the first portion, wherein a cross-sectional area of ​​the first portion on a first reference plane is smaller than a cross-sectional area of ​​the second portion on a second reference plane, wherein both the first reference plane and the second reference plane are parallel to a surface of the metallic glass layer facing away from the semiconductor structure, and wherein a ratio of a thickness of the first portion to a thickness of the metallic glass layer is greater than or equal to 5.55 and less than or equal to 75. A ratio of a thickness of the second portion to a thickness of the metallic glass layer is greater than or equal to 5 and less than or equal to 83.9.

[0019] The ratio of the thickness of the first portion to the thickness of the metallic glass layer is greater than or equal to 5.55, thereby preventing the metallic glass layer from being too thick. If the metallic glass layer is too thick, the metallic glass layer may protrude excessively from the second surface after expansion, resulting in a gap between the two semiconductor devices after the metallic glass layers of the two semiconductor devices are bonded. Therefore, by setting the ratio of the thickness of the first portion to the thickness of the metallic glass layer to be greater than or equal to 5.55, the gap between the two semiconductor devices caused by an excessively thick metallic glass layer can be reduced. Furthermore, the ratio of the thickness of the second portion to the thickness of the metallic glass layer is less than or equal to 75, thereby preventing the metallic glass layer from being too thin. If the metallic glass layer is too thin, a gap between the metallic glass layers of the two semiconductor devices may be formed after expansion, resulting in insufficient bonding between the metallic glass layers of the two semiconductor devices. Therefore, by setting the ratio of the thickness of the second portion to the thickness of the metallic glass layer to be less than or equal to 75, the insufficient bonding between the metallic glass layers of the two semiconductor devices caused by an excessively thin metallic glass layer can be reduced.

[0020] In some embodiments, the thickness of the metallic glass layer is greater than or equal to and less than or equal to

[0021] Wherein, the thickness of the metallic glass layer is greater than or equal to This can prevent the thickness of the metallic glass layer from being too small. If the thickness of the metallic glass layer is too small, a gap may exist between the metallic glass layers of the two semiconductor devices after expansion, resulting in insufficient bonding of the metallic glass layers of the two semiconductor devices. Therefore, by making the thickness of the metallic glass layer greater than or equal to The phenomenon of insufficient bonding of the metal glass layers of two semiconductor devices caused by the metal glass layer being too thin can be reduced. In addition, the thickness of the metal glass layer is less than or equal to This can prevent the thickness of the metallic glass layer from being too large. If the thickness of the metallic glass layer is too large, the metallic glass layer may bulge out too much from the second surface after expansion, and in this case, a gap will be left between the two semiconductor devices after the metallic glass layers of the two semiconductor devices are bonded. Therefore, by making the thickness of the metallic glass layer less than or equal to The phenomenon of a gap between two semiconductor devices caused by the excessive thickness of the metallic glass layer can be reduced.

[0022] In some embodiments, the thickness of the bonding pad is greater than or equal to and less than or equal to

[0023] Wherein, the thickness of the bonding pad is greater than or equal to It can avoid that the thickness of the bonding pad is too thin, which would result in the metallic glass layer on the surface of the bonding pad being too thick. If the thickness of the metallic glass layer is too thick, the metallic glass layer may bulge out too much from the second surface after expansion. In this case, after the metallic glass layers of the two semiconductor devices are bonded, a gap may exist between the two semiconductor devices. Therefore, by making the thickness of the bonding pad greater than or equal to The gap between the two semiconductor devices caused by the excessive thickness of the metallic glass layer can be reduced. It is possible to avoid the bonding pad being too thick, which would result in the metallic glass layer on the bonding pad being too thin. If the thickness of the metallic glass layer is too thin, a gap may exist between the metallic glass layers of the two semiconductor devices after expansion, thereby resulting in insufficient bonding of the metallic glass layers of the two semiconductor devices. Therefore, by making the bonding pad thickness less than or equal to The phenomenon of insufficient bonding of the metallic glass layers of two semiconductor devices caused by the metallic glass layer being too thin can be reduced.

[0024] In some embodiments, the material of the metallic glass layer includes CuZr.

[0025] Among them, after the bonding process of the metallic glass layers of the two semiconductor devices, when the two semiconductor devices are annealed, when the annealing temperature reaches the crystallization temperature of CuZr, the Cu atoms and Zr atoms in CuZr can undergo atomic position rearrangement. Specifically, the Cu atoms can crystallize and precipitate single-crystalline Cu. At this time, the bonding connection formed after the metallic glass layers of the two semiconductor devices are bonded can include CuZr and single-crystalline Cu. Among them, the resistivity of single-crystalline Cu is lower than the resistivity of CuZr. Therefore, the material of the metallic glass layer includes CuZr, which can reduce the resistivity of the bonding connection. In addition, single-crystalline Cu can also destroy the oxide layer on the bonding surface of the metallic glass layer 342 of the two semiconductor devices 300, thereby improving the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300.

[0026] In another aspect, a chip is provided, comprising: two semiconductor devices provided by any one of the above embodiments, wherein the metallic glass layers of the multiple bonding portions of the two semiconductor devices are bonded to form multiple bonding connection portions.

[0027] The chip is composed of two semiconductor devices provided in some of the above embodiments, and therefore has the same beneficial effects as the semiconductor devices provided in some of the above embodiments, which will not be described in detail here.

[0028] In some embodiments, in a semiconductor device, a bonding pad of a bonding portion has a recess on a surface facing away from a semiconductor structure of the semiconductor device, and a portion of the bonding connection portion is filled in the recess.

[0029] Among them, the surface of the bonding pad facing away from the semiconductor structure is a non-smooth surface with a depression thereon. During the bonding process of the metallic glass layers of the two semiconductor devices, the temperature of the metallic glass layer will increase. When the temperature reaches the supercooled liquid phase region, the metallic glass layer will be in a liquid-like state. Therefore, the metallic glass layer can have fluidity, and then the metallic glass layer can fill the depression on the surface of the bonding pad facing away from the semiconductor structure, thereby increasing the connection effect between the metallic glass layer (that is, the bonding connection portion) and the bonding pad.

[0030] In some embodiments, the material of the bond connection includes CuZr and single crystal Cu.

[0031] After the metallic glass layers of the two semiconductor devices are bonded, when the two semiconductor devices are annealed, when the annealing temperature reaches the crystallization temperature of CuZr, the Cu atoms in the CuZr can crystallize and precipitate single-crystalline Cu. In other words, the bonding connection formed after the metallic glass layers of the two semiconductor devices are bonded can include CuZr and single-crystalline Cu. The resistivity of single-crystalline Cu is lower than that of CuZr, and therefore, the resistivity of the bonding connection can be reduced.

[0032] In another aspect, an electronic device is provided, which includes a circuit board and the chip provided by some of the above embodiments, wherein the chip is disposed on the circuit board.

[0033] Among them, the above-mentioned electronic device has the same structure and beneficial technical effects as the chips provided in some of the above-mentioned embodiments, which will not be repeated here.

[0034] In another aspect, a method for fabricating a semiconductor device is provided. The method comprises: forming a dielectric layer on a surface of a semiconductor structure; forming a plurality of contact holes in the dielectric layer; forming bonding pads in the contact holes; and forming a metallic glass layer in the contact holes, wherein the metallic glass layer overlaps and contacts the bonding pads.

[0035] Among them, the manufacturing method of the above-mentioned semiconductor device is used to manufacture the semiconductor devices provided by some of the above embodiments, and therefore has the same beneficial effects as the semiconductor devices provided by some of the above embodiments, and will not be described in detail here.

[0036] In some embodiments, forming bonding pads within a plurality of contact holes includes: depositing a metal material to fill the contact holes; removing the metal material at the top of the contact holes to form a first recess, with the metal material remaining in the contact holes serving as the bonding pads; the top of the contact holes being the region at one end of the contact holes facing away from the semiconductor structure. Forming a metallic glass layer within the contact holes includes: forming the metallic glass layer within the first recess.

[0037] After removing the metal material at the top of the contact hole, a first recess can be formed, thereby providing space for the metallic glass layer. Furthermore, after removing the metal material at the top of the contact hole, a bonding pad can be formed. This allows the bonding pad to have a flat surface on the side facing away from the semiconductor structure, thereby providing a flat surface for the formation of the metallic glass layer and improving the thickness uniformity of the metallic glass layer.

[0038] In some embodiments, forming a metallic glass layer in the first recess includes: depositing a metallic glass material, the metallic glass material filling the first recess and covering the dielectric layer; removing the metallic glass material covering the dielectric layer and retaining the metallic glass material in the first recess to form the metallic glass layer.

[0039] The first surface of the metallic glass layer may be flush with the second surface of the dielectric layer.

[0040] In some embodiments, forming a metallic glass layer in the first recess includes: depositing a metallic glass material, the metallic glass material filling the first recess and covering the dielectric layer; removing the metallic glass material covering the dielectric layer and the metallic glass material located at the top of the first recess, and the metallic glass material remaining in the first recess is the metallic glass layer, wherein the top of the first recess is the region of the first recess facing away from the semiconductor structure.

[0041] The first surface of the metallic glass layer is closer to the semiconductor structure than the second surface of the dielectric layer. At this point, the first surface of the metallic glass layer can enclose an expansion space with the dielectric layer. During the bonding process of the metallic glass layers at the bonding portion of the two semiconductor devices, the metallic glass layers of the two semiconductor devices can expand, and at this point, the volume of the metallic glass layer can increase. By enclosing an expansion space with the dielectric layer, the metallic glass layer can expand into the expansion space, thereby preventing the metallic glass layer from protruding excessively from the second surface of the dielectric layer after expansion. In this case, after the metallic glass layers of the two semiconductor devices are bonded, a gap may exist between the two semiconductor devices. Therefore, by making the first surface closer to the semiconductor structure than the second surface, the phenomenon of a gap existing after the bonding of the two semiconductor devices due to the expansion of the metallic glass layer can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of this application.

[0043] FIG1 is a structural diagram of an electronic device provided in an embodiment of the present application;

[0044] FIG2 is a structural diagram of a chip in the related art;

[0045] FIG3 is a structural diagram of a chip provided in an embodiment of the present application;

[0046] FIG4 is a structural diagram of a semiconductor device provided in an embodiment of the present application;

[0047] FIG5 is another structural diagram of a semiconductor device provided in an embodiment of the present application;

[0048] FIG6 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0049] 7 to 14 are diagrams showing steps of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0050] FIG15 is another flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0051] FIG16 is another flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0052] FIG17 is another flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0053] FIG18 is another flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0054] 19 to 24 are diagrams showing another step of the method for manufacturing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0056] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0057] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0058] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0059] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°.

[0060] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0061] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the areas of regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0062] FIG1 is a structural diagram of an electronic device provided in an embodiment of the present application.

[0063] Referring to FIG. 1 , an embodiment of the present application provides an electronic device 1000 . The electronic device 1000 may include any one of a CMOS (complementary metal-oxide-semiconductor) image sensor, a NAND memory, a high-bandwidth memory, a mobile phone, a tablet computer (pad), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and the like. The embodiment of the present application does not impose any particular limitation on the specific form of the electronic device 1000 .

[0064] As shown in FIG. 1 , the electronic device 1000 may include a chip packaging structure 2000 and a circuit board 3000 , and the chip packaging structure 2000 is electrically connected to the circuit board 3000 .

[0065] The chip package structure 2000 may include a chip 100 and a package substrate 200. The chip 100 may be packaged in the package substrate 200. In this case, the chip 100 may be disposed on a circuit board 3000 through the package substrate 200. The chip 100 may be a 3D IC (3-dimension integrated circuit).

[0066] FIG2 is a structural diagram of a chip 100 in the related art.

[0067] Referring to FIG. 2 , in some examples, the chip 100 may include two semiconductor devices 300. The semiconductor device 300 may include a semiconductor structure 310 and a connection layer 320, wherein the connection layer 320 is disposed on one side of the semiconductor structure 310. The connection layer 320 may include a plurality of pads 321 and an intermediate layer 322. The plurality of pads 321 may be embedded in the intermediate layer 322 and may be electrically connected to the semiconductor structure 310.

[0068] The plurality of pads 321 of one semiconductor device 300 may be fixedly connected and electrically connected to the plurality of pads 321 of another semiconductor device 300 , thereby making the two semiconductor devices 300 fixedly connected and electrically connected.

[0069] The semiconductor structure 310 of the chip 100 may include a plurality of transistors. With the continuous development of semiconductor technology, the size of transistors has gradually decreased, and accordingly, the size of the pads 321 has gradually decreased. Accordingly, in the related art, Cu (copper) is used as the material of the pads 321, and the pads 321 of the two semiconductor devices 300 are hybrid-bonded (HB), so that the two semiconductor devices 300 are electrically interconnected through the pads 321. The hybrid bonding technology requires a smaller area of ​​the pads 321, so that the connection of the smaller pads 321 can be achieved, thereby improving the interconnection bandwidth between the two semiconductor devices 300.

[0070] During the connection process of the Cu pads 321, the two semiconductor devices 300 are first aligned with high precision and brought into initial contact to achieve hybrid bonding. Annealing is then performed. During the annealing process, the Cu pads 321 in the two semiconductor devices 300 expand due to heat and squeeze each other, thereby increasing the contact area between the Cu pads 321 in the two semiconductor devices 300 and even causing the Cu in the Cu pads 321 in the two semiconductor devices 300 to diffuse into each other, thereby achieving good ohmic contact between the Cu pads 321 in the two semiconductor devices 300.

[0071] The bonding result of the Cu pad 321 is affected by various factors, thereby affecting the subsequent electrical and reliability tests of the chip 100. For example, factors affecting the bonding result of the Cu pad 321 include: the surface roughness of the Cu pad, the surface oxide layer, and the proportion of nano-twinned copper and small-grain copper in the Cu pad 321.

[0072] In the related art, the following three methods can be used to achieve the bonding effect of the Cu pad 321.

[0073] Method 1: Before bonding, the Cu pads 321 are pre-treated with plasma to place the Cu in the pads 321 in an "excited state," thereby facilitating bonding of the Cu pads 321 in the two semiconductor devices 300. Method 1 requires high-vacuum plasma bombardment equipment, which is relatively expensive. Therefore, method 1 is costly.

[0074] Method 2: Before bonding the Cu pad 321, the bonding surface of the Cu pad 321 is cleaned with an acid solution to remove the oxide layer on the bonding surface of the Cu pad 321 and improve the interfacial energy of the Cu pad 321. It should be noted that the bonding surface of the Cu pad 321 refers to the surface of the Cu pad 321 facing away from the semiconductor structure 310. However, in Method 2, after the bonding surface of the Cu pad 321 is acid-cleaned, some gaps are introduced on the bonding surface of the Cu pad 321, thereby affecting the contact effect between the two Cu pads 321 and thus affecting the bonding effect of the Cu pad 321.

[0075] Method three, adjust the conditions of ECP to increase the proportion of nano-twin copper and small-grain copper. It should be noted that the Cu pad 321 can be formed by an ECP (electro-chemical-deposition) process. The proportion of nano-twin copper crystal orientation is approximately 40%, and the diffusion coefficient of nano-twin copper is relatively high. Therefore, the higher the proportion of nano-twin copper, the better the bonding effect of the two Cu pads 321. However, nano-twin copper usually appears concentrated at the edge of the Cu pad 321, and the proportion of nano-twin copper is usually less than 40% of the area of ​​the bonding surface of the Cu pad 321. Therefore, the proportion of nano-twin copper is low, and the bonding effect of the Cu pads 321 of the two semiconductor devices 300 is poor. The challenges faced in adjusting the conditions of ECP to achieve a larger area of ​​nano-twin copper on the bonding surface of a smaller Cu pad 321 are relatively large.

[0076] In summary, when the above-mentioned methods 1, 2 and 3 are applied to the hybrid bonding of the Cu pad 321 , the bonding effect of the Cu pad 321 is poor, thereby resulting in poor results of the electrical test and reliability test of the chip 100 .

[0077] Based on this, an embodiment of the present application provides a chip.

[0078] FIG3 is a structural diagram of a chip 100 provided in an embodiment of the present application.

[0079] Referring to FIG. 3 , chip 100 may include two semiconductor devices 300 . Semiconductor devices 300 include a semiconductor structure 310 and an interconnect layer 330 . Interconnect layer 330 is located on one side of semiconductor structure 310 . Interconnect layer 330 includes multiple spaced bonding portions 340 . Bonding portions 340 include bonding pads 341 and a metallic glass layer 342 . Bonding pads 341 are connected to semiconductor structure 310 , and metallic glass layer 342 covers a side of bonding pads 341 away from semiconductor structure 310 . The metallic glass layers 342 of the multiple bonding portions 340 of the two semiconductor devices 300 are bonded to form multiple bonding connections 400 .

[0080] 3 , the structure within the dotted frame indicated by number 400 is the bonding connection portion 400 , wherein the dotted frame indicated by number 400 is only for illustrating the position of the bonding connection portion 400 and does not represent the actual boundary of the bonding connection portion 400 .

[0081] In a semiconductor device 300, a semiconductor structure 310 and an interconnect layer 330 are stacked along a first direction F1. As shown in FIG3 , for the semiconductor device 300 located below, the direction indicated by arrow F1 is the first direction F1. The first direction F1 may be perpendicular to the interconnect layer 330. For the other semiconductor device 300, that is, the semiconductor device 300 located above, the first direction corresponding to the other semiconductor device 300 is opposite to the first direction F1 corresponding to the semiconductor device 300 located below.

[0082] In some examples, the semiconductor structure 310 may include a functional structure 311 , a spacer layer 312 , and a routing layer 313 .

[0083] The functional structure 311 may include functional devices, wherein the functional devices are used to implement the functions of the semiconductor device 300. In the chip 100, the functions of the two semiconductor devices 300 may be different.

[0084] For example, when the chip 100 is a NAND memory, the functional device of the functional structure 311 in one semiconductor device 300 can be a storage cell string, wherein the storage cell string can realize a storage function, while the functional device of the functional structure 311 in another semiconductor device 300 can be a logic circuit or a storage circuit.

[0085] The spacer layer 312 may be made of an insulating material. For example, the material of the spacer layer 312 may include oxide, such as SiO 2 (silicon dioxide). In addition, the material of the spacer layer 312 may also include SiOCN (silicon oxycarbon nitride).

[0086] The material of the routing layer 313 may include a conductive material, for example, a metal material. The routing layer 313 may be electrically connected to the functional devices of the functional structure 311. The electrical connection structure between the routing layer 313 and the functional devices is not shown in FIG3 .

[0087] The routing layer 313 may include a plurality of metal routing lines.

[0088] In some examples, the semiconductor structure 310 may further include a substrate (not shown in FIG. 3 ), wherein the substrate may be disposed on a side of the functional structure 311 facing away from the wiring layer 313 .

[0089] For example, the substrate can be made of silicon or other semiconductor materials. For example, the substrate includes a combination of one or more of the following materials: silicon, silicon carbide, and gallium nitride. Alternatively or additionally, the substrate can include other elemental semiconductor materials such as germanium. In some examples, the substrate is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some examples, the substrate is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0090] The plurality of bonding portions 340 of the interconnect layer 330 are spaced apart to insulate the plurality of bonding portions 340 from one another. The bonding pads 341 of the bonding portions 340 may be made of a metal material. For example, the material of the bonding pads 341 may include at least one of gold, silver, copper, aluminum, titanium, molybdenum, tungsten, nickel, and chromium. The material of the bonding pads 341 may be adjusted as needed and is not limited in the embodiments of the present application.

[0091] For example, the bonding pad 341 may be electrically connected to a metal trace in the trace layer 313 , wherein one metal trace may be electrically connected to at least one bonding pad 341 .

[0092] FIG4 is a structural diagram of a semiconductor device 300 provided in an embodiment of the present application.

[0093] Referring to FIG. 4 , the metallic glass layer 342 is conductive.

[0094] The metallic glass layer 342 may be located on a side of the bonding pad 341 away from the semiconductor structure 310 , and the metallic glass layer 342 may contact the bonding pad 341 , so that the metallic glass layer 342 may be electrically connected to the bonding pad 341 , and the metallic glass layer 342 may be electrically connected to the semiconductor structure through the bonding pad 341 .

[0095] 3 , after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, the metallic glass layers 342 of the two semiconductor devices 300 can be bonded to form a bonding connection 400. The two semiconductor devices 300 can include the same number of bonding portions 340. For example, each semiconductor device 300 can include N1 bonding portions 340. The metallic glass layers 342 of the N1 bonding portions 340 in one semiconductor device 300 can be bonded one-to-one with the metallic glass layers 342 of the N1 bonding portions 340 in the other semiconductor device 300, thereby forming N1 bonding connections 400. N1 is a positive integer greater than or equal to 1.

[0096] The semiconductor structure 310 in one semiconductor device 300 can be electrically connected to the bonding connection portion 400 through the bonding pad 341 of the semiconductor device 300, and the bonding connection portion 400 can be electrically connected to the semiconductor structure 310 of another semiconductor device 300 through the bonding pad 341 of another semiconductor device 300, so that the semiconductor structures 310 in the two semiconductor devices 300 can be electrically connected to exchange information.

[0097] The metallic glass layer 342 exhibits liquid-like properties at high temperatures. Specifically, when the metallic glass layer 342 is between the glass transition temperature and the crystallization temperature, its Young's modulus decreases, and its hardness also decreases, causing the metallic glass layer 342 to soften. At this point, the metallic glass layer 342 exhibits properties similar to a liquid. The temperature range between the glass transition temperature and the crystallization temperature is called the supercooled liquid phase. During this period, the metallic glass layer 342 has not reached its melting point and therefore has not melted.

[0098] During the bonding process of the metallic glass layers 342 of the bonding portions 340 of the two semiconductor devices 300, the metallic glass layers 342 of the bonding portions 340 of the two semiconductor devices 300 are aligned with high precision, hybrid bonded, and then annealed. During the annealing process, when the temperature reaches the supercooled liquid phase, the metallic glass layers 342 of the two semiconductor devices 300 can soften and form a liquid-like state, thereby generating a liquid-like flow effect, thereby reducing the gap at the contact interface of the metallic glass layers 342 of the two semiconductor devices 300, thereby improving the contact effect of the metallic glass layers 342 of the two semiconductor devices 300, thereby improving the bonding effect of the two semiconductor devices 300, and further improving the electrical connection quality of the two semiconductor devices 300, thereby improving the subsequent electrical testing and reliability testing of the chip 100.

[0099] In addition, before the metallic glass layers 342 of the two semiconductor devices 300 are bonded, an oxide layer may exist on the surface of the metallic glass layer 342. The metallic glass layer 342 is an amorphous structure (i.e., a crystalline structure) at a microscopic level. The metal atoms in the metallic glass layer 342 do not occupy the lowest energy sites, so the metal atoms are structurally in a higher energy state. In this case, the metallic glass layer 342 can activate the movement of local metal atomic clusters through ultrasonic vibration at room temperature. The movement of the atomic clusters can enable the atomic clusters to break through the oxide layer at the bonding interface of the metallic glass layer 342. At this time, the metallic glass layers 342 in the two semiconductor devices 300 can break through the surface oxide layer for bonding. Therefore, the bonding effect of the metallic glass layers 342 in the two semiconductor devices 300 is better. In addition, since the movement of the atomic clusters in the metallic glass layer 342 can break through the surface oxide layer at room temperature, the metallic glass layers 342 in the two semiconductor devices 300 can be bonded under room temperature conditions.

[0100] In addition, after the metallic glass layers 342 of the two semiconductor devices 300 are mixed and bonded, during the annealing process, the movement of the metal atomic clusters will be more intense, which is more conducive to the metal atomic clusters breaking through the oxide layer at the bonding interface of the metallic glass layer 342, thereby improving the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300.

[0101] In some examples, the annealing temperature may be greater than or equal to 250° C. and less than or equal to 450° C. In this case, the annealing temperature is relatively low, but the metallic glass layers 342 of the two semiconductor devices 300 can achieve a better bonding effect.

[0102] Illustratively, the annealing temperature may be approximately 300°C.

[0103] Next, a semiconductor device 300 will be introduced.

[0104] 4 , in this embodiment, the interconnect layer 330 further includes a dielectric layer 350 . The bonding portion 340 is embedded in the dielectric layer 350 . Here, the bonding pad 341 and the metallic glass layer 342 of the bonding portion 340 are both embedded in the dielectric layer 350 .

[0105] The projection of the bonding pad 341 in the second direction F2 partially covers the dielectric layer 350, while the projection of the metallic glass layer 342 in the second direction F2 partially covers the dielectric layer 350. The second direction F2 is parallel to the surface of the dielectric layer 350 facing away from the semiconductor structure 310. As shown in FIG4 , the direction indicated by arrow F2 is the second direction F2. It should be noted that there are multiple directions parallel to the surface of the dielectric layer 350 facing away from the semiconductor structure 310, and any direction parallel to the surface of the dielectric layer 350 facing away from the semiconductor structure 310 is the second direction F2.

[0106] The dielectric layer 350 exposes the first surface 3421 of the metallic glass layer 342 . The first surface 3421 is the surface of the metallic glass layer 342 facing away from the semiconductor structure 310 . The dielectric layer 350 does not cover the first surface 3421 of the metallic glass layer 342 .

[0107] The dielectric layer 350 includes a second surface 3501 facing away from the semiconductor structure 310 .

[0108] In some examples, the first surface 3421 of the metallic glass layer 342 may be coextensive with the second surface 3501 of the semiconductor structure 310 .

[0109] FIG5 is another structural diagram of a semiconductor device 300 provided in an embodiment of the present application.

[0110] Referring to FIG. 5 , in some other examples, the first surface 3421 is closer to the semiconductor structure 310 than the second surface 3501 .

[0111] The distance between the first surface 3421 and the semiconductor structure 310 in the first direction F1 is a first distance H1, and the distance between the second surface 3501 and the semiconductor structure 310 in the first direction F1 is a second distance H2. The first distance H1 is smaller than the second distance H2.

[0112] In this example, the metallic glass layer 342 is recessed within the dielectric layer 350. At this point, the first surface 3421 of the metallic glass layer 342 can enclose an expansion space with the dielectric layer 350. During the bonding process of the metallic glass layer 342 at the bonding portion 340 of the two semiconductor devices 300, the metallic glass layer 342 of the two semiconductor devices 300 can expand, and the volume of the metallic glass layer 342 can increase. By enclosing the expansion space between the first surface 3421 of the metallic glass layer 342 and the dielectric layer 350, the metallic glass layer 342 can expand into the expansion space. This prevents the metallic glass layer 342 from protruding excessively beyond the second surface 3501 of the dielectric layer 350 after expansion, which could result in a gap between the metallic glass layers 342 of the two semiconductor devices 300 after bonding. In this embodiment of the present application, by positioning the first surface 3421 closer to the semiconductor structure 310 than the second surface 3501, the gap between the two semiconductor devices 300 after bonding due to the expansion of the metallic glass layer 342 can be reduced.

[0113] In some embodiments, the distance between the first surface 3421 and the second surface 3501 in the first direction F1 is greater than or equal to and less than or equal to The first direction F1 is perpendicular to the first surface 3421. In other words, the depth of the expansion space in the first direction F1 is greater than or equal to and less than or equal to

[0114] The greater the distance between the first surface 3421 and the second surface 3501 in the first direction F1, the larger the volume of the expansion space; conversely, the smaller the distance between the first surface 3421 and the second surface 3501 in the first direction F1, the smaller the volume of the expansion space.

[0115] In the embodiment of the present application, the distance between the first surface 3421 and the second surface 3501 in the first direction F1 is greater than or equal to The metallic glass layer 342 can have sufficient expansion space to avoid the metallic glass layer 342 from protruding too much from the second surface 3501 after expansion due to lack of expansion space, resulting in a gap between the two semiconductor devices 300 after the metallic glass layer 342 is bonded, thereby affecting the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300. Therefore, by making the distance between the first surface 3421 and the second surface 3501 in the first direction F1 greater than or equal to The phenomenon of a gap between two semiconductor devices 300 after bonding via the metallic glass layer 342 can be reduced.

[0116] By making the distance between the first surface 3421 and the second surface 3501 in the first direction F1 less than or equal to This can prevent the expansion space of the metallic glass layer 342 from being too large, which would result in the metallic glass layer 342 being unable to fill the expansion space after expansion. If the expansion space is too large, a gap would exist between the metallic glass layers 342 of the two semiconductor devices 300 after expansion, thereby affecting the contact effect of the metallic glass layers 342 of the two semiconductor devices 300. Therefore, by making the distance between the first surface 3421 and the second surface 3501 in the first direction F1 less than or equal to The influence of the excessive expansion space on the bonding effect of the metallic glass layers 342 of the two semiconductor devices 300 can be reduced.

[0117] In some examples, the distance between the first surface 3421 and the second surface 3501 in the first direction F1 is equal to At this time, it is possible to avoid the metallic glass layer 342 from expanding too much out of the second surface 3501 due to insufficient expansion space, thereby affecting the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300. It is also possible to reduce the impact of insufficient contact between the metallic glass layers 342 of the two semiconductor devices 300 due to excessive expansion space, thereby affecting the bonding effect of the metallic glass layers 342 of the two semiconductor devices 300.

[0118] 5 , in some embodiments, the dielectric layer 350 includes a first isolation layer 351 , an interposer 352 , and a second isolation layer 353 sequentially stacked on the semiconductor structure 310 ; wherein the second surface 3501 of the dielectric layer 350 refers to the surface of the second isolation layer 353 facing away from the interposer 352 .

[0119] The first isolation layer 351 has an insulating property and may be made of an insulating material. For example, the material of the first isolation layer 351 may include oxide, such as SiO 2 (silicon dioxide). In addition, the material of the first isolation layer 351 may also include silicon oxynitride and carbon monoxide.

[0120] In some examples, the thickness of the first isolation layer 351 may be greater than or equal to Less than or equal to

[0121] For example, the thickness of the first isolation layer 351 may be equal to

[0122] The material of the interposer 352 may include SiN (silicon nitride).

[0123] In some examples, the thickness of the interposer 352 may be greater than or equal to and less than or equal to

[0124] For example, the thickness of the interposer 352 may be equal to

[0125] The second isolation layer 353 has an insulating property and may be made of an insulating material. For example, the material of the second isolation layer 353 may include oxide, such as SiO 2 (silicon dioxide). In addition, the material of the second isolation layer 353 may also include silicon oxynitride and carbon monoxide.

[0126] In some examples, the thickness of the second isolation layer 353 may be greater than or equal to Less than or equal to

[0127] For example, the thickness of the second isolation layer 353 may be equal to

[0128] The bonding pad 341 is embedded in the first isolation layer 351 , the intermediate layer 352 and the second isolation layer 353 , and the metallic glass layer 342 is embedded in the second isolation layer 353 .

[0129] The projection of the bonding pad 341 in the second direction F2 covers the first isolation layer 351, the interposer 352, and a portion of the second isolation layer 353, while the projection of the metallic glass layer 342 in the second direction F2 covers a portion of the second isolation layer 353. The second direction F2 is parallel to the second surface 3501.

[0130] Continuing to refer to FIG. 5 , in some embodiments, the ratio of the thickness H4 of the bonding pad 341 to the thickness H3 of the metallic glass layer 342 is greater than or equal to 10.55 and less than or equal to 158.9, that is, 10.55≤H4 / H3≤158.9.

[0131] Here, H4 / H3 is greater than or equal to 10.55, thereby preventing the thickness H3 of the metallic glass layer 342 from being too large. If the thickness of the metallic glass layer 342 is too large, the metallic glass layer 342 may protrude excessively from the second surface 3501 after expansion. In this case, after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, a gap may exist between the two semiconductor devices 300. Therefore, by ensuring that H4 / H3 is greater than or equal to 10.55, the phenomenon of a gap between the two semiconductor devices 300 caused by an excessive thickness of the metallic glass layer 342 can be reduced.

[0132] Furthermore, H4 / H3 is less than or equal to 158.9, thereby preventing the thickness H3 of the metallic glass layer 342 from being too small. If the thickness of the metallic glass layer 342 is too small, a gap may form between the metallic glass layers 342 of the two semiconductor devices 300 after expansion, thereby resulting in insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300. Therefore, by setting H4 / H3 to less than or equal to 158.9, the phenomenon of insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 caused by an excessively small thickness of the metallic glass layer 342 can be reduced.

[0133] For example, the ratio of the thickness H4 of the bonding pad 341 to the thickness H3 of the metallic glass layer 342 is greater than or equal to 21.67 and less than or equal to 26.

[0134] In some embodiments, the thickness H4 of the bonding pad 341 is greater than or equal to and less than or equal to

[0135] Wherein, by making the thickness H4 of the bonding pad 341 greater than or equal to This can prevent the thickness H4 of the bonding pad 341 from being too thin, thereby preventing the metallic glass layer 342 on the surface of the bonding pad 341 from being too thick. If the thickness of the metallic glass layer 342 is too large, the metallic glass layer 342 may bulge out too much from the second surface 3501 after expansion. In this case, after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, a gap may exist between the two semiconductor devices 300. Therefore, by making the thickness H4 of the bonding pad 341 greater than or equal to The phenomenon of a gap between the two semiconductor devices 300 caused by the excessive thickness of the metallic glass layer 342 can be reduced.

[0136] By making the thickness H4 of the bonding pad 341 less than or equal to It is possible to avoid the thickness H4 of the bonding pad 341 being too large, thereby preventing the metallic glass layer 342 on the surface of the bonding pad 341 from being too thin. If the thickness of the metallic glass layer 342 is too thin, a gap may exist between the metallic glass layers 342 of the two semiconductor devices 300 after expansion, thereby causing the metallic glass layers 342 of the two semiconductor devices 300 to be insufficiently bonded. Therefore, by making the thickness H4 of the bonding pad 341 less than or equal to This can reduce the problem of insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 due to the metallic glass layer 342 being too thin.

[0137] For example, the thickness H4 of the bonding pad 341 is equal to At this time, the gap between the two semiconductor devices 300 caused by the excessive thickness of the metallic glass layer 342 can be reduced, and the insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 caused by the excessive thickness of the metallic glass layer 342 can also be reduced.

[0138] 5 , in some embodiments, the bonding pad 341 includes a first portion 3411 and a second portion 3412 . One end of the first portion 3411 is connected to the semiconductor structure 310 . The second portion 3412 is connected to the other end of the first portion 3411 . For example, one end of the first portion 3411 may be electrically connected to the routing layer 313 .

[0139] In which, the cross-sectional area of ​​the first portion 3411 on the first reference plane is smaller than the cross-sectional area of ​​the second portion 3412 on the second reference plane, wherein the first reference plane and the second reference plane are both parallel to the surface of the metallic glass layer 342 facing away from the semiconductor structure 310, that is, the first reference plane and the second reference plane are both parallel to the first surface 3421 of the metallic glass layer 342, wherein the first reference plane passes through the first portion 3411, and the second reference plane passes through the second portion 3412.

[0140] The density of the metal wiring in the wiring layer 313 is relatively high. By providing the first portion 3411 with a smaller cross-sectional area in the bonding pad 341 , the first portion 3411 can be easily connected to the metal wiring.

[0141] The second portion 3412 has a larger cross-sectional area, and the metallic glass layer 342 is disposed on the side of the second portion 3412 facing away from the first portion 3411. The bearing surface of the second portion 3412 can thereby increase the area of ​​the metallic glass layer 342, thereby increasing the contact area between the metallic glass layers 342 in the two semiconductor devices 300, thereby improving the bonding effect of the metallic glass layers 342 in the two semiconductor devices 300. The bearing surface of the second portion 3412 refers to the surface of the second portion 3412 that is connected to the metallic glass layer 342.

[0142] The ratio of the thickness H5 of the first portion 3411 to the thickness H3 of the metallic glass layer 342 is greater than or equal to 5.55 and less than or equal to 75, that is, 5.55≤H5 / H3≤75.

[0143] Here, H5 / H3 is greater than or equal to 5.55, thereby preventing the thickness H3 of the metallic glass layer 342 from being too large. If the thickness of the metallic glass layer 342 is too large, the metallic glass layer 342 may protrude excessively from the second surface 3501 after expansion. In this case, a gap may be formed between the two semiconductor devices 300 after the metallic glass layers 342 of the two semiconductor devices 300 are bonded. Therefore, by ensuring that H5 / H3 is greater than or equal to 5.55, the phenomenon of a gap between the two semiconductor devices 300 caused by an excessive thickness of the metallic glass layer 342 can be reduced.

[0144] Furthermore, H5 / H3 is less than or equal to 75, thereby preventing the thickness H3 of the metallic glass layer 342 from being too small. If the thickness of the metallic glass layer 342 is too small, a gap may exist between the metallic glass layers 342 of the two semiconductor devices 300 after expansion, resulting in insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300. Therefore, by setting H5 / H3 to be less than or equal to 75, the phenomenon of insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 caused by the metallic glass layer 342 being too small can be reduced.

[0145] In some examples, the thickness H5 of the first portion 3411 is greater than or equal to Less than or equal to

[0146] For example, the thickness H5 of the first portion 3411 is equal to

[0147] The ratio of the thickness H6 of the second portion 3412 to the thickness H3 of the metallic glass layer 342 is greater than or equal to 5 and less than or equal to 83.9, that is, 5≤H6 / H3≤83.9.

[0148] Here, H6 / H3 is greater than or equal to 5, thereby preventing the thickness H3 of the metallic glass layer 342 from being too large. If the thickness of the metallic glass layer 342 is too large, the metallic glass layer 342 may protrude excessively from the second surface 3501 after expansion. In this case, a gap may be formed between the two semiconductor devices 300 after the metallic glass layers 342 of the two semiconductor devices 300 are bonded. Therefore, by setting H6 / H3 greater than or equal to 5, the phenomenon of a gap between the two semiconductor devices 300 caused by an excessive thickness of the metallic glass layer 342 can be reduced.

[0149] Furthermore, H6 / H3 is less than or equal to 83.9, thereby preventing the thickness H3 of the metallic glass layer 342 from being too small. If the thickness of the metallic glass layer 342 is too small, a gap may exist between the metallic glass layers 342 of the two semiconductor devices 300 after expansion, resulting in insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300. Therefore, by setting H6 / H3 to less than or equal to 83.9, the phenomenon of insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 caused by an excessively small thickness of the metallic glass layer 342 can be reduced.

[0150] In some examples, the thickness H6 of the second portion 3412 is greater than or equal to Less than or equal to

[0151] For example, the thickness H6 of the second portion 3412 is equal to

[0152] In some embodiments, the thickness H3 of the metallic glass layer 342 is greater than or equal to and less than or equal to

[0153] The thickness H3 of the metallic glass layer 342 is greater than or equal to This can prevent the thickness H3 of the metallic glass layer 342 from being too small. If the thickness of the metallic glass layer 342 is too small, a gap may exist between the metallic glass layers 342 of the two semiconductor devices 300 after expansion, thereby causing the metallic glass layers 342 of the two semiconductor devices 300 to be insufficiently bonded. Therefore, by making the thickness H3 of the metallic glass layer 342 greater than or equal to The phenomenon of insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 due to the metallic glass layer 342 being too thin can be reduced.

[0154] In addition, the thickness H3 of the metallic glass layer 342 is less than or equal to This can prevent the thickness H3 of the metallic glass layer 342 from being too large. If the thickness H3 of the metallic glass layer 342 is too large, the metallic glass layer 342 may bulge out too much from the second surface 3501 after expansion. In this case, after the metallic glass layers 342 of the two semiconductor devices 300 are bonded, a gap may be left between the two semiconductor devices 300. Therefore, by making the thickness H3 of the metallic glass layer 342 less than or equal to The phenomenon of a gap between the two semiconductor devices 300 caused by the excessive thickness of the metallic glass layer 342 can be reduced.

[0155] In some examples, the thickness H3 of the metallic glass layer 342 is greater than or equal to and less than or equal to At this time, the phenomenon of insufficient bonding of the metallic glass layers 342 of the two semiconductor devices 300 due to the thickness of the metallic glass layer 342 being too small can be reduced, and the phenomenon of a gap between the two semiconductor devices 300 due to the thickness of the metallic glass layer 342 being too large can also be reduced.

[0156] In some embodiments, the material of the metallic glass layer 342 includes CuZr (copper zirconium).

[0157] After the metallic glass layers 342 of the two semiconductor devices 300 are bonded, when the two semiconductor devices 300 are annealed, when the annealing temperature reaches the crystallization temperature of CuZr, the Cu atoms in the CuZr can crystallize, precipitating single-crystalline Cu. In other words, the bonding connection 400 formed after the metallic glass layers 342 of the two semiconductor devices 300 are bonded can include CuZr and single-crystalline Cu. The resistivity of single-crystalline Cu is lower than that of CuZr. Therefore, including CuZr in the material of the metallic glass layer 342 can reduce the resistivity of the bonding connection 400.

[0158] In some examples, the resistivity of the bond connection 400 is on the order of 10E−7Ωm.

[0159] In some examples, the resistance of the metal bond connection 400 is approximately 0.0002Ω.

[0160] In some examples, the material of the metallic glass layer 342 includes CuXZr100-X, where the ratio of Cu atoms to Zr atoms in the metallic glass layer 342 is X:100-X, where X is greater than or equal to 30 and less than or equal to 90.

[0161] By setting X to be greater than or equal to 30, it is possible to prevent the proportion of Cu atoms in the metallic glass layer 342 from being too small, thereby preventing a small amount of single-crystal Cu from being formed. The smaller the proportion of single-crystal Cu, the greater the resistivity of the bond connection 400 formed after the metallic glass layers 342 in the two semiconductor devices 300 are bonded. Therefore, by setting X to be greater than or equal to 30, the problem of excessive resistivity in the bond connection 400 caused by an excessively small proportion of Cu atoms can be reduced.

[0162] In addition, by making X greater than or equal to 90, it is possible to avoid the proportion of Cu atoms in the metallic glass layer 342 being too large, thereby causing the properties of the metallic glass layer 342 to be close to the bonding pad 341 made of Cu, thereby affecting the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300.

[0163] For example, X=85, in this case, 100-X=15. In this case, the material of the metallic glass layer 342 includes Cu85Zr15.

[0164] In some of the above embodiments, the semiconductor device 300 provided in the embodiments of the present application is introduced in conjunction with FIG. 4 and FIG. 5 . Next, the chip 100 formed by bonding two semiconductor devices 300 is introduced.

[0165] Referring back to FIG. 3 , in some embodiments, in the semiconductor device 300 , the bonding pad 341 of the bonding portion 340 has a recess on a surface facing away from the semiconductor structure 310 of the semiconductor device 300 , and a portion of the bonding connection portion 400 is filled in the recess.

[0166] Among them, the surface of the bonding pad 341 facing away from the semiconductor structure 310 is a non-smooth surface with a depression thereon. During the bonding process of the metallic glass layer 342 of the two semiconductor devices 300, the temperature of the metallic glass layer 342 will increase. When the temperature reaches the supercooled liquid phase, the metallic glass layer 342 will be in a liquid-like state. Therefore, the metallic glass layer 342 can be fluid, and then the metallic glass layer 342 can fill the depression on the surface of the bonding pad 341 facing away from the semiconductor structure 310, thereby enhancing the connection effect between the metallic glass layer 342 (that is, the bonding connection portion 400) and the bonding pad 341.

[0167] Next, a method for manufacturing the semiconductor device 300 is introduced.

[0168] FIG6 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0169] Please refer to FIG. 6 , the method for manufacturing a semiconductor device includes the following steps S1 - S4 .

[0170] S1. Forming a dielectric layer on the surface of the semiconductor structure.

[0171] The structure of the semiconductor structure 310 has been introduced in some of the above embodiments and will not be described in detail here.

[0172] 7 to 14 are diagrams showing the steps of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0173] 7 to 10 , in some examples, the dielectric layer 350 may include a first isolation layer 351, an intermediary layer 352, and a second isolation layer 353. The materials of the first isolation layer 351, the intermediary layer 352, and the second isolation layer 353 have been described in some of the above embodiments and are not further described here.

[0174] When forming the dielectric layer 350 , a first isolation layer 351 may first be formed on the surface of the wiring layer 313 of the semiconductor structure 310 .

[0175] Next, an interposer 352 is formed on a surface of the first isolation layer 351 facing away from the semiconductor structure 310 .

[0176] Then, a second isolation layer 353 is formed on a surface of the interposer 352 facing away from the semiconductor structure 310 .

[0177] The first isolation layer 351, the intermediate layer 352, and the second isolation layer 353 may be formed by a thin film deposition process. The thin film deposition process may include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of one or more of atomic layer deposition (ALD) and electrochemical deposition (ECP) processes.

[0178] S2. Form a plurality of contact holes on the dielectric layer.

[0179] Referring to FIG. 10 , in some examples, contact hole 360 ​​may be a stepped hole. For example, contact hole 360 ​​may include a first section hole 361 and a second section hole 362 , wherein first section hole 361 and second section hole 362 are connected and arranged sequentially along first direction F1. First section hole 361 penetrates first isolation layer 351 , and second section hole 362 penetrates interposer 352 and second isolation layer 353 . First section hole 361 exposes routing layer 313 of semiconductor structure 310 .

[0180] The cross-sectional area of ​​the first hole section 361 is smaller than the cross-sectional area of ​​the second hole section 362. The cross-sectional area of ​​the first hole section 361 refers to the cross-sectional area of ​​the first hole section 361 on the first reference plane. The cross-sectional area of ​​the second hole section 362 refers to the cross-sectional area of ​​the second hole section 362 on the second reference plane. Both the first reference plane and the second reference plane are perpendicular to the first direction F1. The first reference plane passes through the first hole section 361, and the second reference plane passes through the second hole section 362.

[0181] Wherein, step S2 may include the following steps: S21 to S24.

[0182] 7 , S21 , a plurality of first-stage holes 3601 are formed on the dielectric layer 350 , the first-stage holes 3601 penetrating the first isolation layer 351 , the interlayer 352 , and the second isolation layer 353 . The cross-sectional area of ​​the first-stage holes 3601 may be equal to the cross-sectional area of ​​the first-stage holes 361 .

[0183] In some examples, in step S21 , the first-stage hole 3601 may be formed by an etching process.

[0184] Please refer to FIG. 8 , S22 , filling a plurality of first-stage holes 3601 with a sacrificial medium 3602 .

[0185] Please refer to Figure 9, S23, a plurality of second-stage holes 3603 are formed on the dielectric layer 350, and the second-stage holes 3603 penetrate the intermediate layer 352 and the second isolation layer 353. In the process of forming the second-stage holes 3603, the sacrificial dielectric 3602 in the intermediate layer 352 and the sacrificial dielectric 3602 in the second isolation layer 353 are removed.

[0186] Among them, the second stage hole 3603 can be used as the second section hole 362.

[0187] For example, in step S23, the second-stage hole 3603 may be formed by an etching process. In step S23, the sacrificial dielectric 3602 located in the first isolation layer 351 is retained.

[0188] 10 , S24 , the sacrificial dielectric 3602 (as shown in FIG9 ) in the first isolation layer 351 is removed to form the contact hole 360. For example, in step S24 , the sacrificial dielectric 3602 in the first isolation layer 351 may be removed by an etching process.

[0189] A plurality of contact holes are formed through the above steps S21 to S24 .

[0190] 10 is a stepped hole, but in other examples, the cross-sectional area of ​​the contact hole 360 ​​may remain constant along the first direction F1 , or the cross-sectional area of ​​the contact hole 360 ​​may gradually increase along the first direction F1 .

[0191] S3. Form a bonding pad in the contact hole.

[0192] 12 , the bonding pad 341 includes a first portion 3411 and a second portion 3412. One end of the first portion 3411 is connected to the semiconductor structure 310. The second portion 3412 is connected to the other end of the first portion 3411. The first portion 3411 and the second portion 3412 can be formed in the same process.

[0193] The structures of the first part 3411 and the second part 3412 have been introduced in some of the above embodiments and will not be repeated here.

[0194] FIG15 is another flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0195] Please refer to FIG15 , step S3 may include the following steps S31 and S32:

[0196] S31 . Depositing a metal material to fill the contact hole with the metal material.

[0197] Referring to FIG. 11 , in step S31 , the metal material 371 may not only fill the contact hole 360 ​​, but may also cover the surface of the dielectric layer 350 facing away from the semiconductor structure 310 , ie, the second surface 3501 .

[0198] The metal material may include at least one of gold, silver, copper, aluminum, titanium, molybdenum, tungsten, nickel and chromium.

[0199] In step S31, the metal material 371 may be formed by a thin film deposition process to fill the contact hole 360. For example, the thin film deposition process may include one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and electrochemical deposition.

[0200] In step S31 , the metal material 371 may completely fill the contact hole 360 ​​, and a portion of the metal material may protrude from the contact hole 360 ​​.

[0201] S32, removing the metal material at the top of the contact hole to form a first recess, and the metal material remaining in the contact hole is a bonding pad; the top is the area of ​​the contact hole away from the semiconductor structure.

[0202] Please refer to Figure 12. In step S32, in addition to removing the metal material 371 located on the top of the contact hole 360, the metal material 371 located on the second surface 3501 of the dielectric layer 350 is also removed. At this time, the metal material remaining in the contact hole 360 ​​can be used as the bonding pad 341.

[0203] The metal material on the second surface 3501 of the dielectric layer 350 and the metal material on the top of the contact hole 360 ​​may be removed by a grinding process.

[0204] For example, the polishing process may include a CMP (chemical mechanical polishing) process.

[0205] After step S32, bonding pad 341 is formed. Bonding pad 341 includes a third surface 3413 facing away from semiconductor structure 310, while dielectric layer 350 includes a second surface 3501 facing away from semiconductor structure 310. After step S32, third surface 3413 is closer to semiconductor structure 310 than second surface 3501. Third surface 3413 of bonding pad 341 and the top area of ​​contact hole 360 ​​form a first recess 3604. First recess 3604 is part of contact hole 360.

[0206] In step S32, a first recess 3604 may be formed to provide a space for the metallic glass layer 342. Furthermore, after removing the metal material at the top of the contact hole, a bonding pad 341 may be formed. In this case, the side of the bonding pad 341 facing away from the semiconductor structure 310 may have a flat surface.

[0207] The metal material 371 on the second surface 3501 of the dielectric layer 350 can be removed by a grinding process first, and then the metal material 371 at the top of the contact hole 360 ​​can be removed. When removing the metal material 371 at the top of the contact hole 360, the depth of the first recess 3604 can be controlled by adjusting the grinding pressure and grinding time during the grinding process.

[0208] In some examples, the depth of the first recess 3604 in the first direction F1 is greater than or equal to and less than or equal to

[0209] Wherein, by making the depth of the first recess 3604 in the first direction F1 greater than or equal to This can prevent the first recess 3604 from being too shallow, which would cause the metallic glass layer 342 disposed in the first recess 3604 to be too thin, thereby ensuring that the metallic glass layer 342 has sufficient thickness. However, if the metallic glass layer 342 is too thin, a gap may exist between the metallic glass layer 342 and the metallic glass layer 342 in another semiconductor device 300 after expansion, thereby causing insufficient bonding between the metallic glass layers 342 in the two semiconductor devices 300, affecting the bonding effect of the metallic glass layers 342 in the two semiconductor devices 300, and further affecting the electrical connection effect of the metallic glass layers 342 in the two semiconductor devices 300.

[0210] By making the depth of the first recess 3604 in the first direction F1 less than or equal to This prevents the first recess 3604 from being too deep, which would result in the metallic glass layer 342 being too thick within the first recess 3604. However, if the metallic glass layer 342 is too thick, it may easily cause the metallic glass layer 342 to protrude excessively from the second surface 3501 of the dielectric layer 350 after expansion. This may result in a gap between the metallic glass layers 342 of the two semiconductor devices 300 after bonding, thus affecting the connection between the two semiconductor devices 300. Furthermore, an excessively thick metallic glass layer 342 may result in material waste.

[0211] For example, the depth of the first recess 3604 in the first direction F1 is equal to At this time, the metallic glass layer 342 can have a sufficient thickness to ensure the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300, and it can also prevent the metallic glass layer 342 from being too thick, causing the metallic glass layer 342 to expand and flow between the dielectric layers 350 of the two semiconductor devices 300, thereby affecting the connection effect between the metallic glass layers 342 of the two semiconductor devices 300.

[0212] S4. Forming a metallic glass layer in the contact hole, wherein the metallic glass layer overlaps and contacts the bonding pad.

[0213] After step S3, step S4 can be performed, wherein, referring to FIG. 14 , a metallic glass layer 342 can be formed in the contact hole 360 ​​and on the surface of the bonding pad 341 facing away from the semiconductor structure 310. At this time, the metallic glass layer 342 contacts the bonding pad 341, and the metallic glass layer 342 can be electrically connected to the bonding pad 341.

[0214] In summary, the semiconductor device 300 is prepared through the above steps S1 to S4. The metallic glass layer 342 in the semiconductor device 300 prepared through the above steps S1 to S4 has liquid-like properties when the temperature reaches or approaches the supercooled liquid phase region. During the bonding process of the metallic glass layer 342 of the bonding portion 340 in the two semiconductor devices 300, the metallic glass layers 342 in the two semiconductor devices 300 are aligned with high precision and initially mixed and bonded, and then annealed. During the annealing process, when the temperature reaches or approaches the supercooled liquid phase region, the metallic glass layers 342 of the two semiconductor devices 300 can soften and form a liquid-like state, thereby producing an effect similar to liquid flow, thereby reducing the gap at the contact interface of the metallic glass layers 342 of the two semiconductor devices 300, and further improving the contact effect of the metallic glass layers 342 of the two semiconductor devices 300, thereby improving the bonding effect of the two semiconductor devices 300, and thus improving the subsequent electrical testing and reliability testing of the chip 100.

[0215] Furthermore, the metallic glass layer 342 has an amorphous structure (i.e., no crystalline structure) at a microscopic level. The metal atoms in the metallic glass layer 342 do not occupy the lowest energy sites, so the metal atoms are structurally in a higher energy state. In this case, the metallic glass layer 342 can activate the movement of localized metal atomic clusters through ultrasonic vibration at room temperature. The movement of the atomic clusters can allow the atomic clusters to break through the oxide layer at the bonding interface of the metallic glass layer 342, thereby achieving a better bonding effect between the metallic glass layers 342 of the two semiconductor devices 300. Furthermore, the metallic glass layers 342 of the two semiconductor devices 300 can be bonded at room temperature.

[0216] In addition, during the annealing process, the movement of the metal atomic clusters will be more intense, which is more conducive to the metal atomic clusters breaking through the oxide layer at the bonding interface of the metallic glass layer 342, thereby improving the bonding effect of the metallic glass layer 342 in the two semiconductor devices 300.

[0217] Continuing to refer to FIG. 15 , in some examples, when the method for manufacturing a semiconductor device includes steps S31 and S32 , step S4 may include the following step S41 .

[0218] S41 , forming a metallic glass layer in the first recess.

[0219] In step S32 , the side of the bonding pad 341 facing away from the semiconductor structure 310 has a flat surface, which can provide a flat surface for forming the metallic glass layer, and is beneficial for improving the thickness uniformity of the metallic glass layer 342 .

[0220] In some examples, referring back to FIG. 4 , the thickness of metallic glass layer 342 may be equal to the depth of first recess 3604 , while in other examples, referring back to FIG. 14 , the thickness of metallic glass layer 342 may be less than the depth of first recess 3604 (as shown in FIG. 12 ).

[0221] Next, the step S41 in the method for manufacturing a semiconductor device is described by taking the case where the thickness of the metallic glass layer 342 is smaller than the depth of the first recess 3604 as an example.

[0222] FIG16 is another flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0223] Referring to FIG. 16 , in some examples, step S41 may include the following steps S411 to S412 .

[0224] S411 , depositing a metallic glass material, where the metallic glass material fills the first recess and covers the surface of the dielectric layer facing away from the semiconductor structure.

[0225] Referring to FIG. 13 , in step S411 , the metallic glass material 3420 may be formed in the first recess 3604 (as shown in FIG. 12 ) and on the second surface 3501 of the dielectric layer 350 by a thin film deposition process.

[0226] For example, the metallic glass material 3420 may include CuZr. When the metallic glass material 3420 is formed in the first recess 3604 (as shown in FIG. 12 ) and the second surface 3501 of the dielectric layer 350 by a PVD process, an alloy target including CuZr may be pre-formed, and then the metallic glass material 3420 may be deposited on the first recess 3604 and the second surface 3501 by single-target sputtering.

[0227] The deposition time of the metallic glass material 3420 is relatively short, and the deposition of the metallic glass material 3420 of one semiconductor device 300 can be completed in about 10 minutes. Therefore, the time cost of using the metallic glass layer 342 to connect the semiconductor device 300 is relatively low.

[0228] In the example shown in FIG13 , in step S411, the metallic glass material 3420 may fill the first recess 3604 and protrude beyond the first recess 3604. At this time, the deposition thickness of the metallic glass material 3420 corresponding to the first recess 3604 is greater than the depth of the first recess 3604. The metallic glass material 3420 corresponding to the first recess 3604 refers to the thickness of the metallic glass material 3420 covered by the first recess 3604 in the first direction F1.

[0229] For example, the difference between the deposition thickness of the metallic glass material 3420 corresponding to the first recess 3604 and the depth of the first recess 3604 may be equal to

[0230] In some examples, the deposition thickness of metallic glass material 3420 corresponding to first recess 3604 is greater than or equal to Less than or equal to

[0231] In other examples, the metallic glass material 3420 may only fill a portion of the first recess 3604. In this case, a portion of the metallic glass material 3420 may be located in the bottom region of the first recess 3604, another portion of the metallic glass material 3420 may cover the sidewalls of the top region of the first recess 3604, and another portion of the metallic glass material 3420 may cover the second surface 3501 of the dielectric layer 350.

[0232] S412, removing the metallic glass material covering the dielectric layer and the metallic glass material located at the top of the first recess, and the metallic glass material remaining in the first recess is a metallic glass layer, wherein the top of the first recess is a region of the first recess away from the semiconductor structure.

[0233] 14 , in step S412, the metallic glass material 3420 on the second surface 3501 of the dielectric layer 350 and the metallic glass material 3420 at the top of the first recess 3604 are removed, while the metallic glass material 3420 at the bottom of the first recess 3604 serves as the metallic glass layer 342. At this point, the first surface 3421 of the metallic glass layer 342 is closer to the semiconductor structure 310 than the second surface 3501.

[0234] At this time, the metallic glass layer 342 is recessed into the dielectric layer 350. The first surface 3421 of the metallic glass layer 342 can enclose an expansion space with the dielectric layer 350. During the bonding process of the metallic glass layer 342 at the bonding portion 340 of the two semiconductor devices 300, the metallic glass layer 342 of the two semiconductor devices 300 can expand, increasing the volume of the metallic glass layer 342. By enclosing the expansion space with the first surface 3421 of the metallic glass layer 342 and the dielectric layer 350, the metallic glass layer 342 can expand into the expansion space, thereby preventing the metallic glass layer 342 from protruding excessively from the second surface 3501 of the dielectric layer 350 after expansion. In this case, a gap may exist between the two semiconductor devices 300 after the metallic glass layers 342 of the two semiconductor devices 300 are bonded. Therefore, by making the first surface 3421 closer to the semiconductor structure 310 than the second surface 3501 , the phenomenon of a gap between the two semiconductor devices 300 being bonded due to expansion of the metallic glass layer 342 can be reduced.

[0235] For example, in step S412 , the metallic glass material 3420 on the second surface 3501 of the dielectric layer 350 and the metallic glass material 3420 on the top of the first recess 3604 may be removed by a grinding process.

[0236] For example, the polishing process may include a CMP (chemical mechanical polishing) process.

[0237] The metallic glass material 3420 on the second surface 3501 of the dielectric layer 350 can be first removed by a grinding process, and then the metallic glass material 3420 at the top of the first recess 3604 can be removed. When removing the metallic glass material 3420 at the top of the first recess 3604, the distance between the first surface 3421 and the second surface 3501 of the metallic glass layer 342 in the first direction F1 can be controlled by adjusting the grinding pressure and grinding time during the grinding process.

[0238] In some examples, in step S412, the distance between the first surface 3421 of the metallic glass layer 342 and the second surface 3501 of the dielectric layer 350 in the first direction F1 is greater than or equal to Less than or equal to

[0239] For example, the distance between the first surface 3421 of the metallic glass layer 342 and the second surface 3501 of the dielectric layer 350 in the first direction F1 is equal to

[0240] In step S412 , the metallic glass material 3420 on the second surface 3501 of the dielectric layer 350 and the metallic glass material 3420 on the top of the first recess 3604 are removed, and the metallic glass layer 342 occupies part of the space of the first recess 3604 .

[0241] FIG17 is another flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0242] Please refer to FIG. 17 . In some other examples, step S41 may include steps S411 and S413 , wherein step S413 may be performed after step S411 .

[0243] S413 , removing the metallic glass material on the surface of the dielectric layer facing away from the semiconductor structure, and retaining the metallic glass material in the first recess to form a metallic glass layer.

[0244] The metallic glass layer 342 formed in step S413 may occupy the entire space of the first recess 3604 (as shown in FIG12 ). In this case, the structure of the semiconductor device 300 may be shown in FIG4 . For example, in step S413 , the metallic glass material 3420 on the second surface 3501 of the dielectric layer 350 may be removed by a grinding process. For example, the grinding process may include a CMP (chemical mechanical polish) process.

[0245] In the embodiments shown in Figures 7 to 14 , during step S3, when forming the bonding pad in the contact hole, the bonding pad 341 can directly contact the sidewall of the contact hole 360. In other examples, before forming the bonding pad 341, a barrier layer and a seed layer can be formed in the contact hole 360. In this case, the bonding pad 341 can be formed by electrochemical deposition.

[0246] The following describes a method for preparing the bonding pad 341 by taking the electrochemical deposition process as an example.

[0247] Figure 18 is another flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application; Figures 19 to 24 are step diagrams of the method for preparing a semiconductor device provided in an embodiment of the present application.

[0248] Please refer to FIG. 18 , step S3 may include the following steps S28 and S29 .

[0249] S28. Form a barrier layer in the contact hole.

[0250] 19 , in step S28 , the barrier layer 372 may be formed by a thin film deposition process. In step S28 , the barrier layer 372 also covers the surface of the dielectric layer 350 facing away from the semiconductor structure 310 .

[0251] In some examples, the barrier layer 372 may include Ta (tantalum) and tantalum nitride. The barrier layer 372 is conductive, and thus, the barrier layer 372 may be conductively connected to the semiconductor structure 310 .

[0252] S29. Form a seed layer in the contact hole.

[0253] 20 , in step S29 , the seed layer 373 may be formed by physical vapor deposition. In step S29 , the seed layer 373 also covers the surface of the barrier layer 372 facing away from the semiconductor structure 310 .

[0254] In some examples, the seed layer 373 may include Cu, which is a conductive material, and thus the seed layer 373 may be conductively connected to the barrier layer 372 .

[0255] After step S29 , step S3 may be performed to form a bonding pad in the contact hole.

[0256] It should be noted that the bonding pad 341 is formed in the contact hole 360. In this case, the bonding pad 341 can be spaced apart from the hole wall of the contact hole 360. For example, a barrier layer 372 and a seed layer 373 are spaced apart between the bonding pad 341 and the hole wall of the contact hole 360. The barrier layer 372 can prevent Cu in the bonding pad 341 from diffusing into the interconnect layer 330, thereby ensuring the insulation of the interconnect layer 330. The formation of the seed layer 373 in the contact hole 360 ​​can facilitate the bonding of the bonding pad 341.

[0257] Wherein, step S3 may include the following steps S33 and S34.

[0258] S33, depositing metal material to fill the contact hole with the metal material.

[0259] Referring to FIG. 21 , in step S33, the metal material may not only fill the contact hole 360 ​​but may also cover the second surface 3501 of the dielectric layer 350. In the embodiment of the present application, when the metal material 371 covers the second surface 3501, the metal material 371 may directly contact the second surface 3501. In this case, the positional relationship between the metal material 371 and the second surface 3501 may be as shown in FIG. 11 Alternatively, the metal material 371 may be spaced apart from the second surface 3501. In this case, a barrier layer 372 and a seed layer 373 are spaced apart from the metal material 371 and the second surface 3501.

[0260] The deposition process of the metal material 371 has been introduced in some of the above embodiments and will not be repeated here.

[0261] S34, removing the metal material at the top of the contact hole and the seed layer at the top of the contact hole to form a second recess, and the metal material remaining in the contact hole is a bonding pad; the top of the contact hole is the area at one end of the contact hole away from the semiconductor structure.

[0262] Referring to FIG. 22 , in step S34, in addition to removing the metal material 371 at the top of the contact hole 360, the metal material 371 on the surface of the seed layer 373 facing away from the second surface 3501 is also removed. Furthermore, the seed layer 373 on the surface of the barrier layer 372 facing away from the second surface 3501 and the seed layer 373 at the top of the contact hole 360 ​​are also removed. The metal material 371 remaining in the contact hole 360 ​​can serve as the bonding pad 341.

[0263] At this point, the bonding pad 341, the seed layer 373 in the contact hole 360, and the barrier layer 372 in the contact hole 360 ​​can enclose a second recess 3605. In FIG22 , the dotted box indicated by the reference numeral 3605 is the location of the second recess 3605. It should be noted that the dotted box indicated by the reference numeral 3605 is only used to indicate the location of the second recess 3605 and does not represent the actual boundary of the second recess 3605.

[0264] After step S34 , step S4 may be performed to form a metallic glass layer in the contact hole, where the metallic glass layer overlaps and contacts the bonding pad.

[0265] In some examples, step S4 may include S414 and S415.

[0266] S414 , depositing a metallic glass material to fill the second recess with the metallic glass material.

[0267] Referring to FIG. 23 , in step S414 , the metallic glass material 3420 may be filled in the second recess 3605 (as shown in FIG. 22 ). At this time, the metallic glass layer 342O may completely fill the second recess 3605 and protrude from the second recess 3605 .

[0268] In addition, the metallic glass material 3420 may also cover the surface of the barrier layer 372 facing away from the second surface 3501 of the dielectric layer 350 .

[0269] S415 , removing the metallic glass material on the top of the second recess, and the metallic glass material remaining in the second recess is a metallic glass layer, wherein the top of the second recess is a region of the second recess facing away from the semiconductor structure.

[0270] Referring to FIG. 24 , the metallic glass layer 342 formed in step S415 may occupy part of the space of the second recess 3605 (as shown in FIG. 22 ). Therefore, the thickness of the metallic glass layer 342 is less than the depth of the second recess 3605 . At this time, the first surface 3421 of the metallic glass layer 342 is closer to the semiconductor structure 310 than the second surface 3501 .

[0271] The metallic glass layer 342 is recessed within the dielectric layer 350. At this point, the first surface 3421 of the metallic glass layer 342 can enclose an expansion space with the dielectric layer 350. During the bonding process of the metallic glass layer 342 at the bonding portion 340 of the two semiconductor devices 300, the metallic glass layer 342 of the two semiconductor devices 300 can expand, increasing its volume. By enclosing the expansion space between the first surface 3421 of the metallic glass layer 342 and the dielectric layer 350, the metallic glass layer 342 can expand into the expansion space, thereby preventing the metallic glass layer 342 from protruding excessively beyond the second surface 3501 of the dielectric layer 350 after expansion. This could potentially create a gap between the two semiconductor devices 300 after the metallic glass layers 342 of the two semiconductor devices 300 are bonded. Therefore, by making the first surface 3421 closer to the semiconductor structure 310 than the second surface 3501 , the phenomenon of a gap between the two semiconductor devices 300 being bonded due to expansion of the metallic glass layer 342 can be reduced.

[0272] In some examples, the method for preparing a semiconductor device may further include: S416 , removing the barrier layer 372 on the second surface.

[0273] 24 , after the barrier layer 372 on the second surface 3501 is removed, the second surface 3501 of the dielectric layer 350 is exposed. The barrier layer 372 can be electrically connected to the metallic glass layer 342 via the seed layer 373. Therefore, after the barrier layer 372 on the second surface 3501 is removed, electrical connection between the multiple metallic glass layers 342 via the barrier layer 372 can be avoided.

[0274] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: semiconductor structures and interconnect layers; The interconnection layer is located on one side of the semiconductor structure, and the interconnection layer includes a plurality of bonding parts arranged at intervals, and the bonding parts include bonding pads and a metallic glass layer, wherein the bonding pads are connected to the semiconductor structure, and the metallic glass layer covers a side of the bonding pads away from the semiconductor structure.

2. The semiconductor device according to claim 1, wherein: The interconnection layer further comprises: a dielectric layer, the bonding portion is embedded in the dielectric layer, the dielectric layer exposes a first surface of the metallic glass layer, and the first surface is a surface of the metallic glass layer away from the semiconductor structure; The dielectric layer includes a second surface facing away from the semiconductor structure; The first surface is closer to the semiconductor structure than the second surface.

3. The semiconductor device according to claim 2, characterized in that The distance between the first surface and the second surface in the first direction is greater than or equal to and less than or equal to Wherein, the first direction is perpendicular to the first surface.

4. The semiconductor device according to claim 2 or 3, characterized in that: The dielectric layer includes a first isolation layer, an intermediate layer, and a second isolation layer sequentially stacked on the semiconductor structure; The bonding pad is embedded in the first isolation layer, the intermediate layer and the second isolation layer, and the metallic glass layer is embedded in the second isolation layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: A ratio of the thickness of the bonding pad to the thickness of the metallic glass layer is greater than or equal to 10.55 and less than or equal to 158.

9.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The bonding pad comprises a first portion and a second portion, one end of the first portion is connected to the semiconductor structure, the second portion is connected to the other end of the first portion, a cross-sectional area of ​​the first portion on a first reference plane is smaller than a cross-sectional area of ​​the second portion on a second reference plane, wherein the first reference plane and the second reference plane are both parallel to a surface of the metallic glass layer facing away from the semiconductor structure; Wherein, the ratio of the thickness of the first portion to the thickness of the metallic glass layer is greater than or equal to 5.55 and less than or equal to 75; A ratio of a thickness of the second portion to a thickness of the metallic glass layer is greater than or equal to 5 and less than or equal to 83.

9.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The thickness of the metallic glass layer is greater than or equal to and less than or equal to 8. The semiconductor device according to any one of claims 1 to 7, characterized in that: The thickness of the bonding pad is greater than or equal to and less than or equal to 9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The material of the metallic glass layer includes CuZr.

10. A chip, characterized in that: include: Two semiconductor devices according to any one of claims 1 to 9, wherein the metallic glass layers of the plurality of bonding portions of the two semiconductor devices are bonded to form a plurality of bonding connection portions.

11. The chip according to claim 10, characterized in that: In the semiconductor device, a bonding pad of the bonding portion has a recess on a surface facing away from the semiconductor structure of the semiconductor device, and a portion of the bonding connection portion is filled in the recess.

12. The chip according to claim 10 or 11, characterized in that: The material of the bonding connection includes CuZr and single crystal Cu.

13. An electronic device, characterized in that: include: Circuit boards; The chip according to any one of claims 10 to 12, wherein the chip is arranged on the circuit board.

14. A method for preparing a semiconductor device, characterized in that: include: forming a dielectric layer on a surface of the semiconductor structure; forming a plurality of contact holes on the dielectric layer; forming a bonding pad in the contact hole; A metallic glass layer is formed in the contact hole, the metallic glass layer overlapping and contacting the bonding pad.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: The step of forming bonding pads in the plurality of contact holes comprises: Depositing a metal material, wherein the metal material fills the contact hole; The metal material at the top of the contact hole is removed to form a first recess, and the metal material remaining in the contact hole is the bonding pad; the top of the contact hole is a region of the contact hole away from one end of the semiconductor structure; The forming of a metallic glass layer in the contact hole comprises: The metallic glass layer is formed in the first recess.

16. The method for preparing a semiconductor device according to claim 15, characterized in that: The forming of the metallic glass layer in the first recess comprises: Depositing a metallic glass material, wherein the metallic glass material fills the first recess and covers a surface of the dielectric layer facing away from the semiconductor structure; The metallic glass material on the surface of the dielectric layer facing away from the semiconductor structure is removed, and the metallic glass material in the first recess is retained to form the metallic glass layer.

17. The method for preparing a semiconductor device according to claim 15, characterized in that: The forming of the metallic glass layer in the first recess comprises: Depositing a metallic glass material, wherein the metallic glass material fills the first recess and covers a surface of the dielectric layer facing away from the semiconductor structure; The metallic glass material on the surface of the dielectric layer facing away from the semiconductor structure and the metallic glass material located at the top of the first recess are removed, and the metallic glass material retained in the first recess is the metallic glass layer, wherein the top of the first recess is the region at one end of the first recess facing away from the semiconductor structure.

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