Display panel and display apparatus

Abstract

A display panel, comprising a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines and a first shading structure. The substrate comprises a display area and a first frame area located on at least one side of the display area. The first frame area comprises: a first fan-out area and a bending area which are successively arranged in a direction away from the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area, the plurality of data lines being electrically connected to the plurality of sub-pixels. The plurality of data fan-out lines are located in the first fan-out area, are electrically connected to the plurality of data lines, and are configured to provide data signals for the plurality of sub-pixels in the display area. The first shading structure is located in the first fan-out area, the first shading structure being located on the side of the plurality of data fan-out lines away from the substrate, and the orthographic projection of the first shading structure on the substrate partially overlapping the orthographic projections of the plurality of data fan-out lines on the substrate.

Description

Display panel and display device

[0001] This application claims priority to patent application No. PCT / CN2023 / 122646, filed on September 28, 2023, with invention name “Display panel and display device”, and patent application No. 202410186076.1, filed on February 19, 2024, with invention name “Display panel and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, displays using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present application provide a display panel and a display device.

[0007] On the one hand, this embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a first shading structure. The substrate comprises a display area and a first frame area located on at least one side of the display area. The first frame area comprises: a first fan-out area and a bending area arranged in sequence along a direction away from the display area. A plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are electrically connected to the plurality of sub-pixels. The plurality of data fan-out lines are located in the first fan-out area and are electrically connected to the plurality of data lines, and are configured to provide data signals to the plurality of sub-pixels in the display area. The first shading structure is located in the first fan-out area, the first shading structure is located on a side of the plurality of data fan-out lines away from the substrate, and the orthographic projection of the first shading structure on the substrate partially overlaps with the orthographic projection of the plurality of data fan-out lines on the substrate.

[0008] In some exemplary embodiments, the display panel further includes: an isolation groove located in the first fan-out area; the first light-shielding structure is located on a side of the isolation groove close to the display area, and a distance between the orthographic projection of the first light-shielding structure on the substrate and the orthographic projection of the isolation groove on the substrate is greater than 0.

[0009] In some exemplary embodiments, the display panel further comprises: a first isolation dam at least partially located within the isolation trench; and a second isolation dam at least partially located within the isolation trench, the second isolation dam being located on a side of the first isolation dam away from the display area. At least one of the plurality of data fan-out lines comprises: a first extension segment and a second extension segment connected to each other, the first extension segment being located on a side of the second extension segment closer to the display area, the first extension segment and the second extension segment extending in an intersecting direction; the spacing between the first extension segments of two adjacent data fan-out lines being less than or equal to the spacing between the second extension segments of the two adjacent data fan-out lines; and the connection between the first extension segment and the second extension segment being located on a side of the second isolation dam closer to the display area.

[0010] In some exemplary embodiments, a minimum angle between the orthographic projection of the first extension segment of the at least one data fan-out line on the substrate and the orthographic projection of the first isolation dam on the substrate is less than or equal to a minimum angle between the orthographic projection of the second extension segment on the substrate and the orthographic projection of the first isolation dam on the substrate.

[0011] In some exemplary embodiments, the first light-shielding structure includes at least one light-shielding sheet, the length of the light-shielding sheet in the direction from the display area to the first border area is less than the length extending along the edge of the display area, and the light-shielding sheet is provided with a plurality of holes passing through the light-shielding sheet in a direction perpendicular to the substrate.

[0012] In some exemplary embodiments, the display panel further includes: a first frame power line located in the first fan-out area, the first frame power line being configured to provide a first voltage signal to a plurality of sub-pixels in the display area; and the first light shielding structure being connected to the first frame power line.

[0013] In some exemplary embodiments, the first light-shielding structure includes at least one light-shielding sheet, and the at least one light-shielding sheet and the first frame power line are an integrated structure connected to each other.

[0014] In some exemplary embodiments, the display panel further includes a second frame power line located in the first fan-out area, the second frame power line configured to provide a second voltage signal to a plurality of sub-pixels in the display area, the second voltage signal being greater than the first voltage signal. The second frame power line is located on a side of the first frame power line closer to the substrate and on a side of the plurality of data fan-out lines farther from the substrate, with the second frame power line and the first frame power line overlapping in their orthographic projection onto the substrate.

[0015] In some exemplary embodiments, the display panel further includes: at least one planar layer, and the first light shielding structure is in contact with a planar surface of one planar layer close to the surface of the substrate.

[0016] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes at least: a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer sequentially arranged on the substrate; the first light-shielding structure is located in at least one of the following film layers: the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

[0017] In some exemplary embodiments, the display panel further includes: an encapsulation layer and a light-shielding layer; the encapsulation layer is located on a side of the first light-shielding structure away from the substrate, and the light-shielding layer is located on a side of the encapsulation layer away from the substrate; a distance between the orthographic projection of the light-shielding layer on the substrate and the orthographic projection of the first light-shielding structure on the substrate is greater than 0; the material of the light-shielding layer is an opaque organic material.

[0018] In some exemplary embodiments, the display panel further includes: a second light-shielding structure located in the first fan-out area and on a side of the first light-shielding structure away from the display area; and the second light-shielding structure is located on a side of the first light-shielding structure away from the substrate.

[0019] In some exemplary embodiments, the display panel includes, in a direction perpendicular to the display panel, a plurality of display conductive layers and at least one touch conductive layer sequentially disposed on the substrate. The first light shielding structure is located in one of the plurality of display conductive layers, and the second light shielding structure is located in the at least one touch conductive layer.

[0020] In some exemplary embodiments, the display panel further includes: a plurality of data transfer lines located in the display area, at least one of the plurality of data transfer lines including: a first transfer segment extending along a first direction and a second transfer segment extending along a second direction, the plurality of data lines extend along the second direction, and the first direction intersects the second direction; at least one of the plurality of data lines is connected to the first transfer segment of the data transfer line, the second transfer segment of the data transfer line is connected to the data fan-out line, and the data line is located in the first direction on the side of the second transfer segment of the connected data transfer line close to the edge of the display panel.

[0021] In some exemplary embodiments, the display panel further comprises: a plurality of sets of data bending lines located in the bending region and separately arranged, the plurality of data fan-out lines comprising a plurality of sets of data fan-out lines, and the plurality of sets of data fan-out lines are connected to the plurality of sets of data bending lines in a one-to-one correspondence.

[0022] On the other hand, this embodiment provides a display device including the display panel as described above.

[0023] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0024] Summary of the Figures

[0025] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0026] FIG1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0027] FIG2 is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure;

[0028] FIG3 is a schematic diagram of a partial structure of a display area and a first fan-out area according to at least one embodiment of the present disclosure;

[0029] FIG4A is a schematic diagram of the wiring arrangement of the first fan-out area and the bending area according to at least one embodiment of the present disclosure;

[0030] 4B and 4C are schematic diagrams of the partial structure of the first fan-out area in FIG. 4A ;

[0031] FIG5 is a schematic partial cross-sectional view along the QQ' direction in FIG4A;

[0032] FIG6A is a partial enlarged schematic diagram of area S1 in FIG4A ;

[0033] 6B is a schematic diagram of the first gate metal layer, the second gate metal layer and the first source and drain metal layer in FIG. 6A ;

[0034] 6C is a schematic diagram of the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer in FIG. 6A ;

[0035] 6D is a schematic diagram of the first gate metal layer, the second gate metal layer, and the third source and drain metal layer in FIG. 6A ;

[0036] FIG7 is another partial cross-sectional schematic diagram of the first fan-out region according to at least one embodiment of the present disclosure;

[0037] FIG. 8 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0038] Details

[0039] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0040] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0041] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0042] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0043] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between the two elements. For those of ordinary skill in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "connection" can include "electrical connection", and "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0044] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0045] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0046] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0047] The terms “approximately” and “substantially” in the present disclosure do not strictly define the limits and allow for errors within the range of process and measurement errors.

[0048] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0049] As used herein, "A and B are in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0050] The display panel usually includes a display area and a non-display area. The display area is used to display the required image, and the non-display area is used to set the circuit structure for controlling the operation of the display area. The circuit structure includes, for example, a display driver circuit, various wirings, a flexible circuit board, etc. The non-display area can also be provided with various structures to ensure the screen packaging, such as dam glue, etc. Due to the presence of various wirings on the uneven film layer of the display panel, after the light is reflected and refracted between the multiple film layers in the non-display area, when the display panel is in the off state, the user can still see the light reflected from the non-display area, thereby forming a light leakage phenomenon (or bottom reflection phenomenon). In order to prevent light leakage in the non-display area of ​​the display panel, for example, a light shielding layer can be coated on the non-display area to block the light. However, the light shielding layer has problems such as fitting tolerance and manufacturing tolerance, and to meet the requirements of the entire machine, the edge of the light shielding layer is a certain distance away from the display area. Since there is a light leakage area between the edge of the light shielding layer close to the display area and the display area that is not blocked by the light shielding layer, the light in the light leakage area will not be blocked, so that light can be transmitted from the light leakage area. Furthermore, with increasing demand for portable electronic products (such as mobile phones), products with narrow bottom bezels are becoming increasingly popular among consumers. The narrower the bezels of these products, the less space there is for wiring. This reduced spacing between wiring further increases light leakage from the bottom bezel.

[0051] This embodiment provides a display panel comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a first light shielding structure. The substrate comprises a display area and a first frame area located on at least one side of the display area. The first frame area comprises a first fan-out area and a bend area arranged sequentially in a direction away from the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area, and the plurality of data lines are electrically connected to the plurality of sub-pixels. The plurality of data fan-out lines are located in the first fan-out area and electrically connected to the plurality of data lines, and are configured to provide data signals to the plurality of sub-pixels in the display area. The first light shielding structure is located in the first fan-out area and on a side of the plurality of data fan-out lines away from the substrate. The orthographic projection of the first light shielding structure on the substrate partially overlaps with the orthographic projections of the plurality of data fan-out lines on the substrate. For example, the orthographic projection of the first light shielding structure on the substrate may partially overlap with the orthographic projection of each data fan-out line on the substrate; alternatively, the orthographic projection of the first light shielding structure on the substrate may partially overlap with the orthographic projections of some of the plurality of data fan-out lines on the substrate.

[0052] The display panel provided in this embodiment provides a first light-shielding structure in the first fan-out area, and uses the first light-shielding structure to shield the light leakage area of ​​the first fan-out area, thereby improving the light leakage phenomenon in the first frame area of ​​the display panel.

[0053] In some exemplary embodiments, the first light-shielding structure is in contact with the flat layer near the surface of the substrate. For example, the flat layer may be an organic insulating layer and may have a flat surface. This example can ensure the surface flatness of the first light-shielding structure, thereby improving the light leakage phenomenon caused by the reflection and refraction of the non-flat film layer or the wiring arranged on the non-flat film layer. In this example, flatness may refer to the surface undulations observable at a macroscopic scale, for example, under the naked eye or an optical microscope; it may also refer to the microscopic scale, that is, with the help of microscopic morphology characterization means and instruments, such as the microscopic surface roughness and flatness of the corresponding cross section observed using a scanning electron microscope (SEM) or an atomic force microscope (AFM). A flat surface means that the surface has no obvious undulations at the corresponding scale.

[0054] In some exemplary embodiments, the display panel may further include an isolation trench located in the first fan-out region, a first light-shielding structure located on a side of the isolation trench proximal to the display region, and a spacing between the orthographic projection of the first light-shielding structure on the substrate and the orthographic projection of the isolation trench on the substrate being greater than zero. In other words, the orthographic projection of the first light-shielding structure on the substrate and the orthographic projection of the isolation trench on the substrate may not overlap. In this example, the first light-shielding structure is positioned away from the isolation trench to ensure surface flatness of the first light-shielding structure, thereby improving light leakage caused by reflection and refraction from uneven film layers or traces disposed on the uneven film layers.

[0055] In some exemplary embodiments, the display panel may further include: a first isolation dam at least partially positioned within the isolation trench; and a second isolation dam at least partially positioned within the isolation trench. The second isolation dam may be located on a side of the first isolation dam away from the display area. At least one data fan-out line may include: a first extension segment and a second extension segment connected to each other, the first extension segment being located on a side of the second extension segment closer to the display area. The first extension segment and the second extension segment extend in intersecting directions. The spacing between the first extension segments of two adjacent data fan-out lines may be less than or equal to the spacing between the second extension segments of two adjacent data fan-out lines. The connection between the first extension segment and the second extension segment may be located on a side of the second isolation dam closer to the display area. In some examples, the minimum angle between the orthographic projection of the first extension segment of at least one data fan-out line onto the substrate and the orthographic projection of the first isolation dam onto the substrate may be less than or equal to the minimum angle between the orthographic projection of the second extension segment onto the substrate and the orthographic projection of the first isolation dam onto the substrate. For example, the first extension segment may be an oblique extension segment, and the second extension segment may be a vertical extension segment. In this example, by adjusting the connection position of the first extension segment and the second extension segment to be located on the side of the second isolation dam close to the display area, the spacing between adjacent data fan-out lines can be increased, which is beneficial to reducing reflection between adjacent data fan-out lines, thereby reducing the risk of light leakage caused by reflection.

[0056] In some exemplary embodiments, the display panel may further include: a first frame power line located in the first fan-out area. The first frame power line may be configured to provide a first voltage signal to a plurality of sub-pixels in the display area. The first shading structure may be connected to the first frame power line. In some examples, the first shading structure may include at least one shading sheet, and the at least one shading sheet and the first frame power line may be an integral structure connected to each other. For example, the first shading structure and the first frame power line may be located in a display conductive layer (e.g., a third source / drain metal layer). This example avoids the first shading structure made of conductive material floating in the first fan-out area and affecting the performance of the display panel by setting the first shading structure to be connected to the first frame power line. However, this embodiment is not limited to this. In other examples, the first shading structure may be made of non-conductive material, such as an opaque organic material.

[0057] In some exemplary embodiments, the display panel may further include: a second frame power line located in the first fan-out area, the second frame power line may be configured to provide a second voltage signal to multiple sub-pixels in the display area, the second voltage signal may be greater than the first voltage signal, for example, the second voltage signal may be a high-level signal, and the first voltage signal may be a low-level signal. The second frame power line may be located on a side of the first frame power line close to the substrate, and on a side of the multiple data fan-out lines away from the substrate. The orthographic projections of the second frame power line and the first frame power line on the substrate may partially overlap. In some examples, the first shading structure may be connected to the second frame power line to prevent the first shading structure from floating and affecting the performance of the display panel.

[0058] In some exemplary embodiments, the display panel may further include: an encapsulation layer and a light-shielding layer. The encapsulation layer may be located on the side of the first light-shielding structure away from the substrate, and the light-shielding layer may be located on the side of the encapsulation layer away from the substrate. The distance between the orthographic projection of the light-shielding layer on the substrate and the orthographic projection of the first light-shielding structure on the substrate may be greater than 0. In other words, the orthographic projections of the light-shielding layer and the first light-shielding structure on the substrate may not overlap. The material of the light-shielding layer may be different from the material of the first light-shielding structure. For example, the material of the light-shielding layer may be an opaque organic material, such as ink; and the material of the first light-shielding structure may be a conductive material. Alternatively, the material of the light-shielding layer may be ink, and the material of the first light-shielding structure may be a black resin material. In this example, the light leakage area of ​​the first fan-out area can be shielded by the coordinated arrangement of the first light-shielding structure and the light-shielding layer, thereby improving the light leakage problem of the display panel.

[0059] In some exemplary embodiments, the display panel may further include: a second light-shielding structure located in the first fan-out area. The second light-shielding structure may be located on a side of the first light-shielding structure away from the display area, and the second light-shielding structure may be located on a side of the first light-shielding structure away from the substrate. In some examples, in a direction perpendicular to the display panel, the display panel may include: a plurality of display conductive layers and at least one touch conductive layer sequentially arranged on the substrate. The first light-shielding structure may be located in one of the display conductive layers, for example, it may be located in a display conductive layer closest to the touch conductive layer among the plurality of display conductive layers; the second light-shielding structure may be located in at least one touch conductive layer. In this example, the light leakage area of ​​the first fan-out area can be shielded by cooperating with the second light-shielding structure, thereby improving the light leakage problem of the display panel.

[0060] The solution of this embodiment is illustrated below through some examples.

[0061] Figure 1 is a schematic diagram of a display panel of at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display panel may include: a display area AA and a border area (also referred to as a non-display area) located outside the display area AA. The border area may include: a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining side of the display area AA. The first border area B1 may be located on one side of the display area AA along the second direction D2. The first border area B1 may be connected to the second border area B2. For example, the first border area B1 may be the lower border area of ​​the display panel, and the second border area B2 may include: a left border area, a right border area, and an upper border area of ​​the display panel.

[0062] In some examples, as shown in FIG1 , the display area AA may be a flat area including a plurality of sub-pixels constituting a pixel array. The plurality of sub-pixels may be configured to display a dynamic image or a still image. The display area AA may also be referred to as an active area. In some examples, the display area AA may be rectangular. However, this embodiment is not limited thereto. For example, the display area AA may be circular or elliptical. In some examples, the display panel may be a flexible display panel, and thus the display panel may be deformable, such as curled, bent, folded, or rolled up.

[0063] In some examples, as shown in FIG1 , the display area AA may include: a display structure layer provided on a substrate, or may include a display structure layer and a touch structure layer provided in sequence on a substrate. For example, the display panel may integrate a touch structure to form a structure in which the touch structure is on a thin film package (Touch on Thin Film Encapsulation, referred to as Touch on TFE). The Touch on TFE structure mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The driving chip (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0064] In some examples, the display structure layer may include multiple sub-pixels, multiple gate lines, and multiple data lines. The multiple gate lines may extend along a first direction D1, and the multiple data lines may extend along a second direction D2. The orthographic projections of the multiple gate lines and the multiple data lines on the substrate may intersect to form multiple sub-pixel areas. A sub-pixel may be arranged in a sub-pixel area. The multiple data lines may be electrically connected to the multiple sub-pixels, and the multiple data lines may be configured to provide data signals to the multiple sub-pixels. The multiple gate lines may be electrically connected to the multiple sub-pixels, and the multiple gate lines may be configured to provide gate drive signals to the multiple sub-pixels. For example, the gate drive signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal. In some examples, the first direction D1 may be the extension direction of the gate lines within the display area AA (e.g., the row direction); the second direction D2 may be the extension direction of the data lines within the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 may intersect with each other, for example, may be perpendicular to each other.

[0065] In some examples, a display pixel in display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0066] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.

[0067] In some examples, the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal. When a display pixel includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a display pixel includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0068] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0069] Figure 2 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure. Figure 2 illustrates the structure of a sub-pixel in the display area as an example. In some examples, as shown in Figure 2, in a direction perpendicular to the display panel, the display area of ​​the display panel may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially arranged on the substrate 10. Among them, the display structure layer may include at least a circuit structure layer 12 and a light-emitting structure layer 13. The circuit structure layer 12 may include at least: pixel circuits of multiple sub-pixels, and the pixel circuit of each sub-pixel may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements of multiple sub-pixels.

[0070] In some examples, FIG2 illustrates each sub-pixel as including a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second-type transistor 22 may be an oxide thin-film transistor.

[0071] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, disposed on the substrate 10. The multiple display conductive layers of this example may include: a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating (GI) layer 101 may be provided between the first semiconductor layer and the first gate metal layer, and a second gate insulating layer 102 may be provided between the first gate metal layer and the second gate metal layer; a third gate insulating layer 103 may be provided between the second gate metal layer and the second semiconductor layer; a fourth gate insulating layer 104 may be provided between the second semiconductor layer and the third gate metal layer; an interlayer insulating layer 105 may be provided between the third gate metal layer and the first source-drain metal layer; a passivation (PVX) layer 106 and a first flattening (PLN) layer 107 may be provided between the first source-drain metal layer and the second source-drain metal layer, and the first flattening layer 107 may be located on the side of the passivation layer 106 away from the substrate 10; a second flattening layer 108 may be provided between the second source-drain metal layer and the third source-drain metal layer; and a third flattening layer 109 may be provided on the side of the third source-drain metal layer away from the substrate 10. Among them, the first gate insulating layer 101, the second gate insulating layer 102, the third gate insulating layer 103, the fourth gate insulating layer 104, the interlayer insulating layer 105 and the passivation layer 106 can be inorganic insulating layers, and the first flat layer 107, the second flat layer 108 and the third flat layer 109 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can be further provided on the side of the first semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel and can also increase the adhesion of the film layer in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can be further provided on the side of the buffer layer close to the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor. In other examples, the passivation layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the first flat layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0072] In some examples, as shown in FIG2 , the first semiconductor layer in the display area may include at least a first active layer 210 of the first-type transistor 21. The first active layer 210 of the first-type transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate 213 of the first-type transistor 21 and a first plate 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first-type transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 232 of the capacitor 23 and a third gate 224 of the second-type transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may overlap. The second semiconductor layer may include at least a second active layer 220 of the second-type transistor 22. The third gate metal layer may include at least a second gate 223 of the second-type transistor 22. The orthographic projection of the second gate 223 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The orthographic projection of the third gate 224 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The third gate 224 may be the bottom gate of the second-type transistor 22, and the second gate 223 may be the top gate of the second-type transistor 22.

[0073] In some examples, as shown in FIG2 , the first source-drain metal layer in the display area may include at least: a first source 211 and a first drain 212 of the first-type transistor 21, and a second source 221 and a second drain 222 of the second-type transistor 22. The interlayer insulating layer 105 may have a plurality of pixel vias (e.g., a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The interlayer insulating layer 105, the fourth gate insulating layer 104, the third gate insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210. The interlayer insulating layer 105, the third gate insulating layer 104, the third gate insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The interlayer insulating layer 105, fourth gate insulating layer 104, and third gate insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220. The first source 211 of the first-type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second-type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second-type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can include at least a first transfer electrode 241. The first transfer electrode 241 can be electrically connected to the first drain 212 of the first-type transistor 21 of the pixel circuit through a fifth pixel via defined through the passivation layer 106 and the first planarization layer 107. The third source / drain metal layer may include at least a second transfer electrode 242. The second transfer electrode 242 may be connected to the first transfer electrode 241 through a sixth pixel via hole formed in the second planar layer 108. In this example, the first transfer electrode 241 and the second transfer electrode 242 may be used to electrically connect the pixel circuit to the light-emitting element.

[0074] In some examples, the gate lines of the display area may be located in the first gate metal layer and the third gate metal layer, the data lines of the display area may be located in the second source / drain metal layer, the high-potential power lines of the display area may be located in the second source / drain metal layer, and the low-potential power lines of the display area may be located in the third source / drain metal layer. This embodiment is not limited to this.

[0075] In some examples, as shown in FIG2 , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the third planar layer 109 and electrically connected to the second transfer electrode 242 through a seventh pixel via provided in the third planar layer 109. The pixel definition layer 134 is disposed on the first electrode 131 and the third planar layer 109. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0076] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light according to the required grayscale.

[0077] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0078] In some examples, as shown in FIG2 , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141, 143 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display panel and relieve stress in the first and third encapsulation layers 141, 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure: inorganic / organic / inorganic / organic / inorganic.

[0079] In some examples, the touch structure layer 15 of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0080] In some examples, as shown in FIG2 , in a direction perpendicular to the display panel, the touch structure layer 15 of the display area may include: a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a protective layer 154, arranged in sequence. The display panel of this example may include two touch conductive layers. The touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the protective layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an interconnected integral structure. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias provided in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an interconnected integral structure; the second touch conductive layer may include a plurality of first connecting portions, wherein the first connecting portions may be interconnected with adjacent first touch electrodes via vias defined in the touch interlayer insulating layer. In some examples, the first touch electrodes may be drive (Tx) electrodes, and the second touch electrodes may be sense (Rx) electrodes. Alternatively, the first touch electrodes may be sense (Rx) electrodes, and the second touch electrodes may be drive (Tx) electrodes. This embodiment is not limited to this.

[0081] In some examples, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygonal shapes, which are not limited in the embodiments of the present disclosure.

[0082] In some examples, the first and second touch electrodes may be transparent conductive electrodes. In other examples, the first and second touch electrodes may be in the form of a metal mesh. The metal mesh may be formed by interweaving multiple metal wires. The metal mesh may include multiple mesh patterns, and the mesh pattern may be a polygon formed by multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0083] In some examples, as shown in Figure 1, the first frame area B1 may include: a first fan-out area B11, a bending area B12 (also referred to as a bendable portion) and a second fan-out area B13 (also referred to as an extension portion) arranged in sequence along a direction away from the display area AA. The first fan-out area B11 may be connected to the display area AA, the first fan-out area B11 may be connected to the second frame area B2, and the bending area B12 may be connected to the first fan-out area B11 and the second fan-out area B13. The bending area B12 may be configured to bend the second fan-out area B13 to the back of the display area AA. The second fan-out area B13 may be provided with a plurality of first contact pads connected to the driver chip, and a plurality of second contact pads connected to the flexible circuit board, and the plurality of second contact pads may be located on the side of the plurality of first contact pads away from the bending area B12.

[0084] Figure 3 is a schematic diagram of the partial structure of the display area and the first fan-out area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the display area AA may be provided with multiple sub-pixels PX, multiple data lines DL, and multiple data transfer lines 31. The multiple sub-pixels PX are electrically connected to the multiple data lines DL. The multiple data lines DL may extend along the second direction D2 and be arranged along the first direction D1. The data transfer lines 31 may include: a first transfer section 311 extending along the first direction D1 and a second transfer section 312 extending along the second direction D2. The second transfer sections 312 of the data transfer lines 31 may be arranged at intervals between the multiple data lines DL. The data lines DL are connected to the first transfer sections 311 of the data transfer lines 31, and the first transfer sections 311 are connected to the second transfer sections 312. The data lines DL may be located on a side of the second transfer sections 312 of the data transfer lines 31 to which they are connected, closer to the edge of the display panel, in the first direction D1. The second transfer section 312 of the data transfer line 31 may extend to the first fan-out area B11 and be connected to the data fan-out line 41 in the first fan-out area B11 .

[0085] In some examples, the plurality of data lines DL may include a first group of data lines and a second group of data lines. The first group of data lines may extend directly to the first fan-out area B11 and be connected to the corresponding plurality of data fan-out lines 41. The second group of data lines may be connected to the plurality of data fan-out lines 41 via a plurality of data adapter lines 31. The first group of data lines may be located on a side of the second group of data lines that is close to an edge of the display panel. However, this embodiment is not limited thereto. In other examples, the plurality of data lines within the display area may all be connected to the data fan-out lines via data adapter lines.

[0086] In this example, the data line and the data fan-out line are connected through a data adapter line, which can reduce the number of obliquely arranged data fan-out lines in the first fan-out area and reduce the inclination angle of the data fan-out line, thereby facilitating a reduction in the length of the first fan-out area along the second direction D2. This reduces the light leakage area in the first frame area and increases the screen-to-body ratio, thereby facilitating a full-screen display.

[0087] In some examples, as shown in Figure 3, the first fan-out area B11 may be provided with an isolation trench 40, a first isolation dam DAM1 (also referred to as a first dam glue) at least partially located within the isolation trench 40, and a second isolation dam DAM2 (also referred to as a second dam glue) at least partially located within the isolation trench 40. The isolation trench 40 extends at least along the first direction D1 within the first fan-out area B11. The first isolation dam DAM1 may extend toward the second border area to form a ring-shaped dam surrounding the display area AA; the second isolation dam DAM2 may extend toward the second border area to form a ring-shaped dam surrounding the display area AA. Within the first fan-out area B11, the isolation trench 40, the first isolation dam DAM1, and the second isolation dam DAM2 may all extend along the first direction D1. The first isolation dam DAM1 may be located on the side of the second isolation dam DAM2 closer to the display area AA. Within the first fan-out area B11, the second isolation dam DAM2 may be located on the side of the first isolation dam DAM1 closer to the bending area B12. In some examples, the isolation trench 40 may be formed by removing the organic insulating layer, and the first isolation dam DAM1 and the second isolation dam DAM2 may be formed by retaining a partial region of the organic insulating layer within the isolation trench 40 .

[0088] In some examples, as shown in FIG3 , the data fan-out line 41 within the first fan-out area B11 may include a first extension segment 411 and a second extension segment 412 connected to each other. The first extension segment 411 may be located on the side of the second extension segment 412 closer to the display area AA. The first extension segment 411 may be directly connected to the data line DL, or may be connected to the second transfer segment 312 of the data transfer line 31. The second extension segment 412 may extend toward the bending area B12 and connect to the data bending line provided within the bending area B12. The extension directions of the first extension segment 411 and the second extension segment 412 intersect. For example, the second extension segment 412 may extend along the second direction D2, with the extension direction of the first extension segment 411 intersecting both the first direction D1 and the second direction D2. The first extension segment 411 may also be referred to as an oblique extension segment, and the second extension segment 412 may also be referred to as a vertical extension segment. The spacing between the first extension segments 411 of adjacent data fan-out lines 41 may be smaller than the spacing between the second extension segments 412 of adjacent data fan-out lines 41.

[0089] In some examples, the minimum angle between the orthographic projection of the first extension section 411 of at least one data fan-out line 41 on the substrate and the orthographic projection of the first isolation dam DAM1 on the substrate may be less than or equal to the minimum angle between the orthographic projection of the second extension section 412 on the substrate and the orthographic projection of the first isolation dam DAM1 on the substrate. For example, if the first isolation dam DAM1 extends along a first direction D1, the minimum angle between the orthographic projection of the first extension section 411 on the substrate and the orthographic projection of the first isolation dam DAM1 on the substrate may be a clockwise angle or a counterclockwise angle between the first extension section 411 and the first direction D1, for example, the angle may be less than 90 degrees. The minimum angle between the orthographic projection of the second extension section 412 on the substrate and the orthographic projection of the first isolation dam DAM1 on the substrate may be a clockwise angle or a counterclockwise angle between the second extension section 412 and the first direction D1, for example, the angle may be approximately 90 degrees.

[0090] In some examples, as shown in FIG3 , the connection location of the first extension section 411 and the second extension section 412 of the plurality of data fan-out lines 41 can be located on the side of the second isolation dam DAM2 close to the display area AA. The orthographic projection of the connection location of the first extension section 411 and the second extension section 412 of the plurality of data fan-out lines 41 on the substrate may not overlap with the orthographic projection of the second isolation dam DAM2 on the substrate. For example, the orthographic projection of the connection location of the first extension section 411 and the second extension section 412 of at least one data fan-out line 41 on the substrate can be located within the orthographic projection of the first isolation dam DAM1 on the substrate, or can be located on the side of the first isolation dam DAM1 close to the display area AA. This example, by reducing the length of the first extension section 411 of the data fan-out line 41 and increasing the length of the second extension section 412 of the data fan-out line 41, can help increase the spacing (Space) between adjacent data fan-out lines 41, thereby reducing the risk of reflection between adjacent data fan-out lines and reducing the risk of light leakage in the first border area.

[0091] In some examples, as shown in FIG3 , the first light shielding structure 45 can be located on a side of the multiple data fan-out lines 41 away from the substrate. The orthographic projection of the first light shielding structure 45 on the substrate can be in the shape of an elongated strip extending along the first direction D1. The orthographic projection of the first light shielding structure 45 on the substrate can overlap with the orthographic projection of the first extension segments 411 of the multiple data fan-out lines 41 on the substrate. For example, the orthographic projection of the first light shielding structure 45 on the substrate partially overlaps with the orthographic projection of the first extension segment 411 of each data fan-out line 41 on the substrate. The first light shielding structure 45 can be located on a side of the isolation trench 40 close to the display area AA and does not overlap with the orthographic projection of the isolation trench 40 on the substrate.

[0092] Figure 4A is a schematic diagram of the wiring arrangement of the first fan-out area and the bending area of ​​at least one embodiment of the present disclosure. Figures 4B and 4C are schematic diagrams of the local structure of the first fan-out area in Figure 4A. Figures 4A to 4C provide an overall schematic diagram of multiple groups of data fan-out lines in the first fan-out area and multiple groups of data bending lines in the bending area. Figures 4A to 4C only simply illustrate the arrangement of multiple groups of data fan-out lines, and this embodiment does not limit the specific appearance of multiple groups of data fan-out lines. Figure 4B mainly illustrates the position and structure of the second frame power line, and Figure 4C mainly illustrates the position and structure of the first frame power line and the first shading structure. Figure 5 is a schematic diagram of a local cross-section along the Q-Q' direction in Figure 4A.

[0093] Figure 6A is a partially enlarged schematic diagram of region S1 in Figure 4A. Figure 6B is a schematic diagram of the first gate metal layer, the second gate metal layer, and the first source / drain metal layer in Figure 6A. Figure 6C is a schematic diagram of the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer in Figure 6A. Figure 6D is a schematic diagram of the first gate metal layer, the second gate metal layer, and the third source / drain metal layer in Figure 6A. Figures 6A to 6D provide an overall schematic diagram of the second group of touch bending lines 55b, the second group of first power bending lines 52b, and the second group of data bending lines 51b.

[0094] In some examples, as shown in Figures 4A to 4C, the multiple data fan-out lines in the first fan-out area B11 can include six groups of data fan-out lines, for example, including a first group of data fan-out lines 41a, a second group of data fan-out lines 41b, a third group of data fan-out lines 41c, a fourth group of data fan-out lines 41d, a fifth group of data fan-out lines 41e, and a sixth group of data fan-out lines 41f. The first group of data fan-out lines 41a, the second group of data fan-out lines 41b, the third group of data fan-out lines 41c, the fourth group of data fan-out lines 41d, the fifth group of data fan-out lines 41e, and the sixth group of data fan-out lines 41f can be arranged sequentially along the first direction D1. In this example, by dividing the multiple data fan-out lines into multiple groups, the length of the oblique extension section can be reduced, the risk of reflection between adjacent data fan-out lines can be reduced, and the risk of light leakage in the first border area can be reduced.

[0095] In some examples, as shown in Figure 5, adjacent data fan-out lines may be located in different conductive layers. The multiple data fan-out lines may include: multiple first data fan-out lines 41a located in the first gate metal layer and multiple second data fan-out lines 41b located in the second gate metal layer. The multiple first data fan-out lines 41a and the multiple second data fan-out lines 41b may be arranged alternately one by one. The interval between the orthographic projections of adjacent first data fan-out lines 41a and second data fan-out lines 41b on the substrate may be greater than 0. In other words, the orthographic projections of adjacent first data fan-out lines 41a and second data fan-out lines 41b on the substrate may not overlap. This embodiment is not limited to this. In other examples, the multiple data fan-out lines may all be arranged in the first gate metal layer, or, may all be arranged in the second gate metal layer.

[0096] In some examples, at least one data fan-out line may include a first extending section 411 and a second extending section 412 connected to each other. The first extending section 411 and the second extending section 412 may be an integral structure connected to each other.

[0097] In some examples, as shown in Figures 4A to 6D, the first fan-out area B11 may also be provided with a first light shielding structure 45, a first frame power line 42, a second frame power line 43, and third frame power lines 44a and 44b. The first frame power line 42 is configured to provide a first voltage signal to multiple sub-pixels in display area AA; the second frame power line 43 can be configured to provide a second voltage signal to multiple sub-pixels in display area AA. The second voltage signal can be greater than the first voltage signal. For example, the second voltage signal can be a high-level signal, and the first voltage signal can be a low-level signal. The first frame power line 42 can be connected to multiple low-potential power lines 32 in display area AA, and the second frame power line 43 can be connected to multiple high-potential power lines 33 in display area AA. For example, the multiple low-potential power lines 32 can be located in the third source and drain metal layer, and the multiple high-level power lines 33 can be located in the second source and drain metal layer. The first frame power line 42 can be connected to the third frame power lines 44a and 44b in the first frame area or the second frame area.

[0098] In some examples, as shown in Figures 4A to 5, the first frame power line 42 and the first light shielding structure 45 can be located on the side of the second frame power line 43 away from the substrate. The first frame power line 42 can extend along the first direction D1 within the first fan-out area B11. The first light shielding structure 45 can be located on the side of the first frame power line 42 away from the display area AA. The first light shielding structure 45 can be located on the side of the isolation groove 40 close to the display area AA. In other words, in the second direction D2, the first light shielding structure 45 can be located between the first frame power line 42 and the isolation groove 40. The first light shielding structure 45 may include a light shielding sheet 451. The length of the light shielding sheet 451 extending along the first direction D1 can be greater than the length extending along the second direction D2.

[0099] In some examples, the first frame power line 42 and the first light-shielding structure 45 can be a same-layer structure, for example, both are located in the third source-drain metal layer. The first frame power line 42 is connected to the light-shielding sheet 451 of the first light-shielding structure 45, for example, the two are an integrated structure connected to each other. As shown in Figure 5, the light-shielding sheet 451 can be set on the second flat layer 108, and the light-shielding sheet 451 is close to the surface of the substrate and contacts the second flat layer 108, which can ensure the flatness of the light-shielding sheet 451, and the orthographic projection of the light-shielding sheet 451 on the substrate overlaps with the orthographic projection of multiple data fan-out lines on the substrate, thereby blocking light leakage caused by reflection due to the unevenness of the film layer where the data fan-out lines are located.

[0100] In some examples, as shown in FIG6D , the integrated structure of the first frame power supply line 42 and the light shielding sheet 451 may be provided with a plurality of holes that pass through the entire integrated structure in a direction perpendicular to the main surface of the substrate to increase the air permeability of the integrated structure. In the case where the light shielding sheet is a conductive material such as a metal or an alloy, its air permeability is poor. The provision of a plurality of holes can prevent the film layer below the light shielding sheet 451, especially the organic film layer (such as the second flat layer 108), from emitting water vapor and other problems that cannot be eliminated when it is heated or humidified, thereby avoiding problems such as deformation and warping of the internal film layer of the display panel caused by this. In some examples, the plurality of holes on the light shielding sheet 451 can be arranged in a regular array, which can help improve the uniformity of air permeability and reduce the difficulty of manufacturing. In other examples, the plurality of holes on the light shielding sheet 451 can be irregularly arranged.

[0101] In some examples, the second frame power line 43 may include: a first sub-power line 431 located in the first source-drain metal layer and a second sub-power line 432 located in the second source-drain metal layer. The orthographic projection of the first sub-power line 431 of the second frame power line 43 on the substrate may at least partially overlap with the orthographic projection of the second sub-power line 432 on the substrate. For example, the orthographic projection of the first sub-power line 431 of the second frame power line 43 on the substrate may cover the orthographic projection of the second sub-power line 432 on the substrate. The second sub-power line 432 may be located on the side of the isolation groove 40 close to the display area AA, and the orthographic projection of the second sub-power line 432 on the substrate may not overlap with the orthographic projection of the isolation groove 40 on the substrate. Within the first fan-out area B11, the orthographic projection of the integrated structure of the first frame power line 42 and the first light-shielding structure 45 on the substrate may cover the orthographic projection of the second sub-power line 432 on the substrate.

[0102] In some examples, the second sub-power line 432 may be provided with a plurality of holes that penetrate the entire second sub-power line 432 in a direction perpendicular to the main surface of the substrate to increase the air permeability of the second sub-power line 432 and prevent the film layer below the second sub-power line 432, especially the organic film layer (such as the first flat layer 107), from emitting water vapor that cannot be eliminated when exposed to heat and moisture, thereby avoiding problems such as deformation and warping of the internal film layer of the display panel caused by this.

[0103] In some examples, as shown in Figures 4B and 6B , the first sub-power line 431 located in the first source / drain metal layer may include a first power main portion 4311, a first power extension portion 4312 extending from the first power main portion 4311 toward a side away from the display area AA, and three power connection portions 431-1, 431-2, and 431-3 extending from the first power extension portion 4312 toward the bend area B12. The three power connection portions 431-1, 431-2, and 431-3 may be spaced apart and connected one-to-one with the three sets of second power bend lines within the bend area B12. The orthographic projection of the first sub-power line 431 on the substrate may overlap with the orthographic projection of the isolation trench 40 on the substrate; for example, the orthographic projections of the first power extension portion 4312 and the three power connection portions 431-1, 431-2, and 431-3 of the first sub-power line 431 on the substrate may partially overlap with the orthographic projection of the isolation trench 40 on the substrate. The first power main portion 4311 of the first sub power line 431 extends along the first direction D1 , and an orthographic projection of the first power main portion 4311 on the substrate may be located within an orthographic projection range of the second sub power line 432 on the substrate.

[0104] In some examples, the third frame power lines 44a and 44b may be co-layered with the first sub-power line 431. For example, the third frame power lines 44a and 44b may be located in the first source / drain metal layer. The third frame power lines 44a and 44b may be located on a side of the first sub-power line 431 of the second frame power line 43 that is away from the display area AA. The third frame power lines 44a and 44b may be located on either side of the first power extension portion 4312 of the first sub-power line 431 of the second frame power line 43 along the first direction D1. The third frame power line 44a may extend to the left frame area of ​​the second frame area, and the third frame power line 44b may extend to the right frame area of ​​the second frame area. The orthographic projection of the third frame power line 44a on the substrate may overlap with the orthographic projection of the first group of data fan-out lines 41a on the substrate, and the orthographic projection of the third frame power line 44b on the substrate may overlap with the orthographic projection of the sixth group of data fan-out lines 41f on the substrate. The orthographic projection of the third frame power lines 44a and 44b on the substrate may overlap with the orthographic projection of the isolation groove 40 on the substrate. For example, the third frame power lines 44a and 44b may be connected to the first frame power line 42 through the first shading structure 45. However, this embodiment is not limited to this. In other examples, the third frame power lines 44a and 44b may be directly connected to the first frame power line 42 at the connecting corner of the first frame area and the second frame area.

[0105] In some examples, as shown in Figures 4A to 4C, the bending region B12 may be provided with multiple groups of data bending lines, for example, including a first group of data bending lines 51a, a second group of data bending lines 51b, a third group of data bending lines 51c, a fourth group of data bending lines 51d, a fifth group of data bending lines 51e, and a sixth group of data bending lines 51f. Each group of data bending lines may include multiple data bending lines. The first group of data bending lines 51a may be connected to the first group of data fan-out lines 41a, the second group of data bending lines 51b may be connected to the second group of data fan-out lines 41b, the third group of data bending lines 51c may be connected to the third group of data fan-out lines 41c, the fourth group of data bending lines 51d may be connected to the fourth group of data fan-out lines 41d, the fifth group of data bending lines 51e may be connected to the fifth group of data fan-out lines 41e, and the sixth group of data bending lines 51f may be connected to the sixth group of data fan-out lines 41f.

[0106] In some examples, the bending area B12 can also be provided with multiple groups of first power bending lines (for example, including a first group of first power bending lines 52a, a second group of first power bending lines 52b, a third group of first power bending lines 52c and a fourth group of first power bending lines 52d), multiple groups of second power bending lines (for example, including a first group of second power bending lines 53a, a second group of second power bending lines 53b, a third group of second power bending lines 53c), multiple groups of control bending lines (for example, a first group of control bending lines 54a, a second group of control bending lines 54b), and multiple groups of touch bending lines (for example, including a first group of touch bending lines 55a, a second group of touch bending lines 55b, a third group of touch bending lines 55c and a fourth group of touch bending lines 55d). Each group of first power bending lines may include: at least one first power bending line; each group of second power bending lines may include at least one second power bending line; each group of control bending lines may include multiple control bending lines; each group of touch bending lines may include: multiple touch bending lines.

[0107] In some examples, the first group of control bending lines 54a, the first group of first power bending lines 52a, the first group of touch bending lines 55a, the first group of data bending lines 51a, the second group of touch bending lines 55b, the second group of first power bending lines 52b, the second group of data bending lines 51b, the first group of second power bending lines 53a, the third group of data bending lines 51c, the second group of second power bending lines 53b, the fourth group of data bending lines 51d, the third group of second power bending lines 53c, the fifth group of data bending lines 51e, the third group of first power bending lines 52c, the third group of touch bending lines 55c, the sixth group of data bending lines 51f, the fourth group of touch bending lines 55d, the fourth group of first power bending lines 52d and the second group of control bending lines 54b can be arranged in sequence along the first direction D1. The first group of data bending lines 51a can be located between two groups of first power bending lines, and the sixth group of data bending lines 51f can be located between two groups of first power bending lines. The second group of data bending lines 51b through the fifth group of data bending lines 51e can be arranged alternately with the three groups of second power bending lines. This exemplary routing arrangement helps reduce the length of the diagonal data fan-out lines.

[0108] In some examples, the multiple bending lines of the bending region B12 may be located in the same conductive layer, for example, in the second source / drain metal layer. This embodiment is not limited to this. In other examples, the multiple bending lines of the bending region may be located in the first source / drain metal layer or the second source / drain metal layer.

[0109] In some examples, as shown in FIG5 , the first planar layer 107, the second planar layer 108, and the third planar layer 109 in the isolation trench 40 can be removed. The first isolation dam DAM1 can be formed by stacking multiple dam bases, for example, by stacking a first dam base on the same layer as the second planar layer 108, a second dam base on the same layer as the third planar layer 109, and a third dam base on the same layer as the pixel definition layer 134. The second isolation dam DAM2 can be formed by stacking multiple dam bases, for example, by stacking a first dam base on the same layer as the first planar layer 107, a second dam base on the same layer as the second planar layer 108, a third dam base on the same layer as the third planar layer 109, and a fourth dam base on the same layer as the pixel definition layer 134. This embodiment is not limited to this. In other examples, a third isolation dam can be provided on the side of the second isolation dam away from the first isolation dam.

[0110] In some examples, as shown in FIG5 , the display panel may further include: a light-shielding layer 47 located on the side of the encapsulation layer 14 and the touch structure layer 15 away from the substrate. The orthographic projection of the light-shielding layer 47 on the substrate may at least partially overlap with the orthographic projection of the isolation groove 40 on the substrate. For example, the orthographic projection of the light-shielding layer 47 on the substrate may cover the orthographic projection of the isolation groove 40 on the substrate. The spacing between the orthographic projection of the light-shielding layer 47 and the first light-shielding structure 45 on the substrate is greater than 0, that is, the orthographic projections of the two on the substrate do not overlap. The material of the light-shielding layer 47 may be an opaque organic material, such as ink. In this way, the light leakage phenomenon in the first frame area may be improved by cooperating with the first light-shielding structure 45 and the light-shielding layer 47.

[0111] In other examples, the first light-shielding structure may include: a plurality of light-shielding sheets independently arranged in sequence along the first direction, and the plurality of light-shielding sheets may be connected to the first frame power line. Alternatively, at least one light-shielding sheet among the plurality of light-shielding sheets is connected to the first frame power line, and at least one light-shielding sheet is connected to the second frame power line. Alternatively, the plurality of light-shielding sheets may all be connected to the second frame power line. For example, the light-shielding sheet may be located in the third source-drain metal layer, and connected to the first sub-power line or the second sub-power line of the second frame power line exposed by the isolation groove through the connecting electrode. This embodiment is not limited to this.

[0112] In other examples, the first light-shielding structure may include: a plurality of light-shielding sheets, and the plurality of light-shielding sheets may be of the same layer structure, for example, all located in the second source-drain metal layer or the third source-drain metal layer; or, the plurality of light-shielding sheets may be arranged in multiple source-drain metal layers, for example, some of the plurality of light-shielding sheets may be located in the second source-drain metal layer, and another portion of the light-shielding sheets may be located in the third source-drain metal layer. In other examples, a flat layer may be provided on the side of the first source-drain metal layer close to the substrate, and the plurality of light-shielding sheets of the first light-shielding structure may be located in the first source-drain metal layer, or may be located in the first source-drain metal layer and the second source-drain metal layer, or may be located in the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

[0113] In other examples, the material of the first light-shielding structure may be an opaque organic material, such as a black resin material. The first light-shielding structure may be located on the third planar layer 109. For example, the first light-shielding structure may be prepared after the pixel definition layer 134, or may be prepared before the pixel definition layer 134. The first light-shielding structure may be a whole block structure extending along the first direction, or may be a plurality of block structures arranged along the first direction. However, this embodiment is not limited to this. In other examples, the first light-shielding structure may be located on the second planar layer or the first planar layer.

[0114] FIG7 is another partial cross-sectional schematic diagram of the first fan-out region of at least one embodiment of the present disclosure. In some examples, the display panel may further include: a second light-shielding structure 46 located in the first fan-out region B11. The second light-shielding structure 46 may be located on the side of the first light-shielding structure 45 away from the display area AA. The orthographic projections of the second light-shielding structure 46 and the first light-shielding structure 45 on the substrate may not overlap. The orthographic projection of the second light-shielding structure 46 on the substrate may at least partially overlap with the orthographic projection of the isolation trench 40 on the substrate. For example, the orthographic projection of the second light-shielding structure 46 on the substrate may be located within the orthographic projection range of the isolation trench 40 on the substrate. The orthographic projections of the second light-shielding structure 46 and the light-shielding layer 47 on the substrate may partially overlap, or may not overlap.

[0115] In some examples, the first touch conductive layer of the first fan-out area B11 may include a first touch lead line 511, and the second touch conductive layer may include a second touch lead line 512. The second light shielding structure 46 may include a first light shielding block 461 located in the first touch conductive layer and a second light shielding block 462 located in the second touch conductive layer. The orthographic projections of the first light shielding block 461 and the second light shielding block 462 on the substrate may partially overlap or may not overlap. At least one of the first light shielding block 461 and the second light shielding block 462 may be floating and not transmit electrical signals; alternatively, at least one of the first light shielding block 461 and the second light shielding block 462 may be connected to a ground line. This embodiment is not limited to this. In other examples, the second light shielding structure may include at least one first light shielding block located in the first touch conductive layer, or at least one second light shielding block located in the second touch conductive layer.

[0116] The remaining structures of the display panel of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0117] In this example, the first light-shielding structure, the second light-shielding structure, and the light-shielding layer are arranged in coordination to effectively block the light leakage area of ​​the first fan-out region, thereby improving the light leakage problem of the display panel.

[0118] Figure 8 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 8 , this embodiment provides a display device 91 comprising a display panel 910 according to the aforementioned embodiment. In some examples, display panel 910 may be an OLED display panel, such as an OLED display panel with an integrated touchscreen structure. Display device 91 may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, or may be a product or component with both touchscreen and display functions.

[0119] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0120] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display panel, comprising: A substrate, comprising a display area and a first frame area located on at least one side of the display area; The first frame area includes: a first fan-out area and a bending area which are sequentially arranged in a direction away from the display area; A plurality of sub-pixels are located in the display area; a plurality of data lines, located in the display area and electrically connected to the plurality of sub-pixels; a plurality of data fan-out lines, located in the first fan-out area and electrically connected to the plurality of data lines, configured to provide data signals to the plurality of sub-pixels in the display area; A first light shielding structure is located in the first fan-out area. The first light shielding structure is located on a side of the multiple data fan-out lines away from the substrate. The orthographic projection of the first light shielding structure on the substrate partially overlaps with the orthographic projection of the multiple data fan-out lines on the substrate.

2. The display panel according to claim 1, further comprising: an isolation trench located in the first fan-out region; The first light shielding structure is located at a side of the isolation groove close to the display area, and a distance between an orthographic projection of the first light shielding structure on the substrate and an orthographic projection of the isolation groove on the substrate is greater than 0.

3. The display panel according to claim 2, further comprising: a first isolation dam at least partially located in the isolation trench and a second isolation dam at least partially located in the isolation trench, wherein the second isolation dam is located on a side of the first isolation dam away from the display area; At least one of the multiple data fan-out lines includes: a first extension section and a second extension section that are connected to each other, the first extension section is located on a side of the second extension section close to the display area, and the extension directions of the first extension section and the second extension section intersect; the spacing between the first extension sections of two adjacent data fan-out lines is less than or equal to the spacing between the second extension sections of the two adjacent data fan-out lines; and the connection position of the first extension section and the second extension section is located on a side of the second isolation dam close to the display area.

4. The display panel according to claim 3, wherein: The minimum angle between the orthographic projection of the first extension segment of the at least one data fan-out line on the substrate and the orthographic projection of the first isolation dam on the substrate is less than or equal to the minimum angle between the orthographic projection of the second extension segment on the substrate and the orthographic projection of the first isolation dam on the substrate.

5. The display panel according to claim 1, wherein: The first shading structure includes at least one shading sheet, the length of the shading sheet in the direction from the display area to the first frame area is smaller than the length extending along the edge of the display area, and the shading sheet is provided with a plurality of holes penetrating the shading sheet in a direction perpendicular to the substrate.

6. The display panel according to claim 1, further comprising: A first frame power line located in the first fan-out area, the first frame power line being configured to provide a first voltage signal to a plurality of sub-pixels in the display area; The first light shielding structure is connected to the first frame power line.

7. The display panel according to claim 6, wherein: The first light-shielding structure includes at least one light-shielding sheet, and the at least one light-shielding sheet and the first frame power line are an integrated structure connected to each other.

8. The display panel according to claim 6 or 7, further comprising: A second frame power line located in the first fan-out area, the second frame power line is configured to provide a second voltage signal to a plurality of sub-pixels in the display area, the second voltage signal being greater than the first voltage signal; The second frame power line is located on a side of the first frame power line close to the substrate and on a side of the plurality of data fan-out lines away from the substrate. The second frame power line and the first frame power line are located on the substrate. The orthographic projections of .

9. The display panel according to claim 1, further comprising: At least one planar layer, the first light shielding structure is close to the surface of the substrate and contacts with a planar surface of the planar layer.

10. The display panel according to claim 9, wherein: In a direction perpendicular to the display panel, the display panel includes at least: a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged in sequence on the substrate; the first light-shielding structure is located in at least one of the following film layers: the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

11. The display panel according to claim 1, further comprising: Encapsulation layer and light shielding layer; The encapsulation layer is located on a side of the first light-shielding structure away from the substrate, and the light-shielding layer is located on a side of the encapsulation layer away from the substrate; The distance between the orthographic projection of the light-shielding layer on the substrate and the orthographic projection of the first light-shielding structure on the substrate is greater than 0; the material of the light-shielding layer is an opaque organic material.

12. The display panel according to claim 1, further comprising: A second light-shielding structure is located in the first fan-out area and on a side of the first light-shielding structure away from the display area; The second light shielding structure is located on a side of the first light shielding structure away from the substrate.

13. The display panel according to claim 12, wherein: In a direction perpendicular to the display panel, the display panel comprises: a plurality of display conductive layers and at least one touch conductive layer sequentially arranged on the substrate; The first light shielding structure is located in one of the plurality of display conductive layers, and the second light shielding structure is located in the at least one touch conductive layer.

14. The display panel according to claim 1, further comprising: A plurality of data transfer lines are located in the display area, wherein at least one of the plurality of data transfer lines comprises: a first transfer segment extending along a first direction and a second transfer segment extending along a second direction, the plurality of data lines extend along the second direction, and the first direction intersects the second direction; at least one of the plurality of data lines is connected to the first transfer segment of the data transfer line, the second transfer segment of the data transfer line is connected to the data fan-out line, and the data line is located in the first direction on the side of the second transfer segment of the data transfer line to which it is connected, close to an edge of the display panel.

15. The display panel according to claim 1, further comprising: A plurality of sets of data bending lines are located in the bending area and are separately arranged, the plurality of data fan-out lines include a plurality of sets of data fan-out lines, and the plurality of sets of data fan-out lines are connected to the plurality of sets of data bending lines in a one-to-one correspondence.

16. A display device comprising the display panel according to any one of claims 1 to 15.

Images