Data encoding method and related device

Abstract

Embodiments of the present application provide a data encoding method and a related device, capable of reducing the complexity of encoding while the length of an internal encoding codeword and the redundancy cost are not changed. Specifically, for a first data stream having undergone external encoding, every k consecutive bits in the first data stream need to undergo internal encoding, and k is an odd number greater than 1. XOR is performed on the bits among the k bits, other than one target bit, in pairs to obtain (k-1) / 2 bits in total, and then second FEC encoding is performed on a bit sequence comprising the (k-1) / 2 bits and the target bit to obtain p check bits, wherein n bits in internal encoding codewords after the internal encoding comprise k consecutive bits and p check bits. It can be seen that the embodiments of the present application adopt a mode of first XOR and then encoding, for example, codeword processing of (128, 119) can be implemented by means of an encoder (69, 60), and the complexity of encoding is reduced while the length of the internal encoding codeword and the redundancy cost are not changed.

Description

A data encoding method and related device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 28, 2023, with application number 202311295101.1 and application name “A data encoding method and related device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of optical communications, and in particular to a data encoding method and related devices. Background Art

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTNs) are developing toward high capacity and ultra-high speeds. Forward error correction (FEC) is used to correct errors in transmitted data, resolving transmission errors and recovering the original data from the received data.

[0004] In 400GZR scenarios, optical modules use CFEC as the error correction coding scheme, with staircase codes as the outer code and two-bit extended Hamming codes as the inner code. In future 1.6TZR scenarios, due to the significant increase in transmission rates, the power consumption issues faced by existing CFEC (Concatenated-FEC) schemes will become even more stringent, necessitating a more energy-efficient coding and decoding solution.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a data encoding method and related devices, which reduce the complexity of encoding without changing the length of the inner code word and the redundancy cost.

[0007] In the first aspect, an embodiment of the present application provides a data encoding method. Specifically, k consecutive bits in a first data stream that has been encoded by a first forward error correction (FEC) are first obtained, and the first FEC encoding can be regarded as an outer code encoding. Wherein, k is an odd number greater than 1, and the consecutive k bits include a bit set and a target bit, and the bit set includes (k-1) / 2 bit subsets, and each bit subset includes 2 bits. Next, the consecutive k bits are inner-coded to obtain a codeword, and the specific operation of the inner-code encoding is as follows: first, 2 bits in each bit subset are XORed to obtain 1 bit to obtain a total of (k-1) / 2 bits, and then the bit sequence including (k-1) / 2 bits and the target bit is subjected to a second FEC encoding to obtain p check bits. Wherein, the codeword after inner-code encoding includes consecutive k bits and p check bits, and p is an integer greater than or equal to 1.

[0008] In this embodiment, for the first data stream that has been outer-coded, every k consecutive bits in the first data stream need to be inner-coded, where k is an odd number greater than 1. Specifically, the remaining bits of the k bits, except for one target bit, are XORed in pairs to obtain a total of (k-1) / 2 bits. Furthermore, a second FEC encoding is performed on the bit sequence including (k-1) / 2 bits and the target bit to obtain p check bits. After the inner code encoding, the n bits in the inner code codeword include k consecutive bits and p check bits. It can be seen that the embodiment of the present application adopts a method of first XORing and then encoding. For example, the codeword processing of (128,119) can be achieved by using a (69,60) encoder, which reduces the complexity of the encoding while not changing the inner codeword length and redundancy cost.

[0009] In some possible implementations, the two bits in each bit subset are two adjacent bits in the continuous k bits. The method of selecting two adjacent bits for XOR is easier to implement and is conducive to standardization.

[0010] In some possible implementations, if the p check bits are located after k consecutive bits in the codeword, the target bit is the last bit among the k consecutive bits. Alternatively, if the p check bits are located before k consecutive bits in the codeword, the target bit is the first bit among the k consecutive bits. In other words, selecting the first or last bit in the k-bit information sequence as the target bit and arranging the check sequence of the p check bits immediately adjacent to the target bit is more conducive to achieving a uniform distribution of the information sequence and the check sequence in the inner codeword.

[0011] In some possible implementations, after performing inner code encoding on k consecutive bits to obtain a codeword, the method further includes: performing symbol mapping and polarization division on 8 bits from a 4-bit subset in a second data stream including at least one codeword to obtain a dual-polarization (DP)-16QAM symbol. The 4 bit subsets are respectively mapped to the X-polarization direction I component, X-polarization direction Q component, Y-polarization direction I component, and Y-polarization direction Q component of the DP-16QAM symbol via Gray mapping. That is, any component of the DP-16QAM symbol is obtained by Gray mapping from two bits of a bit subset participating in an exclusive-OR operation. Therefore, typically, at most one erroneous bit will occur in two bits mapped to the same PAM4 symbol, reducing the possibility of erroneous bits.

[0012] In some possible implementations, the second FEC code uses a finite field GF(2 m ) BCH coding or extended BCH coding with error correction of t bits enriches the coding methods that can be used for inner code coding. Among them, mt≤p, and That is, GF(2 m ) is not unique. For example, if the value of m is reduced by 1, the number of check bits can be reduced by t using this encoding method, thereby increasing the code rate and reducing the code overhead while keeping the length of the information unchanged.

[0013] In some possible implementations, k=119, and the second FEC encoding uses GF(2 m ) is GF(2 8 ) or GF(2 7 ), which improves the feasibility of inner code encoding in the scenario of k=119.

[0014] In some possible implementations, the length of the codeword is n, and the second FEC encoding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following:

[0015] n=133,k=119,GF(2 m )=GF(2 7 ), t=2, p=14;

[0016] n=135,k=119,GF(2 m )=GF(2 8 ), t=2, p=16.

[0017] In some possible implementations, the length of the codeword is n, and the second FEC encoding uses a finite field GF(2 m ) extended BCH code with t bits of error correction, p check bits including q bits of cyclic redundancy check (CRC) extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following:

[0018] n=128,k=119,GF(2 m )=GF(2 7 ), t=1, p=9, q=2;

[0019] n=134,k=119,GF(2 m )=GF(2 7 ), t=2, p=15, q=1;

[0020] n=135,k=119,GF(2 m )=GF(2 7 ), t=2, p=16, q=2;

[0021] n=136,k=119,GF(2 m )=GF(2 8 ), t=2, p=17, q=1;

[0022] n=137,k=119,GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

[0023] In the second aspect, an embodiment of the present application provides a data encoding method. Specifically, first obtain k consecutive bits in a first data stream that has undergone a first FEC encoding. The first FEC encoding can be regarded as an outer code encoding. Wherein, k is an integer greater than or equal to 3, the consecutive k bits include v bit subsets, each bit subset includes 3 bits, and v is an integer greater than or equal to 1. Next, the consecutive k bits are inner-coded to obtain a codeword. The specific operation of the inner-code encoding is as follows: first, XOR the 3 bits in each bit subset to obtain 1 bit to obtain a total of v bits, and then perform a second FEC encoding on the bit sequence including the v bits to obtain p check bits. The codeword after inner-code encoding includes k consecutive bits and p check bits, and p is an integer greater than or equal to 1.

[0024] In this embodiment, for the first data stream that has been encoded by the outer code, every k consecutive bits in the first data stream need to be encoded by the inner code, where k is an odd number greater than 1. Specifically, a total of v bits can be obtained by performing XOR on every 3 bits of the k bits. Furthermore, the v bits are subjected to a second FEC encoding to obtain p check bits. After the inner code encoding, the n bits in the inner code codeword include k consecutive bits and p check bits. It can be seen that the embodiment of the present application adopts a method of first XORing and then encoding. For example, the codeword processing of (128,119) can be achieved by using a (50,41) encoder, which reduces the complexity of the encoding while not changing the inner codeword length and redundancy cost.

[0025] In some possible implementations, the three bits in each bit subset are three consecutive bits among k consecutive bits. Selecting every three consecutive bits for XOR is easier to implement and is conducive to standardization.

[0026] In some possible implementations, k=v×3, that is, among the k bits, it is possible to perform XOR on every 3 bits, which has good practicality.

[0027] In some possible implementations, the k consecutive bits also include r target bits, where k = v × 3 + r, and r = 1 or 2. Performing a second FEC encoding on the bit sequence including v bits to obtain p parity bits includes performing a second FEC encoding on the bit sequence including v bits and r target bits to obtain p parity bits. In other words, this solution can also be applied to scenarios where k is not divisible by 3, expanding the application scenarios of this solution.

[0028] In some possible implementations, if the p check bits are located after k consecutive bits in the codeword, the target bits are the last r bits of the k consecutive bits. Alternatively, if the p check bits are located before k consecutive bits in the codeword, the target bits are the first r bits of the k consecutive bits. In other words, selecting the first r bits or the last r bits of the k-bit information sequence as the target bits and arranging the check sequence of the p check bits adjacent to the target bits is more conducive to achieving a uniform distribution of the information sequence and the check sequence in the inner codeword.

[0029] In some possible implementations, after performing inner code encoding on k consecutive bits to obtain a codeword, the method further includes: performing symbol mapping and polarization partitioning on 12 bits from a four-bit subset in a second data stream including at least one codeword to obtain a DP-64QAM symbol, wherein the four bit subsets are respectively mapped to an I component in the X polarization direction, a Q component in the X polarization direction, an I component in the Y polarization direction, and a Q component in the Y polarization direction of the DP-64QAM symbol via Gray mapping, with the X polarization direction and the Y polarization direction being orthogonal to each other. In other words, any component of the DP-64QAM symbol is obtained by Gray mapping from three bits of a bit subset that participate in an exclusive-OR operation. Therefore, typically, at most one erroneous bit will occur among the three bits mapped to the same PAM8 symbol, thereby reducing the possibility of bit errors.

[0030] In some possible implementations, the second FEC code uses a finite field GF(2 m ) BCH coding or extended BCH coding with error correction of t bits enriches the coding methods that can be used for inner code coding. Among them, mt≤p, and v+r≤2 m -1-p, that is, GF(2 m ) is not unique. For example, if the value of m is reduced by 1, the number of check bits can be reduced by t using this encoding method, thereby increasing the code rate and reducing the code overhead while keeping the length of the information unchanged.

[0031] In some possible implementations, k=119, and the second FEC encoding uses GF(2 m ) is GF(2 8 )、GF(2 7 ) or GF(2 6 ), which improves the feasibility of inner code encoding in the scenario of k=119.

[0032] In some possible implementations, the length of the codeword is n, and the second FEC encoding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following:

[0033] n=131,k=119,GF(2 m )=GF(2 6 ), t=2, p=12;

[0034] n=133,k=119,GF(2 m )=GF(2 7 ), t=2, p=14;

[0035] n=135,k=119,GF(2 m )=GF(2 8 ), t=2, p=16.

[0036] In some possible implementations, the length of the codeword is n, and the second FEC encoding uses a finite field GF(2 m ) extended BCH code with t bits of error correction, p check bits including q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following:

[0037] n=127,k=119,GF(2 m )=GF(2 6 ), t=1, p=8, q=2;

[0038] n=128,k=119,GF(2 m )=GF(2 7 ), t=1, p=9, q=2;

[0039] n=132,k=119,GF(2 m )=GF(2 6 ), t=2, p=13, q=1;

[0040] n=133,k=119,GF(2 m )=GF(2 6 ), t=2, p=14, q=2;

[0041] n=134,k=119,GF(2 m )=GF(2 7 ), t=2, p=15, q=1;

[0042] n=135,k=119,GF(2 m )=GF(2 7 ), t=2, p=16, q=2;

[0043] n=136,k=119,GF(2 m )=GF(2 8 ), t=2, p=17, q=1;

[0044] n=137,k=119,GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

[0045] In a third aspect, an embodiment of the present application provides a data encoding device, which includes: an acquisition unit and an encoding unit. The acquisition unit is used to: acquire k consecutive bits in a first data stream that has been encoded by a first FEC, where k is an odd number greater than 1, and the k consecutive bits include a bit set and a target bit, and the bit set includes (k-1) / 2 bit subsets, and each bit subset includes 2 bits. The encoding unit is used to: perform inner code encoding on the k consecutive bits to obtain a codeword. The encoding unit is specifically used to: perform XOR on the two bits in each bit subset to obtain 1 bit, so as to obtain a total of (k-1) / 2 bits; and perform a second FEC encoding on the bit sequence including (k-1) / 2 bits and the target bit to obtain p check bits. The codeword after inner code encoding includes k consecutive bits and p check bits, where p is an integer greater than or equal to 1.

[0046] In some possible implementations, the two bits in each bit subset are two adjacent bits in the consecutive k bits.

[0047] In some possible implementations, the p check bits are located after k consecutive bits in the codeword, and the target bit is the last bit among the k consecutive bits. Alternatively, the p check bits are located before k consecutive bits in the codeword, and the target bit is the first bit among the k consecutive bits.

[0048] In some possible embodiments, the data encoding device further includes a mapping unit, wherein the mapping unit is configured to perform symbol mapping and polarization division on 8 bits from 4 bit subsets in a second data stream including at least one codeword to obtain a DP-16QAM symbol, wherein the 4 bit subsets are respectively mapped to the X polarization direction I component, the X polarization direction Q component, the Y polarization direction I component, and the Y polarization direction Q component of the DP-16QAM symbol, and the X polarization direction and the Y polarization direction are orthogonal to each other.

[0049] In some possible implementations, the second FEC encoding uses GF(2 m ) BCH code or extended BCH code with t bits of error correction, where m and t are integers greater than or equal to 1, mt≤p, and

[0050] In some possible implementations, k=119, and the second FEC encoding uses GF(2 m ) is GF(2 8 ) or GF(2 7 ).

[0051] In some possible implementations, the length of the codeword is n, and the second FEC encoding adopts GF(2 m) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following:

[0052] n=133,k=119,GF(2 m )=GF(2 7 ), t=2, p=14;

[0053] n=135,k=119,GF(2 m )=GF(2 8 ), t=2, p=16.

[0054] In some possible implementations, the length of the codeword is n, and the second FEC encoding uses a finite field GF(2 m ) extended BCH code with t bits of error correction, p check bits including q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following:

[0055] n=128,k=119,GF(2 m )=GF(2 7 ), t=1, p=9, q=2;

[0056] n=134,k=119,GF(2 m )=GF(2 7 ), t=2, p=15, q=1;

[0057] n=135,k=119,GF(2 m )=GF(2 7 ), t=2, p=16, q=2;

[0058] n=136,k=119,GF(2 m )=GF(2 8 ), t=2, p=17, q=1;

[0059] n=137,k=119,GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

[0060] In a fourth aspect, an embodiment of the present application provides a data encoding device, which includes: an acquisition unit and an encoding unit. The acquisition unit is used to: acquire k consecutive bits in a first data stream that has undergone a first FEC encoding, k is an integer greater than or equal to 3, the k consecutive bits include v bit subsets, each bit subset includes 3 bits, and v is an integer greater than or equal to 1. The encoding unit is used to: perform inner code encoding on the k consecutive bits to obtain a codeword. The encoding unit is specifically used to: perform XOR on the three bits in each bit subset to obtain 1 bit, so as to obtain a total of v bits; and perform a second FEC encoding on the bit sequence including v bits to obtain p check bits. The codeword after inner code encoding includes k consecutive bits and p check bits, and p is an integer greater than or equal to 1.

[0061] In some possible implementations, the 3 bits in each bit subset are 3 consecutive bits among the consecutive k bits.

[0062] In some possible implementations, k=v×3.

[0063] In some possible implementations, the consecutive k bits also include r target bits, k=v×3+r, r=1 or 2, and the encoding unit is specifically used to: perform a second FEC encoding on the bit sequence including v bits and r target bits to obtain p check bits.

[0064] In some possible implementations, if the p check bits are located after k consecutive bits in the codeword, the target bits are the last r bits of the k consecutive bits. Alternatively, if the p check bits are located before k consecutive bits in the codeword, the target bits are the first r bits of the k consecutive bits.

[0065] In some possible embodiments, the data encoding device further includes a mapping unit, which is used to: perform symbol mapping and polarization division on 12 bits from 4 bit subsets in a second data stream including at least one codeword to obtain 1 DP-64QAM symbol, wherein the 4 bit subsets are respectively mapped to the X polarization direction I component, X polarization direction Q component, Y polarization direction I component and Y polarization direction Q component of the DP-64QAM symbol, and the X polarization direction and the Y polarization direction are orthogonal to each other.

[0066] In some possible implementations, the second FEC encoding uses GF(2 m ) BCH code or extended BCH code with error correction of t bits, where m and t are integers greater than or equal to 1, mt≤p, and v+r≤2 m -1-p.

[0067] In some possible implementations, k=119, and the second FEC encoding uses GF(2 m ) is GF(2 8 )、GF(2 7 ) or GF(2 6 ).

[0068] In some possible implementations, the length of the codeword is n, and the second FEC encoding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following:

[0069] n=131,k=119,GF(2 m )=GF(2 6 ), t=2, p=12;

[0070] n=133,k=119,GF(2 m )=GF(2 7 ), t=2, p=14;

[0071] n=135,k=119,GF(2 m )=GF(2 8 ), t=2, p=16.

[0072] In some possible implementations, the length of the codeword is n, and the second FEC encoding uses a finite field GF(2 m ) extended BCH code with t bits of error correction, p check bits including q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following:

[0073] n=127,k=119,GF(2 m )=GF(2 6 ), t=1, p=8, q=2;

[0074] n=128,k=119,GF(2 m )=GF(2 7 ), t=1, p=9, q=2;

[0075] n=132,k=119,GF(2 m )=GF(2 6 ), t=2, p=13, q=1;

[0076] n=133,k=119,GF(2 m )=GF(2 6), t=2, p=14, q=2;

[0077] n=134,k=119,GF(2 m )=GF(2 7 ), t=2, p=15, q=1;

[0078] n=135,k=119,GF(2 m )=GF(2 7 ), t=2, p=16, q=2;

[0079] n=136,k=119,GF(2 m )=GF(2 8 ), t=2, p=17, q=1;

[0080] n=137,k=119,GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

[0081] In the fifth aspect, an embodiment of the present application provides a chip, which includes a processor and a memory, the memory and the processor are interconnected through lines, instructions are stored in the memory, and the processor is used to execute the method described in any embodiment of the first aspect and the second aspect.

[0082] In a sixth aspect, an embodiment of the present application provides a data transmission system, which includes a data sending device and a data receiving device, wherein the data sending device is used to execute the method described in any embodiment of the first aspect and the second aspect and send data to the data receiving device, and the data receiving device is used to perform operations such as decoding on the received data.

[0083] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a computer, the method described in any one of the embodiments of the first and second aspects is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application;

[0085] FIG2 is a schematic diagram of another communication system used in an embodiment of the present application;

[0086] FIG3 is a flow chart of a data encoding method provided in an embodiment of the present application;

[0087] FIG4( a ) is a schematic diagram of an implementation method of performing an XOR operation on every two bits in an embodiment of the present application;

[0088] FIG4( b ) is a schematic diagram of another implementation of performing an XOR operation on every two bits in an embodiment of the present application;

[0089] FIG4( c ) is a schematic diagram of an implementation method of performing an XOR operation on every three bits in an embodiment of the present application;

[0090] FIG5 is a schematic diagram of an implementation method of internal code encoding in an embodiment of the present application;

[0091] FIG6 is a schematic diagram of a first application scenario of internal code encoding in an embodiment of the present application;

[0092] FIG7 is a schematic diagram of a second application scenario of internal code encoding in an embodiment of the present application;

[0093] FIG8 is a schematic diagram of a third application scenario of internal code encoding in an embodiment of the present application;

[0094] FIG9 is a schematic diagram of a fourth application scenario of internal code encoding in an embodiment of the present application;

[0095] FIG10 is a schematic diagram of a fifth application scenario of internal code encoding in an embodiment of the present application;

[0096] FIG11 is a schematic diagram of a sixth application scenario of internal code encoding in an embodiment of the present application;

[0097] FIG12 is a schematic diagram of a seventh application scenario of internal code encoding in an embodiment of the present application;

[0098] FIG13 is a schematic structural diagram of a data encoding device according to an embodiment of the present application;

[0099] FIG14 is another structural diagram of the data encoding device in an embodiment of the present application. DETAILED DESCRIPTION

[0100] The embodiment of the present application provides a data encoding method and related devices, which reduce the complexity of encoding without changing the inner code word length and redundancy cost. It should be noted that the terms "first", "second", etc. in the specification of this application, the claims, and the above-mentioned drawings are used to distinguish similar objects, rather than to limit a specific order or precedence. It should be understood that the above-mentioned terms can be interchangeable under appropriate circumstances so that the embodiments described in this application can be implemented in a sequence other than the content described in this application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or devices.

[0101] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application. As shown in FIG1 , the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches or routers, and the transmitting device 01 is also called a client-side chip (host chip) located at the transmitting end, and the receiving device 05 is also called a client-side chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client-side chip is sometimes also called a client-side device (host device). The transmitting device 01 and the transmitting processing module 02 can be connected via an attachment unit interface (AUI), and the receiving device 05 and the receiving processing module 04 can be connected via an AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module may be an 800ZR module (a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in the communication system may support bidirectional transmission or unidirectional transmission, without limitation herein.

[0102] FIG2 is a schematic diagram of another communication system used in an embodiment of the present application. As shown in FIG2 , at the transmitting end, a signal source provides a data stream to be transmitted; a transmitting data processor receives the data stream and performs data processing including encoding, interleaving, and modulation on it to obtain a symbol data stream, which is then sent to a transmitting signal processor for framing. The signal is then transmitted through a channel to a receiving device. After receiving a distorted signal caused by noise or other damage in the channel, the receiving device sends it to a receiving signal processor for dispersion compensation, synchronization, phase recovery, and other operations. The signal is then sent to a receiving data processor for demodulation, deinterleaving, and decoding. The original data is then recovered and sent to the destination. The transmitting data processing and transmitting signal processing shown in FIG2 can be applied to the transmitting processing module 02 shown in FIG1 , and the receiving data processing and receiving signal processing shown in FIG2 can be applied to the receiving processing module 04 shown in FIG1 .

[0103] It should be understood that the distinction between "inner" in inner code and "outer" in outer code is based solely on the distance between the entity performing the data operations and the channel transmission medium. The entity performing the inner code operations is closer to the channel transmission medium, while the entity performing the outer code operations is farther away. In the embodiment of this application, using Figure 1 as an example, the transmitting processing module 02 encodes the data twice before sending it to the channel transmission medium. The data encoded first by the transmitting processing module 02 is farther away from the channel transmission medium, while the data encoded later by the transmitting processing module 02 is closer to the channel transmission medium. Therefore, the data encoded first by the transmitting processing module 02 is referred to as outer-coded data, while the data encoded later by the transmitting processing module 02 is referred to as inner-coded data. Correspondingly, the data decoded first by the receiving processing module 04 is referred to as inner-coded data, while the data decoded later by the receiving processing module 04 is referred to as outer-coded data. In one possible implementation, both the inner and outer codes described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting end processing module 02 may use staircase code for outer code encoding, use Hamming code for inner code encoding, or use Bose-Chaudhuri-Hocquenghem (BCH) code for inner code encoding.

[0104] It should be noted that the above content is an exemplary description of the application scenarios of the data encoding method provided in the embodiment of the present application, and does not constitute a limitation on the application scenarios of the data encoding method. It is known to those skilled in the art that as business needs change, its application scenarios can be adjusted according to application needs, and the embodiments of the present application do not list them one by one. The following mainly introduces the data encoding method applied to the data sending end. The data decoding method applied to the receiving end can be understood as the inverse operation of the data encoding method. On the basis of the determination of the data encoding method, the data decoding method is also clear, and this application will no longer provide a detailed introduction to the data decoding method.

[0105] Figure 3 is a schematic flow chart of a data encoding method provided in an embodiment of the present application. This data encoding method includes the following steps, which are described in detail below. It should be understood that, for ease of explanation, the first FEC encoding described below is equivalent to the outer code encoding described above. The inner code encoding provided in this embodiment of the present application includes two operations: grouped XOR and second FEC encoding. The following description can be understood based on this.

[0106] 101. Obtain k consecutive bits from a first data stream that has undergone first FEC encoding.

[0107] In the embodiments of the present application, the k consecutive bits in the first data stream are the k information bits to be encoded by the inner code. It should be understood that, for the inner code, the k information bits to be encoded by the inner code may include information bits and check bits in the outer code codeword. Considering that the embodiments of the present application primarily introduce inner code encoding, the information bits appearing below can be understood as information bits encoded by the inner code. It should also be understood that the present application does not limit the specific implementation of the outer code encoding. As an example, the outer code encoding can specifically adopt staircase (512, 510) encoding.

[0108] 102. Perform an XOR operation on every s bits of k consecutive bits of the first data stream to obtain a sequence to be encoded.

[0109] It should be understood that, since the inner code codeword after inner code encoding, the consecutive s bits will be mapped into a symbol through Gray mapping and sent to the channel for transmission, under non-extremely harsh channel conditions, only one bit error will occur in these consecutive s bits. Symbol mapping methods include but are not limited to Quadrature Phase Shift Keying (QPSK) and Quadrature Amplitude Modulation (QAM), and further polarization symbol division is performed to obtain dual-polarization (DP) symbols, such as DP-QPSK, DP-8QAM, DP-16QAM, DP-32QAM and DP-64QAM. As an example, when DP-16QAM is used, two consecutive bits in the inner codeword will be mapped to the same PAM4 symbol. As another example, when DP-64QAM is used, three consecutive bits in the inner codeword will be mapped to the same PAM8 symbol. Therefore, the embodiment of the present application considers performing an XOR operation on every two or three bits of k consecutive bits of the first data stream before encoding. The following takes k=119 as an example to introduce several possible XOR operation methods.

[0110] FIG4(a) is a schematic diagram of an implementation method of performing an XOR operation on every two bits in an embodiment of the present application. As shown in FIG4(a), in a possible implementation method, since 119 is an odd number, there is one bit in the information sequence of 119 bits that cannot be subjected to a pairwise XOR operation. This bit is referred to as the target bit. It should be understood that the target bit can be any bit in the information sequence. Typically, the target bit is the first bit or the last bit in the information sequence. For example, as shown in FIG4(a), the target bit is the last bit in the information sequence. 118For the sake of convenience, the remaining 118 bits in the information sequence except the target bit are referred to as a bit set. The bit set includes 59 bit subsets, and each bit subset includes 2 bits. Then, the 2 bits in each bit subset are XORed to obtain 1 bit, so a total of 59 bits can be obtained, as shown in Figure 4(a) b0-b 58 In this embodiment, the two bits in each bit subset are two adjacent bits in the 119-bit information sequence. As shown in FIG4(a), a0 and a1 are XORed to obtain b0, a2 and a3 are XORed to obtain b1, ..., a 116 and a 117 XOR to get b 58 . Furthermore, the target bit a in the information sequence 118 As one of the bits b in the sequence to be encoded 59 , the sequence to be encoded includes b0-b obtained by XOR 58 and b 59 .

[0111] FIG4(b) is a schematic diagram of another embodiment of the present application for performing an XOR operation on every two bits. Different from the embodiment shown in FIG4(a), in another possible embodiment, the two bits in each bit subset can also be any two non-adjacent bits in the 119-bit information sequence. The specific method is not limited here. For example, as shown in FIG4(b), a0 and a 59 XOR to get b0, a2 and a 60 XOR to get b1, ..., a 58 and a 117 XOR to get b 58 . Furthermore, the target bit a in the information sequence 118 As one of the bits b in the sequence to be encoded 59 , the sequence to be encoded includes b0-b obtained by XOR 58 and b 59 .

[0112] It should be noted that based on the implementation of the 2-bit XOR shown in Figures 4(a) and 4(b), this application does not limit the specific value of k. If k is an odd number greater than 1, then the information sequence including k bits will definitely contain a target bit that does not participate in the XOR. If k is an even number, then all k bits in the information sequence can be XORed in pairs.

[0113] Figure 4(c) is a schematic diagram of an implementation method of performing an XOR operation on every 3 bits in an embodiment of the present application. As shown in Figure 4(c), in another possible implementation method, since the remainder when 119 is divided by 3 is 2, there are 2 bits in the information sequence of 119 bits that cannot be subjected to a 3-bit XOR operation. These 2 bits are referred to as target bits here. It should be understood that these 2 target bits can be any 2 bits in the information sequence. Usually, these 2 target bits are the first 2 bits or the last 2 bits in the information sequence. For example, as shown in Figure 4(c), these 2 target bits are the last 2 bits in the information sequence. 117 and a 118 For the sake of convenience, the remaining 117 bits in the information sequence except the target bit are referred to as a bit set. The bit set includes 39 bit subsets, and each bit subset includes 3 bits. Then, the 3 bits in each bit subset are XORed to obtain 1 bit, so that a total of 39 bits can be obtained, as shown in Figure 4(c) b0-b 38 In this embodiment, the 3 bits in each bit subset are 3 consecutive bits in the 119-bit information sequence, as shown in FIG4(c), a0, a1 and a2 are XORed to obtain b0, ..., a 114 ,a 115 and a 116 XOR to get b 38 . Furthermore, the target bit a in the information sequence 117 and a 118 As two bits b in the sequence to be encoded 39 and b 40 , the sequence to be encoded includes b0-b obtained by XOR 38 ,b 39 and b 40 .

[0114] It should be noted that, based on the implementation of the 3-bit XOR shown in FIG4(c), this application does not limit the specific value of k. For example, k can also be an integer multiple of 3, in which case all k bits of the information sequence can be subjected to a 3-bit XOR. For another example, k may be divided by 3 with a remainder of 1, in which case one of the k bits of the information sequence is the target bit that does not participate in the XOR, and all other bits can be subjected to a 3-bit XOR.

[0115] 103. Perform a second FEC encoding on the sequence to be encoded.

[0116] Figure 5 is a schematic diagram of an implementation of inner code encoding in an embodiment of the present application. As shown in Figure 5, the sequence to be encoded refers to the bit sequence to be subjected to the second FEC encoding. The sequence to be encoded includes the bits obtained by the XOR operation in step 102. Furthermore, the sequence to be encoded may also include target bits that are not subjected to the XOR operation. The specific situation depends on the value of k. Please refer to the relevant description of step 102. Here, k = 119 is used as an example. The second FEC encoding of the sequence to be encoded generates a check sequence including p check bits. For the inner code word obtained by the inner code encoding, the inner code word includes a k-bit information sequence and p check bits. That is, the length of the inner code word is n = k + p, where p is an integer greater than or equal to 1. In other words, the second FEC encoding performed on the sequence to be encoded is only used to generate the check sequence. The inner code word obtained by encoding still includes a k-bit information sequence. For example, if the target bit is the last bit in the sequence to be encoded, the check sequence in the inner code word is located after the information sequence. For another example, if the target bit is the first bit in the sequence to be encoded, the check sequence in the inner code word is located before the information sequence. It should be noted that the above-mentioned second FEC coding can adopt BCH coding or extended BCH coding, wherein the p check bits in the inner code codeword using BCH coding do not include a cyclic redundancy check (CRC) extended check bit, and the p check bits in the inner code codeword using extended BCH coding include 1-bit or 2-bit CRC extended check bits.

[0117] In a possible implementation manner, for a coding scheme using 2-bit XOR and 3-bit XOR, the second FEC coding may specifically use GF(2 m ) BCH code with t bits of error correction, where m and t are both integers greater than or equal to 1. GF refers to a finite field, also known as a Galois Field, 2 m represents the order of the finite field. The second FEC code has an error correction capability of t bits, meaning that an inner codeword can correct up to t bits of errors. If the P parity bits do not include the CRC extended check bit, then p = m × t; if the P parity bits include a 1-bit CRC extended check bit, then p = m × t + 1; if the P parity bits include a 2-bit CRC extended check bit, then p = m × t + 2.

[0118] In another possible implementation, for a 2-bit XOR encoding scheme, if Then the second FEC code can also use GF(2 m-1) BCH codeword to further simplify the inner code encoding scheme. Among them, if the P check bits do not include the CRC extended check bit, then p = (m-1) × t; if the P check bits include 1 bit of CRC extended check bit, then p = (m-1) × t + 1; if the P check bits include 2 bits of CRC extended check bits, then p = (m-1) × t + 2. It should be understood that when the second FEC encoding adopts GF(2 m ) is coded as n0. When the second FEC code is GF(2 m-1 ) is a BCH codeword, the length of the inner codeword is recorded as n1, n0 = k + (m-1)t = n1-t. In this case, the original (n0, k) codeword is replaced by the (n1, k) codeword. In other words, using this encoding method can reduce the number of check bits by t, thereby increasing the codeword rate and reducing the codeword overhead while keeping the information length unchanged.

[0119] In another possible implementation, for a coding scheme using 3-bit XOR, k bits are recorded as including v bit subsets, each bit subset includes 3 bits, v is an integer greater than or equal to 1, and the number of CRC extended check bits included in the p check bits is recorded as r. If v+r≤2 m-1 -1-p, the second FEC code can also use GF(2 m-1 ) to further simplify the inner code encoding scheme. Among them, if the P check bits do not include the CRC extended check bit, then p = (m-1) × t; if the P check bits include 1 bit of CRC extended check bit, then p = (m-1) × t + 1; if the P check bits include 2 bits of CRC extended check bits, then p = (m-1) × t + 2. If v + r ≤ 2 m-2 -1-p, the second FEC code can also use GF(2 m-2 ) to further simplify the inner code encoding scheme. If the P check bits do not include the CRC extended check bit, then p = (m-2) × t; if the P check bits include a 1-bit CRC extended check bit, then p = (m-2) × t + 1; if the P check bits include a 2-bit CRC extended check bit, then p = (m-2) × t + 2.

[0120] 104. Perform symbol mapping and polarization division on the second data stream.

[0121] It should be understood that the second data stream includes at least one inner codeword encoded by an inner code. As an example, for a coding scheme using a 2-bit XOR, symbol mapping and polarization division are performed on every 8 bits in the second data stream to obtain a DP-16QAM symbol. The 8 bits involved in the symbol mapping and polarization division are from the 4 bit subsets in the information sequence that participate in the XOR operation. As another example, for a coding scheme using a 3-bit XOR, symbol mapping and polarization division are performed on every 12 bits in the second data stream to obtain a DP-64QAM symbol. The 12 bits involved in the symbol mapping and polarization division are from the 4 bit subsets in the information sequence that participate in the XOR operation. It should be understood that the 4 bit subsets are respectively mapped to the X-polarization direction I-phase component, X-polarization direction Q-phase component, Y-polarization direction I-phase component, and Y-polarization direction Q-phase component of the DP-16QAM symbol or DP-64QAM symbol. The X polarization direction and the Y polarization direction are orthogonal to each other. That is, any component of a DP-16QAM symbol is mapped to two bits of a bit subset participating in an XOR operation, and any component of a DP-64QAM symbol is mapped to three bits of a bit subset participating in an XOR operation. It should also be understood that the four bit subsets mapped to the DP-16QAM symbol or DP-64QAM symbol can come from the same codeword or different codewords, and this is not limited here.

[0122] It should be noted that, taking the information sequence length of the inner code encoding as 119 bits as an example, the embodiment of the present application provides a variety of possible inner code encoding parameters. When the DP-16QAM scheme is adopted, the specific parameters are shown in Table 1 below, and when the DP-64QAM scheme is adopted, the specific parameters are shown in Table 2 below. Among them, n represents the length of the inner code codeword, k represents the information sequence length of the inner code codeword, w represents the coding length (including the sequence to be encoded and the check sequence), f represents the length of the sequence to be encoded, GF(2 m ) represents a finite field. t represents the error correction capability of the inner code. OH represents the overhead of the inner code codeword, which refers to the ratio of the length of the check sequence to the length of the information sequence in the inner code codeword, that is, OH = (nk) / k. The "no extension" in the remarks refers to the absence of a CRC extended check bit in the check sequence, the "single-bit extension" in the remarks refers to the presence of a 1-bit CRC extended check bit in the check sequence, and the "double-bit extension" in the remarks refers to the presence of a 2-bit CRC extended check bit in the check sequence.

[0123] Table 1

[0124] For the solutions provided in Table 1, Solution 1 is defined in the finite field GF(27 ) error correction capability t = 1 code, the complexity of encoding and decoding can be reduced under the existing technology through the XOR method. The actual encoded codeword in scheme 5-7 is based on the finite field GF(2 8 ) on the system BCH (255, 239) with t = 2, the codeword is shortened by 179 bits to obtain the codeword of the actual code BCH (76, 60) of Scheme 5, which has a stronger coding gain than Scheme 1. On the basis of Scheme 5, by adding single-bit and double-bit CRC extension check bits respectively, the codewords of the actual code BCH (77, 60) of Scheme 6 and the actual code BCH (78, 60) of Scheme 7 can be obtained, which can further improve the coding gain on the basis of Scheme 5. The actual coding codewords in Schemes 2-4 are based on the finite field GF (2 7 ) on the system BCH (127, 113) with t = 2, the codeword is shortened by 53 bits to obtain the codeword of the actual code BCH (74, 60) of Scheme 2. Based on Scheme 2, adding single-bit and double-bit CRC extension check bits respectively can obtain the codewords of the actual code BCH (75, 60) of Scheme 3 and the actual code BCH (76, 60) of Scheme 4. Compared with Schemes 5-7, Schemes 2-4 meet the above-mentioned requirements. Therefore, the original finite field GF(2 8 ) is replaced by a low-complexity finite field GF(2 7 ).

[0125] Table 2

[0126] For the schemes provided in Table 2, the actual encoding of schemes 1 and 2 is defined in the finite field GF(2 6 ) and GF(2 7 ) has an error correction capability of t = 1. The actual coding of schemes 3-5 is a finite field GF(2 6 ) on the BCH code with error correction capability t = 2, the actual encoding of schemes 6-8 is the finite field GF(2 7 ) on the BCH code with error correction capability t = 2, the actual encoding of candidate schemes 9-11 is the finite field GF(2 8 ) on a BCH code with error correction capability t = 2.

[0127] It should be noted that in some possible scenarios, the inner code coding scheme in the DP-16QAM modulation mode is compatible with the inner code coding scheme in the DP-64QAM modulation mode. Table 3 below provides parameters for inner code coding that are compatible with the two modulation modes. In actual applications, the encoders corresponding to the two modulation modes can be integrated together so that they can be flexibly selected according to actual needs.

[0128] Table 3

[0129] Several specific inner code coding embodiments are introduced below in conjunction with relevant parameters of the inner code coding.

[0130] Example 1: In DP-16QAM modulation mode, the inner code is (128,119)+GF(2 7 ) is encoded on (69,60).

[0131] FIG6 is a schematic diagram of the first application scenario of the inner code encoding in the embodiment of the present application. As shown in FIG6, the inner code encoding codeword length is 128 bits, the information sequence length is 119 bits, and the check sequence length is 9 bits. First, 118 bits are selected from the 119-bit information sequence A to form a sequence A', which is recorded as A'=[a'0,a'1,...a' 117 ], A' can be any 118 bits in A. To facilitate subsequent channel interleaving and modulation, the first 118 bits in A can be selected as A', that is, A'=[a0,a1,…a 117 Then, two adjacent bits in A' are grouped together and XORed to obtain 59 bits [b0, b1, ..., b 58 ]. At the same time, the bits in A that are not selected into A' are recorded as A\A', and A\A' will skip the group XOR operation with b0~b 58 Combined together to form the sequence to be encoded B[0:59]=[b0,b1,…,b 59 ], which means as follows: Then, the coded sequence is encoded using the extended Hamming code (69,60) to generate a 9-bit parity bit [p0, p1, ..., p8]. The extended Hamming code (69,60) is constructed over the finite field GF(2 7 ) is obtained by shortening 59 bits. Finally, the generated codeword C[0:127]=[c0,c1,…,c 127 ] can be expressed as It should be understood that in the above process, SD-FEC (128, 119) is still the systematic code, that is, the (69, 60) code is only used to generate parity bits and does not participate in the actual transmission.

[0132] Example 2: In DP-16QAM modulation mode, the inner code is (133,119)+GF(2 7 ) is encoded at (74,60).

[0133] FIG7 is a schematic diagram of the second application scenario of the inner code encoding in the embodiment of the present application. As shown in FIG7, the inner code encoding codeword length is 133 bits, the information sequence length is 119 bits, and the check sequence length is 14 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is encoded using BCH(74,60) to generate a 14-bit check bit [p0, p1, ..., p 13 ]. Among them, BCH(74,60) is constructed on the finite field GF(2 7 ) on t = 2 BCH (127,113), obtained by shortening 53 bits. GF ​​(2 7 The generating polynomial of BCH(74,60) on ) can be expressed as: g(x)=M1(x)M3(x)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1) =x 14 +x 9 +x 8 +x 6 +x 5 +x 4 +x 2 +x+1

[0134] Among them, M1(x) and M3(x) correspond to α respectively. 1 With α 3 The minimum polynomial of α is a finite field GF(2 7 ) primitive element. The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 14 m(x) is divided by g(x) using modulo 2 division to obtain the remainder polynomial r(x). The coefficients of each term in r(x) are the check sequence P[0:13]. Finally, the information sequence A and the check sequence P form the complete codeword of the inner code (133,119), denoted as C[0:132] = [c0,c1,…,c 132 ], which can be expressed as

[0135] Example 3: In DP-16QAM modulation mode, the inner code is (134,119)+GF(2 7 ) is encoded at (75,60).

[0136] FIG8 is a schematic diagram of the third application scenario of the inner code encoding in the embodiment of the present application. As shown in FIG8, the inner code encoding codeword length is 134 bits, the information sequence length is 119 bits, and the check sequence length is 15 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is extended by BCH(75,60) to generate a 15-bit check bit [p0, p1, ..., p 14 ] Among them, the extended BCH (75, 60) is obtained by adding a single-bit parity check on the basis of BCH (74, 60) in Example 2. GF (2 7 The generator polynomial of the extended BCH (75,60) on ) can be expressed as: g1(x)=g(x)(x+1)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)(x+1) =x 15 +x 14 +x 10 +x 8 +x 7 +x 4 +x 3 +1

[0137] The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 15 m(x) is divided by g1(x) using modulo 2 division to obtain the remainder polynomial r(x). The coefficients of each term in r(x) are the check sequence P[0:14]. Finally, the information sequence A and the check sequence P form the complete codeword of the inner code (134,119), denoted as C[0:133] = [c0,c1,…,c 133 ], which can be expressed as

[0138] Example 4: In DP-16QAM modulation mode, the inner code is (135,119)+GF(2 7 ) is encoded at (76,60).

[0139] FIG9 is a schematic diagram of the fourth application scenario of the inner code encoding in the embodiment of the present application. As shown in FIG9, the inner code encoding codeword length is 135 bits, the information sequence length is 119 bits, and the check sequence length is 16 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is extended by BCH(76,60) encoding to generate a 16-bit check bit [p0, p1, ..., p 15] Among them, the extended BCH (76, 60) is obtained by adding a double-bit parity check on the basis of BCH (74, 60) in Example 2. GF (2 7 The generator polynomial of the extended BCH (76,60) on ) can be expressed as: g2(x)=g(x)(x 2 +1)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)(x 2 +1) =x 16 +x 14 +x 11 +x 10 +x 9 +x 7 +x 5 +x 3 +x+1

[0140] The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 16 m(x) is divided by g2(x) using modulo 2 division to obtain the remainder polynomial r(x). The coefficients of each term in r(x) are the check sequence P[0:15]. Finally, the information sequence A and the check sequence P form the complete codeword of the inner code (135,119), denoted as C[0:134] = [c0,c1,…,c 134 ], which can be expressed as

[0141] Example 5: In DP-16QAM modulation mode, the inner code is (135,119)+GF(2 8 ) is encoded at (76,60).

[0142] As shown in FIG9 , the inner code codeword length is 135 bits, the information sequence length is 119 bits, and the check sequence length is 16 bits. First, the information sequence A[0:118] is used to generate the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is encoded using BCH(76,60) to generate a 16-bit check bit [p0, p1, …, p 15 ]. Among them, BCH(76,60) is constructed on the finite field GF(2 8 ) is obtained by shortening 179 bits. 8 The generating polynomial of BCH(76,60) on ) can be expressed as: g3(x)=M1(x)M3(x)=(x 8 +x 4+x 3 +x 2 +1)(x 8 +x 6 +x 5 +x 4 +x 2 +x+1) =x 16 +x 14 +x 13 +x 11 +x 10 +x 9 +x 8 +x 6 +x 5 +x+1

[0143] The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 16 m(x) is divided by g3(x) using modulo 2 division to obtain the remainder polynomial r(x). The coefficients of each term in r(x) are the check sequence P[0:15]. Finally, the information sequence A and the check sequence P form the complete codeword of the inner code (135,119), denoted as C[0:134] = [c0,c1,…,c 134 ], which can be expressed as

[0144] Example 6: In DP-16QAM modulation mode, the inner code is (136,119)+GF(2 8 ) is encoded at (77,60).

[0145] FIG10 is a schematic diagram of the fifth application scenario of the inner code encoding in the embodiment of the present application. As shown in FIG10, the inner code encoding codeword length is 136 bits, the information sequence length is 119 bits, and the check sequence length is 17 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is extended by BCH(77,60) encoding to generate a 17-bit check bit [p0, p1, ..., p 16 ]. The extended BCH (77, 60) is obtained by adding a single-bit parity check on the basis of BCH (76, 60) in Example 5. GF (2 8 The generator polynomial of the extended BCH (77,60) on ) can be expressed as: g4(x)=g3(x)(x+1)=(x 8 +x 4 +x 3 +x 2 +1)(x 8 +x 6 +x 5 +x4 +x 2 +x+1)(x+1) =x 17 +x 16 +x 15 +x 13 +x 12 +x 8 +x 7 +x 5 +x 2 +1

[0146] The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 17 m(x) is divided by g4(x) using modulo 2 division to obtain the remainder polynomial r(x). The coefficients of each term in r(x) are the check sequence P[0:16]. Finally, the information sequence A and the check sequence P form the complete codeword of the inner code (136,119), denoted as C[0:135] = [c0,c1,…,c 135 ], which can be expressed as

[0147] Example 7: In DP-16QAM modulation mode, the inner code is (137,119)+GF(2 8 ) is encoded at (78,60).

[0148] FIG11 is a schematic diagram of the sixth application scenario of the inner code encoding in the embodiment of the present application. As shown in FIG11, the inner code encoding codeword length is 137 bits, the information sequence length is 119 bits, and the check sequence length is 18 bits. First, the information sequence A[0:118] generates the sequence to be encoded B[0:59] in the same way as in Example 1. Then, the sequence to be encoded is extended by BCH(78,60) encoding to generate 18-bit check bits [p0, p1, ..., p 17 ] Among them, the extended BCH (78, 60) is obtained by adding a double-bit parity check on the basis of BCH (76, 60) in Example 5. GF (2 8 The generator polynomial of the extended BCH (78,60) on ) can be expressed as: g5(x)=g3(x)(x 2 +1) =(x 8 +x 4 +x 3 +x 2 +1)(x 8 +x 6 +x 5 +x 4 +x 2 +x+1)(x 2 +1) =x 18 +x15 +x 14 +x 12 +x 9 +x 7 +x 6 +x 5 +x 3 +x 2 +x+1

[0149] The 60 bits to be encoded are used as coefficients of a polynomial with a maximum degree of 59 to obtain the information polynomial m(x). 18 m(x) is divided by g5(x) using modulo 2 division to obtain the remainder polynomial r(x). The coefficients of each term in r(x) are the check sequence P[0:17]. Finally, the information sequence A and the check sequence P form the complete codeword of the inner code (137,119), denoted as C[0:136] = [c0,c1,…,c 136 ], which can be expressed as

[0150] Example 8: In DP-64QAM modulation mode, the inner code is (128,119)+GF(2 7 ) is encoded on (50,41).

[0151] FIG12 is a schematic diagram of the seventh application scenario of the inner code encoding in the embodiment of the present application. As shown in FIG12, the inner code encoding codeword length is 128 bits, the information sequence length is 119 bits, and the check sequence length is 9 bits. First, 117 bits are selected from the 119-bit information sequence A to form a sequence A', which is recorded as A'=[a'0,a'1,...a' 116 ], A' can be any 117 bits in A. To facilitate subsequent channel interleaving and modulation, the first 117 bits in A can be selected as A', that is, A'=[a0,a1,…a 116 Then the three consecutive bits in A' are grouped together and XORed to obtain 39 bits [b0, b1, ..., b 38 ]. At the same time, the bits in A that are not selected into A' are recorded as A\A', and A\A' will skip the group XOR operation with b0~b 38 Combined together to form the sequence to be encoded B[0:40]=[b0,b1,…,b 40 ], which means as follows: Then, the coded sequence is encoded using the extended Hamming code (50,41) to generate a 9-bit parity bit [p0,p1,…,p8]. The extended Hamming code (50,41) is constructed over the finite field GF(2 7) is obtained by shortening 79 bits. Finally, the generated codeword C[0:127]=[c0,c1,…,c 127 ] can be expressed as

[0152] Figure 13 is a schematic structural diagram of a data encoding device in an embodiment of the present application. As shown in Figure 13, the data encoding device includes an acquisition unit 201, an encoding unit 202, and a mapping unit 203. The acquisition unit 201 is used to perform the operations of step 101 above, the encoding unit 202 is used to perform the operations of steps 102 and 103 above, and the mapping unit 203 is used to perform the operations of step 104 above. It should be understood that the data encoding device provided in this application can also be implemented in other ways. For example, the unit division in the above device is only a logical functional division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of the present application can be integrated into a processing unit, or can be independent physical units, or two or more functional units can be integrated into a processing unit. The above-mentioned integrated units can be implemented in the form of hardware or software functional units.

[0153] Figure 14 is another structural diagram of the data encoding device in an embodiment of the present application. As shown in Figure 14, the data encoding device includes a processor 301 and a transceiver 302. The processor 301 and the transceiver 302 are interconnected via a line. Specifically, the transceiver 302 is used to perform data transmission and reception operations, and the processor 301 is used to perform other operations other than data transmission and reception. In one possible embodiment, the processor 301 may include the encoding unit 202 and the mapping unit 203 shown in Figure 13 above, and the transceiver 302 includes the acquisition unit 201 shown in Figure 13 above. Optionally, the data encoding device may further include a memory 303, wherein the memory 303 is used to store program instructions and data.

[0154] The present application also provides a chip. This chip integrates circuitry and one or more interfaces for implementing the functions of the processor 301 described above. When the chip integrates memory, it can perform the method steps of any one or more of the aforementioned embodiments. When the chip does not integrate memory, it can be connected to an external memory via an interface. The chip implements the actions performed by the transmitting device or receiving device in the aforementioned embodiments based on program code stored in the external memory.

[0155] Finally, it should be noted that the above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A data encoding method, characterized in that: include: Acquire k consecutive bits in a first data stream that has been encoded by a first forward error correction (FEC), where k is an odd number greater than 1, and the k consecutive bits include a bit set and a target bit, where the bit set includes (k-1) / 2 bit subsets, and each of the bit subsets includes 2 bits; The k consecutive bits are inner-coded to obtain a codeword, wherein the inner-coded encoding includes: XORing two bits in each of the bit subsets to obtain one bit, so as to obtain a total of (k-1) / 2 bits; Performing a second FEC encoding on a bit sequence including the (k-1) / 2 bits and the target bit to obtain p check bits, wherein the codeword includes the consecutive k bits and the p check bits, and p is an integer greater than or equal to 1.

2. The method according to claim 1, characterized in that The two bits in each of the bit subsets are two adjacent bits in the continuous k bits.

3. The method according to claim 1 or 2, characterized in that: The p check bits are located after the consecutive k bits in the codeword, and the target bit is the last bit of the consecutive k bits; or, In the codeword, the p check bits are located before the consecutive k bits, and the target bit is the first bit of the consecutive k bits.

4. The method according to any one of claims 1 to 3, characterized in that After performing inner code encoding on the continuous k bits to obtain a codeword, the method further includes: Symbol mapping and polarization division are performed on 8 bits from 4 bit subsets in a second data stream including at least one of the codewords to obtain a dual-polarization DP-16QAM symbol, wherein the 4 bit subsets are respectively mapped to an I component in an X polarization direction, a Q component in an X polarization direction, an I component in a Y polarization direction, and a Q component in a Y polarization direction of the DP-16QAM symbol, and the X polarization direction is orthogonal to the Y polarization direction.

5. The method according to any one of claims 1 to 4, characterized in that The second FEC code uses a finite field GF(2 m ) BCH code or extended BCH code with t bits of error correction, m and t are both integers greater than or equal to 1, mt≤p, and 6. The method according to any one of claims 1 to 5, characterized in that k=119, the second FEC encoding uses GF(2 m ) is GF(2 8 ) or GF(2 7 ).

7. The method according to any one of claims 1 to 6, characterized in that The length of the codeword is n, and the second FEC coding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following terms: n = 133, k = 119, GF(2 m )=GF(2 7 ), t=2, p=14; n=135, k=119, GF(2 m )=GF(2 8 ), t=2, p=16.

8. The method according to any one of claims 1 to 6, characterized in that The length of the codeword is n, and the second FEC coding adopts the finite field GF(2 m ) extended BCH code with t error correction bits, wherein the p check bits include q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following terms: n = 128, k = 119, GF(2 m )=GF(2 7 ), t=1, p=9, q=2; n=134, k=119, GF(2 m )=GF(2 7 ), t=2, p=15, q=1; n=135, k=119, GF(2 m )=GF(2 7 ), t=2, p=16, q=2; n=136, k=119, GF(2 m )=GF(2 8 ), t=2, p=17, q=1; n=137, k=119, GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

9. A data encoding method, characterized in that: include: Obtain k consecutive bits in a first data stream that has been encoded by a first forward error correction (FEC), where k is an integer greater than or equal to 3, the k consecutive bits include v bit subsets, each of the bit subsets includes 3 bits, and v is an integer greater than or equal to 1; The k consecutive bits are inner-coded to obtain a codeword, wherein the inner-coded encoding includes: XORing three bits in each of the bit subsets to obtain one bit, so as to obtain a total of v bits; Performing a second FEC encoding on the bit sequence including the v bits to obtain p check bits, wherein the codeword includes the consecutive k bits and the p check bits, and p is an integer greater than or equal to 1.

10. The method according to claim 9, characterized in that The three bits in each of the bit subsets are three consecutive bits in the consecutive k bits.

11. The method according to claim 9 or 10, characterized in that: k=v×3.

12. The method according to claim 9 or 10, characterized in that: The continuous k bits also include r target bits, k=v×3+r, r=1 or 2, and performing the second FEC encoding on the bit sequence including the v bits to obtain p check bits includes: The second FEC encoding is performed on a bit sequence including the v bits and the r target bits to obtain the p check bits.

13. The method according to claim 12, characterized in that In the codeword, the p check bits are located after the consecutive k bits, and the target bits are the last r bits of the consecutive k bits; or, In the codeword, the p check bits are located before the consecutive k bits, and the target bits are the first r bits of the consecutive k bits.

14. The method according to any one of claims 9 to 13, characterized in that After performing inner code encoding on the continuous k bits to obtain a codeword, the method further includes: Symbol mapping and polarization division are performed on 12 bits from 4 bit subsets in a second data stream including at least one of the codewords to obtain a dual-polarization DP-64QAM symbol, wherein the 4 bit subsets are respectively mapped to an I component in an X polarization direction, a Q component in an X polarization direction, an I component in a Y polarization direction, and a Q component in a Y polarization direction of the DP-64QAM symbol, and the X polarization direction is orthogonal to the Y polarization direction.

15. The method according to any one of claims 9 to 14, characterized in that The second FEC code uses a finite field GF(2 m ) BCH code or extended BCH code with error correction of t bits, where m and t are integers greater than or equal to 1, mt≤p, and v+r≤2 m -1-p.

16. The method according to any one of claims 9 to 15, characterized in that k=119, the second FEC encoding uses GF(2 m ) is GF(2 8 )、GF(2 7 ) or GF(2 6 ).

17. The method according to any one of claims 9 to 16, characterized in that The length of the codeword is n, and the second FEC coding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following terms: n = 131, k = 119, GF(2 m )=GF(2 6 ), t=2, p=12; n=133, k=119, GF(2 m )=GF(2 7 ), t=2, p=14; n=135, k=119, GF(2 m )=GF(2 8 ), t=2, p=16.

18. The method according to any one of claims 9 to 16, characterized in that The length of the codeword is n, and the second FEC coding adopts the finite field GF(2 m ) extended BCH code with t error correction bits, wherein the p check bits include q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following terms: n = 127, k = 119, GF(2 m )=GF(2 6 ), t=1, p=8, q=2; n=128, k=119, GF(2 m )=GF(2 7 ), t=1, p=9, q=2; n=132, k=119, GF(2 m )=GF(2 6 ), t=2, p=13, q=1; n=133, k=119, GF(2 m )=GF(2 6 ), t=2, p=14, q=2; n=134, k=119, GF(2 m )=GF(2 7 ), t=2, p=15, q=1; n=135, k=119, GF(2 m )=GF(2 7 ), t=2, p=16, q=2; n=136, k=119, GF(2 m )=GF(2 8 ), t=2, p=17, q=1; n=137, k=119, GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

19. A data encoding device, characterized in that: include: Acquisition unit and encoding unit; The acquisition unit is used to: acquire k consecutive bits in a first data stream that has been encoded by a first forward error correction (FEC), where k is an odd number greater than 1, and the k consecutive bits include a bit set and a target bit, where the bit set includes (k-1) / 2 bit subsets, and each of the bit subsets includes 2 bits; The encoding unit is used to: perform inner code encoding on the continuous k bits to obtain a code word; The encoding unit is specifically used to: perform XOR on two bits in each of the bit subsets to obtain one bit, so as to obtain a total of (k-1) / 2 bits; Performing a second FEC encoding on a bit sequence including the (k-1) / 2 bits and the target bit to obtain p check bits, wherein the codeword includes the consecutive k bits and the p check bits, and p is an integer greater than or equal to 1.

20. The data encoding device according to claim 19, characterized in that: The two bits in each of the bit subsets are two adjacent bits in the continuous k bits.

21. The data encoding device according to claim 19 or 20, characterized in that: The p check bits are located after the consecutive k bits in the codeword, and the target bit is the last bit of the consecutive k bits; or, In the codeword, the p check bits are located before the consecutive k bits, and the target bit is the first bit of the consecutive k bits.

22. The data encoding device according to any one of claims 19 to 21, characterized in that: The data encoding device further comprises a mapping unit, wherein the mapping unit is used for: Symbol mapping and polarization division are performed on 8 bits from 4 bit subsets in a second data stream including at least one of the codewords to obtain a dual-polarization DP-16QAM symbol, wherein the 4 bit subsets are respectively mapped to an I component in an X polarization direction, a Q component in an X polarization direction, an I component in a Y polarization direction, and a Q component in a Y polarization direction of the DP-16QAM symbol, and the X polarization direction is orthogonal to the Y polarization direction.

23. The data encoding device according to any one of claims 19 to 22, characterized in that: The second FEC code uses a finite field GF(2 m ) BCH code or extended BCH code with t bits of error correction, m and t are both integers greater than or equal to 1, mt≤p, and 24. The data encoding device according to any one of claims 19 to 23, characterized in that: k=119, the second FEC encoding uses GF(2 m ) is GF(2 8 ) or GF(2 7 ).

25. The data encoding device according to any one of claims 19 to 24, characterized in that: The length of the codeword is n, and the second FEC coding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following terms: n = 133, k = 119, GF(2 m )=GF(2 7 ), t=2, p=14; n=135, k=119, GF(2 m )=GF(2 8 ), t=2, p=16.

26. The data encoding device according to any one of claims 19 to 24, characterized in that: The length of the codeword is n, and the second FEC coding adopts the finite field GF(2 m ) extended BCH code with t error correction bits, wherein the p check bits include q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following terms: n = 128, k = 119, GF(2 m )=GF(2 7 ), t=1, p=9, q=2; n=134, k=119, GF(2 m )=GF(2 7 ), t=2, p=15, q=1; n=135, k=119, GF(2 m )=GF(2 7 ), t=2, p=16, q=2; n=136, k=119, GF(2 m )=GF(2 8 ), t=2, p=17, q=1; n=137, k=119, GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

27. A data encoding device, characterized in that: include: Acquisition unit and encoding unit; The acquisition unit is used to: acquire k consecutive bits in the first data stream after the first forward error correction FEC encoding, where k is an integer greater than or equal to 3, the k consecutive bits include v bit subsets, each of the bit subsets includes 3 bits, and v is an integer greater than or equal to 1; The encoding unit is used to: perform inner code encoding on the continuous k bits to obtain a code word; The encoding unit is specifically used for: performing XOR on three bits in each of the bit subsets to obtain one bit, so as to obtain a total of v bits; Performing a second FEC encoding on the bit sequence including the v bits to obtain p check bits, wherein the codeword includes the consecutive k bits and the p check bits, and p is an integer greater than or equal to 1.

28. The data encoding device according to claim 27, characterized in that: The three bits in each of the bit subsets are three consecutive bits in the consecutive k bits.

29. The data encoding device according to claim 27 or 28, characterized in that: k=v×3.

30. The data encoding device according to claim 27 or 28, characterized in that: The continuous k bits also include r target bits, k=v×3+r, r=1 or 2, and the encoding unit is specifically used for: The second FEC encoding is performed on a bit sequence including the v bits and the r target bits to obtain the p check bits.

31. The data encoding device according to claim 30, characterized in that: In the codeword, the p check bits are located after the consecutive k bits, and the target bits are the last r bits of the consecutive k bits; or, In the codeword, the p check bits are located before the consecutive k bits, and the target bits are the first r bits of the consecutive k bits.

32. The data encoding device according to any one of claims 27 to 31, characterized in that: The data encoding device further comprises a mapping unit, wherein the mapping unit is used for: Symbol mapping and polarization division are performed on 12 bits from 4 bit subsets in a second data stream including at least one of the codewords to obtain a dual-polarization DP-64QAM symbol, wherein the 4 bit subsets are respectively mapped to an I component in an X polarization direction, a Q component in an X polarization direction, an I component in a Y polarization direction, and a Q component in a Y polarization direction of the DP-64QAM symbol, and the X polarization direction is orthogonal to the Y polarization direction.

33. The data encoding device according to any one of claims 27 to 32, characterized in that: The second FEC code uses a finite field GF(2 m ) BCH code or extended BCH code with error correction of t bits, where m and t are integers greater than or equal to 1, mt≤p, and v+r≤2 m -1-p.

34. The data encoding device according to any one of claims 27 to 33, characterized in that: k=119, the second FEC encoding uses GF(2 m ) is GF(2 8 )、GF(2 7 ) or GF(2 6 ).

35. The data encoding device according to any one of claims 27 to 34, characterized in that: The length of the codeword is n, and the second FEC coding adopts GF(2 m ) BCH code with t bits of error correction, n, k, GF(2 m ), the corresponding relationship between t and p is one of the following terms: n = 131, k = 119, GF(2 m )=GF(2 6 ), t=2, p=12; n=133, k=119, GF(2 m )=GF(2 7 ), t=2, p=14; n=135, k=119, GF(2 m )=GF(2 8 ), t=2, p=16.

36. The data encoding device according to any one of claims 27 to 34, characterized in that: The length of the codeword is n, and the second FEC coding adopts the finite field GF(2 m ) extended BCH code with t error correction bits, wherein the p check bits include q bits of cyclic redundancy check CRC extended check bits, n, k, GF(2 m ), the corresponding relationship between t, p and q is one of the following terms: n = 127, k = 119, GF(2 m )=GF(2 6 ), t=1, p=8, q=2; n=128, k=119, GF(2 m )=GF(2 7 ), t=1, p=9, q=2; n=132, k=119, GF(2 m )=GF(2 6 ), t=2, p=13, q=1; n=133, k=119, GF(2 m )=GF(2 6 ), t=2, p=14, q=2; n=134, k=119, GF(2 m )=GF(2 7 ), t=2, p=15, q=1; n=135, k=119, GF(2 m )=GF(2 7 ), t=2, p=16, q=2; n=136, k=119, GF(2 m )=GF(2 8 ), t=2, p=17, q=1; n=137, k=119, GF(2 m )=GF(2 8 ), t=2, p=18, q=2.

37. A chip, characterized in that: The chip includes a processor and a memory, wherein the memory and the processor are connected to each other via a line, instructions are stored in the memory, and the processor is used to execute the method according to any one of claims 1 to 18.

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