Data processing method and related apparatus

Abstract

Disclosed in the embodiments of the present application are a data processing method and a related apparatus. Specifically, for a first data stream subjected to outer code encoding, inner code encoding is further performed on the first data stream to obtain a second data stream comprising at least one inner code codeword. The inner code encoding uses extended BCH encoding over a GF(28) that corrects two bit errors. The inner code codeword comprises 119 information bits and 17 check bits, totaling 136 bits. The 17 check bits comprise a 1-bit CRC extended check bit. That is, the embodiments of the present application use single-bit extended BCH (136,119) encoding having the capability to correct two bit errors. In existing 400G ZR scenarios, data padding and convolutional interleaving between outer code encoding and inner code encoding are both implemented using 119 bits as granularity. Therefore, an inner code encoding scheme provided in the embodiments of the present application is compatible with the 400G ZR scenarios and also enhances the performance of concatenated encoding.

Description

A data processing method and related device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 28, 2023, with application number 202311295265.4 and application name “A data processing method and related device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of optical communications, and in particular to a data processing method and related devices. Background Art

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTNs) are developing toward high capacity and ultra-high speeds. Forward error correction (FEC) is used to correct errors in transmitted data, resolving transmission errors and recovering the original data from the received data.

[0004] In 400G ZR scenarios, concatenated-FEC (CFEC) is used in optical modules as an error correction coding scheme. Staircase codes are used as the outer code, and two-bit extended Hamming codes are used as the inner code. In future 1.6T ZR scenarios, due to the significant increase in transmission rates, the performance of existing CFEC schemes will not be able to meet the link budget. A scheme with higher coding gain is urgently needed.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a data processing method and related devices, which are compatible with 400G ZR scenarios while improving the performance of cascade coding.

[0007] In the first aspect, an embodiment of the present application provides a data processing method. First, a first data stream that has been encoded by a first forward error correction (FEC) is obtained. The first FEC encoding can be regarded as an outer code. Then, a second FEC encoding is performed on each consecutive 119 bits in the first data stream to obtain a codeword to obtain a second data stream including at least one codeword. Each codeword includes 119 information bits and 17 check bits, a total of 136 bits. The second FEC encoding adopts a finite field GF(2 8) extended BCH code with 2 bits of error correction, and 17 check bits including a 1-bit cyclic redundancy check (CRC) extended check bit.

[0008] In this embodiment, the embodiment of the present application adopts a single-bit extended BCH (136, 119) code with an error correction capability of 2 bits. In the existing 400G ZR scenario, the data padding and convolution interleaving between the outer code and the inner code are both implemented with a granularity of 119 bits. Therefore, the inner code coding scheme provided by the embodiment of the present application can replace the Hamming code with a 1-bit error correction capability with a single-bit extended BCH code or its extended code with a 2-bit error correction capability while being compatible with the 400G ZR scenario, thereby improving the performance of the cascaded coding.

[0009] In some possible implementations, after performing the second FEC encoding on every consecutive 119 bits in the second data stream to obtain a codeword, the method further includes: performing symbol mapping and polarization division on every consecutive 8 bits in each codeword in the second data stream to obtain a dual-polarization (DP)-16QAM symbol, for a total of 17 DP-16QAM symbols. Any component of the DP-16QAM symbol is obtained by mapping two consecutive bits in the same codeword. In this way, the two bits with different error probabilities in any component are evenly distributed across each inner codeword, which helps improve the performance of inner code encoding.

[0010] In some possible embodiments, after symbol mapping and polarization division are performed on every 8 consecutive bits in a codeword to obtain one DP-16QAM symbol, the method further includes: obtaining a DP-16QAM symbol set, the DP-16QAM symbol set including L rows and 17 columns of DP-16QAM symbols, where L is an integer greater than or equal to 1, and the 17 DP-16QAM symbols in each row of the DP-16QAM symbol set are obtained by symbol mapping and polarization division of 136 bits in a codeword. Channel interleaving is performed on the DP-16QAM symbol set to obtain a third data stream. The third data stream includes 17 DP-16QAM symbol subsets, each DP-16QAM symbol subset includes L DP-16QAM symbols, and each DP-16QAM symbol subset is from the L DP-16QAM symbols in a corresponding column of the DP-16QAM symbol set. The f-th DP-16QAM symbol subset in the third data stream corresponds to the DP-16QAM symbol in the f-th column of the DP-16QAM symbol set, where 0≤f≤16. It should be understood that channel interleaving, before the DP-16QAM symbol stream is input into a channel for transmission, can enhance resilience to channel burst errors.

[0011] In some possible implementations, the first data stream undergoes bit padding after the first FEC encoding, where the number of padded bits is 119 × 6 = 714. The total amount of padded data includes 119-bit data blocks, which is an integer multiple of 16. This facilitates synchronization and alignment of convolutional interleaving. This solution enables the new cascade architecture to be more compatible with the 400G ZR data frame structure.

[0012] In some possible implementations, the first data stream is further subjected to convolutional interleaving after being subjected to the first FEC coding, which can reduce the transmission of error correlation between the inner code coding and the outer code coding and more effectively resist burst errors.

[0013] In some possible implementations, convolution interleaving includes delaying bits from a bit-stuffed data stream according to 16 delay lines. Each delay line includes a different number of storage units, with the delay line with the smallest number of storage units including 0 storage units. The difference in the number of storage units between two adjacent delay lines is 2, and each storage unit is used to store 119 bits. Input bits are sequentially input into the 16 delay lines according to the sequence of the 16 delay lines. Each delay line inputs 119 bits at a time and outputs 119 bits at a time. After convolution interleaving, the continuous 16×119 bits output include 119 bits output by each delay line. This embodiment provides a specific implementation method for convolution interleaving, which has good practical effects.

[0014] In some possible implementations, each consecutive 119 bits in the first data stream includes 59 bit subsets and a target bit, and each bit subset includes 2 bits. Performing a second FEC encoding on each consecutive 119 bits in the first data stream to obtain a codeword includes: performing an XOR on the 2 bits in each bit subset to obtain 1 bit, so as to obtain a total of 59 bits; encoding the bit sequence including the 59 bits and the target bit to obtain 17 check bits, and the consecutive 119 bits are the information bits in the codeword. The embodiment of the present application adopts a method of first XORing and then encoding. For example, the codeword processing of (136,119) can be achieved by using a (77,60) encoder, which reduces the complexity of the encoding while not changing the inner codeword length and redundancy cost.

[0015] In some possible implementations, before obtaining the first data stream after the first FEC encoding, the method further includes: distributing the input data stream to obtain four distributed data streams; and performing the first FEC encoding on each distributed data stream. This data method is advantageously compatible with throughput scenarios such as 1.6T, 800G, and 400G.

[0016] In some possible implementations, the first FEC encoding uses staircase (512, 510) encoding, which has better practical effects.

[0017] In a second aspect, an embodiment of the present application provides a data processing device, which includes: an acquisition unit and an encoding unit. The acquisition unit is used to: acquire a first data stream that has been encoded by a first FEC; The encoding unit is used to: perform a second FEC encoding on each consecutive 119 bits in the first data stream to obtain a codeword, so as to obtain a second data stream including at least one codeword. Each codeword includes 119 information bits and 17 check bits, a total of 136 bits, and the second FEC encoding adopts a finite field GF(2 8 ) 2-bit extended BCH code for error correction, 17 check bits including 1-bit CRC extended check bit.

[0018] In some possible implementations, the data processing device further includes a mapping unit configured to perform symbol mapping and polarization division on every eight consecutive bits in each codeword in the second data stream to obtain one DP-16QAM symbol, thereby obtaining a total of 17 DP-16QAM symbols.

[0019] In some possible implementations, the data processing apparatus further includes a channel interleaving unit. The channel interleaving unit is configured to: obtain a DP-16QAM symbol set, the DP-16QAM symbol set including L rows and 17 columns of DP-16QAM symbols, where L is an integer greater than or equal to 1, and the 17 DP-16QAM symbols in each row of the DP-16QAM symbol set are obtained by symbol mapping and polarization division of 136 bits in a codeword; and perform channel interleaving on the DP-16QAM symbol set to obtain a third data stream, the third data stream including 17 DP-16QAM symbol subsets, each DP-16QAM symbol subset including L DP-16QAM symbols, each DP-16QAM symbol subset coming from the L DP-16QAM symbols in a corresponding column of the DP-16QAM symbol set, where the fth DP-16QAM symbol subset in the third data stream corresponds to the DP-16QAM symbol in the fth column of the DP-16QAM symbol set, and 0≤f≤16.

[0020] In some possible implementations, the data processing device further includes a padding unit. After the first FEC encoding, the first data stream is further bit-padded by the padding unit, wherein the number of padded bits is 119×6=714.

[0021] In some possible implementations, the data processing apparatus further includes a convolution interleaving unit, and the first data stream is subjected to convolution interleaving by the convolution interleaving unit after being bit-stuffed.

[0022] In some possible implementations, the convolutional interleaving unit is specifically configured to delay bits from a bit-stuffed data stream according to 16 delay lines. Each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between two adjacent delay lines is 2, each storage unit is configured to store 119 bits, input bits are sequentially input into the 16 delay lines according to the sequence of the 16 delay lines, each delay line inputs 119 bits at a time and outputs 119 bits at a time, and the continuous 16×119 bits output after convolutional interleaving include 119 bits output by each delay line.

[0023] In some possible implementations, each consecutive 119 bits in the first data stream includes 59 bit subsets and a target bit, where each bit subset includes 2 bits. The encoding unit is specifically configured to: perform an exclusive-OR operation on the two bits in each bit subset to obtain 1 bit, for a total of 59 bits; and encode the bit sequence including the 59 bits and the target bit to obtain 17 check bits, where the consecutive 119 bits are information bits in the codeword.

[0024] In some possible implementations, the data processing device further includes a processing unit. Before obtaining the first data stream that has undergone the first FEC encoding, the processing unit is configured to: distribute the input data stream to obtain four distribution data streams; and perform the first FEC encoding on each distribution data stream.

[0025] In some possible implementations, the first FEC encoding uses staircase (512, 510) encoding.

[0026] In a third aspect, an embodiment of the present application provides a chip comprising a processor and a memory, the memory and the processor being interconnected via lines, instructions being stored in the memory, and the processor being used to execute the method described in any embodiment of the first aspect.

[0027] In a fourth aspect, an embodiment of the present application provides a data transmission system, which includes a data sending device and a data receiving device, wherein the data sending device is used to execute the method described in any embodiment of the first aspect and send data to the data receiving device, and the data receiving device is used to perform operations such as decoding on the received data.

[0028] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a computer, the method described in any embodiment of the first aspect is implemented.

[0029] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0030] In this embodiment, the first data stream which has been encoded by the outer code is further encoded by the inner code to obtain a second data stream which includes at least one inner code word. The inner code is encoded by GF(2 8 ) extended BCH coding with 2 bits of error correction, the inner code codeword includes 119 information bits and 17 check bits, a total of 136 bits, and the 17 check bits include a 1-bit cyclic redundancy check (CRC) extended check bit. In other words, the embodiment of the present application adopts a single-bit extended BCH (136,119) coding with an error correction capability of 2 bits. In the existing 400G ZR scenario, the data padding and convolution interleaving between the outer code coding and the inner code coding are both implemented with a granularity of 119 bits. Therefore, the inner code coding scheme provided by the embodiment of the present application is compatible with the 400G ZR scenario while also improving the performance of cascade coding. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application;

[0032] FIG2 is a schematic diagram of another communication system used in an embodiment of the present application;

[0033] FIG3 is a schematic diagram of an implementation of a data processor at a transmitting end according to an embodiment of the present application;

[0034] FIG4 is a flow chart of a data processing method provided in an embodiment of the present application;

[0035] FIG5 is a schematic diagram of the structure of an encoded data frame;

[0036] FIG6( a ) is a schematic diagram of a first implementation method of convolutional interleaving in an embodiment of the present application;

[0037] FIG6( b ) is a schematic diagram of a second implementation method of convolutional interleaving in an embodiment of the present application;

[0038] FIG7 is a schematic diagram of an application scenario of internal code encoding in an embodiment of the present application;

[0039] FIG8 is a schematic diagram of an application scenario of channel interleaving according to an embodiment of the present application;

[0040] FIG9 is a schematic diagram of an implementation of a multi-channel parallel transmitting end data processor in an embodiment of the present application;

[0041] FIG10 is a schematic diagram of an implementation method of data distribution in an embodiment of the present application;

[0042] FIG11 is a schematic structural diagram of a data processing device according to an embodiment of the present application;

[0043] FIG12 is another structural diagram of the data processing device in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The embodiments of the present application provide a data processing method and related devices, which improve the performance of cascade coding while being compatible with 400G ZR scenarios. It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, rather than to limit a specific order or sequence. It should be understood that the above terms can be interchangeable where appropriate, so that the embodiments described in this application can be implemented in an order other than that described in this application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or that are inherent to these processes, methods, products or devices.

[0045] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application. As shown in FIG1 , the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches or routers, and the transmitting device 01 is also called a client-side chip (host chip) located at the transmitting end, and the receiving device 05 is also called a client-side chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client-side chip is sometimes also called a client-side device (host device). The transmitting device 01 and the transmitting processing module 02 can be connected via an attachment unit interface (AUI), and the receiving device 05 and the receiving processing module 04 can be connected via an AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module may be an 800ZR module (a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in the communication system may support bidirectional transmission or unidirectional transmission, without limitation herein.

[0046] FIG2 is a schematic diagram of another communication system used in an embodiment of the present application. As shown in FIG2 , at the transmitting end, a signal source provides a data stream to be transmitted; a transmitting data processor receives the data stream and performs data processing including encoding, interleaving, and modulation on it to obtain a symbol data stream, which is then sent to a transmitting signal processor for framing. The signal is then transmitted through a channel to a receiving device. After receiving a distorted signal caused by noise or other damage in the channel, the receiving device sends it to a receiving signal processor for dispersion compensation, synchronization, phase recovery, and other operations. The signal is then sent to a receiving data processor for demodulation, deinterleaving, and decoding. The original data is then recovered and sent to the destination. The transmitting data processing and transmitting signal processing shown in FIG2 can be applied to the transmitting processing module 02 shown in FIG1 , and the receiving data processing and receiving signal processing shown in FIG2 can be applied to the receiving processing module 04 shown in FIG1 .

[0047] Figure 3 is a schematic diagram of one embodiment of a transmitting data processor in accordance with an embodiment of the present application. As shown in Figure 3, the transmitting data processor sequentially performs outer code encoding, padding bit insertion, convolutional interleaving, inner code encoding, symbol mapping and polarization division, and channel interleaving on the input data stream. It should be understood that in actual applications, the operations performed by the transmitting data processor include, but are not limited to, those illustrated in Figure 3. For example, the encoded data frame obtained by outer code encoding may also be scrambled before convolutional interleaving.

[0048] It should be understood that the distinction between "inner" in inner code and "outer" in outer code is based solely on the distance between the entity performing the data operations and the channel transmission medium. The entity performing the inner code operations is closer to the channel transmission medium, while the entity performing the outer code operations is farther away. In the embodiment of this application, using Figure 1 as an example, the transmitting processing module 02 encodes the data twice before sending it to the channel transmission medium. The data encoded first by the transmitting processing module 02 is farther away from the channel transmission medium, while the data encoded later by the transmitting processing module 02 is closer to the channel transmission medium. Therefore, the data encoded first by the transmitting processing module 02 is referred to as outer-coded data, while the data encoded later by the transmitting processing module 02 is referred to as inner-coded data. Correspondingly, the data decoded first by the receiving processing module 04 is referred to as inner-coded data, while the data decoded later by the receiving processing module 04 is referred to as outer-coded data. In one possible implementation, both the inner and outer codes described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting end processing module 02 may use staircase code for outer code encoding, use Hamming code for inner code encoding, or use Bose-Chaudhuri-Hocquenghem (BCH) code for inner code encoding.

[0049] It should be noted that the above content is an exemplary description of the application scenario of the data processing method provided in the embodiment of the present application, and does not constitute a limitation on the application scenario of the data processing method. It is known to those skilled in the art that as business needs change, its application scenario can be adjusted according to application needs, and the embodiment of the present application does not list them one by one. The following mainly introduces the data processing method applied to the data sending end. The data processing method applied to the receiving end can be understood as the inverse operation of the data processing method of the sending end. On the basis of the determination of the data processing method of the sending end, the data processing method of the receiving end is also clear, and this application no longer introduces the data processing method of the receiving end in detail.

[0050] Figure 4 is a schematic flow chart of a data processing method provided in an embodiment of the present application. The data processing method includes the following steps, which are described in detail below. It should be understood that, for ease of explanation, the first FEC encoding described below can be considered the outer code encoding described above, and the second FEC encoding described below can be considered the inner code encoding described above. The following description can be understood based on this.

[0051] 101. Obtain a data stream that has undergone first FEC encoding.

[0052] It should be understood that this application does not limit the specific implementation of the outer code encoding. As an example, the outer code encoding can specifically adopt staircase (512, 510) encoding. In some possible scenarios, the data stream after outer code encoding can also be called a coded data frame, and the bits in the coded data frame are distributed in rows and columns.

[0053] Figure 5 is a schematic diagram of the structure of a coded data frame. As shown in Figure 5, the coded data frame includes 119 rows and 10,970 columns of bits. Among them, the 119 rows and 10,280 columns of bits are information bits of the coded data frame, and the 119 rows and 690 columns of bits are check bits of the coded data frame.

[0054] 102. Perform bit padding on the data stream that has undergone the first FEC encoding.

[0055] In an embodiment of the present application, bit padding is performed on the outer code encoded data stream (encoded data frame), specifically 119×6=714 bits. The present application does not limit the value of the padding bits; for example, the padding bits can all be 0. In one possible implementation, the padding bits are added at the end of the encoded data frame.

[0056] 103. Perform convolution interleaving on the bit-stuffed data stream.

[0057] Specifically, performing convolution interleaving on a bit-filled data stream can obtain a data stream with disrupted data order. The following introduces possible implementation methods of convolution interleaving.

[0058] FIG6(a) is a schematic diagram of the first implementation method of convolution interleaving in an embodiment of the present application. FIG6(b) is a schematic diagram of the second implementation method of convolution interleaving in an embodiment of the present application. As shown in FIG6(a) and FIG6(b), the convolution interleaver includes 16 delay lines, and the convolution interleaver delays the input data according to the 16 delay lines. Among them, the number of storage units included in each delay line is different. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units of each two adjacent delay lines is 2, and each storage unit is used to store 119 bits. The bits in the first bit set are input to the 16 delay lines in sequence according to the sequence numbers of the 16 delay lines. Each delay line inputs 119 bits at a time and outputs 119 bits at a time. The continuous 16×119 bits output after convolution interleaving include 119 bits output by each delay line. For example, 16 delay lines include 0 storage units, 2 storage units, 4 storage units, ..., 30 storage units, and each storage unit is used to store 119 symbols. Then, p delay lines correspond to 16 delay values, and the delay values ​​include 0 bits, 2×119 bits, 4×119 bits, ..., 30×119 bits. It can also be understood that the interleaving depth of the convolution interleaver is 16. It should be noted that the delay values ​​in this application are counted in bits. The more bits the delay value of the delay line includes, the longer the delay (also called time delay) of the delay line to the data. It should be understood that when the delay line does not include a storage unit, the delay of the delay line is 0 symbol, that is, there is no delay in transmission.

[0059] As shown in Figure 6(a), the number of memory cells in the 16 delay lines decreases sequentially according to the sequence of the 16 delay lines. That is, delay line 0 has 30 memory cells, and each delay line decreases by 2 memory cells, until delay line 15 has 0 memory cells. As shown in Figure 6(b), the number of memory cells in the 16 delay lines increases sequentially according to the sequence of the 16 delay lines. That is, delay line 0 has 0 memory cells, and each delay line increases by 2 memory cells, until delay line 15 has 30 memory cells.

[0060] It should be noted that at the same moment, the switches for the input and output of the convolution interleaver are located on the same delay line. After the current delay line inputs 119 bits and outputs 119 bits at a time, the switch is switched to the next delay line to ensure that the bits in the first bit set are input to the 16 delay lines in sequence according to the sequence of the 16 delay lines. The continuous 16×119 bits output after convolution interleaving include 119 bits output by each delay line. The specific data read and write operations are as follows: 119 bits are read from the storage unit closest to the output port of the current delay line. The 119 bits stored in each storage unit in the current delay line are transferred to the next storage unit. The 119 bits are then written to the storage unit closest to the input port in the current delay line. After that, switch to the next delay line and repeat the above operations, and so on.

[0061] It should be understood that the convolutional interleaving processes in Figure 6(a) and Figure 6(b) are inverse operations of each other. That is, when the transmitting processing module adopts the convolutional interleaving structure shown in Figure 6(a), the corresponding convolutional deinterleaving process in the receiving processing module adopts the structure shown in Figure 6(b). Similarly, when the transmitting processing module adopts the convolutional interleaving structure shown in Figure 6(b), the corresponding convolutional deinterleaving process in the receiving processing module adopts the structure shown in Figure 6(a).

[0062] 104. Perform a second FEC encoding on the convolutionally interleaved data stream.

[0063] Specifically, an inner code word is obtained by performing inner code encoding on each consecutive 119 bits in the convolution interleaved data stream. The inner code word includes 119 information bits and 17 check bits, a total of 136 bits. In the embodiment of the present application, the inner code encoding can specifically adopt GF(2 8 ) Single-bit extended BCH coding with 2-bit error correction improves the error correction capability of the inner codeword to 2 bits, improving the performance of concatenated coding. The 17 check bits in the inner codeword include a 1-bit cyclic redundancy check (CRC) extended check bit, so it is called single-bit extended BCH coding. Among them, GF refers to a finite field, also known as a Galois field, 2 8 Represents the order of the finite field.

[0064] It should be noted that BCH code is constructed on the finite field GF(2 m), the number of check bits of the BCH code is equal to m×t, where t represents the error correction capability of the BCH code is t bits. Therefore, for every increase of 1 bit of error correction capability, an additional m bits of overhead will be added. As t gets larger and larger, the performance benefits brought by continuing to increase t will gradually decrease. Since BCH coding will use soft decision decoding, the decoding complexity of BCH coding with t>2 will increase exponentially compared to BCH coding with t=2. In contrast, the BCH coding with t=2 only increases the encoding and decoding complexity slightly compared to Hamming coding. In summary, the embodiment of the present application selects BCH coding with an error correction capability of 2 bits as the inner code.

[0065] It should also be noted that the bit padding between the inner code and outer code in the 400G ZR scenario and the granularity of the convolution interleaving are 119 bits. In order to maintain backward compatibility, the embodiment of the present application maintains the information length of the inner code word at 119 bits, denoted by k. BCH coding may make misjudgments during the decoding process, that is, the received sequence is judged to be an erroneous legal codeword. This situation will lead to error transmission, thereby affecting the decoding performance. The probability of error detection depends on the minimum distance between the inner code codewords. The probability of error transmission can be reduced by adding CRC extended check bits to the inner code codewords. Let r represent the number of bits of the CRC extended check bit, then the length of the inner code codeword n ​​= k + m × t + r = 119 + 2m + r. Further, according to the characteristics of BCH coding, the length of the inner code codeword needs to meet the following conditions: 119 + 2 × m + 1 ≤ 2 m -1. According to the above two formulas, it can be concluded that m is an integer greater than or equal to 8. Since the inner code word will eventually be mapped to the dual-polarization (DP)-16QAM symbol in groups of 8 bits. Therefore, in order to simplify the subsequent symbol mapping, the embodiment of the present application selects the length n of the inner code word to be a multiple of 8. Combining the above two formulas, it can be concluded that (2m+r)%8=1, m≥8, a%b means a modulo b. As m and r increase, the complexity and overhead of the codeword also increase. Therefore, the smallest m and r that satisfy the above relationship should be selected, that is, m=8, r=1. At the same time, for the inner code word, when r>1, as r continues to increase, the help in reducing the probability of false detection will become very limited. Therefore, the embodiment of the present application selects m=8 and r=1, that is, adopts GF(2 8 ) Single-bit extended BCH code (136,119) with 2 bits of error correction is used as the inner code.

[0066] The inner codeword is based on GF(2 8The BCH code (255,239) is generated by shortening 120 bits and adding a single bit of parity check. Its generating polynomial can be expressed as: g(x)=M1(x)M3(x)=(x 8 +x 4 +x 3 +x 2 +1)(x 8 +x 6 +x 5 +x 4 +x 2 +x+1)(x+1) =x 16 +x 14 +x 13 +x 11 +x 10 +x 9 +x 8 +x 6 +x 5 +x+1

[0067] Among them, M1(x) and M3(x) correspond to GF(2 8 ) element α 1 With α 3 The minimum polynomial of α is a finite field GF(2 8 ) primitive element. The 119 bits of the information sequence are used as coefficients of a polynomial with a highest degree of 118 to obtain the information polynomial m(x). 17 m(x) is divided by g(x) using modulo 2 division to obtain the remainder polynomial r(x). The coefficients of each term in r(x) are the check sequence P[0:16]. Finally, the information sequence and the check sequence form the inner codeword (136,119), denoted as C[0:135] = [c0,c1,…,c 135 ], which can be expressed as

[0068] Figure 7 is a schematic diagram of an application scenario of the inner code encoding in the embodiment of the present application. As shown in Figure 7, 118 bits are selected from the 119-bit information sequence A[0:118] to form a sequence A', which is recorded as A'=[a'0,a'1,...a' 117 A' can be any 118 bits in the information sequence A. To facilitate subsequent channel interleaving and modulation, the first 118 bits in the information sequence A can be selected as A', that is: A'=[a0,a1,…a 117 Then, two adjacent bits in A' are grouped together and XORed to obtain 59 bits [b0, b1, ..., b 58 ]. At the same time, the bits in the information sequence A that are not selected into A', denoted as A\A', will skip the group XOR operation and be combined with b0~b57 Combined together to form the sequence to be encoded B[0:59]=[b0,b1,…,b 59 ], which means as follows: Generate the sequence to be encoded B[0:59], then perform BCH(77,60) encoding on the sequence to be encoded B, and generate 17-bit check bits [p0,p1,…,p 16 ]. Among them, BCH (77,60) is based on GF (2 8 The BCH (255, 239) is generated by shortening 179 bits and adding a single bit of parity check. Its generating polynomial g(x) is the same as the above polynomial g(x). The 60 bits to be encoded are used as the coefficients of the polynomial with the highest degree of 59 to obtain the information polynomial m(x). 17 m(x) is divided by g(x) using modulo 2 division to obtain the remainder polynomial r(x). The coefficients of each term in r(x) are the check sequence P[0:16]. Finally, the information sequence A and the check sequence P form the inner codeword (136,119), denoted as C[0:135] = [c0,c1,…,c 135 ], which can be expressed as: It can be seen that the embodiment of the present application adopts the method of first XOR and then encoding. For example, the codeword processing of (136,119) can be realized by the encoder of (77,60), which reduces the complexity of encoding while not changing the inner codeword length and redundancy cost.

[0069] 105. Perform symbol mapping and polarization division on the codewords encoded by the second FEC.

[0070] Specifically, symbol mapping and polarization division are performed on every 8 consecutive bits in the inner codeword to obtain one DP-16QAM symbol. Since the inner code length becomes 136 bits, each codeword will be mapped into 17 DP-16QAM symbols during symbol mapping and polarization distribution. Among them, every 2 bits of the 8 bits involved in symbol mapping and polarization division form a group that is mapped to the X polarization direction I-phase component, X polarization direction Q-phase component, Y polarization direction I-phase component, and Y polarization direction Q-phase component of the DP-16QAM symbol. Among them, the X polarization direction and the Y polarization direction are orthogonal to each other. Considering that any component of the DP-16QAM symbol is obtained by mapping the two bits of the inner codeword, and since the binary bit DP-16QAM symbol adopts Gray mapping, the error probability of the two bits mapped to any component of the DP-16QAM symbol is inconsistent. In order to improve the performance of concatenated coding, any component of the DP-16QAM symbol is mapped from two consecutive bits in the same codeword. In this way, the two bits with different error probabilities in any component are evenly distributed in each inner codeword.

[0071] 106. Perform channel interleaving on the DP-16QAM symbol set.

[0072] FIG8 is a schematic diagram of an application scenario of channel interleaving in an embodiment of the present application. As shown in FIG8 , a DP-16QAM symbol set including 8×17 DP-16QAM symbols obtained by mapping 8 inner codewords is taken as an example. The DP-16QAM symbol set is distributed as 8 rows and 17 columns of DP-16QAM symbols. The DP-16QAM symbols in the DP-16QAM symbol set are denoted as {s i,j}, represents the jth DP-16QAM symbol obtained by mapping the i-th inner codeword, 0≤i≤7, 0≤j≤16. The channel interleaving method provided in the embodiment of the present application is to complete row and column interleaving with the DP-16QAM symbol as the granularity, that is, the DP-16QAM symbols after channel interleaving are output in the order of columns, and each column is output in the order from row 0 to row 7. Taking Figure 8 as an example, the output order of the DP-16QAM symbols after channel interleaving is: {s 0,0}-{s 7,0} are output in sequence, and the first column {s 0,1}-{s 7,1} Output in sequence, ..., {s in the 15th column 0,15}-{s 7,15} are output in sequence, and the 16th column {s 0,16}-{s 7,16} are output in sequence.

[0073] The above describes the data processing method provided in the embodiments of the present application. It should be understood that in some possible scenarios, considering the potential need for FEC schemes to be compatible with throughput rates such as 1.6T, 800G, and 400G, as well as the issue of hardware implementation at ultra-high throughput, a multi-channel parallel data processing solution can also be proposed based on the aforementioned embodiments. Figure 9 is a schematic diagram of an implementation of a multi-channel parallel transmitting end data processor in the embodiments of the present application. As shown in Figure 9, the input data stream is first distributed to obtain four data streams, and then each distributed data stream is processed according to the data processing method shown in Figure 3.

[0074] Figure 10 is a schematic diagram of an implementation method of data distribution in an embodiment of the present application. As shown in Figure 10, first obtain continuous 4×119×10280 bits of data, and then poll and distribute them according to the granularity of h bits to obtain 4 data frames. The bits in each data frame are arranged into 119 rows and 10280 columns. The 4 data frames are respectively outer-coded to obtain 4 coded data frames, and then each coded data frame is subsequently processed in the manner shown in Figure 3. It should be understood that 10280% (4×h) = 0, for example, h = 1, 257, 514 or 1285. This solution can be well compatible with throughput rates such as 1.6T, 800G, and 400G. As an example, when the input data frame is a 1.6T service, the data frame can be distributed into 4 channels for processing as shown in Figure 9. As another example, when the input data frame is an 800G service, the data frame can be distributed into 2 channels for processing, and the other 2 channels can be turned off to save power consumption. As another example, when the input data frame is a 400G service, data frame distribution can be omitted, and the data frame can be directly processed as shown in Figure 3, and the other three paths can be turned off to save power consumption.

[0075] Figure 11 is a schematic diagram of the structure of a data processing device in an embodiment of the present application. As shown in Figure 11, the data processing device includes an acquisition unit 201, a padding unit 202, a convolutional interleaving unit 203, an encoding unit 204, a mapping unit 205, and a channel interleaving unit 206. The acquisition unit 201 is used to perform the operation of step 101 above, the padding unit 202 is used to perform the operation of step 102 above, the convolutional interleaving unit 203 is used to perform the operation of step 103 above, the encoding unit 204 is used to perform the operation of step 104 above, the mapping unit 205 is used to perform the operation of step 105 above, and the channel interleaving unit 206 is used to perform the operation of step 106 above. It should be understood that the data processing device provided in this application can also be implemented in other ways. For example, the unit division in the above device is merely a logical functional division. In actual implementation, other division methods can be used, for example, multiple units or components can be combined or integrated into another system. In addition, the functional units in various embodiments of the present application can be integrated into a single processing unit, can be independent physical units, or can be two or more functional units integrated into a single processing unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0076] Figure 12 is another structural diagram of a data processing device in an embodiment of the present application. As shown in Figure 12, the data processing device includes a processor 301 and a transceiver 302. The processor 301 and the transceiver 302 are interconnected via a line. Specifically, the transceiver 302 is used to perform data transmission and reception operations, and the processor 301 is used to perform other operations besides data transmission and reception. In one possible implementation, the processor 301 may include the padding unit 202, the convolution interleaving unit 203, the encoding unit 204, the mapping unit 205, and the channel interleaving unit 206 shown in Figure 11 above, and the transceiver 302 includes the acquisition unit 201 shown in Figure 11 above. Optionally, the data processing device may further include a memory 303, wherein the memory 303 is used to store program instructions and data.

[0077] The present application also provides a chip. This chip integrates circuitry and one or more interfaces for implementing the functions of the processor 301 described above. When the chip integrates memory, it can perform the method steps of any one or more of the aforementioned embodiments. When the chip does not integrate memory, it can be connected to an external memory via an interface. The chip implements the actions performed by the transmitting device or receiving device in the aforementioned embodiments based on program code stored in the external memory.

[0078] Finally, it should be noted that the above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A data processing method, characterized in that: include: Acquire a first data stream that has been encoded by a first forward error correction (FEC); Performing a second FEC encoding on each of the consecutive 119 bits in the first data stream to obtain a codeword, so as to obtain a second data stream including at least one codeword, wherein each of the codewords includes 119 information bits and 17 check bits, a total of 136 bits, and the second FEC encoding adopts a finite field GF(2 8 ) 2-bit extended BCH code for error correction, 17 check bits including 1-bit cyclic redundancy check CRC extended check bit.

2. The method according to claim 1, characterized in that After performing a second FEC encoding on every consecutive 119 bits in the second data stream to obtain a codeword, the method further includes: Symbol mapping and polarization division are performed on every 8 consecutive bits in each of the codewords in the second data stream to obtain one dual-polarization DP-16QAM symbol, so as to obtain a total of 17 DP-16QAM symbols.

3. The method according to claim 2, characterized in that After performing symbol mapping and polarization division on every 8 consecutive bits in the codeword to obtain a DP-16QAM symbol, the method further includes: Obtain a DP-16QAM symbol set, the DP-16QAM symbol set comprising L rows and 17 columns of DP-16QAM symbols, where L is an integer greater than or equal to 1, and the 17 DP-16QAM symbols in each row of the DP-16QAM symbol set are obtained by performing symbol mapping and polarization division on 136 bits in one of the codewords; Channel interleaving is performed on the DP-16QAM symbol set to obtain a third data stream, the third data stream comprising 17 DP-16QAM symbol subsets, each of the DP-16QAM symbol subsets comprising L DP-16QAM symbols, each of the DP-16QAM symbol subsets coming from the L DP-16QAM symbols corresponding to a column in the DP-16QAM symbol set, wherein the f-th DP-16QAM symbol subset in the third data stream corresponds to the DP-16QAM symbol in the f-th column in the DP-16QAM symbol set, 0≤f≤16.

4. The method according to any one of claims 1 to 3, characterized in that The first data stream is bit-filled after being encoded by the first FEC, wherein the number of filled bits is 119×6=714.

5. The method according to claim 4, characterized in that The first data stream is also subjected to convolution interleaving after the bit filling.

6. The method according to claim 5, characterized in that The convolution interleaving comprises: The bits from the bit-filled data stream are delayed according to 16 delay lines, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between every two adjacent delay lines is 2, each storage unit is used to store 119 bits, the input bits are input into the 16 delay lines in sequence according to the sequence numbers of the 16 delay lines, each delay line inputs 119 bits at a time and outputs 119 bits at a time, and the continuous 16×119 bits output after convolution interleaving include 119 bits output by each delay line.

7. The method according to any one of claims 1 to 6, characterized in that Each of the continuous 119 bits in the first data stream includes 59 bit subsets and a target bit, each of the bit subsets includes 2 bits, and performing the second FEC encoding on each of the continuous 119 bits in the first data stream to obtain a codeword includes: XORing two bits in each of the bit subsets to obtain one bit, so as to obtain a total of 59 bits; The bit sequence including the 59 bits and the target bit is encoded to obtain 17 check bits, and the continuous 119 bits are information bits in the codeword.

8. The method according to any one of claims 1 to 7, characterized in that Before acquiring the first data stream encoded by the first FEC, the method further includes: Perform data distribution on the input data stream to obtain 4 distribution data streams; The first FEC encoding is performed on each of the distribution data streams.

9. The method according to any one of claims 1 to 8, characterized in that The first FEC coding adopts staircase (512, 510) coding.

10. A data processing device, characterized in that: include: Acquisition unit and encoding unit; The acquisition unit is used to: acquire a first data stream that has been encoded by a first forward error correction (FEC); The encoding unit is used to perform a second FEC encoding on each of the consecutive 119 bits in the first data stream to obtain a codeword, so as to obtain a second data stream including at least one codeword, wherein each of the codewords includes 119 information bits and 17 check bits, a total of 136 bits, and the second FEC encoding adopts a finite field GF(2 8 ) 2-bit extended BCH code for error correction, 17 check bits including 1-bit cyclic redundancy check CRC extended check bit.

11. The data processing device according to claim 10, characterized in that: The data processing device further comprises a mapping unit; The mapping unit is used to perform symbol mapping and polarization division on every 8 consecutive bits in each codeword in the second data stream. One dual-polarization DP-16QAM symbol is obtained to obtain a total of 17 DP-16QAM symbols.

12. The data processing device according to claim 11, characterized in that: The data processing device further comprises a channel interleaving unit; The channel interleaving unit is used to: obtain a DP-16QAM symbol set, the DP-16QAM symbol set includes L rows and 17 columns of DP-16QAM symbols, where L is an integer greater than or equal to 1, and the 17 DP-16QAM symbols in each row of the DP-16QAM symbol set are obtained by symbol mapping and polarization division of 136 bits in one codeword; Channel interleaving is performed on the DP-16QAM symbol set to obtain a third data stream, the third data stream comprising 17 DP-16QAM symbol subsets, each of the DP-16QAM symbol subsets comprising L DP-16QAM symbols, each of the DP-16QAM symbol subsets coming from the L DP-16QAM symbols corresponding to a column in the DP-16QAM symbol set, wherein the f-th DP-16QAM symbol subset in the third data stream corresponds to the DP-16QAM symbol in the f-th column in the DP-16QAM symbol set, 0≤f≤16.

13. The data processing device according to any one of claims 10 to 12, characterized in that: The data processing device further includes a filling unit, and the first data stream is bit-filled by the filling unit after being encoded by the first FEC, wherein the number of filled bits is 119×6=714.

14. The data processing device according to claim 13, characterized in that: The data processing device also includes a convolution interleaving unit, and the first data stream is subjected to convolution interleaving by the convolution interleaving unit after the bit filling.

15. The data processing device according to claim 14, characterized in that: The convolution interleaving unit is specifically used for: The bits from the bit-filled data stream are delayed according to 16 delay lines, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between every two adjacent delay lines is 2, each storage unit is used to store 119 bits, the input bits are input into the 16 delay lines in sequence according to the sequence numbers of the 16 delay lines, each delay line inputs 119 bits at a time and outputs 119 bits at a time, and the continuous 16×119 bits output after convolution interleaving include 119 bits output by each delay line.

16. The data processing device according to any one of claims 10 to 15, characterized in that: Each continuous 119 bits in the first data stream includes 59 bit subsets and a target bit, each of the bit subsets includes 2 bits, and the encoding unit is specifically used for: XORing two bits in each of the bit subsets to obtain one bit, so as to obtain a total of 59 bits; The bit sequence including the 59 bits and the target bit is encoded to obtain 17 check bits, and the continuous 119 bits are information bits in the codeword.

17. The data processing device according to any one of claims 10 to 16, characterized in that: The data processing device further includes a processing unit, which is used to: Perform data distribution on the input data stream to obtain 4 distribution data streams; The first FEC encoding is performed on each of the distribution data streams.

18. The data processing device according to any one of claims 10 to 17, characterized in that: The first FEC coding adopts staircase (512, 510) coding.

19. A chip, characterized in that: The chip includes a processor and a memory, wherein the memory and the processor are connected to each other via a line, instructions are stored in the memory, and the processor is used to execute the method according to any one of claims 1 to 9.

Images