Display panel and display device

Abstract

A display panel and a display device. The display panel comprises pixel drive circuits, wherein the pixel drive circuits each comprise a driving transistor and an eighth transistor, and the eighth transistor has a first electrode connected to a corresponding third initial signal line, and a second electrode connected to a first electrode of the driving transistor. The display panel comprises a substrate (100), a first active layer, and a first conductive layer which are stacked in sequence; the first active layer comprises first sub-active parts (781), second sub-active parts (782), and ninth active parts (79); the ninth active parts each are connected between a corresponding first sub-active part and a corresponding second sub-active part; the first sub-active parts and the second sub-active parts are used for forming channel regions of the eighth transistor; the first conductive layer comprises first reset signal lines; part of the structure of each first reset signal line is used for forming a gate of a corresponding eighth transistor; and the orthographic projection of the first reset signal lines on the substrate and the orthographic projection of the ninth active parts on the substrate are not overlapped. The display panel can mitigate the problem of chromaticity coordinate shift of the display panel.

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311267064.3, entitled “Display Panel and Display Device,” filed on September 27, 2023. The disclosure of the aforementioned Chinese patent application is hereby incorporated by reference in its entirety as part of this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] In the related art, there is a leakage problem in the transistors in the display panel, which causes the color coordinates of the display panel to drift.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes a pixel driving circuit, the pixel driving circuit including a driving transistor and an eighth transistor, the driving transistor being configured to input a driving current to a second electrode thereof using a first electrode thereof according to a gate voltage thereof, the first electrode of the eighth transistor being connected to a third initial signal line, and the second electrode thereof being connected to the first electrode of the driving transistor;

[0008] The display panel includes:

[0009] substrate;

[0010] a first active layer located on one side of the base substrate, the first active layer comprising a first sub-active portion, a second sub-active portion, and a ninth active portion, the ninth active portion being connected between the first sub-active portion and the second sub-active portion, the first sub-active portion being used to form a first channel region of the eighth transistor, and the second sub-active portion being used to form a second channel region of the eighth transistor;

[0011] a first conductive layer located on a side of the first active layer facing away from the base substrate, the first conductive layer including a first reset signal line, the orthographic projection of the first reset signal line on the base substrate covering the orthographic projection of the first sub-active portion on the base substrate and the orthographic projection of the second sub-active portion on the base substrate, a partial structure of the first reset signal line being used to form the gate of the eighth transistor, and the orthographic projection of the first reset signal line on the base substrate and the orthographic projection of the ninth active portion on the base substrate not overlapping.

[0012] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes: a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply terminal, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor;

[0013] The first active layer further comprises:

[0014] a fifth active portion, the fifth active portion being used to form a channel region of the fifth transistor;

[0015] a third active portion, the third active portion being used to form a channel region of the driving transistor;

[0016] The first conductive layer further comprises:

[0017] a first conductive portion, wherein an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form a gate of the driving transistor;

[0018] an enable signal line, wherein an orthographic projection of the enable signal line on the base substrate covers an orthographic projection of the fifth active portion on the base substrate, and a partial structure of the enable signal line is used to form a gate of the fifth transistor;

[0019] Wherein, the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the first reset signal line on the base substrate both extend along a first direction;

[0020] In the same pixel driving circuit, the orthographic projection of the first reset signal line on the base substrate is located on a side of the orthographic projection of the enable signal line on the base substrate away from the orthographic projection of the first conductive portion on the base substrate.

[0021] In an exemplary embodiment of the present disclosure, the gate of the eighth transistor includes a first gate and a second gate;

[0022] The first reset signal line includes:

[0023] a first main line, an orthographic projection of the first main line on the base substrate extending along the first direction and covering an orthographic projection of the first sub-active portion on the base substrate, wherein a portion of the first main line is used to form a first gate of the eighth transistor;

[0024] a first protrusion connected to the first main line, wherein an orthographic projection of the first protrusion on the base substrate is located on a side of the orthographic projection of the first main line on the base substrate away from an orthographic projection of the first conductive portion on the base substrate;

[0025] The orthographic projection of the first protruding portion on the base substrate covers the orthographic projection of the second sub-active portion on the base substrate, and a partial structure of the first protruding portion is used to form the second gate of the eighth transistor.

[0026] In an exemplary embodiment of the present disclosure, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light-emitting unit;

[0027] The first active layer further comprises:

[0028] a seventh active portion, the seventh active portion being used to form a channel region of the seventh transistor;

[0029] An orthographic projection of the first reset signal line on the base substrate covers an orthographic projection of the seventh active portion on the base substrate, and a portion of the first reset signal line is used to form a gate of the seventh transistor;

[0030] In the same pixel driving circuit, in the first direction, the orthographic projection of the first sub-active portion on the base substrate is located between the orthographic projection of the second sub-active portion on the base substrate and the orthographic projection of the seventh active portion on the base substrate.

[0031] In an exemplary embodiment of the present disclosure, the first active layer further includes:

[0032] a tenth active portion connected to an end of the first sub-active portion away from the second sub-active portion;

[0033] an eleventh active portion connected between the third active portion and the fifth active portion;

[0034] The display panel further includes:

[0035] The fourth conductive layer includes a first bridge portion, wherein the first bridge portion is connected to the tenth active portion and the eleventh active portion through via holes.

[0036] In an exemplary embodiment of the present disclosure, the first active layer further includes:

[0037] a twelfth active portion connected to a side of the second sub-active portion away from the first sub-active portion;

[0038] The display panel further includes:

[0039] The fourth conductive layer is located on a side of the first conductive layer away from the base substrate, and the fourth conductive layer includes a second bridge portion, and the second bridge portion is connected to the third initial signal line and the twelfth active portion through via holes.

[0040] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, a first electrode of the first transistor being connected to a first initial signal line, and a second electrode of the first transistor being connected to a second electrode of the driving transistor, wherein an orthographic projection of the first initial signal line on the substrate extends along the first direction;

[0041] The second bridging portion includes:

[0042] The first sub-bridge portion and the first initial signal line are located in different conductive layers, and the orthographic projection of the first sub-bridge portion on the base substrate extends along the first direction and at least partially overlaps with the orthographic projection of the first initial signal line on the base substrate.

[0043] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0044] a shielding layer, located between the base substrate and the first active layer, the shielding layer comprising:

[0045] a plurality of shielding portions, wherein the shielding portions and the third active portions are provided correspondingly, and the orthographic projections of the shielding portions on the base substrate cover the orthographic projections of the corresponding third active portions on the base substrate;

[0046] a first connecting portion connected between two adjacent shielding portions, wherein an orthographic projection of the first connecting portion on the base substrate extends along a second direction, and the second direction intersects the first direction;

[0047] The second bridging portion includes:

[0048] A second sub-bridge portion, wherein an orthographic projection of the second sub-bridge portion on the base substrate extends along the second direction and at least partially overlaps with an orthographic projection of the first connecting portion on the base substrate.

[0049] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0050] a third conductive layer;

[0051] a fourth conductive layer, the fourth conductive layer being located on a side of the first conductive layer facing away from the base substrate, the third conductive layer being located between the first conductive layer and the fourth conductive layer, and the third conductive layer including the third initial signal line;

[0052] An orthographic projection of the third initial signal line on the base substrate extends along the first direction and at least partially overlaps with an orthographic projection of the enable signal line on the base substrate.

[0053] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, wherein a first electrode of the first transistor is connected to the first initial signal line, and a second electrode of the first transistor is connected to the second electrode of the driving transistor;

[0054] The first initial signal line includes:

[0055] a second main body line, wherein an orthographic projection of the second main body line on the base substrate extends along a first direction;

[0056] a second protrusion connected to the second main body line, wherein an orthographic projection of the second protrusion on the base substrate is located on one side of an orthographic projection of the second main body line on the base substrate in a second direction, and the second direction intersects the first direction;

[0057] The orthographic projection of the second protruding portion on the base substrate and the orthographic projection of the ninth active portion on the base substrate at least partially overlap.

[0058] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, a first electrode of the first transistor being connected to a first initial signal line, a second electrode of the first transistor being connected to a second electrode of the driving transistor, and the first transistor being an N-type transistor.

[0059] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0060] a second active layer, located on a side of the first conductive layer facing away from the substrate, the second active layer comprising a first active portion, the first active portion being used to form a channel region of the first transistor;

[0061] a third conductive layer located on a side of the second active layer facing away from the base substrate, the third conductive layer including a second reset signal line, the orthographic projection of the second reset signal line on the base substrate covering the orthographic projection of the first active portion on the base substrate, and a partial structure of the second reset signal line used to form a top gate of the first transistor.

[0062] In an exemplary embodiment of the present disclosure, the third conductive layer also includes the first initial signal line, the orthographic projection of the first initial signal line on the base substrate and the orthographic projection of the first reset signal line on the base substrate both extend along the first direction, and the orthographic projection of the first initial signal line on the base substrate and the orthographic projection of the first reset signal line in the adjacent upper row of pixel driving circuits on the base substrate at least partially overlap.

[0063] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a second transistor, a first electrode of the second transistor being connected to the gate electrode of the driving transistor, a second electrode being connected to the second electrode of the driving transistor, and the second transistor being an N-type transistor;

[0064] The second active layer further comprises:

[0065] a second active portion, the second active portion being configured to form a channel region of the second transistor;

[0066] The third conductive layer further comprises:

[0067] a first gate line, an orthographic projection of the first gate line on the base substrate extending along a first direction and covering an orthographic projection of the second active portion on the base substrate, wherein a portion of the first gate line is used to form a top gate of the second transistor;

[0068] The first active layer further comprises:

[0069] a third active portion, the third active portion being used to form a channel region of the driving transistor;

[0070] The first conductive layer further comprises:

[0071] a first conductive portion, wherein an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form a gate of the driving transistor;

[0072] In the same pixel driving circuit, the orthographic projection of the second reset signal line on the base substrate is located on a side of the orthographic projection of the first gate line on the base substrate away from the orthographic projection of the first conductive portion on the base substrate.

[0073] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes: a fourth transistor, a first electrode of the fourth transistor being connected to the data line, and a second electrode of the fourth transistor being connected to the first electrode of the driving transistor;

[0074] The first active layer further comprises:

[0075] a fourth active portion, the fourth active portion being used to form a channel region of the fourth transistor;

[0076] The first conductive layer further comprises:

[0077] a second gate line, an orthographic projection of the second gate line on the base substrate extending along the first direction and covering an orthographic projection of the fourth active portion on the base substrate, wherein a portion of the second gate line is used to form a gate of the fourth transistor;

[0078] Wherein, in the same pixel driving circuit, the orthographic projection of the second gate line on the base substrate is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the first gate line on the base substrate.

[0079] In an exemplary embodiment of the present disclosure, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light-emitting unit;

[0080] The display panel includes a plurality of pixel driving circuits arrayed in a first direction and a second direction, the first direction and the second direction intersecting each other, and the display panel includes a plurality of second initial signal lines, the orthographic projections of the plurality of second initial signal lines on the base substrate extending along the first direction and spaced apart along the second direction;

[0081] The display panel further includes:

[0082] A plurality of second initial connection lines, the orthographic projections of the second initial connection lines on the substrate extend along the second direction, and the second initial connection lines are connected between two adjacent second initial signal lines in the second direction to form a grid structure with the second initial signal lines.

[0083] In an exemplary embodiment of the present disclosure, two adjacent second initial connection lines and two adjacent second initial signal lines connected thereto form a ring structure, wherein the plurality of ring structures include a first ring structure, a second ring structure, and a third ring structure;

[0084] The first annular structure and the second annular structure are distributed in the first direction, the first annular structure and the third annular structure are distributed in the second direction, and the first annular structure and the third annular structure are staggered in the first direction;

[0085] The second annular structure and the third annular structure are distributed in the second direction, and the second annular structure and the third annular structure are staggered in the first direction.

[0086] In an exemplary embodiment of the present disclosure, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes a sixth transistor, a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit;

[0087] The first active layer includes:

[0088] a sixth active portion, the sixth active portion being configured to form a channel region of the sixth transistor;

[0089] The first conductive layer includes:

[0090] An enable signal line, wherein an orthographic projection of the enable signal line on the base substrate covers an orthographic projection of the sixth active portion on the base substrate, and a partial structure of the enable signal line is used to form a gate of the sixth transistor.

[0091] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0092] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0093] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0094] FIG1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;

[0095] FIG2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in FIG1 ;

[0096] FIG3 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit disclosed herein;

[0097] FIG4 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0098] FIG5 is a structural diagram of the shielding layer in FIG4 ;

[0099] FIG6 is a structural diagram of the first active layer in FIG4 ;

[0100] FIG7 is a structural diagram of the first conductive layer in FIG4 ;

[0101] FIG8 is a structural diagram of the second conductive layer in FIG4 ;

[0102] FIG9 is a structural diagram of the second active layer in FIG4 ;

[0103] FIG10 is a structural diagram of the third conductive layer in FIG4 ;

[0104] FIG11 is a structural diagram of the fourth conductive layer in FIG4 ;

[0105] FIG12 is a structural diagram of the fifth conductive layer in FIG4;

[0106] FIG13 is a structural diagram of the sixth conductive layer in FIG4;

[0107] FIG14 is a structural diagram of the shielding layer and the first active layer in FIG4 ;

[0108] FIG15 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG4 ;

[0109] FIG16 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG4 ;

[0110] FIG17 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG4 ;

[0111] FIG18 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG4 ;

[0112] FIG19 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG4 ;

[0113] FIG20 is a structural layout diagram of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG4 ;

[0114] FIG. 21 is a partial cross-sectional view of the display panel shown in FIG. 4 taken along the dotted line BB. DETAILED DESCRIPTION

[0115] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Identical reference numerals in the figures represent identical or similar structures, and thus detailed descriptions thereof will be omitted.

[0116] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0117] This exemplary embodiment first provides a pixel driving circuit, as shown in Figures 1 and 2. Figure 1 is a structural diagram of an exemplary embodiment of the pixel driving circuit disclosed in the present invention, and Figure 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 1.

[0118] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. A first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and a gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2; a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and a gate of the fifth transistor T5 is connected to the enable signal terminal EM; a gate of the driving transistor T3 is connected to a node N; a first electrode of the second transistor T2 is connected to the node N, a second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and a gate of the second transistor T2 is connected to the first gate driving signal terminal G1; a first electrode of the sixth transistor T6 is connected to the first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and a gate of the fifth transistor T5 is connected to the enable signal terminal EM; a gate of the driving transistor T3 is connected to a node N; a first electrode of the second transistor T2 is connected to the node N, a second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and a gate of the second transistor T2 is connected to the first gate driving signal terminal G1; The pixel driving circuit is connected to the second electrode of the driving transistor T3, the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, the gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the first reset signal terminal Re1; the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3, and the gate of the first transistor T1 is connected to the second reset signal terminal Re2; the first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3, and the gate of the eighth transistor T8 is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive a light-emitting unit OLED. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. The second transistor T2 may be an N-type transistor, for example, an N-type metal oxide transistor. N-type transistors have a relatively low leakage current, thereby preventing leakage of power from the node N through the second transistor T2 during the light-emitting phase. Meanwhile, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type low-temperature polysilicon transistors. P-type transistors have a relatively high carrier mobility, thereby facilitating the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio.The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to actual conditions.

[0119] As shown in Figure 2, where G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, and EM represents the timing of the enable signal terminal EM, the driving method of the pixel driving circuit may include a first reset phase t1, a second reset phase t2, a data writing phase t3, a third reset phase t5, and a light emitting phase t6.

[0120] During the first reset phase t1, the first reset signal terminal Re1 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3 to improve the hysteresis problem of the driving transistor T3. During the second reset phase t2, the first gate drive signal terminal G1 outputs a high-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the node N through the first transistor T1 and the second transistor T2. During the data writing phase t3, the second gate drive signal terminal G2 outputs a low-level signal, the first gate drive signal terminal G1 outputs a high-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the node N through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal and Vth is the threshold voltage of the driving transistor T3. In the third reset phase t5: the first reset signal terminal Re1 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. In the light-emitting phase t6: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata + Vth stored in the capacitor C. The output current formula of the driving transistor is as follows: I = (μWCox / 2L)(Vgs-Vth) 2

[0121] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the above pixel driving circuit is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0122] As shown in Figure 2, during the fourth phase t4 between the data writing phase t3 and the third reset phase t5, the second transistor T2 is turned on, and the signal at the third initial signal terminal Vinit3 leaks to the node N through the eighth transistor T8, the driving transistor T3, and the second transistor T2, thereby affecting the normal emission of the light-emitting unit during the light-emitting phase, thereby causing the color coordinates of the display panel to drift. In addition, during the light-emitting phase, the current output by the driving transistor T3 is also shunted to the first initial signal terminal Vinit1 through the first transistor T1, thereby affecting the normal emission brightness of the light-emitting unit and causing the color coordinates of the display panel to drift.

[0123] Based on this, this exemplary embodiment first provides a pixel driving circuit. FIG3 is a schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed herein. First, this exemplary embodiment configures the first transistor T1 as an N-type transistor. N-type transistors have a relatively low leakage current. This configuration reduces leakage current from the output terminal of the driving transistor T3 to the first initial signal terminal through the first transistor T1, thereby alleviating the aforementioned color coordinate drift issue.

[0124] In addition, in this exemplary embodiment, the eighth transistor T8 can also be set to a dual-gate structure, that is, the eighth transistor T8 includes two channel regions arranged at intervals. This setting can reduce the leakage current of the eighth transistor T8, thereby reducing the leakage current from the third initial signal terminal to the node N. This setting can also improve the above-mentioned color coordinate drift problem.

[0125] In this exemplary embodiment, the first reset signal terminal Re1 can also periodically turn on the seventh transistor in subsequent light-emitting phases to periodically reset the first electrode of the light-emitting unit, thereby improving the problem of low-frequency flickering in the display panel. For example, the first reset signal terminal Re1 can turn on the seventh transistor in a sustain frame when no data signal is written.

[0126] This exemplary embodiment further provides a display panel, which may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer stacked in sequence. Insulating layers may be provided between adjacent layers. As shown in Figures 4-20, Figure 4 is a structural layout of an exemplary embodiment of the display panel disclosed herein, Figure 5 is a structural layout of the blocking layer in Figure 4, Figure 6 is a structural layout of the first active layer in Figure 4, Figure 7 is a structural layout of the first conductive layer in Figure 4, Figure 8 is a structural layout of the second conductive layer in Figure 4, Figure 9 is a structural layout of the second active layer in Figure 4, Figure 10 is a structural layout of the third conductive layer in Figure 4, Figure 11 is a structural layout of the fourth conductive layer in Figure 4, Figure 12 is a structural layout of the fifth conductive layer in Figure 4, Figure 13 is a structural layout of the sixth conductive layer in Figure 4, Figure 14 is a structural layout of the blocking layer and the first active layer in Figure 4, and Figure 15 is a structural layout of the blocking layer, the first active layer, and the first conductive layer in Figure 4. FIG16 is a structural layout diagram of the blocking layer, the first active layer, the first conductive layer, and the second conductive layer in FIG4 ; FIG17 is a structural layout diagram of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG4 ; FIG18 is a structural layout diagram of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG4 ; FIG19 is a structural layout diagram of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG4 ; FIG20 is a structural layout diagram of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG4 . The display panel may include multiple pixel drive circuits shown in FIG3 . As shown in FIG4 , the plurality of pixel driving circuits may include a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2 adjacently distributed in a first direction X. At least portions of the structures of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may be arranged in mirror symmetry about a mirror symmetry plane AA. The mirror symmetry plane AA may be perpendicular to the substrate. Furthermore, at least portions of the orthographic projection of the first pixel driving circuit Pix1 on the substrate and the orthographic projection of the second pixel driving circuit Pix2 on the substrate may be arranged symmetrically about the intersection of the mirror symmetry plane AA and the substrate as an axis of symmetry. The first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may form a repeating unit, and the display panel may include a plurality of repeating units arranged in an array in the first direction X and the second direction Y.

[0127] As shown in Figures 4, 5, and 14, the shielding layer may include a plurality of shielding portions 81 and a first connecting portion 82, wherein the first connecting portion 82 is connected between two adjacent shielding portions 81, and the orthographic projection of the first connecting portion 82 on the base substrate extends along the second direction Y. It should be understood that in other exemplary embodiments, the display panel may not include a shielding layer.

[0128] As shown in Figures 4, 6, 14 and 15, the first active layer may include: a first sub-active portion 781, a second sub-active portion 782, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a nineteenth active portion 719 and a twentieth active portion 720. The first sub-active portion 781 is used to form the first channel region of the eighth transistor; the second sub-active portion 782 is used to form the second channel region of the eighth transistor T8; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the ninth active portion 79 is connected between the first sub-active portion 781 and the second sub-active portion 782; the tenth active portion 710 is connected to the first sub-active portion 781 away from the second The shielding portion 81 is connected to one side of the sub-active portion 782; the eleventh active portion 711 is connected between the fifth active portion 75 and the third active portion 73; the twelfth active portion 712 is connected to the side of the second sub-active portion 782 away from the first sub-active portion 781; the thirteenth active portion 713 is connected to the side of the fourth active portion 74 away from the third active portion 73; the fourteenth active portion 714 is connected to the side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to the side of the fifth active portion 75 away from the third active portion 73; the nineteenth active portion 719 is connected between the third active portion 73 and the sixth active portion 76; and the twentieth active portion 720 is connected between the seventh active portion 77 and the sixth active portion 76. The orthographic projection of the shielding portion 81 on the substrate can cover the orthographic projection of the third active portion 73 on the substrate, and the shielding portion 81 can reduce the influence of light on the driving characteristics of the driving transistor T3. The first active layer may be formed of polysilicon material. Accordingly, the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be P-type low-temperature polysilicon thin film transistors.

[0129] As shown in Figures 4, 7, and 15, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, and a first reset signal line Re1. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 3; the enable signal line EM can be used to provide the enable signal terminal in Figure 3; and the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 3. The orthographic projections of the second gate line G2, the enable signal line EM, and the first reset signal line Re1 on the substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the substrate overlaps the orthographic projection of the fourth active portion 74 on the substrate, and a portion of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projections of the fifth active portion 75 and the sixth active portion 76 on the substrate, and a portion of the enable signal line EM is used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate can overlap the orthographic projection of the seventh active portion 77, the orthographic projection of the first sub-active portion 781, and the orthographic projection of the second sub-active portion 782. Portions of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73. The first conductive portion 11 can be used to form the gate of the drive transistor T3 and the first electrode of the capacitor C.

[0130] As shown in Figures 4, 7, and 15, in the same pixel driving circuit, the orthographic projection of the first reset signal line Re1 on the base substrate can be located on a side where the orthographic projection of the enable signal line EM on the base substrate is away from the orthographic projection of the first conductive part 11 on the base substrate.

[0131] As shown in Figures 4, 7, and 15, the first reset signal line includes: a first main line Re11 and a first raised portion Re12. The orthographic projection of the first main line Re11 on the substrate extends along the first direction X and covers the orthographic projection of the first sub-active portion 781 on the substrate. Part of the structure of the first main line Re11 is used to form the first gate of the eighth transistor T8. The first raised portion Re12 is connected to the first main line Re11, and the orthographic projection of the first raised portion Re12 on the substrate is located on a side of the orthographic projection of the first main line Re11 on the substrate that is away from the orthographic projection of the first conductive portion 11 on the substrate. The orthographic projection of the first raised portion Re12 on the substrate covers the orthographic projection of the second sub-active portion 782 on the substrate. Part of the structure of the first raised portion Re12 is used to form the second gate of the eighth transistor T8. This arrangement can prevent the first raised portion Re12 from being too close to the first conductive portion 11, thereby affecting the stability of the voltage on the first conductive portion 11.

[0132] As shown in Figures 4, 7, and 15, in the same pixel driving circuit, in the first direction X, the orthographic projection of the first sub-active portion 781 on the base substrate is located between the orthographic projection of the second sub-active portion 782 on the base substrate and the orthographic projection of the seventh active portion on the base substrate. Thus, two mirror-symmetrical pixel driving circuits can share the twelfth active portion 712, which can improve the integration of the display panel.

[0133] In this exemplary embodiment, the shielding layer can also be connected to a stable power supply terminal. For example, the shielding layer can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, and the third initial signal terminal in Figure 3. The shielding portion 81 can shield the noise of other signals from affecting the driving transistor T3. The display panel can use the first conductive layer as a mask to perform a conductor processing on the first active layer. That is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer can form a conductor structure.

[0134] As shown in Figures 4, 8, and 16, the second conductive layer may include: a third gate line 2G1, a third reset signal line 2Re2, and a second conductive portion 22. The orthographic projection of the third gate line 2G1 on the base substrate and the orthographic projection of the third reset signal line 2Re2 on the base substrate extend along the first direction X. The third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 3, and the third reset signal line 2Re2 is used to provide the second reset signal terminal in Figure 3. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate. The second conductive portion 22 is used to form a second electrode of the capacitor C. The second conductive layer may further include a second connecting portion 23, and adjacent second conductive portions 22 in the first direction X can be connected through the second connecting portion 23.

[0135] As shown in Figures 4, 9, and 17, the second active layer may include an active portion 9, which may include a first active portion 91, a second active portion 92, a sixteenth active portion 916, a seventeenth active portion 917, and an eighteenth active portion 918. The first active portion 91 is used to form the channel region of the first transistor T1, and the second active portion 92 is used to form the channel region of the second transistor T2. The sixteenth active portion 916 is connected to a side of the first active portion 91 away from the second active portion 92, the seventeenth active portion 917 is connected between the first active portion 91 and the second active portion 92, and the eighteenth active portion 918 is connected to a side of the second active portion 92 away from the first active portion 91. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G1 on the substrate can overlap the orthographic projection of the second active portion 92 on the substrate, and a portion of the third gate line 2G1 can be used to form the bottom gate of the second transistor T2. The orthographic projection of the third reset signal line 2Re2 on the substrate can overlap the orthographic projection of the first active portion 61 on the substrate, and a portion of the third reset signal line 2Re2 can be used to form the bottom gate of the first transistor T1.

[0136] As shown in Figures 4, 10, and 18, the third conductive layer may include a second reset signal line 3Re2, a first gate line 3G1, a first initial signal line Vinit1, and a third initial signal line Vinit3. The orthographic projection of the second reset signal line 3Re2 on the base substrate, the orthographic projection of the first gate line 3G1 on the base substrate, the orthographic projection of the first initial signal line Vinit1 on the base substrate, and the orthographic projection of the third initial signal line Vinit3 on the base substrate may all extend along the first direction X. The second reset signal line 3Re2 may be used to provide the second reset signal terminal in Figure 3, the orthographic projection of the second reset signal line 3Re2 on the base substrate may cover the orthographic projection of the first active portion 91 on the base substrate, and a partial structure of the second reset signal line 3Re2 may be used to form the top gate of the first transistor T1. At the same time, the second reset signal line 3Re2 may be connected to the third reset signal line 2Re2 through a via located in the frame area of ​​the display panel. The first gate line 3G1 can be used to provide the first gate drive signal terminal in Figure 3. The orthographic projection of the first gate line 3G1 on the substrate can cover the orthographic projection of the second active portion 92 on the substrate. Part of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the frame area of ​​the display panel. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in Figure 3, and the third initial signal line Vinit3 can be used to provide the third initial signal terminal in Figure 3. The orthographic projection of the first initial signal line Vinit1 on the substrate can at least partially overlap with the orthographic projection of the first reset signal line Re1 in the adjacent previous row of pixel drive circuits on the substrate. The orthographic projection of the third initial signal line Vinit3 on the substrate can at least partially overlap with the orthographic projection of the enable signal line EM in the pixel drive circuit of the current row on the substrate. This arrangement can improve the transmittance of the display panel. The first initial signal line Vinit1 may include a second main line Vinit11 and a second raised portion Vinit12. The orthographic projection of the second main line Vinit11 on the substrate extends along the first direction X. The second raised portion Vinit12 is connected to the second main line Vinit11, and the orthographic projection of the second raised portion Vinit12 on the substrate is located to one side of the orthographic projection of the second main line Vinit11 on the substrate in the second direction Y. The orthographic projection of the second raised portion Vinit12 on the substrate at least partially overlaps with the orthographic projection of the ninth active portion 79 on the substrate. The second raised portion Vinit12 can stabilize the voltage of the ninth active portion 79, thereby reducing leakage current from the ninth active portion 79 to the source and drain of the eighth transistor.In addition, the display panel can use the third conductive layer as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0137] As shown in Figures 4, 11, and 19, the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a second initial signal line Vinit2, and a second initial connection line 4Vinit2.

[0138] As shown in Figures 4, 11, and 19, the first bridge portion 41 can be connected to the tenth active portion 710 and the eleventh active portion 711 through vias, respectively, to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The second bridge portion 42 is connected to the third initial signal line Vinit3 and the twelfth active portion 712 through vias, respectively, to connect the first electrode of the eighth transistor T8 and the third initial signal terminal. The second bridge portion 42 includes a first sub-bridge portion 421 and a second sub-bridge portion 422. The orthographic projection of the first sub-bridge portion 421 on the base substrate extends along the first direction X and at least partially overlaps with the orthographic projection of the first initial signal line Vinit1 on the base substrate. The orthographic projection of the second sub-bridge portion 422 on the base substrate extends along the second direction Y and at least partially overlaps with the orthographic projection of the first connecting portion 82 on the base substrate. This arrangement can improve the light transmittance of the display panel. The third bridge portion 43 can be connected to the sixteenth active portion 916 and the first initial signal line Vinit1 through vias, respectively, to connect the first electrode of the first transistor T1 and the first initial signal terminal. The fourth bridge portion 44 can be connected to the seventeenth active portion 917 and the nineteenth active portion 719 through vias, respectively, to connect the second electrode of the first transistor T1 and the second electrode of the driving transistor T3. The fifth bridge portion 45 is connected to the eighteenth active portion 918 and the first conductive portion 11 through vias, respectively, to connect the first electrode of the second transistor T2 and the gate of the driving transistor T3. The second conductive portion 22 can have an opening 221 formed therein, and a via connected between the fifth bridge portion 45 and the first conductive portion 11 is provided through the opening 221. The sixth bridge portion 46 can be connected to the twentieth active portion 720 through a via to connect the second electrode of the seventh transistor. The seventh bridge portion 47 can be connected to the thirteenth active portion 713 through a via to connect the first electrode of the fourth transistor. The eighth bridge portion 48 can be connected to the second connection portion 23 and the fifteenth active portion 715 through vias to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. The second initial signal line Vinit2 can be connected to the fourteenth active portion through a via to connect the first electrode of the seventh transistor T7.

[0139] The orthographic projection of the second initial signal line Vinit2 on the base substrate extends along a first direction X. The orthographic projection of the second initial connecting line 4Vinit2 on the base substrate extends along a second direction Y. The second initial connecting line 4Vinit2 is connected between two adjacent second initial signal lines Vinit2 in the second direction Y, thereby forming a grid structure with the second initial signal lines Vinit2. The grid structure of the second initial signal lines Vinit2 can reduce the voltage difference between the second initial signal terminals at different positions on the display panel, thereby improving the uniformity of the display panel.

[0140] As shown in Figures 4, 11, and 19, two adjacent second initial connection lines 4Vinit2 and two adjacent second initial signal lines Vinit2 connected thereto form a ring structure, wherein the plurality of ring structures include a first ring structure V1, a second ring structure V2, and a third ring structure V3; the first ring structure V1 and the second ring structure V2 are distributed in the first direction X, the first ring structure V1 and the third ring structure V3 are distributed in the second direction Y, and the first ring structure V1 and the third ring structure V3 are staggered in the first direction X; the second ring structure V2 and the third ring structure V3 are distributed in the second direction Y, and the second ring structure V2 and the third ring structure V3 are staggered in the first direction X. Partial structures of the first ring structure V1 and the second ring structure V2 are not fully illustrated.

[0141] In this exemplary embodiment, one second initial connection line 4Vinit2 may be provided for every four columns of pixel driving circuits. It should be understood that in other exemplary embodiments, each second initial connection line 4Vinit2 may also correspond to other numbers of columns of pixel driving circuits.

[0142] As shown in Figures 4, 12, and 20, the fifth conductive layer may include: a ninth bridge portion 59, a tenth bridge portion 510, an eleventh bridge portion 511, and a first fan-out line FIPH. The ninth bridge portion 59 may be connected to the eighth bridge portion 48 via a via to connect to the first electrode of the fifth transistor T5. The tenth bridge portion 510 may be connected to the seventh bridge portion 47 via a via to connect to the first electrode of the fourth transistor. The orthographic projection of the first fan-out line FIPH on the substrate may extend along the first direction X. The first fan-out line FIPH may serve as a fan-out line connecting a data line in a FIP (Fanout In Pixel).

[0143] As shown in Figures 4 and 13, the sixth conductive layer may include: a data line Da, a first power line VDD, and a second fan-out line FIPV. The orthographic projections of the data line Da, the first power line VDD, and the second fan-out line FIPV on the substrate may extend along the second direction Y. The data line Da is used to provide the data signal terminal in Figure 3, and the first power line VDD is used to provide the first power terminal in Figure 3. The data line Da may be connected to the tenth bridge portion 510 through a via to connect the data signal terminal and the first electrode of the fourth transistor. The first power line VDD may be connected to the ninth bridge portion through a via to connect the first electrode of the fifth transistor and the first power terminal. The second fan-out line FIPV may serve as a fan-out line connecting the data line in the FIP (Fanout In Pixel, fan-out area in the pixel), and the second fan-out line FIPV may be connected to the eleventh bridge portion 511 through a via.

[0144] The orthographic projection of the ninth bridge portion 59 on the substrate can overlap the orthographic projections of the first active portion 91 and the second active portion 92 on the substrate. The ninth bridge portion 59 can reduce the effects of light on the characteristics of the first transistor T1 and the second transistor T2. The orthographic projection of the ninth bridge portion 59 on the substrate can also at least partially overlap with the orthographic projection of the fifth bridge portion 45 on the substrate. The ninth bridge portion 59 can shield the fifth bridge portion 45 from noise interference from other signals, thereby improving the stability of the gate voltage of the driving transistor T3.

[0145] In adjacent repeating units in the first direction X, adjacent first power lines VDD are connected to each other. The first power lines VDD may form a grid structure through the eighth bridge portion 48 . The grid structure of the power lines may reduce the voltage drop of the power signal thereon.

[0146] It should be noted that, as shown in Figures 4, 19, and 20, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the sixth conductive layer facing away from the substrate represent vias connecting the sixth conductive layer to other layers facing the substrate. Different vias represented by black squares in different locations can penetrate different insulating layers.

[0147] As shown in FIG21 , a partial cross-sectional view of the display panel shown in FIG4 taken along dotted line BB is shown. The display panel may further include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planarization layer 108, and a second planarization layer 109. The substrate 100, the shielding layer, the first insulating layer 101, the first active layer, the second insulating layer 102, the first conductive layer, the third insulating layer 103, the second conductive layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third conductive layer, the first dielectric layer 106, the fourth conductive layer, the passivation layer 107, the first planarization layer 108, the fifth conductive layer, the second planarization layer 109, and the sixth conductive layer are stacked in sequence. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure. The materials of the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The materials of the first planarizing layer 108 and the second planarizing layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The passivation layer 97 can be a silicon oxide layer. The base substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The material of the first conductive layer, the second conductive layer, and the third conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate thereof. The material of the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate thereof, or a titanium / aluminum / titanium laminate thereof. The square resistance of any one of the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be less than the square resistance of any one of the first conductive layer, the second conductive layer, and the third conductive layer. The display panel may further include an electrode layer, a light-emitting unit layer, etc., located on the side of the sixth conductive layer facing away from the base substrate.

[0148] It should be noted that the proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structural names, and they do not have a specific order of meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the base substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the base substrate extending in a straight line or bending along that direction.

[0149] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0150] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0151] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0152] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and an eighth transistor, the driving transistor is used to input a driving current to a second electrode thereof using a first electrode thereof according to a gate voltage thereof, the first electrode of the eighth transistor is connected to a third initial signal line, and the second electrode is connected to the first electrode of the driving transistor; The display panel comprises: substrate substrate; a first active layer, located on one side of the base substrate, the first active layer comprising a first sub-active portion, a second sub-active portion, and a ninth active portion, the ninth active portion being connected between the first sub-active portion and the second sub-active portion, the first sub-active portion being used to form a first channel region of the eighth transistor, and the second sub-active portion being used to form a second channel region of the eighth transistor; A first conductive layer is located on a side of the first active layer away from the base substrate, the first conductive layer includes a first reset signal line, the orthographic projection of the first reset signal line on the base substrate covers the orthographic projection of the first sub-active portion on the base substrate and the orthographic projection of the second sub-active portion on the base substrate, a partial structure of the first reset signal line is used to form a gate of the eighth transistor, and the orthographic projection of the first reset signal line on the base substrate and the orthographic projection of the ninth active portion on the base substrate do not overlap.

2. The display panel according to claim 1, wherein: The pixel driving circuit further includes: a fifth transistor, a first electrode of the fifth transistor being connected to the first power supply terminal, and a second electrode of the fifth transistor being connected to the first electrode of the driving transistor; The first active layer further comprises: a fifth active portion, the fifth active portion being used to form a channel region of the fifth transistor; a third active portion, the third active portion being used to form a channel region of the driving transistor; The first conductive layer further comprises: a first conductive portion, wherein an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form a gate of the driving transistor; An enable signal line, wherein the orthographic projection of the enable signal line on the base substrate covers the orthographic projection of the fifth active portion on the base substrate, and a partial structure of the enable signal line is used to form forming a gate of the fifth transistor; Wherein, the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the first reset signal line on the base substrate both extend along a first direction; In the same pixel driving circuit, the orthographic projection of the first reset signal line on the base substrate is located on a side where the orthographic projection of the enable signal line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate.

3. The display panel according to claim 2, wherein: The gate of the eighth transistor includes a first gate and a second gate; The first reset signal line comprises: a first main body line, an orthographic projection of the first main body line on the base substrate extending along the first direction and covering an orthographic projection of the first sub-active portion on the base substrate, and a partial structure of the first main body line being used to form a first gate of the eighth transistor; A first protrusion connected to the first main line, wherein an orthographic projection of the first protrusion on the base substrate is located on a side of the orthographic projection of the first main line on the base substrate away from an orthographic projection of the first conductive portion on the base substrate; The orthographic projection of the first protruding portion on the base substrate covers the orthographic projection of the second sub-active portion on the base substrate, and a partial structure of the first protruding portion is used to form the second gate of the eighth transistor.

4. The display panel according to claim 1, wherein: The pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit also includes a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light-emitting unit; The first active layer further comprises: a seventh active portion, the seventh active portion being used to form a channel region of the seventh transistor; The orthographic projection of the first reset signal line on the base substrate covers the orthographic projection of the seventh active portion on the base substrate, and a partial structure of the first reset signal line is used to form a gate of the seventh transistor; Among them, in the same pixel driving circuit, in the first direction, the orthographic projection of the first sub-active portion on the base substrate is located between the orthographic projection of the second sub-active portion on the base substrate and the orthographic projection of the seventh active portion on the base substrate.

5. The display panel according to claim 2, wherein: The first active layer further comprises: a tenth active portion connected to an end of the first sub-active portion away from the second sub-active portion; an eleventh active portion, the eleventh active portion being connected between the third active portion and the fifth active portion; The display panel further includes: A fourth conductive layer includes a first bridge portion, wherein the first bridge portion is connected to the tenth active portion and the eleventh active portion through via holes.

6. The display panel according to claim 2, wherein: The first active layer further comprises: a twelfth active portion connected to a side of the second sub-active portion away from the first sub-active portion; The display panel further includes: The fourth conductive layer is located on a side of the first conductive layer away from the base substrate, and the fourth conductive layer includes a second bridge portion, and the second bridge portion is connected to the third initial signal line and the twelfth active portion through via holes.

7. The display panel according to claim 6, wherein: The pixel driving circuit further comprises a first transistor, a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a second electrode of the driving transistor, and an orthographic projection of the first initial signal line on the substrate extends along the first direction; The second bridging portion comprises: The first sub-bridge portion and the first initial signal line are located in different conductive layers, and the orthographic projection of the first sub-bridge portion on the base substrate extends along the first direction and at least partially overlaps with the orthographic projection of the first initial signal line on the base substrate.

8. The display panel according to claim 6, wherein: The display panel further includes: A shielding layer, located between the base substrate and the first active layer, the shielding layer comprising: A plurality of shielding parts, wherein the shielding parts and the third active parts are arranged correspondingly, and the orthographic projections of the shielding parts on the base substrate cover the orthographic projections of the corresponding third active parts on the base substrate; A first connecting portion connected between two adjacent shielding portions, wherein an orthographic projection of the first connecting portion on the base substrate extends along a second direction, and the second direction intersects the first direction; The second bridging portion comprises: A second sub-bridge portion, wherein the orthographic projection of the second sub-bridge portion on the base substrate is along the The second direction extends and at least partially overlaps with the orthographic projection of the first connecting portion on the base substrate.

9. The display panel according to claim 2, wherein: The display panel further includes: a third conductive layer; a fourth conductive layer, the fourth conductive layer being located on a side of the first conductive layer away from the base substrate, the third conductive layer being located between the first conductive layer and the fourth conductive layer, and the third conductive layer comprising the third initial signal line; The orthographic projection of the third initial signal line on the base substrate extends along the first direction and at least partially overlaps with the orthographic projection of the enable signal line on the base substrate.

10. The display panel according to claim 1, wherein: The pixel driving circuit further comprises a first transistor, a first electrode of the first transistor being connected to the first initial signal line, and a second electrode of the first transistor being connected to the second electrode of the driving transistor; The first initial signal line comprises: A second main body line, the orthographic projection of the second main body line on the base substrate extending along a first direction; A second protrusion connected to the second main body line, wherein an orthographic projection of the second protrusion on the base substrate is located on one side of an orthographic projection of the second main body line on the base substrate in a second direction, and the second direction intersects the first direction; The orthographic projection of the second protruding portion on the base substrate and the orthographic projection of the ninth active portion on the base substrate at least partially overlap.

11. The display panel according to claim 1, wherein: The pixel driving circuit further includes a first transistor, a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a second electrode of the driving transistor, and the first transistor is an N-type transistor.

12. The display panel according to claim 11, wherein: The display panel further includes: a second active layer, located on a side of the first conductive layer away from the substrate, the second active layer comprising a first active portion, the first active portion being used to form a channel region of the first transistor; a third conductive layer, located on a side of the second active layer away from the substrate, the third conductive layer comprising a second reset signal line, the orthographic projection of the second reset signal line on the substrate covers the orthographic projection of the first active portion on the substrate, and the second reset signal line A portion of the structure of the signal line is used to form a top gate of the first transistor.

13. The display panel according to claim 12, wherein: The third conductive layer also includes the first initial signal line, the orthographic projection of the first initial signal line on the base substrate and the orthographic projection of the first reset signal line on the base substrate both extend along the first direction, and the orthographic projection of the first initial signal line on the base substrate and the orthographic projection of the first reset signal line in the adjacent previous row of pixel driving circuits on the base substrate at least partially overlap.

14. The display panel according to claim 12, wherein: The pixel driving circuit further includes a second transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, a second electrode is connected to the second electrode of the driving transistor, and the second transistor is an N-type transistor; The second active layer further comprises: a second active portion, the second active portion being used to form a channel region of the second transistor; The third conductive layer further comprises: a first gate line, wherein an orthographic projection of the first gate line on the base substrate extends along a first direction and covers an orthographic projection of the second active portion on the base substrate, and a partial structure of the first gate line is used to form a top gate of the second transistor; The first active layer further comprises: a third active portion, the third active portion being used to form a channel region of the driving transistor; The first conductive layer further comprises: a first conductive portion, wherein an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form a gate of the driving transistor; Wherein, in the same pixel driving circuit, the orthographic projection of the second reset signal line on the base substrate is located on a side where the orthographic projection of the first gate line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate.

15. The display panel according to claim 14, wherein: The pixel driving circuit further includes: a fourth transistor, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The first active layer further comprises: a fourth active portion, the fourth active portion being used to form a channel region of the fourth transistor; The first conductive layer further comprises: a second gate line, an orthographic projection of the second gate line on the base substrate extending along the first direction and covering an orthographic projection of the fourth active portion on the base substrate, and a partial structure of the second gate line being used to form a gate of the fourth transistor; Wherein, in the same pixel driving circuit, the orthographic projection of the second gate line on the base substrate is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the first gate line on the base substrate.

16. The display panel according to claim 1, wherein: The pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit also includes a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light-emitting unit; The display panel comprises a plurality of pixel driving circuits arrayed in a first direction and a second direction, the first direction and the second direction intersect, the display panel comprises a plurality of second initial signal lines, the orthographic projections of the plurality of second initial signal lines on the base substrate extend along the first direction and are spaced apart along the second direction; The display panel further includes: A plurality of second initial connection lines, wherein the orthographic projections of the second initial connection lines on the substrate extend along the second direction, and the second initial connection lines are connected between two adjacent second initial signal lines in the second direction to form a grid structure with the second initial signal lines.

17. The display panel according to claim 16, wherein: Two adjacent second initial connection lines and two adjacent second initial signal lines connected thereto form a ring structure, wherein the plurality of ring structures include a first ring structure, a second ring structure, and a third ring structure; The first annular structure and the second annular structure are distributed in the first direction, the first annular structure and the third annular structure are distributed in the second direction, and the first annular structure and the third annular structure are staggered in the first direction; The second annular structure and the third annular structure are distributed in the second direction, and the second annular structure and the third annular structure are staggered in the first direction.

18. The display panel according to claim 16, wherein: The pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit also includes a sixth transistor, a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit; The first active layer comprises: a sixth active portion, the sixth active portion being used to form a channel region of the sixth transistor; The first conductive layer comprises: An enable signal line, wherein the orthographic projection of the enable signal line on the base substrate covers the orthographic projection of the sixth active portion on the base substrate, and a partial structure of the enable signal line is used to form a gate of the sixth transistor.

19. A display device, wherein: The display device comprises the display panel according to any one of claims 1-18.

Images