Display panel, driving circuit, shift register, and driving method for shift register

Abstract

A display panel, a driving circuit, a shift register, and a driving method for the shift register, which relate to the technical field of display. The shift register comprises: an input circuit (10), which, in response to a first clock signal provided by a first clock signal end, transmits to a first input node an input signal provided by an input end; a voltage stabilizing circuit (20), which transmits, under the control of the voltage of the first input node, a first control signal to a first output node; a first control circuit (30), which transmits a second control signal to a second output node under the control of a second clock signal provided by a second clock signal end and the voltage of the first input node; a second control circuit (40), which controls the first control signal and the second control signal under the control of the voltage of the first input node and the second control signal; and an output circuit (50), which outputs, under the control of the first control signal and the second control signal, a signal of a second voltage end or a third voltage end via an output end, wherein the second voltage end and the output end can be conducted by means of the voltage of a first voltage end.

Description

Display panel, driving circuit, shift register and driving method thereof

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311280233.7 filed on September 28, 2023, entitled “Display panel, driving circuit, shift register and driving method thereof”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel, a driving circuit, a shift register, and a driving method of the shift register. Background Art

[0004] In a display panel using light-emitting diodes as light-emitting devices, its pixel circuits are usually scanned using signals output by a driving circuit, which includes multiple shift registers. When the output signals of existing shift registers switch, there is a signal delay, which also causes a delay in the image.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] The present disclosure provides a display panel, a driving circuit, a shift register, and a driving method of the shift register, which can improve the signal delay problem.

[0008] According to one aspect of the present disclosure, there is provided a shift register, comprising:

[0009] an input circuit connected to the input terminal, the first clock signal terminal, and the first input node, and configured to transmit the input signal provided by the input terminal to the first input node in response to the first clock signal provided by the first clock signal terminal;

[0010] a voltage stabilizing circuit connected to the first voltage terminal, the first output node, and the first input node, and configured to transmit a first control signal to the first output node under the control of the voltage of the first input node;

[0011] a first control circuit connected to the second voltage terminal, the second clock signal terminal, the third voltage terminal, the second output node, and the first input node, and configured to transmit a second control signal to the second output node under the control of a second clock signal provided by the second clock signal terminal and the voltage of the first input node;

[0012] a second control circuit connected to the third voltage terminal, the first input node, the first output node, and the second output node, and configured to control the first control signal and the second control signal under the control of the voltage of the first input node and the second control signal;

[0013] The output circuit is connected to the first output node, the second output node, the second voltage terminal, the third voltage terminal and the output terminal, and is configured to output the signal of the second voltage terminal or the third voltage terminal from the output terminal under the control of the first control signal and the second control signal; the voltage of the first voltage terminal can turn on the second voltage terminal and the output terminal.

[0014] In an exemplary embodiment of the present disclosure, the first control circuit includes:

[0015] a first control subcircuit connected to the second input node, the second voltage terminal, and the second clock signal terminal, and configured to be turned on or off under the control of the second clock signal;

[0016] a second control subcircuit connected to the connection node, the first input node, and the third voltage terminal, and configured to be turned on or off under the control of the voltage of the first input node;

[0017] The third control subcircuit is connected to the second input node and the connection node, and is configured to be turned on or off under the control of the voltage of the third voltage terminal.

[0018] In an exemplary embodiment of the present disclosure, the first control subcircuit includes a first control transistor, the second control subcircuit includes a second control transistor, and the third control subcircuit includes a third control transistor and a first capacitor;

[0019] The gate of the first control transistor is connected to the second clock signal terminal, the first electrode is connected to the second voltage terminal, and the second electrode is connected to the second input node;

[0020] The gate of the second control transistor is connected to the first input node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the connection node;

[0021] The gate of the third control transistor is connected to the connection node via a first capacitor, the first electrode is connected to the connection node, and the second electrode is connected to the second input node.

[0022] In an exemplary embodiment of the present disclosure, the voltage stabilizing circuit includes a voltage stabilizing transistor and a second capacitor;

[0023] The voltage stabilizing transistor has a gate connected to the first input node and the second capacitor, a first electrode connected to the first voltage terminal, and a second electrode connected to the second capacitor and the first output node.

[0024] In an exemplary embodiment of the present disclosure, the second control circuit includes a fourth control subcircuit and a fifth control subcircuit;

[0025] The fourth control subcircuit is connected to the third voltage terminal, the first input node and the second output node, and is configured to control the second control signal under the control of the voltage of the first input node;

[0026] The fifth control subcircuit is connected to the third voltage terminal, the first output node, and the second output node, and is configured to control the first control signal under the control of the voltage of the second output node.

[0027] In an exemplary embodiment of the present disclosure, the fourth control subcircuit includes a fourth control transistor; the fifth control subcircuit includes a fifth control transistor;

[0028] The gate of the fourth control transistor is connected to the first input node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the second output node;

[0029] The fifth control transistor has a gate connected to the second output node, a first electrode connected to the third voltage terminal, and a second electrode connected to the first output node.

[0030] In an exemplary embodiment of the present disclosure, the input circuit includes an input transistor, wherein a gate of the input transistor is connected to the first clock signal terminal, a first electrode is connected to the input terminal, and a second electrode is connected to the first input node;

[0031] The output circuit includes a first output transistor, a third capacitor, a second output transistor and a fourth capacitor;

[0032] The gate of the first output transistor is connected to the first output node, the first electrode is connected to the second voltage terminal, the second electrode is connected to the output terminal, and the third capacitor is connected to the first output node and the second voltage terminal;

[0033] The second output transistor has a gate connected to the second output node, a first electrode connected to the third voltage terminal, and a second electrode connected to the output terminal. The fourth capacitor is connected to the second output node and the third voltage terminal.

[0034] In an exemplary embodiment of the present disclosure, the shift register further includes:

[0035] A first isolation circuit is connected to the first input node and the voltage stabilizing circuit.

[0036] In an exemplary embodiment of the present disclosure, the shift register further includes:

[0037] The second isolation circuit is connected to the connection node and the second output node.

[0038] In an exemplary embodiment of the present disclosure, the first isolation circuit includes a first isolation transistor; the second isolation circuit includes a second isolation transistor;

[0039] The gate of the first isolation transistor is connected to the second voltage terminal, the first electrode is connected to the first input node, and the second electrode is connected to the voltage stabilizing circuit;

[0040] The second isolation transistor has a gate connected to the second voltage terminal, a first electrode connected to the connection node, and a second electrode connected to the second output node.

[0041] According to one aspect of the present disclosure, a driving circuit is provided, comprising a plurality of cascaded shift registers, wherein the shift register is any one of the shift registers described above.

[0042] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0043] A driving backplane comprising a plurality of pixel circuits and a first driving circuit, wherein the pixel circuits are arranged in an array along row and column directions; the first driving circuit is any one of the driving circuits described above, and an output end of the first driving circuit is connected to at least one row of the pixel circuits;

[0044] The light emitting devices are distributed in an array on one side of the driving backplane.

[0045] In an exemplary embodiment of the present disclosure, the pixel circuit includes a plurality of transistors; the number of the first driving circuits is two; the display panel further includes a second driving circuit;

[0046] The gates of some transistors in the same pixel circuit are connected to the output end of the first driving circuit, and the gates of another part of the transistors are connected to the output end of the second driving circuit; and the two first driving circuits are connected to the gates of different transistors in the pixel circuit.

[0047] In an exemplary embodiment of the present disclosure, the pixel circuit includes a driving transistor, a write transistor, a compensation transistor, a first reset transistor, a second reset transistor, a first emission control transistor, a second emission control transistor, and a storage capacitor; the first reset transistor and the compensation transistor are N-type metal oxide transistors, and the driving transistor, the write transistor, the second reset transistor, the first emission control transistor, and the second emission control transistor are P-type polysilicon transistors;

[0048] The first electrode of the first light-emitting control transistor is used to receive a first power supply signal, and the second electrode is connected to the first electrode of the driving transistor, the second electrode of the driving transistor is connected to the first electrode of the second light-emitting control transistor, and the second electrode of the second light-emitting control transistor is connected to the light-emitting device; the first electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the gate of the driving transistor; the first electrode of the first reset transistor is used to receive a first reset signal, and the second electrode is connected to the second electrode of the compensation transistor; the first electrode of the second reset transistor is used to receive a second reset signal, and the second electrode is connected to the second electrode of the driving transistor; the first electrode of the write transistor is used to receive a data signal, and the second electrode is connected to the first electrode of the driving transistor; the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate is used to receive the first power supply signal;

[0049] The gate of the first reset transistor and the gate of the compensation transistor are connected to the output end of one of the first drive circuits; the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are connected to the output end of another of the first drive circuits; the gate of the write transistor and the gate of the second reset transistor are connected to the output end of the second drive circuit.

[0050] According to one aspect of the present disclosure, a driving method for a shift register is provided, wherein the shift register is any one of the shift registers described above; the driving method comprises:

[0051] In the first stage, the input circuit is turned on by the first clock signal and the second clock signal, and the first control circuit is turned off; the voltage stabilizing circuit is turned on; the second voltage terminal and the output terminal are controlled to be turned on by the first control signal, and the third voltage terminal and the output terminal are turned off;

[0052] In the second stage, the input circuit is turned off and the first control circuit is turned on by the first clock signal and the second clock signal; the voltage stabilizing circuit is turned on; and the second voltage terminal is controlled to be connected to the output terminal and disconnected from the third voltage terminal by the voltage of the first voltage terminal, the first control signal, and the second control signal.

[0053] In the third stage, the input circuit is turned on by the first clock signal and the second clock signal; the voltage stabilizing circuit is turned off; the second voltage terminal is controlled to be connected to the output terminal, and the third voltage terminal is controlled to be disconnected from the output terminal, by the voltage of the first voltage terminal, the first control signal, and the second control signal;

[0054] In the fourth stage, the input circuit is turned off by the first clock signal and the second clock signal; the voltage stabilizing circuit is turned off; the second voltage terminal and the output terminal are turned off and the third voltage terminal and the output terminal are turned on by the voltage of the third voltage terminal, the first control signal and the second control signal.

[0055] In an exemplary embodiment of the present disclosure, an absolute value of the voltage at the first voltage terminal is greater than an absolute value of the voltage at the second voltage terminal.

[0056] In an exemplary embodiment of the present disclosure, the absolute value of the difference between the absolute value of the voltage at the first voltage terminal and the absolute value of the voltage at the second voltage terminal is 3V.

[0057] In an exemplary embodiment of the present disclosure, a pulse width of the input signal is n times that of the first clock signal and the second clock signal, where n is a positive integer.

[0058] The display panel, driver circuit, shift register, and driving method disclosed herein can control the connection and disconnection between the second voltage terminal and the output terminal using an input signal. Simultaneously, an over-voltage stabilization circuit transmits the voltage of the first voltage terminal to the output circuit, ensuring stable conduction between the second voltage terminal and the output terminal. This eliminates the step that occurs when the voltage of the third voltage terminal outputted at the output terminal changes toward the voltage of the second voltage terminal. Furthermore, this step can be eliminated by externally connecting the first voltage terminal.

[0059] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0061] FIG1 is a top view of an embodiment of a display panel disclosed herein.

[0062] FIG2 is a partial cross-sectional schematic diagram of an embodiment of a display panel disclosed herein.

[0063] FIG3 is a schematic diagram of a pixel circuit in an embodiment of a display panel disclosed herein.

[0064] FIG4 is a partial schematic diagram of an embodiment of a display panel disclosed herein.

[0065] FIG5 is a schematic diagram of a driving circuit in an embodiment of a display panel disclosed herein.

[0066] FIG6 is a schematic diagram of an embodiment of a shift register disclosed herein.

[0067] FIG. 7 is a schematic diagram of an embodiment of a shift register disclosed herein in the first stage.

[0068] FIG8 is a schematic diagram of an embodiment of the shift register disclosed herein in the second stage.

[0069] FIG9 is a schematic diagram of an embodiment of the shift register disclosed herein in the third stage.

[0070] FIG10 is a schematic diagram of an embodiment of the shift register disclosed herein in the fourth stage.

[0071] FIG. 11 is a timing diagram of an embodiment of a driving method of a shift register disclosed herein.

[0072] FIG. 12 is a timing diagram of an embodiment of a driving method for multiple shift registers in the present disclosure.

[0073] FIG13 is a timing diagram of another embodiment of a driving method of a shift register disclosed herein.

[0074] FIG. 14 is a timing diagram of another embodiment of a driving method for multiple shift registers in the present disclosure.

[0075] FIG. 15 is a timing diagram of another embodiment of a driving method for multiple shift registers in the present disclosure. DETAILED DESCRIPTION

[0076] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0077] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0078] The row direction X and the column direction Y herein are two intersecting directions, which may be perpendicular to each other. In the drawings of this disclosure, the row direction X is horizontal and the column direction Y is vertical, but this is not limiting. Those skilled in the art will appreciate that if the display panel is rotated, the actual orientations of the row direction X and the column direction Y may change.

[0079] The transistor in this article includes a gate, a first electrode, and a second electrode. Controlling the gate voltage enables the first electrode and the second electrode to be turned on and off. The first electrode can be a source, and the second electrode can be a drain. Of course, the first electrode can also be a drain, and the second electrode can also be a source. Specifically, if the signal is input through the first electrode, the first electrode becomes the source, and the second electrode becomes the drain. If the signal is input through the second electrode, the second electrode becomes the source, and the first electrode becomes the drain. In other words, the source and drain can be interchanged depending on the input signal.

[0080] For a P-type transistor, when the gate receives a high level, the first and second electrodes are turned off; when the gate receives a low level, the first and second electrodes are turned on. For an N-type transistor, when the gate receives a high level, the first and second electrodes are turned on; when the gate receives a low level, the first and second electrodes are turned off.

[0081] As shown in FIG1 , the present disclosure provides a display panel that can be divided into multiple areas, including a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA can be a continuous annular area surrounding the display area AA or a discontinuous area surrounding the display area AA.

[0082] As shown in Figure 2, the display panel may include a driving backplane BP and a plurality of light-emitting devices LD arranged on one side of the driving backplane BP. Each light-emitting device LD may be distributed in an array along the row direction X and the column direction Y and located in the display area AA. The light-emitting device LD can be driven by the circuit in the driving backplane BP to emit light to display an image.

[0083] As shown in Figure 2, the light-emitting device LD can use an OLED (organic light-emitting diode) made of organic light-emitting materials; it can also use an LED (light-emitting diode) made of inorganic light-emitting materials, such as Micro LED (micrometer light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); it can also use devices such as QLED (quantum dot diode). No special restrictions are made on the specific structure of the light-emitting device LD here.

[0084] As shown in FIG2 , taking an OLED as an example, the light-emitting device LD may include a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked sequentially in a direction away from the driving backplane BP. By applying a first power signal to the first electrode ANO and a second power signal to the second electrode CAT, the light-emitting layer EL can be stimulated to emit light. The specific principle will not be described in detail here. At the same time, in order to limit the range of the light-emitting device LD, a pixel definition layer PDL can be provided on the driving backplane BP. The pixel definition layer PDL and the first electrode ANO are located on the same surface of the driving backplane BP, and the pixel definition layer PDL may have pixel openings that expose each first electrode ANO, thereby defining the range of the light-emitting device LD through each pixel opening.

[0085] As shown in FIG4 , the circuit driving the backplane BP may include a pixel circuit PC and a driving circuit. The pixel circuit PC may be located in the display area AA and arranged in an array along the row direction X and the column direction Y. One pixel circuit PC may be connected to the first electrode ANO of one light-emitting device LD. Of course, the same pixel circuit PC may also be connected to the first electrodes ANO of multiple light-emitting devices LD. The pixel circuit PC may include multiple transistors and capacitors, and may be a 3T1C, 7T1C, or other pixel circuit. nTmC indicates that one pixel circuit PC includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C").

[0086] As shown in Figure 3, taking the pixel circuit PC of the 7T1C structure as an example, it may include a first reset transistor M1, a compensation transistor M2, a drive transistor M3, a write transistor M4, a first emission control transistor M5, a second emission control transistor M6, a second reset transistor M7 and a storage capacitor Cst. The first electrode and the second electrode can be turned on or off by applying a scan signal to the gate of the transistor. The storage capacitor Cst may include an overlapping first plate and a second plate; wherein:

[0087] As shown in FIG3 , the gate of the first emission control transistor M5 is used to input the emission scanning signal EM, the first electrode is used to input the first power signal VDD, and the second electrode is connected to the first electrode of the driving transistor M3. The gate of the driving transistor M3 is connected to the first node N1, the second electrode and the first electrode of the second emission control transistor M6 are connected to the second node N2, and the second electrode of the second emission control transistor M6 and the first electrode ANO of a light-emitting device LD are connected to the fourth node N41. The gate of the second emission control transistor M6 is used to input the emission scanning signal EM. The second electrode CAT of the light-emitting device LD is used to input the second power signal VSS.

[0088] The gate of the first reset transistor M1 is used to input the first reset scanning signal RE1 , the first electrode is used to input the first reset signal VI1 , and the second electrode is connected to the gate of the driving transistor M3 .

[0089] The gate of the write transistor M4 is used to input the write scan signal Gate1 , the first electrode is used to input the data signal DA, and the second electrode and the first electrode of the drive transistor M3 and the second electrode of the first light emission control transistor M5 are connected to the third node N31 .

[0090] The gate of the compensation transistor M2 is used to input the compensation scan signal Gate2 , a first electrode is connected to the second node N2 , and a second electrode is connected to the first node N1 , thereby connecting the second electrode and the gate of the driving transistor M3 .

[0091] The gate of the second reset transistor M7 is used to input the second reset scan signal RE2, the first electrode is used to input the second reset signal VI2, and the second electrode is connected to the fourth node N41, that is, connected to the first electrode ANO of the light emitting device and the second electrode of the driving transistor M3.

[0092] A first plate of the storage capacitor Cst is used to input the first power signal VDD, and a second plate is connected to the first node N1 , thereby being connected to the gate of the driving transistor M3 .

[0093] The working principle of the 7T1C pixel circuit is explained below:

[0094] In the first reset phase, the first reset transistor M1 is turned on by the first reset scan signal RE1, and the first reset signal VI1 is written to the first node N1, thereby resetting the gate of the driving transistor M3 and the second plate of the storage capacitor Cst.

[0095] During the write phase, write transistor M4 and compensation transistor M2 are turned on by write scan signal Gate1 and compensation scan signal Gate2, while other transistors are turned off. Data signal DA is written to first node N1 via third node N31 and second node N2 until the potential reaches Vdata+vth, where Vdata is the voltage of data signal DA and Vth is the threshold voltage of drive transistor M3. Write scan signal Gate1 and compensation scan signal Gate2 can be the same scan signal or synchronized.

[0096] In the second reset phase, the compensation transistor M2, the write transistor M4, the first emission control transistor M5, and the second emission control transistor M6 are turned off. Simultaneously, the second reset transistor M7 is turned on by the second reset scan signal RE2, and a second reset signal VI2 is transmitted to the first electrode of the second reset transistor M7 to reset the first electrode ANO of the light-emitting device LD.

[0097] During the light-emitting phase: the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on by the light-emitting scanning signal EM, and the other transistors are turned off; the driving transistor M3 is turned on by the voltage Vdata + Vth stored in the storage capacitor Cst and the first power signal VDD. Under the action of the first power signal VDD and the second power signal VSS, the light-emitting device LD emits light. Under the action of the storage capacitor Cst, the driving transistor M3 outputs a current, and the output current satisfies the following formula: I = (μWCox / 2L)(Vgs-Vth) 2 ;

[0098] I is the output current of the driving transistor M3; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor M3, and L is the channel length of the driving transistor M3.

[0099] According to the above formula for the output current of the driving transistor M3, the gate voltage Vdata+Vth and the source voltage VDD of the driving transistor M3 in the pixel circuit of the present disclosure are substituted into the above formula to obtain: the output current of the driving transistor M3 I=(μWCox / 2L)(Vdata+Vth-VDD-Vth) 2 It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor M3 and is only related to Vdata, thereby eliminating the influence of the threshold voltage of the driving transistor M3 on its output current. The output current can be controlled solely by the voltage of the data signal DA, thereby controlling the brightness of the light-emitting device.

[0100] The transistors in the aforementioned 7T1C pixel circuit can all be polysilicon transistors, i.e., using an LTPS (Low Temperature Polycrystalline Silicon) process. Alternatively, at least a portion of the transistors can be metal oxide transistors, for example, using an LTPO (Low Temperature Polycrystalline Oxide) process. Specifically, the first reset transistor M1 and the compensation transistor M2 can be metal oxide transistors, while the other transistors can be polysilicon transistors. Metal oxide transistors can reduce leakage. If metal oxide transistors are used, they are N-type transistors, while if polysilicon transistors are used, they can be P-type transistors.

[0101] As shown in FIG4 , a drive circuit WG can be provided in the peripheral area WA and connected to the light-emitting device LD via the pixel circuit PC, applying a first power supply signal to the first electrode ANO of the light-emitting device LD. The number of drive circuits WG can be multiple, and they can be divided into multiple categories, for scanning the transistors in the pixel circuit PC. The drive circuit WG can also be provided entirely or partially within the display area AA, as long as it can scan the pixel circuit PC. Taking the aforementioned 7T1C pixel circuit as an example, the drive circuit WG can be divided into two categories. One category is a gate drive circuit, which is used to scan some of the transistors in the pixel circuit PC (e.g., the first reset transistor M1, the second reset transistor M7, the compensation transistor M2, and the write transistor M4). Specifically, it outputs a first reset scan signal RE1, a second reset scan signal RE2, a compensation scan signal Gate2, and a write scan signal Gate1 to the gates of the first reset transistor M1, the second reset transistor M7, the compensation transistor M2, and the write transistor M4. The other category is a light-emitting drive circuit, which is used to scan the first light-emitting control transistor M5 and the second light-emitting control transistor M6. Specifically, it outputs a scan signal (light-emitting scan signal EM) to the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6. The first reset scan signal RE1, the second reset scan signal RE2, the compensation scan signal Gate2, the write scan signal Gate1, and the emission scan signal EM are all scan signals output by the drive circuit WG. The signals output by the gate drive circuit and the emission drive circuit can turn on and off the transistors in the pixel circuit PC, thereby scanning the pixel circuit PC.

[0102] The peripheral area WA of the display panel may also be provided with a power bus connected to the second electrode CAT of the light emitting device LD, and a second power signal is applied to the second electrode CAT. The current passing through the light emitting device LD can be controlled through the pixel circuit PC, thereby controlling the brightness of the light emitting device LD.

[0103] A driving circuit WG may include multiple cascaded shift registers GOA, where the output of the previous-stage shift register GOA is connected to the input of the next-stage shift register GOA, so that the output signal of the previous-stage shift register GOA serves as the input signal of the next-stage shift register GOA. At the same time, the input signal of the first-stage shift register GOA may be a trigger signal. Furthermore, in some embodiments, the first-stage shift register GOA may be a dummy register, whose output is not connected to the pixel circuit PC but serves only as the input signal of the next-stage shift register GOA. Any shift register GOA may include multiple transistors and capacitors, and may have a structure such as 8T2C or 10T3C, without particular limitation herein.

[0104] As shown in Figure 5, the output signal of the output terminal OUT of the shift register GOA is the above-mentioned scanning signal, and the gates of some transistors of a row of pixel circuits PC can be connected to the output terminal of the first-level shift register GOA; of course, the first-level shift register GOA can be connected to multiple rows of pixel circuits PC and scan multiple rows of pixel circuits PC at the same time, but the output signal of the same shift register GOA may have different effects on different rows of pixel circuits PC. For example, when the pixel circuit PC in the i-th row is in the writing stage, the pixel circuit PC in the i+1-th row is in the first reset stage, where i is a positive integer.

[0105] When controlling the on and off switching of the transistors in the pixel circuit PC, the output signal at the output terminal of the shift register GOA, i.e., the scan signal, needs to switch between a high level and a low level. However, since the transistors need to be turned on and off in response, there is a step on the rising or falling edge of the scan signal, which causes a delay in scanning the pixel circuit PC and, in turn, a delay in switching. For example, the first and second emission control transistors M5 and M6 are P-type transistors. When the emission scan signal EM switches from a high level to a low level, there is a step on the falling edge of the emission scan signal EM, causing a delay in turning on the first and second emission control transistors M5 and M6, and delaying the light emission of the light-emitting device LD.

[0106] To improve this problem, a large number of transistors and capacitors can be added to the shift register GOA, using principles such as bootstrapping to stabilize the signal inside the shift register and reduce the aforementioned step. However, this would result in a larger number of transistors and capacitors in the shift register, making the structure more complex. Therefore, the inventors propose using an external voltage to control the output signal of the shift register GOA, reducing or eliminating the aforementioned step and thus improving the delay. This is explained in detail below:

[0107] As shown in FIG6 , the shift register GOA may include an input circuit 10, a voltage stabilizing circuit 20, a first control circuit 30, a second control circuit 40, and an output circuit 50, wherein:

[0108] The input circuit 10 is connected to the input terminal IN, the first clock signal terminal CK1 and the first input node N11 and is configured to transmit the input signal provided by the input terminal IN to the first input node N11 in response to the first clock signal provided by the first clock signal terminal CK1.

[0109] The voltage stabilizing circuit 20 is connected to the first voltage terminal VGL_L, the first output node N21 and the first input node N11 , and is configured to transmit a first control signal to the first output node N21 under the control of the voltage of the first input node N11 .

[0110] The first control circuit 30 is connected to the second voltage terminal VGL, the second clock signal terminal CK2, the third voltage terminal VGH, the second output node N22 and the first input node N11, and is configured to transmit a second control signal to the second output node N22 under the control of the second clock signal provided by the second clock signal terminal CK2 and the voltage of the first input node N11.

[0111] The second control circuit 40 is connected to the third voltage terminal VGH, the first input node N11, the first output node N21 and the second output node N22, and is configured to control the first control signal and the second control signal under the control of the voltage of the first input node N11 and the second control signal.

[0112] The output circuit 50 is connected to the first output node N21, the second output node N22, the second voltage terminal VGL, the third voltage terminal VGH and the output terminal OUT, and is configured to output the signal of the second voltage terminal VGL or the third voltage terminal VGH from the output terminal OUT under the control of the first control signal and the second control signal; the voltage of the first voltage terminal VGL_L can turn off the second voltage terminal VGL and the output terminal OUT.

[0113] The following describes the effect of the shift register GOA in combination with its working principle:

[0114] As shown in Figure 6, in the first stage, the input circuit 10 can be turned on by the first clock signal and the second clock signal, the first control circuit 30 can be turned off, and the input signal can be transmitted to the first input node N11. The input signal can turn on the voltage stabilizing circuit 20 and transmit the first control signal to the first output node N21. The voltage stabilizing circuit 20 can control the first control signal under the voltage control of the first voltage terminal VGL_L, and control the second voltage terminal VGL and the output terminal OUT to be turned on and the third voltage terminal VGH and the output terminal OUT to be turned off through the first control signal; at this time, the voltage of the output signal of the output terminal OUT is the voltage provided by the second voltage terminal VGL.

[0115] In the second stage, the input circuit 10 is turned off by the first clock signal and the second clock signal, the voltage stabilizing circuit 20 remains on, the first control circuit 30 is turned on, and the second voltage terminal VGL transmits the second control signal to the second output node N22 through the first control circuit 30; the second voltage terminal VGL and the output terminal OUT are controlled to be turned on by the voltage of the first voltage terminal VGL_L, the first control signal and the second control signal, and the third voltage terminal VGH and the output terminal OUT are turned off; at this time, the voltage of the output signal of the output terminal OUT is the voltage provided by the second voltage terminal VGL.

[0116] In the third phase, the first and second clock signals turn on the input circuit 10, while the voltage regulator circuit 20 turns off. The voltage at the first voltage terminal VGL_L, the first control signal, and the second control signal control the connection between the second voltage terminal VGL and the output terminal OUT, while disconnecting the connection between the third voltage terminal VGH and the output terminal OUT. At this point, the voltage of the output signal at the output terminal OUT is the voltage at the second voltage terminal VGL.

[0117] In the fourth phase, the input circuit 10 is shut down by the first and second clock signals; the voltage regulator circuit 20 is turned off; and the voltage at the third voltage terminal VGH, the first control signal, and the second control signal control the second voltage terminal VGL and the output terminal OUT to be disconnected, while the third voltage terminal VGH and the output terminal OUT are connected. At this point, the voltage of the output signal at the output terminal OUT is the voltage at the third voltage terminal VGH.

[0118] The above four stages can constitute one cycle, i.e., the stage following the fourth stage is the first stage of another cycle. The first voltage terminal VGL_L and the second voltage terminal VGL can be used to provide a low level, while the third voltage terminal VGH can be used to provide a high level. As can be seen from the above operating principle, based on the first input signal and the first control signal, before switching from a low level to a high level, the voltage of the first voltage terminal VGL_L can be used to continuously connect the second voltage terminal VGL and the output terminal OUT. When switching from a high level to a low level, the second voltage terminal VGL can be connected to the output terminal OUT, thereby increasing the signal switching speed and eliminating the steps on the rising or falling edges of the output signal. Thus, the first voltage terminal VGL_L and the voltage stabilization circuit 20 can be used to improve delay without providing a bootstrap circuit, which helps simplify the structure of the shift register GOA.

[0119] The following is an exemplary description of part of the circuit of the shift register GOA:

[0120] In some embodiments of the present disclosure, the first control circuit 30 may transmit a second control signal to the second output node N22 or be turned off under the control of the voltages of the first input node N11, the second voltage terminal VGL, and the third voltage terminal VGH. The first control circuit 30 may include a first control sub-circuit 301, a second control sub-circuit 302, and a third control sub-circuit 303, wherein:

[0121] The first control sub-circuit 301 may be connected to the second input node N12 , the second voltage terminal VGL, and the second clock signal terminal CK2 , and may be configured to be turned on or off under the control of the second clock signal.

[0122] The second control sub-circuit 302 may be connected to the connection node N3 , the first input node N11 , and the third voltage terminal VGH, and may be configured to be turned on or off under the control of the voltage of the first input node N11 .

[0123] The third control sub-circuit 303 may be connected to the second input node N12 and the connection node N3 , and configured to be turned on or off under the control of the voltage of the third voltage terminal VGH.

[0124] As shown in FIG6 , in some embodiments of the present disclosure, the second control circuit 40 includes a fourth control subcircuit and a fifth control subcircuit, wherein:

[0125] The fourth control sub-circuit is connected to the third voltage terminal VGH, the first input node N11 and the second output node N22, and is configured to control the second control signal under the control of the voltage of the first input node N11;

[0126] The fifth control sub-circuit is connected to the third voltage terminal VGH, the first output node N21 and the second output node N22 , and is configured to control the first control signal under the control of the voltage of the second output node N22 .

[0127] In some embodiments of the present disclosure, the output circuit 50 may include a first output sub-circuit 501 and a second output sub-circuit 502, wherein:

[0128] The first output sub-circuit 501 can be connected to the first output node N21, the second voltage terminal VGL, and the output terminal OUT, and can be turned on or off by the control of a first control signal. The second output sub-circuit 502 can be connected to the second output node N22, the third voltage terminal VGH, and the output terminal OUT, and can be turned on or off by the control of a second control signal.

[0129] As shown in FIG6 , in some embodiments of the present disclosure, the shift register GOA of the present disclosure may further include a first isolation circuit 60, which may be connected to the first input node N11, the voltage stabilization circuit 20, and the second voltage terminal VGL. The first isolation circuit 60 may be turned on by the voltage of the second voltage terminal VGL, thereby preventing the first output node N21 from leaking to the first input node N11 and providing isolation.

[0130] Optionally, the shift register GOA may further include a second isolation circuit 70, which may be connected to the connection node N3, the second output node N22, and the second voltage terminal VGL. The second isolation circuit 70 may be turned on by the voltage of the second voltage terminal VGL to prevent the second output node N22 from leaking to the second input node N12, thereby providing isolation.

[0131] The specific structure of the shift register GOA is exemplified below:

[0132] As shown in Figure 6, in some embodiments of the present disclosure, the input circuit 10 includes an input transistor T1. The first control subcircuit 301 includes a first control transistor T3, the second control subcircuit 30232 includes a second control transistor T6, and the third control subcircuit 303 includes a third control transistor T4 and a first capacitor C1. The voltage stabilization circuit 20 includes a voltage stabilization transistor T8 and a second capacitor C2. The fourth control subcircuit includes a fourth control transistor T7; the fifth control subcircuit includes a fifth control transistor T9. The first output subcircuit 501 may include a first output transistor T11 and a third capacitor C3, and the second output subcircuit 502 includes a second output transistor T10 and a fourth capacitor C4. The first isolation circuit 60 includes a first isolation transistor T2, and the second isolation circuit 70 includes a second isolation transistor T5; wherein:

[0133] The input transistor T1 has a gate connected to the first clock signal terminal CK1 , a first electrode connected to the input terminal IN, and a second electrode connected to the first input node N11 .

[0134] The first control transistor T3 has a gate connected to the second clock signal terminal CK2, a first electrode connected to the second voltage terminal VGL, and a second electrode connected to the second input node N12. The second control transistor T6 has a gate connected to the first input node N11, a first electrode connected to the third voltage terminal VGH, and a second electrode connected to the connection node N3. The gate of the third control transistor T4 is connected to one plate of the first capacitor C1 and connected to the intermediate node N5. The other plate of the first capacitor C1 is connected to the first electrode of the third control transistor T4 and the connection node N3. The second electrode of the third control transistor T4 is connected to the second input node N12.

[0135] The gate of the voltage-stabilizing transistor T8 is connected to the first input node N11 and one plate of the second capacitor C2, the first electrode is connected to the first voltage terminal VGL_L, and the second electrode is connected to the other plate of the second capacitor C2 and the first output node N21. For example, the gate of the voltage-stabilizing transistor T8 can be connected to the transition node N4, and the transition node N4 can be connected to the first input node N11 via the first isolation transistor T2, thereby connecting the gate of the voltage-stabilizing transistor T8 to the first input node N11. The gate of the first isolation transistor T2 can be connected to the second voltage terminal VGL, the first electrode is connected to the first input node N11, and the second electrode is connected to the transition node N4.

[0136] The gate of the fourth control transistor T7 is connected to the first input node N11, for example, the gate is connected to the transition node N4; the first electrode of the fourth control transistor T7 is connected to the third voltage terminal VGH, and the second electrode is connected to the second output node N22. The gate of the fifth control transistor T9 can be connected to the second output node N22, the first electrode is connected to the third voltage terminal VGH, and the second electrode is connected to the first output node N21.

[0137] The gate of the first output transistor T11 is connected to the first output node N21, the first electrode is connected to the second voltage terminal VGL, and the second electrode is connected to the output terminal OUT. One plate of the third capacitor C3 is connected to the first output node N21, and the other plate is connected to the second voltage terminal VGL.

[0138] The gate of the second output transistor T10 is connected to the second output node N22, the first electrode is connected to the third voltage terminal VGH, and the second electrode is connected to the output terminal OUT. One plate of the fourth capacitor C4 is connected to the second output node N22, and the other plate is connected to the third voltage terminal VGH.

[0139] The second isolation transistor T5 has a gate connected to the second voltage terminal VGL, a first electrode connected to the connection node N3, and a second electrode connected to the second output node N22. The connection node N3 is connected to the second output node N22 through the second isolation transistor T5.

[0140] The following takes the case where all transistors of the shift register GOA are P-type transistors as an example, and combines the shift register GOA in the above embodiment to describe its driving method in detail:

[0141] The first voltage terminal VGL_L outputs a first voltage, and the second voltage terminal VGL outputs a second voltage. Both the first voltage and the second voltage are at a low level, and the absolute value of the first voltage is greater than the absolute value of the second voltage. For example, the difference between the absolute values ​​of the first voltage and the second voltage is 3 V. The third voltage terminal VGH outputs a third voltage, which is at a high level.

[0142] As shown in Figures 7, 11, and 13, in the first phase, the first clock signal is at a low level, and the input signal is at a low level; the input transistor T1 is turned on, the first isolation transistor T2 is always on, and the input signal is transmitted to the first input node N11 and the transition node N4, causing the second control transistor T6, the fourth control transistor T7, and the voltage regulator transistor T8 to be turned on; the third voltage terminal VGH can charge the first capacitor C1 through the second control transistor T6 and the connection node N3. At this time, the third control transistor T4 does not meet the conduction condition and is in the off state; the first voltage terminal VGL_L provides a first voltage to the first output node N21 through the voltage regulator transistor T8, causing the voltage of the output signal of the first output transistor T11 and the output terminal OUT to be the first voltage. At the same time, the second clock signal is at a high level, causing the first control transistor T3 and the third control transistor T4 to be turned off; the third voltage terminal VGH can transmit a third voltage to the second output node N22 through the fourth control transistor T7, causing the fifth control transistor T9 and the second output transistor T10 to be turned off.

[0143] As shown in Figures 8, 11, and 13, in the second phase, the first clock signal becomes high, while the input signal remains low. The input transistor T1 is turned off, and under the action of the second capacitor C2, the second control transistor T6, the voltage regulator transistor T8, and the fourth control transistor T7 remain on. Under the action of the first voltage terminal VGL_L and the third capacitor C3, the first output transistor T11 remains on. At this time, the voltage of the output signal at the output terminal OUT remains at the second voltage of the second voltage terminal VGL. The third voltage terminal VGH continues to control the voltage of the second output node N22, turning off the fifth control transistor T9 and the second output transistor T10. At the same time, the second clock signal becomes a low level, the first control transistor T3 is turned on, and under the continuous action of the third voltage terminal VGH, the voltage difference between the connection node N3 and the third control transistor T4 reaches the turn-on condition, that is, the gate-source voltage difference is greater than the threshold voltage of the third control transistor T4, the third control transistor T4 is turned on, and the second voltage of the second voltage terminal VGL is transmitted to the second output node N22 through the normally-on second isolation transistor T5. The voltage of the second output node N22 is pulled down, but the fifth control transistor T9 and the second output transistor T10 can still be kept turned off.

[0144] As shown in Figures 9, 11, and 13, in the third phase, the first clock signal becomes low, the input signal becomes high, the input transistor T1 turns on, the first isolation transistor T2 is always on, and the input signal turns off the second control transistor T6, the fourth control transistor T7, and the voltage-stabilizing transistor T8. Under the coupling effect of the second capacitor C2, the voltage at the first output node N21 increases due to the high level of the transition node N4, gradually turning off the first output transistor T11. However, the first output transistor T11 can still remain on for a period of time. Combined with the effect of the third capacitor C3, the voltage of the output signal at the output terminal OUT can still maintain the low-level second voltage for a period of time. Under the effect of the first capacitor C1, the third control transistor T4 continues to turn on. Simultaneously, the second clock signal is high, turning off the first control transistor T3. Under the effect of the fourth capacitor C4, the fifth control transistor T9 and the second output transistor T10 remain off.

[0145] As shown in Figures 10, 11, and 13, in the fourth phase, the first clock signal becomes high, the input signal becomes low, the input transistor T1 is turned off, the first isolation transistor T2 is constantly on, and under the action of the second capacitor C2, the second control transistor T6, the fourth control transistor T7, and the voltage regulator transistor T8 are turned off. Under the action of the first capacitor C1, the third control transistor T4 is continuously turned on. At the same time, the second clock signal is low, turning on the first control transistor T3, writing the second voltage to the second output node N22, turning on the fifth control transistor T9 and the second output transistor T10, and the third voltage terminal VGH can write the third voltage to the first output node N21 through the fifth control transistor T9, turning off the first output transistor T11. The output signal at the output terminal OUT is the high-level third voltage.

[0146] Based on the above-mentioned driving method, the output signal is switched from the second voltage of the low level to the third voltage of the high level. During this process, under the action of the first voltage terminal VGL_L, the voltage of the first output node N21 can be stabilized to ensure that the output terminal OUT outputs a stable signal. In addition, by controlling the voltage of the first voltage terminal VGL_L, in particular, the step existing on the falling edge when switching between high and low levels can be eliminated. Compared with adding a large number of transistors and capacitors to utilize the bootstrap principle, the step on the falling edge is eliminated by controlling the internal signal of the shift register. In this way, the first voltage of the external first voltage terminal VGL_L can be realized only by the voltage-stabilizing transistor T8 and the second capacitor C2, and the structure is simpler.

[0147] It should be noted that although the steps of the driving method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0148] As shown in FIG5 , based on the aforementioned driving method, the duration of the output signal, i.e., the width of the high level of the input signal, can be controlled by adjusting the pulse width of the input signal. For a driving circuit WG, multiple shift registers GOA are cascaded. Therefore, the pulse width of the input signal of the first-stage shift register GOA, i.e., the trigger signal STV, can be used to control the pulse width of the output signal of each shift register GOA. Furthermore, the pulse width of the input signal is n times the first and second clock signals, where n is a positive integer, e.g., 1, 2, 3, etc.

[0149] As shown in Figures 11 and 12, the pulse width of the trigger signal STV is the same as the pulse width of the first clock signal (the signal at the first clock signal terminal CK1) and the second clock signal (the signal at the second clock signal terminal CK2), that is, n = 1. Figure 12 shows the timing of the output signals at the output terminals OUT of the four cascaded shift registers GOA, that is, the timing of the output signals from the first output terminal OUT1 to the fourth output terminal OUT4.

[0150] As shown in Figures 13 and 14, the pulse width of the trigger signal STV is 5 times the pulse width of the first clock signal and the second clock signal, that is, n = 5. Figure 14 shows the timing of the output signals of the output terminals OUT of the four cascaded shift registers GOA, that is, the timing of the output signals of the first output terminal OUT1 to the fourth output terminal OUT4.

[0151] As shown in Figure 15 , the pulse width of the trigger signal STV is 14 times the pulse width of the first clock signal and the second clock signal, that is, n = 14. Figure 15 shows the timing of the output signals of the output terminals OUT of the four cascaded shift registers GOA, that is, the timing of the output signals from the first output terminal OUT1 to the fourth output terminal OUT4.

[0152] The shift register GOA described above can be used not only in gate drive circuits but also in light-emitting drive circuits, and can scan not only P-type transistors but also N-type transistors. The gates of some transistors in the same pixel circuit are connected to the output terminal OUT of a first drive circuit, while the gates of other transistors are connected to the output terminal OUT of a second drive circuit; and the two first drive circuits are connected to the gates of different transistors in the pixel circuit.

[0153] In some embodiments of the present disclosure, for the 7T1C pixel circuit using the LTPO process mentioned above, the driving circuit WG may include two identical first driving circuits WG1 and one second driving circuit WG2, one first driving circuit WG1 is a gate driving circuit, which can be used to scan the first reset transistor M1 and the compensation transistor M2, that is, its output terminal OUT is connected to the gates of the first reset transistor M1 and the compensation transistor M2; the other first driving circuit WG1 is a light-emitting driving circuit, which can be used to scan the first light-emitting control transistor M5 and the second light-emitting control transistor M6, that is, its output terminal OUT is connected to the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6.

[0154] The second drive circuit WG2 is different from the first drive circuit WG1, that is, the shift register GOA of the second drive circuit WG2 is different from the shift register GOA of the first drive circuit WG1. The second drive circuit WG2 is used to scan the write transistor M4 and the second reset transistor M7, that is, its output terminal OUT is connected to the gate of the write transistor M4 and the second reset transistor M7.

[0155] It should be noted that in the same pixel circuit, the transistors connected to the same driving circuit WG may be connected to shift registers GOA of different stages, and the output terminal OUT of the same shift register GOA may be connected to transistors of multiple rows of pixel circuits.

[0156] In addition, the number of the first voltage terminal VGL_L, the second voltage terminal VGL and the third voltage terminal VGH in this article is not limited to one, as long as the voltages are the same. For example, multiple transistors are connected to the second voltage terminal VGL. Multiple transistors can be connected to the same voltage terminal, or they can be connected to multiple voltage terminals that can output the second voltage.

[0157] The following is an exemplary description of the film layer of the driver backplane:

[0158] As shown in FIG2 , the driving backplane BP may include a substrate SU and a light shielding layer BSM, a first semiconductor layer SE, a first gate layer GA1, a second gate layer GA2, a second semiconductor layer IG, a third gate layer GA3, a first source and drain layer SD1, and a second source and drain layer SD2, which are sequentially distributed in a direction away from the substrate SU.

[0159] The light shielding layer BSM is disposed on one side of the substrate SU and can be made of metal or other conductive and light shielding materials. The light shielding layer BSM can at least overlap with the driving transistor M3 to prevent the bottom signal and light from affecting the driving transistor M3.

[0160] As shown in Figure 2, the first semiconductor layer SE is arranged on the side of the light-shielding layer BSM away from the substrate SU, and the material of the first semiconductor layer SE can be polycrystalline silicon, which may include the active parts of the driving transistor M3, the write transistor M4, the first light-emitting control transistor M5, the second light-emitting control transistor M6, and the active parts of each transistor of the shift register GOA.

[0161] 2 , the first gate layer GA1 is disposed on a side of the first semiconductor layer SE away from the substrate SU. The first gate layer GA1 may include a storage capacitor Cst, a plate of the first capacitor C1 to the fourth capacitor C4, and gates of some transistors.

[0162] As shown in FIG. 2 , the second gate layer GA2 is disposed on a side of the first gate layer GA1 away from the substrate SU, and includes a storage capacitor Cst and the other plates of the first to fourth capacitors C1 to C4 .

[0163] As shown in FIG2 , the second semiconductor layer IG may be disposed on a side of the second gate layer GA2 away from the substrate SU. The material thereof may be a metal oxide such as IGZO. The second semiconductor layer IG may include active portions of the first reset transistor M1 and the compensation transistor M2 .

[0164] 2 , the third gate layer GA3 may be disposed on a side of the second semiconductor layer IG away from the substrate SU and overlap the second semiconductor layer IG. The third gate layer GA3 may include gates of the first reset transistor M1 and the compensation transistor M2.

[0165] As shown in FIG. 2 , the first source-drain layer SD1 may be disposed on a side of the third gate layer GA3 away from the substrate SU, and may be used to connect some transistors and capacitors.

[0166] As shown in FIG. 2 , the second source / drain layer SD2 is disposed on a side of the first source / drain layer SD1 away from the substrate SU.

[0167] In addition, as shown in FIG2 , the driving backplane BP may further include a buffer layer BUF of an insulating material, a first gate insulating layer GI1, a second gate insulating layer GI2, a first insulating layer IL1, a third gate insulating layer GI3, a second insulating layer IL2, a first planar layer PLN1, and a second planar layer PLN2, wherein:

[0168] The buffer layer BUF may cover the light shielding layer BSM and may be made of inorganic materials such as silicon nitride and silicon oxide. The buffer layer BUF may be a single layer or a multilayer structure, and different layers may have different materials. The first semiconductor layer SE is disposed on the surface of the buffer layer BUF away from the substrate SU.

[0169] The first gate insulating layer GI1 covers the first semiconductor layer SE and may be made of inorganic materials such as silicon nitride and silicon oxide. The first gate layer GA1 is disposed on a surface of the first gate insulating layer GI1 away from the substrate SU.

[0170] The second gate insulating layer GI2 covers the first gate layer GA1 and may be made of inorganic materials such as silicon nitride and silicon oxide. The second gate layer GA2 is disposed on a surface of the second gate insulating layer GI2 away from the substrate SU.

[0171] The first insulating layer IL1 may cover the second gate layer GA2 and may be made of inorganic materials such as silicon nitride and silicon oxide. The first insulating layer IL1 may be a single layer or a multilayer structure, and the materials of different layers may be different. The second semiconductor layer IG is disposed on the surface of the first insulating layer IL1 away from the substrate SU.

[0172] The third gate insulating layer GI3 covers the second semiconductor layer IG and may be made of inorganic materials such as silicon nitride and silicon oxide. The third gate layer GA3 is disposed on a surface of the third gate insulating layer GI3 away from the substrate SU.

[0173] The second insulating layer IL2 may cover the third gate layer GA3 and may be made of inorganic materials such as silicon nitride and silicon oxide. The second insulating layer IL2 may be a single layer or a multilayer structure, and the materials of different layers may be different. The first source and drain layer SD1 is disposed on the surface of the second insulating layer IL2 away from the substrate SU.

[0174] The first planarization layer PLN1 can cover the first source / drain layer SD1. The first planarization layer PLN1 can be made of an organic material such as a resin. Planarization can be achieved through leveling of the organic material. The second source / drain layer SD2 can be disposed on a surface of the first planarization layer PLN1 away from the substrate SU. Furthermore, in some embodiments, a passivation layer can cover the first source / drain layer SD1, and the first planarization layer PLN1 can then cover the passivation layer.

[0175] The second planar layer PLN2 can cover the second source and drain layer SD2 and can be made of an organic material such as resin. The first electrode ANO and the pixel definition layer PDL of the light emitting device LD can be provided on the surface of the second planar layer PLN2 away from the substrate SU.

[0176] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A shift register, comprising: an input circuit connected to the input terminal, the first clock signal terminal and the first input node, and configured to transmit an input signal provided by the input terminal to the first input node in response to a first clock signal provided by the first clock signal terminal; a voltage stabilizing circuit connected to the first voltage terminal, the first output node and the first input node, and configured to transmit a first control signal to the first output node under the control of the voltage of the first input node; a first control circuit connected to the second voltage terminal, the second clock signal terminal, the third voltage terminal, the second output node and the first input node, and configured to transmit a second control signal to the second output node under the control of a second clock signal provided by the second clock signal terminal and the voltage of the first input node; a second control circuit connected to the third voltage terminal, the first input node, the first output node, and the second output node, and configured to control the first control signal and the second control signal under the control of the voltage of the first input node and the second control signal; The output circuit is connected to the first output node, the second output node, the second voltage terminal, the third voltage terminal and the output terminal, and is configured to output the signal of the second voltage terminal or the third voltage terminal from the output terminal under the control of the first control signal and the second control signal; the voltage of the first voltage terminal can turn on the second voltage terminal and the output terminal.

2. The shift register according to claim 1, wherein: The first control circuit comprises: a first control subcircuit connected to the second input node, the second voltage terminal and the second clock signal terminal, and configured to be turned on or off under the control of the second clock signal; a second control subcircuit connected to the connection node, the first input node and the third voltage terminal, and configured to be turned on or off under the control of the voltage of the first input node; The third control subcircuit is connected to the second input node and the connection node, and is configured to be turned on or off under the control of the voltage of the third voltage terminal.

3. The shift register according to claim 2, wherein: The first control subcircuit includes a first control transistor, the second control subcircuit includes a second control transistor, and the third control subcircuit includes a third control transistor and a first capacitor; The gate of the first control transistor is connected to the second clock signal terminal, the first electrode is connected to the second voltage terminal, and the second electrode is connected to the second input node; The gate of the second control transistor is connected to the first input node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the connection node; The gate of the third control transistor is connected to the connection node via the first capacitor, the first electrode is connected to the connection node, and the second electrode is connected to the second input node.

4. The shift register according to claim 1, wherein: The voltage stabilizing circuit includes a voltage stabilizing transistor and a second capacitor; The gate of the voltage stabilizing transistor is connected to the first input node and the second capacitor, the first electrode is connected to the first voltage terminal, and the second electrode is connected to the second capacitor and the first output node.

5. The shift register according to claim 1, wherein: The second control circuit includes a fourth control subcircuit and a fifth control subcircuit; The fourth control subcircuit is connected to the third voltage terminal, the first input node and the second output node, and is configured to control the second control signal under the control of the voltage of the first input node; The fifth control subcircuit is connected to the third voltage terminal, the first output node and the second output node, and is configured to control the first control signal under the control of the voltage of the second output node.

6. The shift register according to claim 5, wherein: The fourth control subcircuit includes a fourth control transistor; the fifth control subcircuit includes a fifth control transistor; The gate of the fourth control transistor is connected to the first input node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the second output node; The gate of the fifth control transistor is connected to the second output node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the first output node.

7. The shift register according to claim 1, wherein: The input circuit comprises an input transistor, a gate of the input transistor is connected to the first clock signal terminal, a first electrode is connected to the input terminal, and a second electrode is connected to the first input node; The output circuit includes a first output transistor, a third capacitor, a second output transistor and a fourth capacitor; The gate of the first output transistor is connected to the first output node, the first electrode is connected to the second voltage terminal, the second electrode is connected to the output terminal, and the third capacitor is connected to the first output node and the second voltage terminal; The gate of the second output transistor is connected to the second output node, the first electrode is connected to the third voltage terminal, the second electrode is connected to the output terminal, and the fourth capacitor is connected to the second output node and the third voltage terminal.

8. The shift register according to claim 2, wherein: The shift register further includes: The first isolation circuit is connected to the first input node and the voltage stabilizing circuit.

9. The shift register according to claim 8, wherein: The shift register further includes: The second isolation circuit connects the connection node and the second output node.

10. The shift register according to claim 9, wherein: The first isolation circuit includes a first isolation transistor; the second isolation circuit includes a second isolation transistor; The gate of the first isolation transistor is connected to the second voltage terminal, the first electrode is connected to the first input node, and the second electrode is connected to the voltage stabilizing circuit; The second isolation transistor has a gate connected to the second voltage terminal, a first electrode connected to the connection node, and a second electrode connected to the second output node.

11. A driving circuit, comprising a plurality of cascaded shift registers, wherein the shift register is the shift register according to any one of claims 1 to 10.

12. A display panel, comprising: A driving backplane, comprising a plurality of pixel circuits and a first driving circuit, wherein the pixel circuits are arranged in an array along a row direction and a column direction; The first driving circuit is the driving circuit according to claim 11, and an output end of the first driving circuit is connected to at least one row of pixel circuits; The light emitting devices are arranged in an array on one side of the driving backplane.

13. The display panel according to claim 12, wherein: The pixel circuit includes a plurality of transistors; the number of the first driving circuits is two; the display panel further includes a second driving circuit; The gates of some transistors in the same pixel circuit are connected to the output end of the first driving circuit, and the gates of another part of the transistors are connected to the output end of the second driving circuit; and the two first driving circuits are connected to the gates of different transistors in the pixel circuit.

14. The display panel according to claim 13, wherein: The pixel circuit includes a driving transistor, a writing transistor, a compensating transistor, a first reset transistor, a second reset transistor, a first light emission control transistor, a second light emission control transistor and a storage capacitor; the first reset transistor and the compensating transistor are N-type metal oxide transistors, and the driving transistor, the writing transistor, the second reset transistor, the first light emission control transistor and the second light emission control transistor are P-type polysilicon transistors; The first electrode of the first light-emitting control transistor is used to receive a first power supply signal, and the second electrode is connected to the first electrode of the driving transistor, the second electrode of the driving transistor is connected to the first electrode of the second light-emitting control transistor, and the second electrode of the second light-emitting control transistor is connected to the light-emitting device; the first electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the gate electrode of the driving transistor; the first electrode of the first reset transistor is used to receive a first reset signal, and the second electrode is connected to the second electrode of the compensation transistor; the first electrode of the second reset transistor is used to receive a second reset signal, and the second electrode is connected to the second electrode of the driving transistor; the first electrode of the write transistor is used to receive a data signal, and the second electrode is connected to the first electrode of the driving transistor; the first plate of the storage capacitor is connected to the gate electrode of the driving transistor, and the second plate is used to receive the first power supply signal; The gate of the first reset transistor and the gate of the compensation transistor are connected to an output end of the first driving circuit; the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are connected to an output end of another first driving circuit; the gate of the write transistor and the gate of the second reset transistor are connected to an output end of the second driving circuit.

15. A driving method for a shift register, wherein the shift register is the shift register according to any one of claims 1 to 10; the driving method comprising: In the first stage, the input circuit is turned on and the first control circuit is turned off by the first clock signal and the second clock signal; The voltage stabilizing circuit is turned on; The first control signal is used to control the second voltage terminal to be connected to the output terminal, and the third voltage terminal to be connected to the output terminal. The output end is turned off; In the second stage, the input circuit is turned off and the first control circuit is turned on by the first clock signal and the second clock signal; The voltage stabilizing circuit is turned on; the second voltage terminal is controlled to be turned on and off from the output terminal, and the third voltage terminal is controlled to be turned on and off from the output terminal, through the voltage of the first voltage terminal, the first control signal and the second control signal; In the third stage, the input circuit is turned on by the first clock signal and the second clock signal; The voltage stabilizing circuit is turned off; the second voltage terminal is controlled to be connected with the output terminal, and the third voltage terminal is controlled to be disconnected from the output terminal through the voltage of the first voltage terminal, the first control signal and the second control signal; In a fourth stage, the input circuit is turned off by the first clock signal and the second clock signal; The voltage stabilizing circuit is turned off; the second voltage terminal and the output terminal are controlled to be turned off and the third voltage terminal and the output terminal are turned on through the voltage of the third voltage terminal, the first control signal and the second control signal.

16. The driving method according to claim 15, wherein: An absolute value of a voltage at the first voltage terminal is greater than an absolute value of a voltage at the second voltage terminal.

17. The driving method according to claim 16, wherein: The absolute value of the difference between the absolute value of the voltage at the first voltage terminal and the absolute value of the voltage at the second voltage terminal is 3V.

18. The driving method according to claim 15, wherein: The pulse width of the input signal is n times that of the first clock signal and the second clock signal, where n is a positive integer.

Images