Capacitor structure, packaging substrate and forming method therefor, and packaging structure

Abstract

A capacitor structure, a packaging substrate and a forming method therefor, and a packaging structure. The capacitor structure comprises at least one conductive plane, each conductive plane comprising a plurality of electrode plates. Each electrode plate comprises: a bonding pad portion, which comprises a bonding pad body portion and a plurality of bonding pad extension portions that are disposed on a side edge of the bonding pad body portion in a first direction; and a connecting portion, which comprises a connecting body portion and a plurality of connecting extension portions that are arranged on a side edge of the connecting body portion in the first direction, wherein the plurality of bonding pad extension portions and the plurality of connecting extension portions form a plurality of extension electrodes; and the bonding pad body portions and the connecting body portions are arranged in a second direction and are connected to each other, and the width of each bonding pad body portion in the first direction is greater than the width of each connecting body portion in the first direction. In each conductive plane, the plurality of electrode plates comprise first electrode plates and second electrode plates, which are adjacent in the first direction, and the plurality of extension electrodes of the first electrode plates and of the second electrode plates are overlapped in the second direction and are alternately arranged so as to form an interdigital capacitor structure.

Description

Capacitor structure, packaging substrate, forming method thereof, and packaging structure

[0001] This application claims priority to Chinese Patent Application No. 202311278695.5 filed on September 28, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a capacitor structure, a packaging substrate, a method for forming the same, and a packaging structure. Background Art

[0003] In semiconductor chip packaging, as chip integration increases, the number of transistors within the chip grows. The switching currents of thousands of transistors generate noise in the power supply path. This power supply noise propagates through the chip's internal circuits, potentially triggering register state transitions and affecting the jitter characteristics of crystal oscillators and phase-locked loops (PLLs), adversely impacting device performance. Therefore, to ensure stable operation of integrated circuits, reducing power supply noise is a critical issue in integrated circuit system design.

[0004] One of the main sources of power supply noise is the impedance of the power supply path, which includes the capacitive reactance generated by the capacitor structures in the power supply network. Reducing power supply noise by reducing impedance is currently a key research topic in the chip packaging field.

[0005] Summary of the Invention

[0006] According to at least one embodiment of the present disclosure, there is provided a capacitor structure, comprising: at least one conductive plane, each conductive plane comprising a plurality of electrode plates, the plurality of electrode plates being arranged side by side and spaced apart from each other in a direction parallel to a main surface of the conductive plane, wherein each electrode plate comprises: a pad portion comprising a pad main portion and a plurality of pad extension portions connected to each other, wherein the plurality of pad extension portions are arranged on sides of the pad main portion in a first direction parallel to the main surface of the conductive plane; and a connecting portion comprising a connecting main portion and a plurality of connecting extension portions connected to each other, wherein the plurality of connecting extension portions are arranged on sides of the connecting main portion in the first direction, the plurality of pad extension portions and the plurality of connecting extension portions constituting a plurality of extended electrodes; wherein the welding portion The pad main body portion and the connecting main body portion are arranged along a second direction and connected to each other, the second direction intersects with the first direction, and the width of the pad main body portion in the first direction is greater than the width of the connecting main body portion in the first direction; the multiple pad extension portions and the multiple connecting extension portions extend along the first direction and are arranged along the second direction at intervals from each other; wherein in each conductive plane, the multiple electrode plates include a first electrode plate and a second electrode plate adjacent to each other in the first direction, the first electrode plate and the second electrode plate are opposite to each other and arranged at intervals in the first direction, and the multiple extended electrodes of the first electrode plate and the multiple extended electrodes of the second electrode plate overlap in the second direction and are arranged alternately with each other to form a finger capacitor structure.

[0007] An embodiment of the present disclosure provides a packaging substrate, comprising the capacitor structure described above.

[0008] An embodiment of the present disclosure provides a method for forming a packaging substrate, comprising: forming a conductive material layer and performing a patterning process on the conductive material layer to form the conductive circuit and an initial conductive plane including a first initial electrode plate and a second initial electrode plate; and performing a thickening process on the initial conductive plane to form the conductive plane, wherein the thickening process comprises forming additional conductive material on the first initial electrode plate and the second initial electrode plate to form thickened first electrode plate and second electrode plate.

[0009] An embodiment of the present disclosure provides a packaging structure, including the above-mentioned packaging substrate; and a chip electrically connected to the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0011] FIG1 shows a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure.

[0012] FIG2A schematically shows a schematic diagram of a power supply network in a packaging structure; FIG2B schematically shows a schematic diagram of an equivalent power supply network in a packaging structure.

[0013] FIG3A is a schematic perspective view of a capacitor structure in a package substrate; FIG3B is a schematic cross-sectional view of a capacitor structure in the package structure taken along line II′ of FIG3A .

[0014] 4A is a schematic perspective view of another capacitor structure in a package substrate; FIG. 4B and FIG. 4C are schematic cross-sectional views of another capacitor structure in the package structure taken along line II′ and line II-II′ of FIG. 4A , respectively.

[0015] FIG5A is a schematic three-dimensional diagram showing another capacitor structure in a package substrate, and FIG5B is a schematic plan view showing a conductive plane in the capacitor structure shown in FIG5A .

[0016] Figure 6A shows a schematic three-dimensional diagram of a capacitor structure according to some embodiments of the present disclosure, and Figures 6B to 6D respectively show schematic plan views of each conductive plane in the capacitor structure shown in Figure 6A; Figure 6E shows a schematic three-dimensional diagram of a capacitor structure according to an alternative embodiment of the present disclosure.

[0017] Figure 7A schematically shows an enlarged plan view of a first electrode plate in a capacitor structure according to some embodiments of the present disclosure; Figure 7B schematically shows an enlarged plan view of a second electrode plate in a capacitor structure according to some embodiments of the present disclosure; Figure 7C schematically shows an enlarged plan view of a first electrode plate and a second electrode plate forming an interdigitated capacitor structure in a capacitor structure according to some embodiments of the present disclosure; Figure 7D schematically shows an enlarged plan view of a plurality of first electrode plates and a plurality of second electrode plates crossing each other to form an interdigitated capacitor structure in a capacitor structure according to some embodiments of the present disclosure.

[0018] 8A and 8B are schematic cross-sectional views of a first capacitor stack structure and a second capacitor stack structure, respectively, in a capacitor structure according to some embodiments of the present disclosure.

[0019] 9A to 9C are schematic plan views respectively illustrating respective conductive planes of a first capacitor stack structure in a capacitor structure according to some embodiments of the present disclosure.

[0020] 10A to 10C are schematic plan views of respective conductive planes of a second capacitor stack structure in a capacitor structure according to some embodiments of the present disclosure.

[0021] FIG. 11 is a schematic cross-sectional view illustrating a partial structure of a package substrate according to some embodiments of the present disclosure.

[0022] 12A to 12F are schematic cross-sectional views schematically illustrating a method of forming a package substrate according to some embodiments of the present disclosure.

[0023] 13A to 13E are schematic cross-sectional views schematically illustrating a method for forming a package substrate according to other embodiments of the present disclosure.

[0024] 14A is a schematic plan view illustrating a power plane and a ground plane of a package substrate in a comparative example; and FIG. 14B is a schematic enlarged plan view illustrating a power plane and a ground plane in a package substrate according to an embodiment of the present disclosure.

[0025] FIG15A is a schematic diagram illustrating a simulation test circuit for a package structure of a comparative example; and FIG15B is a schematic diagram illustrating a simulation test circuit for a package structure of an embodiment of the present disclosure.

[0026] FIG16A shows the simulation test results for the packaging structure of the comparative example, and FIG16B shows the simulation test results for the packaging structure of the embodiment of the present disclosure. FIG16A and FIG16B are schematic diagrams showing the voltage at the power pin of the load chip changing with time in the comparative example and the embodiment, respectively. DETAILED DESCRIPTION

[0027] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0029] The present disclosure provides a capacitor structure, a packaging substrate including the capacitor structure, a method for forming the same, and a packaging structure. Compared to conventional capacitor structures, the capacitor structure of the present disclosure has increased capacitance, thereby reducing capacitive reactance and, in turn, reducing the impedance of the packaging substrate including the capacitor structure and the circuitry within the packaging structure (e.g., a power supply network), thereby reducing power supply noise and improving device performance.

[0030] For example, in the embodiment of the present disclosure, by improving the structure of the electrode plate, for example, setting the electrode plate into a fishbone-like structure (which will be described in detail below), adjacent electrode plates in the same conductive plane can form a fishbone-shaped interdigitated capacitor structure to increase the facing area of ​​adjacent electrode plates in the direction parallel to the conductive plane, thereby increasing the capacitance of the capacitor structure, reducing the capacitive reactance generated by the capacitor structure, and further reducing the impedance in the circuit and the power supply noise caused by the impedance, thereby improving the performance of the device.

[0031] FIG1 shows a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure.

[0032] Referring to FIG. 1 , in some embodiments, a package structure 50 includes a chip 10 and a package substrate 30 . The chip 10 is mounted on and electrically connected to the package substrate 30 . In some embodiments, the package structure 50 may be a flip chip (FC) package. For example, the chip 20 may include a substrate 10 , a device layer 11 , and a plurality of conductive connectors 12 . The substrate 10 may be a semiconductor substrate, such as a silicon substrate. For example, the device layer 11 may include active devices such as transistors, passive devices such as capacitors, or a combination thereof. The conductive connectors 12 may be disposed on a side of the device layer 11 away from the substrate 10 and may provide electrical connections between the chip 20 and the package substrate 30 . The side of the chip 10 having the conductive connectors 12 may be referred to as the active side or front side of the chip 10 , and the side opposite the front side may be referred to as the back side of the chip 20 . For example, the active side of the chip 20 faces the package substrate 30 and is electrically connected to the package substrate 30 via the plurality of conductive connectors 12 .

[0033] In some embodiments, the package substrate 30 may include a core layer 31, a build-up layer 32a, a build-up layer 32b, a solder mask 33a, and a solder mask 33b. In a direction perpendicular to the main surface of the package substrate 30 (e.g., direction D3), the build-up layer 32a and the build-up layer 32b are located on opposite sides of the core layer 31, and the solder mask 33a and the solder mask 33b are located on the side of the build-up layer 32a and the build-up layer 32b away from the core layer 31, respectively. In some embodiments, the core layer 31 includes a core dielectric layer and a conductive structure; the core dielectric layer may include a resin material such as epoxy resin and / or a material such as glass fiber or similar materials, and the present disclosure does not limit the material type of the core layer. The conductive structure in the core layer 31 may include a conductive via penetrating the core dielectric layer and / or a conductive layer (e.g., including a conductive line) located on opposite sides of the core dielectric layer.

[0034] Buildup layer 32a and buildup layer 32b may each include one or more dielectric layers and conductive layers stacked one on top of the other, with one or more conductive layers embedded in the dielectric layer. The conductive components in the one or more conductive layers may be electrically connected to the conductive structures in core layer 31, and the conductive components located in different layers may be connected to each other via conductive vias passing through the dielectric layers. For example, the dielectric layers in the buildup layers may include prepreg, which may include a resin material and glass fiber, or the dielectric layers in the buildup layers may include Ajinomoto Buildup Film (ABF), but the present disclosure is not limited thereto. In some embodiments, solder resist layer 33a and solder resist layer 33b may each have one or more openings (not shown) to expose portions of the conductive components (e.g., conductive pads) in buildup layers 32a and 32b for further electrical connection. For example, at least a portion of the conductive pads (not shown) exposed by solder resist layer 33a is electrically connected to the conductive connector 12 of chip 120a. A conductive plane including a power plane and / or a ground plane may be provided in one or more conductive layers of the package substrate 30 .

[0035] In some embodiments, the package structure 50 further includes an underfill layer 13. The underfill layer 13 fills the space between the chip 20 and the package substrate 30 and surrounds and protects the plurality of conductive connectors 12. In some embodiments, conductive connectors 36 are provided on a side of the package substrate 30 away from the chip 20. The conductive connectors 36 are electrically connected to the chip 20 through the package substrate 30, and the package structure 50 can be further connected to other package components or electronic components through the conductive connectors 36, but the present disclosure is not limited thereto. In other embodiments, the package structure 50 may not have the conductive connectors 36.

[0036] In some embodiments, the chip 20 and the package substrate 30 are electrically connected. For example, the chip 20 may be connected to a power plane, a ground plane, etc. in the package substrate 30 to provide corresponding electrical signals to components in the chip 20 .

[0037] Figure 2A schematically illustrates a power network within a package structure, and Figure 2B schematically illustrates an equivalent power network within the package structure, where LD1 and LD2 represent the two terminals of a load chip, and a power supply S is connected to the load chip. The load chip may be, for example, chip 20 shown in Figure 1 , and power supply S may comprise power provided by a power plane within package substrate 30.

[0038] As shown in Figure 2A, in some examples, the power supply S has internal resistance. In addition, conductive components such as through-holes and pads in the package substrate will have parasitic resistance and parasitic inductance (not shown), and parasitic capacitance C will exist between conductive planes (for example, between the power plane and the ground plane). The power supply network shown in Figure 2A is equivalent to the equivalent power supply network in Figure 2B, where Z represents the impedance of the power supply path. When the power supply path has impedance, a voltage drop is inevitably generated when transient current flows through it, causing the voltage at the power supply pin of the load chip to change with the change of transient current. This is the power supply noise generated by impedance.

[0039] Impedance refers to the resistance to current flow in a circuit with resistance, inductance, and capacitance. The impedance formula is as follows:

[0040] Impedance Z = R + jwL + 1 / jwc; where R, jwL, and 1 / jwc are the resistance, inductance, and capacitance of the circuit, respectively; R, j, w, L, and c are the resistance, imaginary unit, angular frequency of the current, inductance, and capacitance, respectively.

[0041] Inductive reactance and capacitive reactance refer to the resistance to current (e.g., AC) in a circuit, as shown in the above formulas. The impedance and capacitive reactance in a circuit are inversely correlated with the capacitance of the capacitor. For example, if the resistance and inductive reactance in a circuit remain constant, increasing the capacitance will reduce the capacitive reactance, thereby reducing the impedance.

[0042] Impedance may cause a voltage drop in the power path due to transient current. The voltage drop formula is as follows: △V=Z×△I;

[0043] It can be seen from the above formula that increasing the capacitance of the capacitor structure can reduce the impedance, thereby reducing the voltage drop of the transient current on the power path.

[0044] The formula for capacitance is as follows:

[0045] C = εrS / 4πkd, where εr is the relative permittivity of the dielectric layer between the electrodes, S is the area of ​​the capacitor plates facing each other, d is the distance between the capacitor plates, and k is the electrostatic force constant. The capacitance formula shows that the capacitance of a capacitor structure is positively correlated with the area of ​​the capacitor plates facing each other. In other words, increasing the area of ​​the capacitor plates facing each other can help increase the capacitance of the capacitor structure.

[0046] In some embodiments, the integrated circuit system of the package substrate 30 may include a capacitor structure composed of two or more electrode plates. For example, a power plane and a ground plane in the package substrate 30 may be arranged relative to each other to form a capacitor structure. The following describes the capacitor structure in the package substrate in detail. It should be understood that for the sake of simplicity, some subsequent figures only show the relevant diagrams of the capacitor structure, and do not specifically show other components of the package substrate where the capacitor structure is located.

[0047] Figure 3A is a schematic perspective view of a capacitor structure in a package substrate. Figure 3B is a schematic cross-sectional view of a capacitor structure in a package substrate, wherein Figure 3B is an interface view taken along line II' of Figure 3A.

[0048] 3A , capacitor structure 1 includes a first plate layer 60, a first dielectric layer 61, a second plate layer 63, a second dielectric layer 65, and a third plate layer 66 stacked in sequence perpendicular to the main surface of the package substrate. For example, first plate layer 60, second plate layer 63, and third plate layer 66 respectively comprise the first plate E1, second plate E2, and third plate E3 of the capacitor structure. First dielectric layer 61 and second dielectric layer 65 serve as inter-electrode dielectric layers of the capacitor structure.

[0049] The first electrode plate E1 and the third electrode plate E3 are electrically connected to each other, for example, via conductive vias 62 and 64 and a conductive pad 63b. Conductive vias 62 and 64 may be provided in the first dielectric layer 61 and the second dielectric layer 65, respectively. The conductive pad 63b is provided in the second electrode layer 63 and is spaced apart from and electrically isolated from the second electrode plate E2. For example, the second electrode layer 63 includes an anti-pad 63o, which is an opening surrounding the conductive pad 63b and is located between the conductive pad 63b and the second electrode plate E2 to electrically isolate the conductive pad 63b from the second electrode plate E2.

[0050] For example, the first plate E1 and the third plate E3 may be power planes, and the second plate E2 may be a ground plane; or, the first plate E1 and the third plate E3 may be ground planes, and the second plate E2 may be a power plane. In this example, the electrode plates located in each layer may extend continuously in a direction parallel to the main surface of the packaging substrate, and may be, for example, block-shaped or planar. In a direction perpendicular to the main surface of the packaging substrate, the capacitor structure 1 includes a capacitor formed between each adjacent two electrode plates, for example, including a double-layer capacitor formed between the first plate E1 and the second plate E2 and between the second plate E2 and the third plate E3. The capacitor structure shown in Figures 3A and 3B may also be referred to as a parallel plate capacitor structure.

[0051] 4A is a schematic three-dimensional diagram of another capacitor structure in a packaging substrate; FIG. 4B and FIG. 4C are schematic cross-sectional diagrams of the capacitor structure shown in FIG. 4A , and FIG. 4B and FIG. 4C are cross-sectional diagrams taken along line II′ and line II-II′ of FIG. 4A , respectively.

[0052] 4A and 4B , the capacitor structure 2 may include a first conductive plane 70, a first dielectric layer 71, a second conductive plane 73, a second dielectric layer 75, and a third conductive plane 76 stacked in sequence in a direction perpendicular to the main surface of the package substrate. Each conductive plane is provided with a plurality of electrode plates separated from each other; for example, the first conductive plane 70 includes a plurality of first electrode plates E1a and a plurality of second electrode plates E1b; the second conductive plane 73 includes a plurality of first electrode plates E2a and a plurality of second electrode plates E2b; and the third conductive plane 76 includes a plurality of first electrode plates E3a and a plurality of second electrode plates E3b. The first electrode plates and the second electrode plates may be different types of electrode plates; for example, one of the first electrode plate and the second electrode plate may be a power plane, and the other of the first electrode plate and the second electrode plate may be a ground plane. In each conductive plane, a plurality of electrode plates are arranged in an array in a direction parallel to the main surface of the packaging substrate. For example, they can be arranged into an array including multiple rows and columns along direction D1 and direction D2, and in direction D1 and direction D2, a plurality of first electrode plates and a plurality of second electrode plates are arranged alternately; that is, in direction D1 and direction D2, each two adjacent electrode plates are different types of electrode plates and are electrically isolated from each other. Direction D1 and direction D2 are both directions parallel to the main surface of the packaging substrate and the conductive plane (or can be called horizontal directions), and direction D1 and direction D2 intersect with each other, for example, perpendicular to each other. A dielectric layer (not shown) is also provided between adjacent electrode plates on the same conductive plane, and the dielectric layer serves as an inter-electrode dielectric layer of the capacitor structure formed in the horizontal direction.

[0053] In a direction perpendicular to the main surface of the package substrate (e.g., direction D3), the first electrode plate and the second electrode plate may also be arranged alternately with each other. For example, the capacitor structure 2 includes a plurality of capacitor stacking structures, and the plurality of capacitor stacking structures include a first capacitor stacking structure 2a and a second capacitor stacking structure 2b. Figures 4B and 4C respectively show schematic cross-sectional views of the first capacitor stacking structure 2a and the second capacitor stacking structure 2b.

[0054] 4B , the first capacitor stack structure 2a includes a first electrode plate E1a, a second electrode plate E2b, and a first electrode plate E3a stacked in sequence in a direction D3; the first electrode plate E1a and the first electrode plate E3a are electrically connected to each other, for example, through conductive through-holes 72a and conductive through-holes 74a located in the first dielectric layer 71 and the second dielectric layer 75, respectively, and a transition pad 73a located in the conductive plane 73. The conductive plane 73 also includes an anti-pad 73o, which surrounds the transition pad 73a and electrically isolates the transition pad 73a from the electrode plate E2b. In this article, an "anti-pad" refers to an opening located in a conductive plane and is used to electrically isolate the transition pad and the electrode plate located in the conductive plane. In some embodiments, the conductive plane 70 and the conductive plane 76 may further include a transition pad 70b and a transition pad 76b, respectively, so that the second electrode plate E2b can be electrically connected to the second electrode plate (not shown) located on the other conductive plane through the conductive through-holes 72b, 74b and the transition pads 70b, 76b; the conductive plane 70 and the conductive plane 76 further include an anti-pad 70o and an anti-pad 76o, respectively, to electrically isolate the transition pad 70b and the transition pad 76b from the first electrode plates E1a and E3a, respectively. In the first capacitor stacking structure 2a, each adjacent two electrode plates are arranged relative to each other in a direction perpendicular to the main surface of the package to form a capacitor; that is, the first capacitor stacking structure 2a includes a double-layer capacitor formed between the first electrode plate E1a and the second electrode plate E2b and the first electrode plate E3a and the second electrode plate E2b. It should be understood that the number of layers of the electrode plates included in the capacitor stacking structure shown in the figure is only for illustration, and the present disclosure is not limited thereto. More or fewer layers of electrode plates can be provided in the capacitor stack structure based on product and design requirements.

[0055] 4C , the second capacitor stack structure 2b includes a second electrode plate E1b, a first electrode plate E2b, and a second electrode plate E3b stacked sequentially in direction D3. The second electrode plate E1b and the second electrode plate E3b are electrically connected to each other, for example, via conductive vias 72b and 74b located in the first dielectric layer 71 and the second dielectric layer 75, respectively, and a connecting pad 73b located in the conductive plane 73. The conductive plane 73 also includes an anti-pad 73o surrounding the transition pad 73b to electrically isolate the transition pad 73a from the electrode plate E2a. In some embodiments, the conductive plane 70 and the conductive plane 76 may further include a transition pad 70a and a transition pad 76a, respectively, so that the first electrode plate E2a can be electrically connected to the first electrode plate (not shown) located on the other conductive plane through the conductive through-holes 72a, 74a and the transition pads 70a, 76a; the conductive plane 70 and the conductive plane 76 further include anti-pads 70o, 76o surrounding the transition pads 70a, 76a, respectively, to electrically isolate the transition pads 70a and the transition pads 76a from the second electrode plates E1a, E3a. In the second capacitor stacking structure 2b, each adjacent two electrode plates are arranged relative to each other in a direction perpendicular to the main surface of the package to form a capacitor; that is, the second capacitor stacking structure 2b includes a double-layer capacitor formed between the second electrode plate E1b and the first electrode plate E2a and the second electrode plate E3b and the first electrode plate E2a.

[0056] That is, in each capacitor stack structure, multiple first electrode plates are connected to the same network (net), for example, the first network; multiple second electrode plates are connected to the same network, for example, the second network, and the first network and the second network are different. In some embodiments, the first electrode plate and the second electrode plate in the same conductive plane are connected to different networks; different first electrode plates in the same conductive plane can be connected to the same or different networks; different second electrode plates in the same conductive plane can be connected to the same or different networks.

[0057] Referring to FIG. 4A , in some embodiments, multiple capacitor stack structures are arranged in an array along directions D1 and D2. For example, multiple first capacitor stack structures 2a and multiple second capacitor stack structures 2b may be arranged alternately along direction D1 and alternately along direction D2, such that each adjacent two capacitor stack structures are different types of capacitor stack structures, and each adjacent two electrode plates in each conductive plane are different types of electrode plates that are electrically isolated from each other. In each conductive plane, adjacent first and second electrode plates may also constitute a capacitor.

[0058] In some examples, the sizes of the conductive through holes and pads in the capacitor structure 2 may be similar to those in the aforementioned capacitor structure 1; in addition, in the capacitor structure 2, the minimum size of each electrode plate (for example, the length in the direction D2) needs to be set so that the electrode plate can be connected to the conductive through holes of two different networks, and the size (length, width, etc.) of each electrode plate can also be adjusted according to the arrangement of the conductive through holes. For example, as shown in Figure 4A, multiple conductive through holes in adjacent capacitor stacking structures can be roughly aligned in the direction D2, while multiple conductive through holes in adjacent capacitor stacking structures can be staggered and not aligned with each other in the direction D1, but the present disclosure is not limited to this. In other examples, multiple conductive through holes in adjacent capacitor stacking structures can also be roughly aligned in the direction D1. For example, the length L of each electrode plate in the direction D2 can be greater than twice the diameter of the anti-pad, and the spacing requirements between two adjacent anti-pads must be met (for example, the spacing must be greater than or equal to 25μm), the width W of each electrode plate in the direction D1 can be greater than the diameter of a single anti-pad, and the spacing s between adjacent electrode plates must meet the process conditions. Taking the arrangement of FIG4A as an example, in an example where the anti-pad diameter is 160 μm, the length L of each electrode plate in direction D2 must be greater than 320 μm, for example, 950 μm, and the width W of each electrode plate in direction D1 must be at least greater than the diameter of the anti-pad, for example, 200 μm. The spacing S between adjacent electrode plates in their arrangement direction must meet process conditions, for example, 50 μm. It should be understood that the above-mentioned dimensional features are for illustrative purposes only and the present disclosure is not limited thereto.

[0059] Compared to capacitor structure 1, capacitor structure 2 includes not only the capacitance formed by different layers of electrode plates in a direction perpendicular to the main surface of the package substrate, but also capacitance formed by adjacent electrode plates in a direction parallel to the main surface of the package substrate. Therefore, by separating each conductive plane into multiple electrode plates and adopting the above-mentioned structural arrangement, capacitor structure 2 increases the capacitance of the capacitor structure, thereby reducing the impedance in the package structure circuit and, in turn, reducing power supply noise.

[0060] Figure 5A shows a schematic stereoscopic diagram of a capacitor structure 3 in a packaging substrate according to some embodiments of the present disclosure, and Figure 5B shows a schematic plan view of the capacitor structure shown in Figure 5A. Figures 4B and 4C respectively show schematic cross-sectional views taken along line I-I' and line II-II' of Figure 5A. In other words, capacitor structure 2 and capacitor structure 3 have the same cross-sectional structure. The capacitor structure 3 shown in Figure 5A is similar to the capacitor structure 2 shown in Figure 4A, with the difference that: in the capacitor structure 3, the edge of each electrode plate is further provided with a plurality of electrode extensions, and the plurality of electrode extensions of adjacent electrode plates in each conductive plane are cross-linked (i.e., interlaced) with each other to form an interdigitated capacitor structure. The plurality of electrode extensions can also be referred to as finger electrodes.

[0061] 5A, 4B and 4C, the capacitor structure 3 includes conductive planes 70, 73, 76 and dielectric layers 71, 75, and includes multiple first capacitor stacking structures 3a and multiple second capacitor stacking structures 3b; the first capacitor stacking structure 3a includes a first electrode plate E1a, a second electrode plate E2b, and a first electrode plate E3a stacked in sequence in a direction perpendicular to the main surface of the packaging substrate and respectively located on the conductive planes 70, 73, 76, and an inter-electrode dielectric layer located between adjacent electrode plates; the second capacitor stacking structure 3b includes a second electrode plate E1b, a first electrode plate E2a, and a second electrode plate E3b stacked in sequence in a direction perpendicular to the main surface of the packaging substrate and respectively located on the conductive planes 70, 73, 76, and an inter-electrode dielectric layer located between adjacent electrode plates. The cross-sectional structure of the capacitor structure 3a along line II' and line II-II' is substantially the same as the cross-sectional structure of the capacitor structure 2a along line II' and line II-II'. For relevant structural features, reference can be made to the above description of Figures 4A to 4C and will not be repeated here.

[0062] 5A and 5B, a plurality of capacitor stacking structures may be arranged in an array in a direction parallel to the main surface of the package substrate, for example, arranged in an array including multiple rows and columns along direction D1 and direction D2. For example, a plurality of first capacitor stacking structures 3a and a plurality of second capacitor stacking structures 3b are arranged alternately with each other along direction D1, and alternately with each other along direction D2. In each layer of conductive plane, a plurality of first electrode plates and a plurality of second electrode plates are also arranged alternately with each other along directions D1 and D2. That is to say, in direction D1 and direction D2, each two adjacent capacitor stacking structures are different types of capacitor stacking structures; in each layer of conductive plane, each two adjacent electrode plates are different types of electrode plates.

[0063] In some embodiments, each electrode plate includes an electrode main body and an electrode extension portion arranged at the edge of the electrode main body. The electrode extension portion can be arranged on the side of the electrode main body opposite to the other electrode plates, for example, on each side opposite to the other electrode plates. Taking the conductive plane 76 as an example, the first electrode plate E3a includes an electrode main body a0, an electrode extension portion a1, and an electrode extension portion a2, wherein the plurality of electrode extension portions a1 are located on one side or on opposite sides of the electrode main body a0 in the direction D1, and the plurality of electrode extension portions a2 are located on one side or on opposite sides of the electrode main body a0 in the direction D2; the second electrode plate E3b includes an electrode main body b0, an electrode extension portion b1, and an electrode extension portion b2, wherein the plurality of electrode extension portions b1 are located on one side or on opposite sides of the electrode main body b0 in the direction D1, and the plurality of electrode extension portions b2 are located on one side or on opposite sides of the electrode main body b0 in the direction D2. In the first conductive plane 70 and the second conductive plane 73, the first electrode plate and the second electrode plate also have similar structures. In some examples, in each electrode plate, the line width of the electrode extension portion may be 15 μm. In the interdigital capacitor structure formed by adjacent electrode plates, the line spacing between adjacent electrode extension portions may be, for example, 15 μm, but the present disclosure is not limited thereto.

[0064] In each conductive plane, for each group of adjacent first electrode plates and second electrode plates in direction D1 or D2, an electrode extension is provided on the side of the first electrode plate facing the second electrode plate and on the side of the second electrode plate facing the first electrode plate, and the electrode extension of the first electrode plate and the electrode extension of the second electrode plate each extend in a direction parallel to the arrangement direction of the two electrode plates, and overlap and are alternately arranged in a direction perpendicular to the arrangement direction to form an interdigitated capacitor structure.

[0065] For example, with respect to a first electrode plate E3a and a second electrode plate E3b adjacent in direction D1, a plurality of electrode extensions a1 are provided on the side of the first electrode plate E3a facing the second electrode plate E3b, and a plurality of electrode extensions b1 are provided on the side of the second electrode plate E3b facing the first electrode plate E3a. Both the plurality of electrode extensions a1 and the plurality of electrode extensions b1 extend from their respective electrode main bodies toward each other's electrode main bodies in direction D1. That is, the plurality of electrode extensions a1 are located on the side of the electrode main body a0 proximal to the second electrode plate E3b in direction D1 and extend from the edge of the electrode main body a0 toward the electrode main body b0. The plurality of electrode extensions b1 are located on the side of the electrode main body b0 proximal to the first electrode plate E3a in direction D1 and extend from the edge of the electrode main body b0 toward the electrode main body a0. The plurality of electrode extensions a1 and the plurality of electrode extensions b1 overlap and are arranged alternately in direction D2, such that the first electrode plate E3a and the second electrode plate E3b together form a first interdigital capacitor structure. In this article, the overlapping of multiple components in a certain direction means that the orthographic projections of the multiple components on a reference plane perpendicular to the direction overlap with each other; that is, the orthographic projections of the multiple electrode extensions a1 and the multiple electrode extensions b1 on a reference plane perpendicular to the direction D2 (for example, parallel to the direction D1) overlap with each other.

[0066] For the first and second electrode plates E3a and E3b, which are adjacent in direction D2, a plurality of electrode extensions a2 are provided on the side of the first electrode plate E3a facing the second electrode plate E3b, and a plurality of electrode extensions b2 are provided on the side of the second electrode plate E3b facing the first electrode plate E3a. The plurality of electrode extensions a2 and the plurality of electrode extensions b2 each extend from their respective electrode main bodies toward each other's electrode main bodies in direction D2. Specifically, the plurality of electrode extensions a2 are located on the side of the electrode main body a0 near the second electrode plate E3b in direction D2 and extend from the edge of the electrode main body a0 toward the electrode main body b0. The plurality of electrode extensions b2 are located on the side of the electrode main body b0 near the first electrode plate E3a in direction D2 and extend from the edge of the electrode main body b0 toward the electrode main body a0. The plurality of electrode extensions a2 and the plurality of electrode extensions b2 overlap and are arranged alternately in direction D2, thereby forming a second interdigital capacitor structure for the first and second electrode plates E3a and E3b.

[0067] In the capacitor structure 3, multiple first electrode plates and multiple second electrode plates are alternately arranged in a direction parallel to the main surface of the packaging substrate, and the electrode extensions of adjacent electrode plates are opposite to each other and form an interdigitated capacitor structure, thereby increasing the facing area of ​​adjacent electrode plates, thereby further increasing the capacitance of the capacitor structure, which is beneficial to reducing the impedance on the power supply path, reducing the power supply noise caused by impedance, and improving device performance.

[0068] Figure 6A shows a schematic stereoscopic diagram of a capacitor structure 500 according to other embodiments of the present disclosure. Figures 6B to 6D respectively show schematic plan views of each conductive plane in the capacitor structure according to other embodiments of the present disclosure. For the sake of clarity of the drawings, the number of rows of electrode plates shown in Figures 6B to 6D is less than the number of rows of electrode plates shown in Figure 6A. It should be understood that the number of layers of conductive planes shown in Figures 6A to 6D and the number of electrode plates included in each conductive plane are only for illustration, and the present disclosure is not limited thereto. It should be understood that, in this article, the term "electrode plate" only refers to the electrodes in the capacitor structure, and does not include restrictions on the shape of the electrode. It does not limit the electrode to a block or surface shape with a larger area, and the specific shape and structural features of the electrode plate can be referred to the detailed description in the relevant embodiments.

[0069] In some embodiments, the capacitor structure includes at least one conductive plane, each conductive plane includes a plurality of electrode plates, the plurality of electrode plates are arranged side by side and spaced apart from each other in a direction parallel to the main surface of the conductive plane, wherein each electrode plate includes: a pad portion, including a pad main portion and a plurality of pad extension portions connected to each other, wherein the plurality of pad extension portions are arranged on the side of the pad main portion in a first direction parallel to the main surface of the conductive plane; and a connecting portion, including a connecting main portion and a plurality of connecting extension portions connected to each other, wherein the plurality of connecting extension portions are arranged on the side of the connecting main portion in the first direction, and the plurality of pad extension portions and the plurality of connecting extension portions constitute a plurality of extended electrodes; The middle pad main body and the connecting main body are arranged along the second direction and connected to each other, the second direction intersects with the first direction, and the width of the pad main body in the first direction is greater than the width of the connecting main body in the first direction; multiple pad extensions and multiple connecting extensions extend along the first direction and are arranged along the second direction at intervals from each other; wherein in each conductive plane, the multiple electrode plates include a first electrode plate and a second electrode plate adjacent to each other in the first direction, the first electrode plate and the second electrode plate are opposite to each other and arranged at intervals in the first direction, and the multiple extended electrodes of the first electrode plate and the multiple extended electrodes of the second electrode plate overlap in the second direction and are arranged alternately with each other to form a finger capacitor structure.

[0070] For example, referring to Figures 6A and 6B, the capacitor structure 500 includes a first conductive plane 106, and the first conductive plane 106 includes one or more electrode plates E3a and one or more electrode plates E3b; in some embodiments, the electrode plate E3a and the electrode plate E3b can be respectively referred to as the first electrode plate and the second electrode plate, or vice versa.

[0071] In some embodiments, the plurality of electrode plates are arranged in an array in a direction parallel to the main surface of the conductive plane; for example, the plurality of first electrode plates E3a and the plurality of second electrode plates E3b may be arranged alternately in directions D1 and D2 parallel to the main surface of the conductive plane. In some embodiments, the plurality of first electrode plates may be of the same type; the plurality of second electrode plates may be of the same type; the first electrode plates and the second electrode plates may be of different types and electrically isolated from each other; for example, the first electrode plate may be a ground plane and the second electrode plate may be a power plane; or the first electrode plate may be a power plane and the second electrode plate may be a ground plane.

[0072] 7A and 7B are schematic enlarged plan views showing the first electrode plate E3a and the second electrode plate E3b, respectively.

[0073] 7A , in some embodiments, the first electrode plate E3a includes a pad portion 210 and a connecting portion 220. The pad portion 210 may include a pad body portion and a plurality of pad extension portions connected to each other. The plurality of pad extension portions may be located on the sides of the pad body portion in direction D1, for example, on one side or on two opposite sides of the pad body portion. The connecting portion 210 may include a connecting body portion and a plurality of connecting extension portions connected to each other. The plurality of connecting extension portions may be located on the sides of the connecting body portion in direction D1, for example, on one side or on two opposite sides of the connecting body portion. In some embodiments, the first electrode plate E3a may include at least one pad portion and at least one connecting portion.

[0074] For example, the pad portion 210 may include a first pad portion 210a and a second pad portion 210b. The first pad portion 210a may include a first pad body portion 201 and a plurality of first pad extensions 202a connected to each other. The second pad portion 210b may include a second pad body portion 205 and a plurality of second pad extensions 206. The plurality of first pad extensions 202a and the plurality of second pad extensions 206 are located on either side of the first pad body portion 201 and the second pad body portion 205, respectively, in direction D1. In some embodiments, the plurality of first pad extensions 202a may include one or more pad extensions 202a1 and 202a2. The pad extensions 202a1 and 202a2 may have different extension lengths and may be referred to as first and second extension sub-portions of the first pad extension portion, respectively.

[0075] The connecting portion 220 may include a first connecting portion 220a and a second connecting portion 220b. The first connecting portion 220a includes a first connecting body portion 203 and a plurality of first connecting extensions 204 connected to each other. The second connecting portion 220b includes a second connecting body portion 207 and a plurality of second connecting extensions 208a connected to each other. The first connecting extensions 204 and the second connecting extensions 208a are located on either side of the first connecting body portion 203 and the second connecting body portion 207, respectively, in direction D1.

[0076] In some embodiments, the pad portion and the connecting portion may be arranged along direction D2, for example, multiple pad portions and multiple connecting portions may be arranged alternately along direction D2; for example, the first pad portion 210a, the first connecting portion 220a, the second pad portion 210b and the second connecting portion 220b may be arranged in sequence along direction D2; that is, in direction D2, the first connecting portion 220a is located between the first pad portion 210a and the second pad portion 210b, and the second connecting portion 220b is located on the side of the second pad portion 210b away from the first pad portion 220a.

[0077] In some embodiments, the pad body portion and the connecting body portion have different widths, for example, the width of the pad body portion is greater than the width of the connecting body portion. Here, the width of the pad body portion and the connecting body portion refers to the width in a direction (for example, direction D1) perpendicular to the arrangement direction of the pad portion and the connecting portion (for example, direction D2); the width direction of the pad body portion and the connecting body portion is the same as the extension direction of the pad extension portion and the connecting extension portion.

[0078] For example, the first pad body 201 and the second pad body 205 may have substantially the same width w1 in the direction D1; the first connection body 203 and the second connection body 207 may have substantially the same width w2 in the direction D1, and the width w1 is greater than the width w2.

[0079] In some embodiments, from a plan view, the pad body portion and the connecting body portion each have an edge that is opposite to each other in direction D1 and extends along direction D2. The edge of the pad body portion and the edge of the connecting body portion are not aligned in direction D2, that is, they are offset from each other in direction D1. The pad body portion extends beyond (that is, protrudes from) the corresponding edge of the connecting body portion in direction D1. The edges of the pad body portion and the connecting body portion can respectively be their sidewalls.

[0080] For example, opposing edges 201e1 of the first pad body portion 201 may be aligned with opposing edges 205e of the second pad body portion 205 in direction D2; opposing edges 203e of the first connecting body portion 203 may be aligned with opposing edges 207e1 of the second connecting body portion 207 in direction D2. Edges 201e1 of the first pad body portion 201 and 205e of the second pad body portion 205 are not aligned with edges 203e of the first connecting body portion 203 and 207e1 of the second connecting body portion in direction D2, but are offset from each other in direction D1. The first and second pad bodies 201 and 203 extend beyond edges 203e of the first connecting body portion 203 and 207e1 of the second connecting body portion in direction D1.

[0081] 7A , in some embodiments, the pad main body portions 201 and 205 may be block-shaped or similar in shape, and the connection main body portions 203 and 207 may be strip-shaped, and the strips extend along direction D2 , for example.

[0082] In some embodiments, each of the plurality of pad extensions extends from an edge of a corresponding pad body portion away from the pad body portion, for example, extending toward an adjacent electrode plate in a direction perpendicular to the edge of the pad body portion. Similarly, each of the plurality of connection extensions extends from an edge of a corresponding connection body portion away from the connection body portion, for example, extending toward an adjacent electrode plate in a direction perpendicular to the edge of the connection body portion.

[0083] For example, the plurality of pad extensions 202a and 208a protrude from the edges 201e1 and 205e of the corresponding pad body portions 201 and 205, respectively, in direction D1. The plurality of connecting extensions 204 and 208a protrude from the edges 203e and 207e1 of the corresponding connecting body portions 203 and 207, respectively, in direction D1. For example, the plurality of pad extensions 202a and 208a and the plurality of connecting extensions 204 and 208a located on the same side of the pad body portion and the connecting body portion in direction D1 may extend parallel to each other along direction D1 and be arranged along direction D2 and spaced apart from each other. That is, a gap exists between each adjacent extension in direction D2 (e.g., between two adjacent pad extensions, between two adjacent connecting extensions, or between adjacent pad extensions and connecting extensions).

[0084] In some embodiments, the plurality of pad extensions and the plurality of connection extensions may each be strip-shaped or finger-shaped, and may be referred to as finger electrodes, or collectively referred to as extensions of the electrode plate or extended electrodes.

[0085] In some embodiments, at least some of the plurality of pad extensions have the same extension length in direction D1 as the extension length of the plurality of connecting extensions in direction D1. Herein, an extension (pad extension or connecting extension) extends beyond the edge of the main body (pad main body or connecting main body), and the extension length of the extension refers to its length in the direction of extension (e.g., direction D1), that is, the distance from the edge of the main body to the edge of the extension away from the main body in the extension direction.

[0086] For example, the first pad extension 202a1 and the second pad extension 206 may have the same extension length L1. Since the first pad body 201 and the second pad body 205 have substantially the same width and their edges are aligned, the edges of the first pad extension 202a1 and the second pad extension 206 away from the pad body may also be aligned in direction D2. The first connection extension 204 and the second connection extension 208a may have the same extension length L2. Since the first connection body 203 and the second connection body 207 have substantially the same width and their edges are aligned, the edges of the first connection extension 204 and the second connection extension 208a away from the connection body may also be aligned in direction D2.

[0087] Referring to FIG. 7A , the extension length L1 of pad extensions 202a1 and 206 can be substantially the same as the extension length L2 of connector extensions 204 and 208a. Because the pad body and connector body have different widths and the pad body extends beyond the edge of the connector body, the edges of the pad extensions distal from the pad body and the edges of the connector extensions distal from the connector body are not aligned in direction D2 but are offset from each other in direction D1. In alternative embodiments, the extension length L1 of pad extensions 202a1 and 206 can also differ from the extension length L2 of connector extensions 204 and 208a. In some examples, the extension lengths L1 and L2 of the pad extensions and connector extensions can each be greater than or equal to 35 μm, for example, 120 μm.

[0088] In some embodiments, the overall width WE1 of the pad portion 210 in direction D1 is greater than the overall width WE2 of the connecting portion 220 in direction D1. Herein, the overall width of the pad portion or connecting portion refers to its maximum width in direction D1. For example, the overall width of the pad portion in direction D1 is approximately equal to the sum of the width W1 of the pad body and the extended length (L1 or L1×2) of one or two pad extensions; the overall width of the connecting portion in direction D1 is approximately equal to the sum of the width W2 of the connecting body and the extended length (L2 or L2×2) of one or two connecting extensions.

[0089] In some embodiments, the overall width WE2 of the connecting portion 210 can be greater than the width W1 of the pad body; the connecting extensions 204 and 208a can extend beyond the edges 201e1 and 205e of the pad body in the direction D1. This configuration allows the extension of the electrode plate to have a sufficiently large extension length, which helps increase the facing area between the plates in the formed interdigital capacitor, thereby improving the capacitance of the capacitor structure. However, the present disclosure is not limited to this.

[0090] In some embodiments, in the first pad extension 202a, the pad extension 202a1 and the pad extension 202a2 may extend to different lengths. The pad extension 202a2 may be located near the edge 201e2 of the pad body 201 in direction D2, and the pad extension 202a1 is located on a side of the pad extension 202a2 that is away from the edge 201e2 and closer to the connection portion 220a in direction D2. The edge 201e2 of the pad body 201 extends along direction D1 and is away from the connection portion 220a in direction D2. The pad extension 202a2 may also be referred to as a pad edge extension.

[0091] For example, the extension length L3 of the pad extension 202a2 may be less than the extension length L1 of the pad extensions 202a1 and 206 and the extension length L2 of the connecting extensions 204 and 208a. In some embodiments, the overall width of the portion of the first pad portion 210a near the edge 201e2 (i.e., including the pad body portion 201 and the pad extension 202a2) in direction D1 may be substantially equal to the overall width WE2 of the connecting portion 220 in direction D1. The width of the portion of the first pad portion 210a near the edge 201e2 is substantially equal to the sum of the width W1 of the pad body portion 201 and the extension length (L3 or L3×2) of one or both pad extensions 202a2. In some embodiments, the edge of the pad extension 202a2 distal from the pad body portion 201 may be substantially aligned with the edges of the connecting extensions 204 and 208a distal from the connecting body portions 203 and 207 in direction D2.

[0092] Continuing with reference to FIG7A , in some embodiments, the first pad portion 220a and the second pad portion 220b include different types of pads; for example, one of the first pad portion 220a and the second pad portion 220b includes a connecting pad, and the other of the first pad portion 220a and the second pad portion 220b includes an anti-pad, and a transition pad may be provided in the anti-pad. In this article, a "connecting pad" refers to a portion for electrically connecting the electrode plate where it is located to other electrode plates of the same type (for example, both are power planes or both are ground planes) through a conductive through-hole, and the connecting pad is used for landing of the conductive through-hole, that is, the connecting pad is electrically connected to the electrode plate where it is located; a "transition pad" refers to a pad that is located in the same conductive plane as the electrode plate, is located in the opening of the anti-pad, and is electrically isolated from the electrode plate by the anti-pad; a transition pad can be used for electrical connection between other types of electrode plates located in other conductive planes, and the other types of electrode plates refer to the types of electrode plates different from the layer where the transition pad is located.

[0093] For example, the first pad portion 220a includes a connecting pad P3a, which is part of the electrode plate E3a and electrically connected to other parts of the electrode plate E3a and to the conductive via structure V1, thereby enabling the electrode plate E3a to be connected to electrode plates of the same network located on other conductive planes via the conductive via structure V1. The second pad portion 220b may include an anti-pad AP3a, and a transition pad TP3a ​​is disposed within the anti-pad AP3a; the transition pad TP3a ​​is electrically isolated from the first electrode plate E3a by the anti-pad AP3a. In some embodiments, the transition pad TP3a ​​is used to electrically connect other electrode plates located on adjacent conductive planes.

[0094] Continuing with reference to FIG7A , the electrode plate E3a has two ends opposite to each other in direction D2 (for example, the end of the first pad portion 210a away from the connecting portion 220a and the end of the second connecting portion 220b away from the pad portion 210b); in some embodiments, additional extended electrodes may be further provided at the edges of one or both of the two ends of the electrode plate E3a.

[0095] For example, in some embodiments, the first pad portion 210 may further include a plurality of additional extensions 202b connected to the pad main portion 201 and located on a side of the pad main portion 201 away from the connection portion 220a in direction D2. For example, the plurality of additional extensions 202b may protrude from an edge 201e2 of the pad main portion 201 away from the connection portion 220a in direction D2. The plurality of additional extensions 202b may extend substantially parallel to one another along direction D2, be arranged along direction D1, and be spaced apart from one another. That is, a gap is provided between each two adjacent additional extensions 202b.

[0096] In some embodiments, the second connecting portion 220b may further include a plurality of additional extensions 208b connected to the connecting body portion 207 and located on a side of the connecting body portion 207 away from the pad portion 210b in direction D2. For example, the plurality of additional extensions 208b may protrude from an edge 207e2 of the connecting body portion 207 away from the pad portion 210b in direction D2. The edge 207e2 of the connecting body portion 207 extends in direction D1 and away from the pad portion 210b in direction D2. The plurality of additional extensions 208b may extend substantially parallel to each other in direction D2, be arranged in direction D1, and be spaced apart from each other. That is, a gap is provided between each two adjacent additional extensions 208b.

[0097] In some embodiments, as shown in FIG7A , the second connecting body portion 207 includes a connecting body portion 207a and an additional connecting body portion 207b connected to each other. The additional connecting body portion 207b is located on a side of the connecting body portion 207a away from the pad portion 210b and is connected to one of the plurality of second connecting extensions 208a located near edge 207e2 in direction D2. The width of the additional connecting body portion 207b in direction D1 is greater than the width of the connecting body portion 207a in direction D1 and less than the overall width WE2 of the connecting portion 220b in direction D1. In other words, the second connecting extension 208a also protrudes from edge 207e3 of the additional connecting body portion 207b in direction D1. In some embodiments, the width of the additional connection body portion 207b in direction D1 may be approximately equal to the width of the pad body portions 201 and 205 in direction D1; the relative edges of the additional connection body portion 207b in direction D1 may be approximately aligned with the relative edges of the pad body portions 201 and 205 in direction D1 in direction D2, but the present disclosure is not limited to this.

[0098] The plurality of additional extensions 202b and 208b may each be strip-shaped or finger-shaped and may be referred to as additional extended electrodes or additional finger-shaped electrodes. In some embodiments, the extension length of the additional extensions 202b and 208b in direction D2 may be less than the extension lengths of the pad extensions 202a1 and 206 and the connecting extensions 204 and 208a in direction D2, and may be the same as or different from each other, but the present disclosure is not limited thereto.

[0099] Referring to FIG. 7B , the second electrode plate E3b has a similar structure to the first electrode plate E3a. For example, the second electrode plate E3b includes a pad portion 310 and a connecting portion 320. The pad portion 310 may include a first pad portion 310a and a second pad portion 310b. The connecting portion 320 may include a first connecting portion 320a and a second connecting portion 320b. The first pad portion 310a may include a first pad body portion 301 and a plurality of first pad extensions 302a. The plurality of first pad extensions 302a may include pad extensions 302a1 and pad extensions (or pad edge extensions) 302a2. The first pad extensions 302a extend beyond the edge 301e1 of the pad body portion 301 in direction D1. In some embodiments, the first pad portion 310a may further include a plurality of additional extended electrodes 302b extending beyond the edge 301e2 of the pad body portion 301 in direction D2. The second pad portion 310 b may include a second pad body portion 305 and a plurality of second pad extensions 306 extending beyond an edge 305 e of the second pad body portion 305 in the direction D1 .

[0100] The first connection portion 320a may include a first connection body portion 303 and a plurality of first connection extensions 304, each extending beyond an edge 303e of the first connection body portion 303 in direction D1. The second connection portion 320b may include a second connection body portion 307 and a plurality of second connection extensions 308a, each extending beyond edges 307e1 and 307e3 of the second connection body portion 307 in direction D1. The second connection body portion 307 may include a connection body portion 307a and an additional connection body portion 307e2. In some embodiments, the second connection portion 320b may further include a plurality of additional extension electrodes 308b, each of which may protrude beyond an edge 307e2 of the second connection body portion 307 in direction D2. One of the first pad portion 310a and the second pad portion 310b includes a connecting pad P3b, and the other of the first pad portion 310a and the second pad portion 310b includes an anti-pad AP3b, and a transition pad TP3b is provided on the anti-pad AP3b. Unless otherwise defined herein, the structural features of the pad portion and connecting portion of the second electrode plate E3b are substantially the same as those of the pad portion and connecting portion of the first electrode plate E3a described above, and are not further described herein.

[0101] In some embodiments, the sizes of the respective components in the first electrode plate E3a and the second electrode plate E3b are also substantially the same; for example, the width W1 of the pad body portion 201, 205 of the first electrode plate E3a, the width W2 of the connecting body portion 203, 207, the extension length L1 of the pad extension portion 202a1, 206 and the extension length L2 of the connecting extension portion 204 / 206, the extension length L3 of the pad edge extension portion 202a2, the overall width of the pad portion 210, and the width L1 of the pad extension portion 202a1, 206. WE1 and the overall width WE2 of the connecting portion 220 may be approximately equal to the width W1 of the pad main portion 301, 305 of the second electrode plate E3b, the width W2 of the connecting main portion 303, 307, the extension length L1 of the pad extension portion 302a1, 306 and the extension length L2 of the connecting extension portion 304 / 306, the extension length L3 of the pad edge extension portion 302a2, the overall width WE1 of the pad portion 310 and the overall width WE2 of the connecting portion 320.

[0102] In some embodiments, the width of the additional connecting body portion 207b of the first electrode plate E3a in direction D1 is also approximately equal to the width of the additional connecting body portion 307b of the second electrode plate E3b in direction D1. The extension length of at least one of the additional extended electrode 202b and the additional extended electrode 208b of the first electrode plate E3a in direction D2 is approximately equal to the extension length of at least one of the additional extended electrode 302b and the additional extended electrode 308b of the second electrode plate E3b in direction D2. For example, the extension lengths of the additional extended electrode 202b and the additional extended electrode 208b of the first electrode plate E3a in direction D2, and the extension lengths of the additional extended electrode 302b and the additional extended electrode 308b of the second electrode plate E3b in direction D2 may be approximately equal. In some embodiments, the above-described arrangement of the first and second electrode plates E3a and E3b can maximize the facing area between the first and second electrode plates when they are interdigitated to form an interdigital capacitor, thereby increasing the capacitance of the interdigital capacitor structure. Herein, the first electrode plate and the second electrode plate being arranged to cross each other means that the plurality of extended electrodes of the first electrode plate and the plurality of extended electrodes of the second electrode overlap each other in a certain direction and are alternately arranged and spaced apart from each other.

[0103] In some embodiments, the dimensions (e.g., lengths) of the corresponding components of the first and second electrode plates E3a and E3b in direction D2 may also be substantially equal. For example, in direction D2, the lengths of the first pad body portion 201, the first connecting body portion 203, the second pad body portion 205, and the second connecting body portion 207 of the first electrode plate E3a may be substantially equal to the lengths of the first pad body portion 301, the first connecting body portion 303, the second pad body portion 305, and the second connecting body portion 307 of the second electrode plate E3b, respectively. In the first and second electrode plates E3a and E3b, the length of the first connecting body portion is equal to the overall length of the first connecting portion, and the length of the second pad body portion is equal to the overall length of the second pad portion. If the first pad portion includes an additional extended electrode, the overall length of the first pad portion is substantially equal to the sum of the length of the first pad body portion and the extended length of the additional extended electrode. If the first pad portion does not include an additional extended electrode, the overall length of the first pad portion is equal to the length of the first pad body portion. If the second connecting portion includes an additional extended electrode, the overall length of the second connecting portion is approximately equal to the sum of the length of the second connecting body portion and the extended length of the additional extended electrode. If the second connecting portion does not include an additional extended electrode, the overall length of the second connecting portion is equal to the length of the second connecting body portion. In some embodiments, the overall length of the first pad portion and the overall length of the second connecting portion of the first electrode plate E3a are also equal to the overall length of the first pad portion and the overall length of the second connecting portion of the adjacent second electrode plate E3b in direction D1. It should be understood that the lengths of the aforementioned components are all measured in direction D2.

[0104] In some embodiments, in each electrode plate, the widths (or interdigital widths) of the plurality of pad extensions and connecting extensions (i.e., the plurality of extended electrodes) in direction D2 and the spacing between adjacent extensions (i.e., the gaps between adjacent finger electrodes) may be substantially the same, and the interdigital widths of the respective finger electrodes and the gaps between adjacent finger electrodes in the first electrode plate E3a may be substantially equal to the interdigital widths of the respective finger electrodes and the gaps between adjacent finger electrodes in the second electrode plate E3b, respectively. In some embodiments, the line width and line spacing of the extended electrodes may be set as small as possible while satisfying process conditions, thereby allowing for the provision of more extended electrodes per unit area and maximizing the capacitance of the interdigital capacitor structure formed by the adjacent electrode plates.

[0105] In some embodiments, as shown in Figures 7A and 7B, the first electrode plate E3a and the second electrode plate E3b may both be symmetrical structures, for example, they may be symmetrical about a center line extending along the direction D2 and passing through the center of their pad body portion and connection body portion.

[0106] In some embodiments, the number of extensions (i.e., finger electrodes) on corresponding portions of the first electrode plate E3a and the second electrode plate E3b may be equal. For example, the number of first pad extensions 202a, the number of first connection extensions 204, the number of second pad extensions 206, and the number of second connection extensions 208a of the first electrode plate E3a may be substantially equal to the number of first pad extensions 302a, the number of first connection extensions 304, the number of second pad extensions 306, and the number of second connection extensions 308a of the second electrode plate E3b, respectively, but the present disclosure is not limited thereto. In some embodiments, the number of additional extensions of the first electrode plate E3a may be the same as or different from the number of additional extensions of the second electrode plate E3b. For example, for a first electrode plate E3a and a second electrode plate E3b that are adjacent in direction D2, the number of additional extensions on one of the two opposite ends of the first electrode plate E3a in direction D2 may differ from the number of additional extensions on one of the two opposite ends of the second electrode plate E3b in direction D2 by one, e.g., one more or one less. For example, the position of the additional extension of the first electrode plate E3a relative to its pad body portion or connecting body portion may differ from the position of the additional extension of the second electrode plate E3b relative to its pad body portion or connecting body portion.

[0107] In some embodiments, in each electrode plate, the number of first pad extensions may be the same as or different from the number of second pad extensions, and the number of first connection extensions may be the same as or different from the number of second connection extensions. The number of first pad extensions may differ from the number of second connection extensions by one, for example, in the example shown, the number of first pad extensions is one more than the number of second connection extensions. The number of first connection extensions may differ from the number of second pad extensions by one, for example, in the example shown, the number of second pad extensions is one more than the number of first connection extensions. However, the present disclosure is not limited thereto.

[0108] 7A and 7B , in some embodiments, the positions of the connection pad and the anti-pad in the first electrode plate and the second electrode plate may be different; for example, in the first electrode plate, the connection pad is provided in the first pad portion, and the anti-pad is provided in the second pad portion; correspondingly, in the second electrode plate, the connection pad is provided in the second pad portion, and the anti-pad is provided in the first pad portion. However, the present disclosure is not limited to this. In an alternative embodiment, in the first electrode plate, the anti-pad may be provided in the first pad portion, and the connection pad is provided in the second pad portion; correspondingly, in the second electrode plate, the connection pad may be provided in the first pad portion, and the anti-pad is provided in the second pad portion.

[0109] 7A and 7B , in some embodiments, the overall shape of each electrode plate may be substantially fishbone-shaped, and the capacitor structure formed by the intersection of multiple electrode plates may be referred to as a fishbone-shaped interdigitated capacitor structure.

[0110] FIG7C is a schematic enlarged plan view showing a fishbone-shaped interdigital capacitor structure formed by first and second electrode plates adjacent to each other crossing each other in the direction D1.

[0111] Referring to FIG. 7C , in some embodiments, for a first electrode plate and a second electrode plate adjacent to each other in direction D1, the first electrode plate E3a and the second electrode plate E3b are inverted relative to each other in direction D2. For example, an end of the first pad portion of each electrode plate away from the first connection portion and an end of the second connection portion away from the second pad portion are referred to as the head and tail of the electrode plates, respectively. The first electrode plate E3a and the second electrode plate E3b being inverted relative to each other in direction D2 means that the orientations of the head and tail of the first electrode plate E3a in direction D2 are opposite to the orientations of the head and tail of the second electrode plate E3b in direction D2, respectively. That is, the orientation of the head of the first electrode plate E3a is the same as the orientation of the tail of the second electrode plate E3b, and the orientation of the tail of the first electrode plate E3b is the same as the orientation of the head of the second electrode plate E3b. For example, using the orientation shown in the figure as an example, the orientation in direction D2 includes the upward or downward direction in the figure.

[0112] For example, the pad portion 210 of the first electrode plate E3a can be arranged relative to the connecting portion 320 of the second electrode plate E3b in the direction D1, and the multiple pad extensions of the first electrode plate E3a and the multiple connection extensions of the second electrode plate E3b overlap and alternate with each other in the direction D2; the connecting portion 220 of the first electrode plate E3a can be arranged relative to the pad portion 310 of the second electrode plate E3b in the direction D1, and the multiple connection extensions of the first electrode plate E3a and the multiple pad extensions of the second electrode plate E3b overlap and alternate with each other in the direction D2. In this article, the relative arrangement of two components of adjacent electrode plates means that the two components have surfaces facing each other and are spaced apart from each other. It should be understood that a dielectric material is provided between each two adjacent electrode plates in the capacitor structure to serve as the electrode plate dielectric layer of the capacitor structure. For example, a dielectric layer (not shown) is also provided between the first electrode plate and the second electrode plate in the same conductive plane, so that the adjacent first electrode plates and the second electrodes are spaced apart from each other and electrically isolated.

[0113] For example, the first pad portion 210a of the first electrode plate E3a and the second connection portion 320b of the second electrode plate E3b are arranged opposite each other in direction D1, and the multiple first pad extensions 202a of the first electrode plate E3a and the multiple second connection extensions 308a of the second electrode plate E3b overlap and are arranged alternately in direction D2. The first connection portion 220a of the first electrode plate E3a and the second pad portion 310b of the second electrode plate E3b are arranged opposite each other in direction D1, and the multiple first connection extensions 204 of the first electrode plate E3a and the multiple second pad extensions 306 of the second electrode plate E3b overlap and are arranged alternately in direction D2. The second pad portion 210b of the first electrode plate E3a and the first connection portion 320a of the second electrode plate E3b are arranged opposite to each other in the direction D1, and the multiple second pad extension portions 206 of the first electrode plate E3a and the multiple first connection extension portions 304 of the second electrode plate E3b overlap in the direction D2 and are arranged alternately with each other; the second connection portion 220b of the first electrode plate E3a and the first pad portion 310a of the second electrode plate E3b are arranged opposite to each other in the direction D1, and the multiple second connection extension portions 208a of the first electrode plate E3a and the multiple first pad extension portions 302a of the second electrode plate E3b overlap in the direction D2 and are arranged alternately with each other.

[0114] That is, the multiple extended electrodes extending in direction D1 of the first electrode plate E3a and the multiple extended electrodes extending in direction D1 of the second electrode plate E3b overlap in direction D2 and are arranged alternately with each other and spaced apart from each other, thereby forming an interdigitated capacitor structure. That is, each extended electrode extending in direction D1 of the first electrode plate E3a is located on the side of the extended electrode of the second electrode plate E3b or in the gap between adjacent extended electrodes in direction D2; and each extended electrode extending in direction D1 of the second electrode plate E3b is located on the side of the extended electrode of the first electrode plate E3a or in the gap between adjacent extended electrodes in direction D2. In this article, the multiple extended electrodes extending in direction D1 of each electrode plate include multiple pad extensions and multiple connecting extensions, and the multiple extended electrodes extending in direction D2 of each electrode plate include multiple additional extensions.

[0115] Continuing with reference to FIG7C , in some embodiments, the line width of each extended electrode, the spacing between adjacent extended electrodes, and the spacing between adjacent electrode plates can be set as small as possible while satisfying process conditions, so that more extended electrodes can be set per unit area and the area facing each other between adjacent electrode plates can be maximized. For example, in the interdigital capacitor structure, the line width w0 of each extended electrode can be greater than or equal to 15 μm, for example, 15 μm; the line spacing s1 between adjacent extended electrodes can be greater than or equal to 15 μm, for example, 15 μm; the spacing between adjacent electrode plates can be greater than or equal to 15 μm, for example, the minimum spacing s2 between adjacent electrode plates in their arrangement direction can be approximately 15 μm. Here, the line width of the extended electrode is the width in the direction perpendicular to its extension direction (for example, direction D2); the line spacing between adjacent extended electrodes is the spacing between adjacent extended electrodes in the interdigital capacitor structure in the direction perpendicular to the extension direction of the extended electrodes (for example, direction D2); the spacing between adjacent electrode plates is the distance between adjacent electrode plates in their arrangement direction (for example, direction D1). It should be understood that in the embodiment shown in FIG4A , each electrode plate is a block electrode with a larger area; whereas in this embodiment, each electrode plate is fishbone-shaped, wherein the connecting main body portion may have a similar finger-like shape to the extension portion, and the pad main body portion is also a block with a smaller area; therefore, the spacing between adjacent electrode plates in this embodiment may adopt process conditions different from those of the embodiment shown in FIG4A , and the spacing between adjacent electrode plates may be set according to the same process rules as the line spacing between adjacent extended electrodes; for example, in the embodiment shown in FIG4A , the spacing S between adjacent electrode plates needs to be greater than or equal to 50 μm, while the spacing between adjacent electrode plates in this embodiment may be set to have a smaller spacing, for example, greater than or equal to 15 μm, based on the process rules for the line spacing between adjacent extended electrodes. In this way, the capacitance between adjacent electrode plates can be further increased by reducing the spacing between adjacent electrode plates.

[0116] In some examples, in the interdigital capacitor structure, the line width w0 of the extended electrode, the line spacing s1, and the minimum spacing s2 between adjacent electrode plates can be set to be approximately equal to each other, but can also be different, and the present disclosure is not limited to this. It should be understood that the above-mentioned size setting of the interdigital capacitor structure is only for illustration, and the present disclosure is not limited to this. For example, at a more advanced process node, the above-mentioned size of the interdigital capacitor structure can be set to be smaller, for example, it can be the minimum size that meets the process conditions, thereby maximizing the facing area between adjacent electrode plates in the interdigital capacitor structure.

[0117] In some embodiments, through the above-mentioned arrangement of the first electrode plate and the second electrode plate, the first electrode plate and the second electrode plate can be cross-arranged with each other to form an interdigitated capacitor structure, and the facing area of ​​the first electrode plate and the second electrode plate can be maximized, which is beneficial to improving the capacitance of the capacitor structure, and further beneficial to reducing the impedance in the circuit of the packaging substrate and the packaging structure including the capacitor structure, reducing power supply noise, and thus improving device performance.

[0118] FIG7D illustrates a schematic enlarged plan view of a plurality of first electrode plates and a plurality of second electrode plates.

[0119] Referring to FIG. 7D , in some embodiments, a plurality of first electrode plates E3a and a plurality of second electrode plates E3b are arranged alternately in both direction D1 and direction D2. That is, in both direction D1 and direction D2, the first electrode plates are immediately adjacent to the second electrode plates, and the second electrode plates are immediately adjacent to the first electrode plates. In the first and second electrode plates adjacent to each other in direction D2, the additional extended electrodes of the first electrode plates and the additional extended electrodes of the second electrode plates are arranged crosswise. That is, the additional extended electrodes of the first electrode plates and the additional extended electrodes of the second electrode plates overlap along direction D1 and are arranged alternately with each other, and are spaced apart from each other, thereby forming an additional interdigital capacitor structure.

[0120] In the first and second electrode plates adjacent to each other in direction D2, one of the head and tail of the first electrode plate is positioned opposite one of the head and tail of the second electrode plate, and the corresponding additional extended electrodes are arranged in a cross-direction. For example, as shown in FIG7D , the head of the first electrode plate E3a and the tail of the second electrode plate E3b may be positioned opposite each other in direction D2, and the additional extended electrodes 202b of the first electrode plate E3a and the additional extended electrodes 308b of the second electrode plate E3b are arranged in a cross-direction. That is, multiple additional extended electrodes 202b and multiple additional extended electrodes 308b overlap in direction D1 and are arranged alternately and spaced apart, thereby forming an interdigital capacitor. However, the present disclosure is not limited to this.

[0121] In alternative embodiments, as shown in FIG6E , in the first and second electrode plates adjacent to each other in direction D2, the head of the first electrode plate may be arranged opposite to the head of the second electrode plate in direction D2, and the additional extended electrode located at the head of the first electrode plate and the additional extended electrode located at the head of the second electrode plate intersect with each other to form an interdigital capacitor; alternatively, the tail of the first electrode plate may be arranged opposite to the tail of the second electrode plate in direction D2, and the additional extended electrode located at the tail of the first electrode plate and the additional extended electrode located at the tail of the second electrode plate intersect with each other to form an interdigital capacitor; alternatively, in other embodiments, the tail of the first electrode plate may be arranged opposite to the head of the second electrode plate in direction D2, and the additional extended electrode located at the tail of the first electrode plate and the additional extended electrode located at the head of the second electrode plate intersect with each other to form an interdigital capacitor. In the various embodiments described above, for the first and second electrode plates adjacent to each other in direction D2, the orientations of the first and second electrode plates are not limited, as long as the additional extended electrodes of the two electrodes can intersect with each other to form an interdigital capacitor.

[0122] In some embodiments, two first electrode plates and two second electrode plates (e.g., the structure shown in FIG. 7D or a similar structure) may constitute an interdigitated capacitor repeating unit Ru, and each conductive plane of the capacitor structure may include one or more of the repeating units. For example, the interdigitated capacitor repeating unit may be extended in direction D1 and / or direction D2, so that each conductive plane may include multiple interdigitated capacitor repeating units arranged in an array along direction D1 and / or direction D2.

[0123] In some embodiments, an interdigital capacitor repeating unit Ru may include a first repeating unit Ru1 and a second repeating unit Ru2. The first repeating unit Ru1 includes a first electrode plate and a second electrode plate arranged in a direction D1 and constituting the interdigital capacitor; the second repeating unit Ru1 includes a second electrode plate and a first electrode plate arranged in a direction D1 and constituting the interdigital capacitor. In other words, the arrangement direction of the first electrode plate and the second electrode plate in the first repeating unit Ru1 is opposite to the arrangement direction of the first electrode plate and the second electrode plate in the second repeating unit Ru2. For example, in the example shown in FIG7D , in the first repeating unit Ru1, the first electrode plate is located to the left of the second electrode plate; while in the second repeating unit Ru2, the first electrode plate is located to the right of the second electrode plate.

[0124] In an example of an array arrangement of multiple repeating units, the multiple repeating units are arranged in rows along direction D1, and the multiple repeating units in the same row can all be of the same type. That is, multiple repeating units Ru1 can be arranged in rows along direction D1, and multiple repeating units Ru2 can be arranged in rows along direction D1. The multiple repeating units are arranged in columns along direction D2, and the first repeating unit Ru1 and the second repeating unit Ru2 are arranged alternately in direction D2; that is, every two adjacent repeating units in direction D2 can be repeating units of different types.

[0125] It should be understood that the number of repeating units included in the conductive planes shown in the figures is for illustrative purposes only and is not intended to limit the present disclosure. For example, each conductive plane of the capacitor structure may include one or more repeating units Ru1, one or more repeating units Ru2, one or more repeating units Ru, or a combination thereof. The number of repeating units Ru1 and Ru2 may be the same or different.

[0126] In some embodiments, among multiple first electrode plates and second electrode plates located in the same conductive plane, for each electrode plate, one or more sides (for example, each side) of the electrode plate facing other electrode plates are provided with extended electrodes (i.e., pad extensions, connection extensions or additional extensions); and for some electrode plates (for example, some electrode plates close to the edge of the capacitor structure), one or more sides of the electrode plate are not adjacent to other electrode plates, that is, they do not face other electrode plates, and extended electrodes may not be provided on the one or more sides of the electrode plate.

[0127] For example, as shown in FIG6B , among the plurality of first electrode plates E3a and the plurality of second electrode plates E3b, each side of each of the first electrode plate E3a and the second electrode plate E3b that are away from the edge of the capacitor structure (for example, located in the middle region) in a direction parallel to the main surface of the conductive plane faces other adjacent electrode plates and is provided with an extended electrode; that is, for each of these electrode plates, in direction D1, a pad extension is provided on the opposite side of the pad main portion, a connection extension is provided on the opposite side of the connection main portion, and in direction D2, additional extensions are also provided at the opposite ends of the electrode plate. However, the first electrode plate E3a0 and the second electrode plate E3b0 that are close to the edge of the capacitor structure in a direction parallel to the main surface of the conductive plane and are away from the other electrode plates may not be provided with an extended electrode on one or more sides.

[0128] For example, for the first electrode plate E3a0 close to the edge of the capacitor structure in the direction D1, a plurality of pad extensions are provided on a side of the pad body portion close to the adjacent second electrode plate in the direction D1 (e.g., the first side), and a plurality of connecting extensions are provided on a side of the connecting body portion close to the adjacent second electrode plate in the direction D1 (e.g., the first side); and no pad extensions and connecting extensions are provided on a side of the pad body portion and the connecting body portion of the first electrode plate E3a0 away from the adjacent second electrode plate (e.g., the second side). The first side and the second side are two sides of the corresponding parts opposite to each other in the direction D1. In some embodiments, the edges of the pad portion and the connecting portion of the first electrode plate E3a0 on a side away from the adjacent second electrode plate E3b in the direction D1 (i.e., the second side of the pad body portion and the connecting body portion) may be substantially aligned with each other in the direction D2.

[0129] Similarly, for the second electrode plate E3b0 near the edge of the capacitor structure in direction D1, multiple pad extensions are provided on a side of the pad body portion near the adjacent first electrode plate (e.g., the first side) in direction D1, and multiple connecting extensions are provided on a side of the connecting body portion near the adjacent first electrode plate (e.g., the first side) in direction D1; and no pad extensions and connecting extensions are provided on a side of the pad body portion and the connecting body portion of the second electrode plate E3b0 away from the adjacent first electrode plate E3a (e.g., the second side). In some embodiments, the edges of the pad portion and the connecting portion of the second electrode plate E3b0 on a side away from the adjacent first electrode plate E3a in direction D1 (i.e., the second side of the pad body portion and the connecting body portion) may be substantially aligned with each other in direction D2. In some embodiments, the edges of the second side of one or more first electrode plates E3a0 and the edges of the second side of one or more second electrode plates E3b0 arranged in the same column in direction D2 and near the edge of the capacitor structure may be aligned with each other in direction D2, but the present disclosure is not limited thereto. In some embodiments, the first electrode plate E3a0 and the second electrode plate E3b0 located at the edges of the capacitor structure may be respectively referred to as a first edge electrode plate and a second edge electrode plate.

[0130] In some embodiments, for a first electrode plate E3a0 located near an edge of the capacitor structure in direction D2, an additional extension portion may be provided on a side of the first electrode plate E3a0 facing the other adjacent second electrode plate E3b (e.g., one of the leading and trailing portions), while no additional extension portion is provided on a side of the first electrode plate E3a0 located away from the adjacent second electrode plate E3b (e.g., the other of the leading and trailing portions). That is, for the first electrode plate E3a0, either the additional extension portion 202b or the additional extension portion 208b may be omitted.

[0131] Similarly, for the second electrode plate E3b0 near the edge of the capacitor structure in the direction D2, the additional extension portion may be provided on the side of the second electrode plate E3b0 facing the other adjacent first electrode plate E3a (e.g., one of the head and tail portions) in the direction D2, while the additional extension portion is not provided on the side of the second electrode plate E3b0 away from the adjacent first electrode plate E3a (e.g., the other of the head and tail portions). That is, for the second electrode plate E3b0, the additional extension portion 302b may be omitted or the additional extension portion 308b may be omitted. It should be understood that if multiple electrode plates located on the same conductive plane are arranged in only one row and multiple electrode plates are not provided in the column direction, then the multiple electrode plates may not be provided with additional extension portions.

[0132] In some embodiments, among one or more first electrode plates E3a0 and one or more second electrode plates E3b0 located in the same row and close to the edge of the capacitor structure, the edges of one or more first electrode plates E3a0 away from other adjacent electrode plates in direction D2 may be roughly aligned in direction D1 with the edges of one or more second electrode plates E3b0 away from other adjacent electrode plates in direction D2, but the present disclosure is not limited to this.

[0133] 6A , in some embodiments, the capacitor structure 500 includes a plurality of conductive planes and a dielectric layer located between adjacent conductive planes, and the conductive planes and the dielectric layer are alternately stacked in direction D3. Direction D3 is perpendicular to the conductive planes and the main surface of the packaging substrate, that is, perpendicular to the plane in which direction D1 and direction D2 are located. Figures 6C and 6D respectively show schematic plan views of other conductive planes 103 and 106 of the capacitor structure 500. The capacitor structure 500 may include a plurality of capacitor stacking structures, for example, including one or more first capacitor stacking structures cs1 and one or more second capacitor stacking structures cs2; each capacitor stacking structure includes a plurality of electrode plates respectively arranged in a plurality of conductive planes and an inter-electrode dielectric layer located between adjacent electrode plates.

[0134] For example, each first capacitor stacking structure cs1 may include a first electrode plate and a second electrode plate alternately stacked in a direction D3 and an inter-electrode dielectric layer located between adjacent electrode plates; each second capacitor stacking structure cs2 may include a second electrode plate and a first electrode plate alternately stacked in a direction D3 and an inter-electrode dielectric layer located between adjacent electrode plates. In a plurality of conductive planes, each conductive plane includes a plurality of electrode plates separated from each other, the plurality of electrode plates including the first electrode plate of the first capacitor stacking structure cs1 and the second electrode plate of the second capacitor stacking structure cs2, or including the second electrode plate of the first capacitor stacking structure cs1 and the first electrode plate of the second capacitor stacking structure cs2. Each dielectric layer is located between adjacent conductive planes to serve as an inter-electrode dielectric layer.

[0135] For example, the multiple conductive planes include one or more first conductive planes and one or more second conductive planes stacked alternately with each other in direction D3, and a dielectric layer is arranged between adjacent conductive planes, each first conductive plane includes a first electrode plate of a first capacitor stack structure and a second electrode plate of a second capacitor stack structure; each second conductive plane includes a second electrode plate of the first capacitor stack structure and a first electrode plate of the second capacitor stack structure.

[0136] For example, a plurality of capacitor stacking structures may be arranged in an array along directions D1 and D2; for example, one or more first capacitor stacking structures cs1 and one or more second capacitor stacking structures cs2 may be arranged alternately in rows along direction D1, and one or more first capacitor stacking structures cs1 and one or more second capacitor stacking structures cs2 may be arranged alternately in columns along direction D2. In each conductive plane, the first electrode plate and the second electrode plate are arranged alternately along direction D1 and / or direction D2, and the arrangement manner and related structural features of the first electrode plate and the second electrode plate are similar to those described above with respect to the first electrode plate E3a and the second electrode plate E3b in the first conductive plane 106, and are not further described here. That is, in any direction in direction D1, direction D2, and direction D3, the first electrode plate and the second electrode plate are arranged alternately.

[0137] Figures 8A and 8B respectively illustrate schematic cross-sectional views of a first capacitor stack structure CS1 and a second capacitor stack structure CS2 in a capacitor structure according to some embodiments of the present disclosure. Figures 8A and 8B are, for example, cross-sectional views taken along line A-A' and line BB' of Figure 6A, respectively. Figures 9A, 9B, and 9C respectively illustrate schematic plan views of electrode plates located on respective conductive planes in a first capacitor stack structure CS1. Figures 10A, 10B, and 10C respectively illustrate schematic plan views of electrode plates located on respective conductive planes in a second capacitor stack structure CS2.

[0138] In some embodiments, the capacitor structure includes a plurality of first conductive planes, and the first capacitor stacking structure and the second capacitor stacking structure respectively include a plurality of first electrode plates and a plurality of second electrode plates located in the plurality of first conductive planes. In the same first capacitor stacking structure, the plurality of first electrode plates located in different first conductive planes can be electrically connected to each other through a first through-hole structure, and the first through-hole structure extends through the second electrode plate located between adjacent first electrode plates in a direction perpendicular to the conductive plane, and is electrically isolated from the second electrode plate. In the same second capacitor stacking structure, the plurality of second electrode plates located in different first conductive planes are electrically connected to each other through a second through-hole structure, and the second through-hole structure extends through the first electrode plate located between adjacent second electrode plates in a direction perpendicular to the conductive plane, and is electrically isolated from the first electrode plate.

[0139] In some embodiments, the capacitor structure includes multiple second conductive planes, and the first capacitor stacking structure and the second capacitor stacking structure respectively include multiple second electrode plates and multiple first electrode plates located in the multiple second conductive planes; in the same first capacitor stacking structure, the multiple second electrode plates located in different second conductive planes can be electrically connected to each other through a third through-hole structure, the third through-hole structure passes through the first electrode plate located between adjacent second electrode plates and is electrically isolated from the first electrode plate; in the same second capacitor stacking structure, the multiple first electrode plates located in different second conductive planes can be electrically connected to each other through a fourth through-hole structure, the fourth through-hole structure passes through the second electrode plate located between adjacent first electrode plates and is electrically isolated from the second electrode plate.

[0140] For example, referring to Figures 6A to 6D and Figures 8A to 10C, the capacitor structure 500 includes a first conductive plane 100, a dielectric layer 101, a second conductive plane 100, a dielectric layer 105, and a first conductive plane 106 stacked sequentially from bottom to top in direction D3, and may include multiple first capacitor stacking structures cs1 and multiple second capacitor stacking structures cs2; each capacitor stacking structure includes multiple electrode plates respectively arranged on the first conductive plane 100, the second conductive plane 100, and the first conductive plane 106, and an electrode plate dielectric layer located between adjacent electrode plates. It should be understood that the number of conductive plane layers shown in the figures is only for illustration and the present disclosure is not limited thereto.

[0141] For example, the first capacitor stack structure cs1 includes a first electrode plate E1a, a second electrode plate E2b, a first electrode plate E3a and an inter-electrode dielectric layer located between adjacent electrode plates; the first electrode plate E1a, the second electrode plate E2b and the first electrode plate E3a can be respectively arranged on the first conductive plane 100, the second conductive plane 100 and the first conductive plane 106; the portion of the dielectric layer 101 located between the first electrode plate E1a and the second electrode plate E2a and the portion of the dielectric layer 105 located between the second electrode plate E2a and the first electrode plate E3a can be respectively used as the inter-electrode dielectric layer of the first capacitor stack structure cs1.

[0142] For example, the second capacitor stack structure cs2 includes a second electrode plate E1b, a first electrode plate E2a, a second electrode plate E3b and an inter-electrode dielectric layer located between adjacent electrode plates; the second electrode plate E1b, the first electrode plate E2a and the second electrode plate E3b can be respectively arranged on the first conductive plane 100, the second conductive plane 103 and the first conductive plane 106; the portion of the dielectric layer 101 located between the second electrode plate E1b and the first electrode plate E2a and the portion of the dielectric layer 105 located between the first electrode plate E2a and the second electrode plate E3b can be respectively used as the inter-electrode dielectric layer of the first capacitor stack structure cs2.

[0143] That is, the first electrode plate E1a of the first capacitor stack structure cs1 and the second electrode plate E1b of the second capacitor stack cs2 are arranged in the same layer on the first conductive plane 100, the second electrode plate E2b of the first capacitor stack structure cs1 and the first electrode plate E2a of the second capacitor stack cs2 are arranged in the same layer on the second conductive plane 100, and the first electrode plate E3a of the first capacitor stack structure cs1 and the second electrode plate E3b of the second capacitor stack cs2 are arranged in the same layer on the first conductive plane 106. In the first conductive planes 100 and 103, each first electrode plate has a planar structure similar to that of the first electrode plate E3a, and each second electrode plate has a planar structure similar to that of the second electrode plate E3b.

[0144] For example, referring to Figures 9A to 9C, in the first capacitor stack structure cs1, the planar structure of the first electrode plate E3a shown in Figure 9A and the planar structure of the first electrode plate E1a shown in Figure 9C are substantially the same as the planar structure of the first electrode plate described above with reference to Figure 7A, and are not described in detail here; the planar structure of the second electrode plate E2b shown in Figure 9B is similar to the planar structure of the second electrode plate E3b described above with reference to Figure 7B, except that the number of the additional extended electrodes 302b and the additional extended electrodes 308b of the second electrode plate E2b can be the same as the number of the additional extended electrodes 202b and the additional extended electrodes 208b of the first electrode plates E3a and E1a. The number of additional extended electrodes 208b is the same, and the position of the additional extended electrodes of the second electrode plate E2b relative to its pad main body or connecting main body can be roughly the same as the position of the additional extended electrodes of the first electrode plates E3a and E1a relative to their pad main body or connecting main body; the additional extended electrodes 302b and 308b of the second electrode plate E2b can overlap with the additional extended electrodes 202b and 208b of the first electrode plates E3a and E1a in the direction D3, respectively, thereby increasing the facing area between the second electrode plate E2b and the first electrode plates E3a and E1a in the direction D3, which is beneficial to improving the capacitance of the capacitor stack structure. However, the present disclosure is not limited to this. In an alternative embodiment, the second electrode plate E2b may also have a structure roughly the same as the second electrode plate E3b.

[0145] In some embodiments, in each first capacitor stacking structure, a plurality of electrode plates may be roughly aligned with each other in a direction perpendicular to the conductive plane or the main surface of the packaging substrate; for example, the outlines of the orthographic projections of the first electrode plate E3a, the second electrode plate E2b, and the third electrode plate E3a on the main surface of the conductive plane or the packaging substrate may at least partially overlap, for example, completely overlap. For example, the orthographic projections of the other parts of the plurality of electrode plates other than the anti-pad on the main surface of the conductive plane may at least partially overlap with each other, for example, completely overlap. In the case where the orthographic projections of the parts of the electrode plates completely overlap, the facing area between the electrode plates in the capacitor stacking structure can be maximized, thereby facilitating an increase in the capacitance of the capacitor stacking structure.

[0146] For example, referring to Figures 10A to 10C, in the second capacitor stack structure cs2, the planar structure of the second electrode plate E3b shown in Figure 10A and the planar structure of the second electrode plate E1b shown in Figure 10C are substantially the same as the planar structure of the second electrode plate described above with reference to Figure 7B, and are not described in detail here; the planar structure of the first electrode plate E2a shown in Figure 10B is similar to the planar structure of the first electrode plate E3a described above with reference to Figure 7A, except that the number of the additional extended electrodes 202b and the additional extended electrodes 208b of the first electrode plate E2a can be the same as the number of the additional extended electrodes 302b and the additional extended electrodes 308b of the second electrode plates E3b and E1b. The number of additional extended electrodes 308b is the same, and the position of the additional extended electrodes of the first electrode plate E2a relative to its pad body or connecting body can be approximately the same as the position of the additional extended electrodes of the second electrode plates E3b and E1b relative to their pad body or connecting body; the additional extended electrodes 202b and 208b of the first electrode plate E2a can overlap and be approximately aligned with the additional extended electrodes 302b and 308b of the second electrode plates E3b and E1b in the direction D3, respectively, thereby increasing the facing area between the first electrode plate E2a and the second electrode plates E3b and E1b in the direction D3, which is beneficial to improving the capacitance of the capacitor stack structure. However, the present disclosure is not limited to this. In an alternative embodiment, the first electrode plate E2a may also have a structure substantially the same as that of the first electrode plate E3b.

[0147] In some embodiments, the outlines of the orthographic projections of the second electrode plate E3b, the first electrode plate E2a, and the third electrode plate E3b on the main surface of the conductive plane may at least partially overlap, for example, completely overlap. For example, the orthographic projections of the other parts of the plurality of electrode plates other than the anti-pad on the main surface of the conductive plane may at least partially overlap with each other, for example, completely overlap. In the case where the orthographic projections of the parts of the electrode plates completely overlap, the facing area between the electrode plates in the capacitor stack structure can be maximized, thereby facilitating an increase in the capacitance of the capacitor stack structure.

[0148] With reference to Figures 8A, 8B, 9A to 9C, and 10A to 10C, in some embodiments, each capacitor stack structure includes a first pad area R1, a first connection area R2, a second pad area R3, and a second connection area R4. In each capacitor stack structure, each electrode plate has a first pad portion, a first connection portion, a second pad portion, and a second connection portion, respectively, located in the first pad area R1, the first connection area R2, the second pad area R3, and the second connection area R4. Each first electrode plate includes a connecting pad located in the first pad portion, an anti-pad located in the second pad portion, and a transition pad electrically isolated from the first electrode plate by the anti-pad. Each second electrode plate includes an anti-pad located in the first pad portion, a transition pad electrically isolated from the second electrode plate by the anti-pad, and a connecting pad located in the second pad portion. However, the present disclosure is not limited thereto.

[0149] In each capacitor stack structure, multiple first electrode plates located in different conductive planes can be electrically connected to each other via a first conductive via structure. The first conductive via structure includes a conductive via located in an inter-electrode dielectric layer and a transition pad located in a conductive plane between the multiple first electrode plates. The first conductive via structure is electrically isolated from a second electrode plate located in the same conductive plane as the transition pad by an anti-pad. For example, the anti-pad is an annular opening that surrounds the transition pad to achieve electrical isolation between the transition pad and the second electrode plate.

[0150] In each capacitor stack structure, multiple second electrode plates located on different conductive planes can be electrically connected to each other via a second conductive via structure. The second conductive via structure includes a conductive via located in an inter-electrode dielectric layer and a transition pad located in a conductive plane between the multiple second electrode plates. The second conductive via structure is electrically isolated from a first electrode plate located in the same conductive plane as the transition pad by an anti-pad. For example, the anti-pad is an annular opening that surrounds the transition pad to achieve electrical isolation between the transition pad and the first electrode plate.

[0151] For example, as shown in Figures 8A and 9A to 9C, in the first capacitor stack structure CS1, the first pad portion, first connection portion, second pad portion, and second connection portion of each of the first electrode plate E1a, the second electrode plate E2b, and the first electrode plate E3a can be aligned in direction D3. The first electrode plate E1a includes a connection pad P1a located in the first pad portion, a transition pad TP1a located in the second pad portion, and an anti-pad AP1a; the transition pad TP1a is electrically isolated from the first electrode plate E1a by the anti-pad AP1a. The second electrode plate E2b includes a transition pad TP2b and an anti-pad AP2b located in the first pad portion, and a connection pad P2b located in the second pad portion; the transition pad TP2b is electrically isolated from the second electrode plate E2b by the anti-pad AP2b. The first electrode plate E3a includes a connection pad P3a located in the first pad portion, a transition pad TP3a ​​located in the second pad portion, and an anti-pad AP3a; the transition pad TP3a ​​is electrically isolated from the first electrode plate E3a by the anti-pad AP3a.

[0152] In some embodiments, the first electrode plate E1a and the first electrode plate E3a located in different conductive planes are electrically connected to each other through a conductive through-hole structure (first conductive through-hole structure) V1; the conductive through-hole structure V1 is located between adjacent first electrode plates in the direction D3, and for example includes a conductive through-hole 101v1 located in the dielectric layer 101, a transition pad TP2b located in the second conductive plane 100, and a conductive through-hole 105v1 located in the dielectric layer 105; the conductive through-holes 101v1, 105v1 and the transition pad TP2b are electrically connected to each other. Conductive via 101v1 is located between transition pad TP2b and connecting pad P1a of first electrode plate E1a in direction D3, providing electrical connection between transition pad TP2b and first electrode plate E1a. Conductive via 105v1 is located between transition pad TP2b and connecting pad P3a of first electrode plate E3a in direction D3, providing electrical connection between transition pad TP2b and first electrode plate E3a. Transition pad TP2b is surrounded by anti-pad AP2b in a direction parallel to the main surface of the conductive plane, thereby electrically isolating it from second electrode plate E2b. Therefore, first electrode plate E1a and first electrode plate E3a are electrically connected to each other via conductive via structure V1, and are electrically isolated from second electrode plate E2b by anti-pad AP2b.

[0153] In the first capacitor stack structure cs1, the second electrode plate E2b located on the second conductive plane 100 can be electrically connected to the second electrode plate located on another conductive plane (not shown) via a conductive via structure (e.g., a second conductive via structure or a third conductive via structure) V2. The second electrode plate on the other conductive plane may include, for example, a second electrode plate located in an adjacent conductive plane above the first electrode plate E3a shown in FIG8A or a second electrode plate located in an adjacent conductive plane below the first electrode plate E1a shown in FIG8A.

[0154] The conductive via structure V2 may include a conductive via 101v2 located in the dielectric layer 101 , a conductive via 105v2 located in the dielectric layer 105 , a transition pad TP1a located in the first conductive plane 100 , and a transition pad TP3a ​​located in the first conductive plane 106 . The connecting pad P2b of the second electrode plate E2b is electrically connected to the transition pad TP3a ​​through the conductive through-hole 105v2, and can be electrically connected to the transition pad TP1a through the conductive through-hole 101v2; the second electrode plate E2b can be electrically connected to the second electrode plate located on other second conductive planes (for example, a second conductive plane above the first conductive plane 106) through the conductive through-hole 105v2 and the transition pad TP3a ​​and the conductive through-hole (not shown) located above the transition pad TP3a; the second electrode plate E2b can be electrically connected to the second electrode plate located on other second conductive planes (for example, a second conductive plane below the first conductive plane 100) through the conductive through-hole 101v2 and the transition pad TP1a and the conductive through-hole (not shown) located below the transition pad TP1a. Transition pad TP1a and transition pad TP3a ​​are respectively surrounded by anti-pad AP1a and anti-pad AP3a in a direction parallel to the main surface of the conductive plane, and are electrically isolated from first electrode plate E1a and first electrode plate E3a by anti-pad AP1a and anti-pad AP3a. Thus, second electrode plate E2b can be further electrically connected to a second electrode plate located on another second conductive plane via conductive via structure V2, and can be electrically isolated from the first electrode plate by the anti-pad located on the first conductive plane.

[0155] For example, as shown in Figures 8B and 10A to 10C, in the second capacitor stack structure CS2, the first pad portion, first connection portion, second pad portion, and second connection portion of each of the second electrode plate E1b, the first electrode plate E2a, and the second electrode plate E3b may be substantially aligned in direction D3. The second electrode plate E1b includes a transition pad TP1b and an anti-pad AP1b located in the first pad portion, and a connection pad P1b located in the second pad portion; the transition pad TP1b is electrically isolated from the second electrode plate E1b by the anti-pad AP1b. The first electrode plate E2a includes a connection pad P2a located in the first pad portion, and a transition pad TP2a and an anti-pad AP2a located in the second pad portion; the transition pad TP2a is electrically isolated from the first electrode plate E2a by the anti-pad AP2a. The second electrode plate E3b includes a transition pad TP3b and an anti-pad AP3b located in the first pad portion and a connection pad P3b located in the second pad portion; the transition pad TP3b is electrically isolated from the second electrode plate E3b by the anti-pad AP3b.

[0156] In some embodiments, the second electrode plate E1b and the second electrode plate E3b located in different conductive planes are electrically connected to each other through a conductive through-hole structure V3 (or referred to as a second conductive through-hole structure); the conductive through-hole structure V3 is located between adjacent second electrode plates in the direction D3, and for example includes a conductive through-hole 101v3 located in the dielectric layer 101, a transition pad TP2a located in the second conductive plane 100, and a conductive through-hole 105v3 located in the dielectric layer 105; the conductive through-holes 101v3, 105v3 and the transition pad TP2a are electrically connected to each other. Conductive via 101v3 is located in direction D3 between transition pad TP2a and connecting pad P1b of second electrode plate E1b, providing electrical connection between them. Conductive via 105v3 is located in direction D3 between transition pad TP2a and connecting pad P3b of second electrode plate E3b, providing electrical connection between them. Transition pad TP2a is surrounded by anti-pad AP2a in a direction parallel to the main surface of the conductive plane, thereby electrically isolating it from first electrode plate E2a. Therefore, second electrode plate E1b and second electrode plate E3b are electrically connected to each other via conductive via structure V3, and are electrically isolated from first electrode plate E2a by anti-pad AP2a.

[0157] In the second capacitor stack structure cs2, the first electrode plate E2a located on the second conductive plane 103 can be electrically connected to the first electrode plate located on another second conductive plane (not shown) via a conductive via structure V4 (also referred to as a first conductive via structure or a fourth conductive via structure). The first electrode plates on the other conductive planes include, for example, the first electrode plate located in an adjacent conductive plane above the second electrode plate E3b shown in FIG8B or the first electrode plate located in an adjacent conductive plane below the second electrode plate E1b shown in FIG8A.

[0158] The conductive via structure V4 may include a conductive via 101v4 located in the dielectric layer 101 , a conductive via 105v4 located in the dielectric layer 105 , a transition pad TP1b located in the first conductive plane 100 , and a transition pad TP3b located in the first conductive plane 106 . The connecting pad P2a of the first electrode plate E2a is electrically connected to the transition pad TP3b through the conductive through-hole 105v4, and can be electrically connected to the transition pad TP1b through the conductive through-hole 101v4; the first electrode plate E2a can be electrically connected to the first electrode plate located on other second conductive planes (for example, a second conductive plane above the first conductive plane 106) through the conductive through-hole 105v4 and the transition pad TP3b and the conductive through-hole (not shown) located above the transition pad TP3b; the first electrode plate E2a can be electrically connected to the first electrode plate located on other second conductive planes (for example, a second conductive plane below the first conductive plane 100) through the conductive through-hole 101v4 and the transition pad TP1b and the conductive through-hole (not shown) located below the transition pad TP1b. Transition pad TP1b and transition pad TP3b are respectively surrounded by anti-pad AP1b and anti-pad AP3b in a direction parallel to the main surface of the conductive plane, and are electrically isolated from second electrode plate E1b and second electrode plate E3b by anti-pad AP1b and anti-pad AP3b. In this way, first electrode plate E2a can be further electrically connected to a first electrode plate located on another second conductive plane via conductive via structure V4, and can be electrically isolated from the second electrode plate by the anti-pad located in the second conductive plane.

[0159] Referring to Figures 6A to 6D, in some embodiments, multiple capacitor stacking structures may be arranged in an array along direction D1 and direction D2, and the conductive through-hole structures in the multiple capacitor stacking structures may also be arranged into an array including multiple rows and columns along direction D1 and direction D2; for example, in multiple capacitor stacking structures arranged in columns in direction D2, multiple conductive through-hole structures may be roughly aligned in direction D2 and also arranged in columns. Among the multiple capacitor stacking structures located in the same row in direction D1, the conductive through-hole structures (or pad portions) of two adjacent capacitor stacking structures (i.e., the first capacitor stacking structure and the second capacitor stacking structure) are not aligned in direction D1, but are offset from each other in direction D2; in some embodiments, among the multiple capacitor stacking structures located in the same row in direction D1, the conductive through-hole structures (or pad portions) of the multiple first capacitor stacking structures can be roughly aligned in direction D1 and can be arranged in rows, and the conductive through-hole structures (or pad portions) of the multiple second capacitor stacking structures can be roughly aligned in direction D1 and can be arranged in rows, while the conductive through-hole structures (or pad portions) of the first capacitor stacking structure and the second capacitor stacking structure are not aligned in direction D1, but are staggered from each other in direction D2.

[0160] It should be understood that the number of conductive planes of the capacitor structure shown in the figures of the various embodiments of the present disclosure (e.g., 6A and 6E) is for illustrative purposes only, and the present disclosure is not limited thereto; when the capacitor structure includes more conductive planes, each conductive through-hole structure may include more conductive through-holes and / or transition pads, and anti-pads may be provided based on the connection requirements between the electrode plates. Anti-pads and transition pads may not be provided in the conductive planes at both ends (e.g., the topmost conductive plane or the bottommost conductive plane) in the stacking direction (e.g., direction D3) of the conductive planes of the capacitor structure.

[0161] In the capacitor structure 500, each capacitor stack structure includes a plurality of electrode plates stacked in a direction D3 (e.g., a vertical direction), thereby forming a capacitor structure in the vertical direction; in a direction parallel to the main surface of the conductive plane, adjacent electrode plates are arranged to cross each other to form an interdigitated capacitor structure, and by improving the structure of the electrode plates, for example, by arranging the electrode plates into a fishbone shape, the range and size of the interdigitated electrodes can be further increased, thereby further increasing (e.g., maximizing) the facing area between adjacent electrode plates, and further increasing the capacitance of the capacitor structure. By increasing the capacitance of the capacitor structure, the impedance of the package substrate including the capacitor structure and the circuit in which it is located in the package structure can be reduced, thereby reducing power supply noise and improving device performance.

[0162] With reference to Figures 1 and 6A, in some embodiments, the multiple conductive planes of the capacitor structure 500 may be conductive planes arranged in one or more of the core layer 31, the stacking layer 32a, and the stacking layer 32b of the packaging substrate, and may be composed of conductive planes such as power planes and / or ground planes located in the corresponding layers. For example, the multiple first electrode plates in the capacitor structure 500 are multiple power planes, and the multiple second electrode plates are multiple ground planes; or, the multiple first electrode plates are multiple ground planes, and the multiple second electrode plates are multiple power planes; or, the first electrode plates and the second electrode plates may be power planes providing different power supply voltages. In some embodiments, the multiple first electrode plates in the same capacitor stacking structure may be connected to the same network (net), and the multiple second electrode plates in the same capacitor stacking structure may be connected to the same network (net). The multiple first electrode plates in different capacitor stacking structures may be connected to the same or different networks, and the multiple second electrode plates in different capacitor stacking structures may be connected to the same or different networks. In some embodiments, the first electrode plate and the second electrode plate included in each conductive plane in the capacitor structure may be referred to as the first conductive sub-plane and the second conductive sub-plane, respectively. Each conductive sub-plane may be a power plane or a ground plane, etc. It should be understood that the present disclosure does not limit the type of each electrode plate in the conductive plane, as long as the conductive planes are arranged to form the capacitor structure, thereby reducing the impedance in the package structure circuit, reducing power supply noise, and improving device performance.

[0163] In some embodiments, one or more conductive planes of the capacitor structure are respectively located in one or more conductive layers of the package substrate. In one or more of the conductive layers where the conductive planes of the capacitor structure are located, in addition to the conductive planes of the capacitor structure (e.g., power plane, ground plane, etc.), conductive lines may also be included, such as conductive lines for transmitting other electrical signals. The conductive lines and the conductive planes of the capacitor structure are located in the same conductive layer. The conductive lines may be located on the side of the conductive plane in a direction parallel to the main surface of the package substrate, and at least part of the conductive lines and the capacitor structure may be formed by the same patterning process. In some embodiments, the electrode plates arranged in the same layer in the conductive lines and the capacitor structure may have approximately the same thickness. In other embodiments, the thickness of the electrode plates (i.e., the first electrode plate and the second electrode plate) in the capacitor structure may be set to be greater than the thickness of other conductive lines arranged in the same layer, so that it can be beneficial to further increase the facing area between adjacent electrode plates (e.g., power plane and ground plane) in a direction parallel to the main surface of the package substrate, thereby increasing the parasitic capacitance between the power plane and the ground plane, thereby reducing the impedance in the circuit of the package substrate and the package structure including it, so as to reduce power supply noise and improve device performance. Herein, two components being “disposed on the same layer” may include at least portions of the two components being formed by the same patterning process.

[0164] Figure 11 schematically illustrates a schematic cross-sectional view of a package substrate according to some embodiments of the present disclosure. For simplicity, Figure 11 only shows the top conductive layer and solder resist layer of the package substrate, and the components located below the top conductive layer are not specifically shown, but are simply shown as bottom components 30a.

[0165] For example, the packaging substrate 30 includes a conductive layer M, which may be located close to the surface of the packaging substrate in direction D3. The conductive layer M may include a conductive circuit CL and a conductive plane of the capacitor structure 500, and the conductive plane may include multiple electrode plates; the conductive layer M is, for example, close to the solder resist layer 33 of the packaging substrate 30, and the solder resist layer 33 may cover at least a portion of the conductive layer M.

[0166] For example, in the conductive layer M, the conductive plane of the capacitor structure 500 may include one or more first electrode plates Ea and one or more second electrode plates Eb. It should be understood that the planar structure and arrangement of the first electrode plates Ea and the second electrode plates Eb are similar to those described above for the first and second electrode plates in the conductive planes 100, 103, and 106, and are not further described here. For the sake of simplicity, FIG11 schematically illustrates only one first electrode plate Ea, one second electrode plate Eb, and portions of the conductive traces located on the sides of the electrode plates.

[0167] Referring to Figure 11, in some embodiments, the sidewalls of the conductive layer M and its surface away from the bottom structure 30a are covered by a solder resist layer 33. In the conductive layer M, the conductive trace CL may be arranged side by side with the first electrode plate Ea and the second electrode plate Eb. In some embodiments, the thickness of the first electrode plate and the second electrode plate in the conductive plane of the capacitor structure in a direction perpendicular to the main surface of the package substrate is greater than the thickness of the conductive trace in said direction. For example, the first electrode plate Ea and the second electrode plate Eb may have a thickness t2 that is substantially the same as each other, and the thickness t2 is greater than the thickness t1 of the conductive trace CL. In this document, the thickness of the conductive trace and the electrode plate refers to their thickness in a direction perpendicular to the main surface of the package substrate (e.g., direction D3). That is, the first electrode plate Ea and the second electrode plate Eb may protrude from the surface of the conductive trace CL covered by the solder resist layer 33 in a direction perpendicular to the main surface of the package substrate (e.g., the top surface shown in the figure). In some embodiments, the conductive plane of the capacitor structure located in the conductive layer M may be a conductive plane located at the end (e.g., top or bottom) of the capacitor structure in direction D3.

[0168] For example, each of the first electrode plate Ea and the second electrode plate Eb includes a main body 1 and a protrusion 2; the protrusion 2 is located on a side of the main body 1 away from the bottom structure (e.g., the core layer) in a direction perpendicular to the main surface of the package substrate; the thickness of the main body 1 may be approximately the same as the thickness t1 of the conductive line CL, and the protrusion 2 may protrude from the surface of the conductive line CL away from the bottom structure 30a (e.g., the core layer) in a direction perpendicular to the main surface of the package substrate. In some embodiments, in each electrode plate, the main body 1 and the protrusion 2 may be approximately aligned with each other in a direction perpendicular to the main surface of the package substrate, for example, the opposite side walls of the main body 1 in a direction parallel to the main surface of the package substrate may be approximately aligned with the opposite side walls of the protrusion 2 in a direction parallel to the main surface of the package substrate. The orthographic projection of the main body 1 on the main surface of the package substrate and the orthographic projection of the protrusion 2 on the main surface of the package substrate overlap with each other, for example, completely overlap. In some embodiments, the main body 1 and the protrusion 2 may include the same material, or may include different materials. In some examples, there may be an interface between the main body 1 and the protruding portion 2, but the present disclosure is not limited thereto. In other examples, there may not be a clear interface between the main body 1 and the protruding portion 2.

[0169] 12A to 12F are schematic cross-sectional views illustrating steps of a method for forming a conductive layer M in a package substrate according to some embodiments of the present disclosure.

[0170] In some embodiments, a method for forming a packaging substrate includes: forming a conductive material layer, and patterning the conductive material layer to form a conductive circuit and an initial conductive plane including a first initial electrode plate and a second initial electrode plate; and performing a thickening process on the initial conductive plane to form a conductive plane, wherein the thickening process includes forming additional conductive material on the first initial electrode plate and the second initial electrode plate to form thickened first and second electrode plates. In some embodiments, the thickening process further includes: before forming the additional conductive material, forming a patterned mask layer on the conductive material layer, wherein the patterned mask layer covers the conductive circuit and has multiple openings to expose the first and second initial electrode plates; wherein the additional conductive material is formed on the first and second initial electrode plates exposed by the multiple openings of the patterned mask layer.

[0171] Referring to FIG. 12A , for example, an initial conductive layer M' is formed on the bottom structure 30a. The initial conductive layer M' includes a conductive line CL, a first initial electrode plate Ea', and a second initial electrode plate Eb'. For example, one or more first initial electrode plates Ea' and one or more initial electrode plates Eb' constitute an initial conductive plane of the capacitor structure. A method for forming the initial conductive layer M' may include: forming a conductive material layer on the bottom structure 30a. The conductive material layer may include, for example, a metal material such as copper, titanium, nickel, or a combination thereof; patterning the conductive material layer to form a conductive line CL and an initial conductive plane including the first initial electrode plate Ea' and the second initial electrode plate Eb'; the patterning process may include photolithography and etching processes.

[0172] 12B and 12C , a mask layer 90 is formed on the bottom structure 30a to cover the initial conductive layer M'. The mask layer 90 may include a photoresist. Next, the mask layer 90 is patterned to form a plurality of openings 90a in the mask layer 90; the shapes and positions of the plurality of openings 90a may correspond to the shapes and positions of the initial electrode plates Ea' and Eb', so that the plurality of openings 90a expose the surface of the initial electrode plates Ea' and Ea' away from the bottom structure 30a. For example, the patterning process of the mask layer 90 may include a photolithography process or a laser direct imaging process, which removes the portion of the mask layer 90 overlying the initial electrode plates Ea' and Eb'. The photolithography process may include exposure (e.g., contact exposure, proximity exposure, etc.) and a development process. The openings 90a of the mask layer 90 may only expose the surfaces of the electrode plates Ea' and Eb' without exposing the surface of the conductive line CL. That is, after the mask layer 90 is patterned, the sidewalls of the conductive circuit CL and the surface thereof away from the bottom structure 30 a are still covered by the mask layer 90 and are not exposed.

[0173] Referring to Figures 12C and 12D , additional conductive material is formed on the initial electrode plates Ea' and Eb' exposed by the opening 90a of the mask layer 90 to form first and second electrode plates Ea and Eb, thereby increasing the thickness of the electrode plates. The resulting thickened first and second electrode plates Ea and Eb constitute the conductive plane of the capacitor structure, and the conductive plane and conductive traces CL constitute the conductive layer M. Referring to Figure 12E , the mask layer 90 is then removed. In some embodiments, the process illustrated in Figures 12B to 12E may be referred to as a process for thickening the initial conductive plane.

[0174] 12D to 12F , after the mask layer 90 is removed, a solder resist layer 33 may be formed on the conductive layer M to cover the conductive traces CL and the plurality of electrode plates Ea and Eb.

[0175] In the above embodiment, the solder resist layer 33 is formed after the thickening process of the electrode plate, but the present disclosure is not limited to this. In an alternative embodiment, the thickening process of the initial conductive plane can also be performed after the solder resist layer 33 is formed, and the solder resist layer 33 can be used as a mask layer for the thickening process.

[0176] 13A to 13D are schematic cross-sectional views illustrating a process of thickening an initial conductive plane in a method of forming a package substrate according to other embodiments of the present disclosure.

[0177] 13A , an initial conductive layer M′ including a conductive line CL, a first initial electrode plate Ea′ and a second initial electrode plate Eb′ is formed on the bottom structure 30 a . The method of forming the initial conductive layer M′ is similar to that described in FIG. 12A and will not be repeated here.

[0178] 13B, a solder resist layer 33 is formed on the bottom structure 30a to cover the sidewalls of the various members in the initial conductive layer M' and the surface thereof away from the bottom structure 30a.

[0179] 13C , the solder resist layer 33 is patterned to form a plurality of openings 33o in the solder resist layer 33 to expose the surfaces of the plurality of initial electrode plates Ea' and Eb' on a side away from the base structure 30a. In some embodiments, the shapes and positions of the plurality of openings 33o correspond to, for example, completely correspond to, the shapes and positions of the plurality of initial electrode plates Ea' and Eb' in the initial conductive plane, so that the surfaces of the plurality of initial electrode plates Ea' and Eb' on a side away from the base structure 30a can be completely exposed by the plurality of openings 33o.

[0180] 13C and 13D , additional conductive material is formed on the first and second preliminary electrode plates Ea' and Eb' exposed through the plurality of openings 33o in the solder resist layer 33 to form thickened first and second electrode plates Ea and Eb. The surfaces of the first and second electrode plates Ea and Eb on the side away from the bottom structure 30a may be lower than the surface of the solder resist layer 33 away from the bottom structure 30a. Alternatively, the surfaces of the first and second electrode plates Ea and Eb away from the bottom structure 30a may be flush with the surface of the solder resist layer 33 away from the bottom structure 30a in a direction parallel to the main surface of the package substrate. However, the present disclosure is not limited thereto.

[0181] 13D and 13E , in some embodiments, after the thickening process of the electrode plate is completed, an additional solder resist layer 33p may be formed on the side of the electrode plate away from the bottom structure 30a to cover the surface of the first electrode plate Ea and the second electrode plate Eb away from the bottom structure 30a. In other embodiments, the step shown in FIG. 13E may be omitted, so that in the formed packaging substrate, the surface of the first electrode plate Ea and the second electrode plate Eb away from the bottom structure 30a may not be covered by the solder resist layer 33, but may be exposed in the opening of the solder resist layer 33.

[0182] The solder resist layer in the method shown in Figures 12A to 13E may be the solder resist layer 33a or the solder resist layer 33b in the package substrate shown in Figure 1, that is, the conductive layer with a thickened conductive plane in the package substrate may be arranged on a side of the package substrate close to the chip 20, or may be arranged on a side of the package substrate relatively far away from the chip 20. However, the present disclosure is not limited to this. In other examples, the conductive layer with a thickened conductive plane may also be arranged in the package substrate close to the core layer or any other suitable position. When the capacitor structure has multiple conductive planes, one or more conductive planes among the multiple conductive planes can be formed by the above-mentioned thickening process to have a larger thickness than the conductive circuit of the same layer, or, the conductive plane located near the surface layer of the package substrate (i.e., close to the solder resist layer) among the multiple conductive planes is formed to have a larger thickness than the conductive circuit of the same layer.

[0183] In this embodiment, the conductive plane is thickened so that the first electrode plate and the second electrode plate in the conductive plane have a greater thickness. This can further increase the facing area of ​​adjacent electrode plates in the same conductive plane in a direction parallel to the main surface of the packaging substrate (horizontal direction), thereby further increasing the capacitance of the capacitor structure, which is beneficial to reducing the impedance in the circuit where the capacitor structure is located, thereby reducing power supply noise and improving device performance.

[0184] In some embodiments, the improvement in capacitance achieved by the capacitor structure of the disclosed embodiments can be verified through simulation tests.

[0185] For example, take the capacitor structure shown in Figure 3A and the capacitor structure shown in Figure 6A as examples. Take the capacitor structure of Figure 3A as a three-layer structure, which is a ground plane, a power plane, and a ground plane from bottom to top, and the area of ​​each layer is 1mm×1mm. For example, the conductive through-hole diameter is 60μm, the conductive pad diameter is 100μm, the anti-pad diameter is 160μm, and the spacing between adjacent conductive through-holes in the direction parallel to the main surface of the package substrate is 250μm. In the example capacitor structure of Figure 6A, the relevant dimensions are the same as those of the example capacitor structure of Figure 3A above; the simulation results show that the unit area capacitance of the example capacitor structure shown in Figure 3A is 1.855pF / mm 2, the unit area of ​​the exemplary capacitor structure shown in FIG6A is 3.26 pF / mm 2 Therefore, in the above example, it can be seen from the simulation results that, compared with the traditional parallel plate capacitor structure, the capacitance of the fishbone-shaped interdigital capacitor structure of the embodiment of the present disclosure is increased by 75.7%.

[0186] 14A and 14B show an application example of using the electrode plate structure of the embodiment of the present disclosure on the power plane and the ground plane of the package substrate. The technical effects of the embodiment of the present disclosure are described below based on actual application examples.

[0187] Referring to Figures 14A and 14B , for example, the package substrate includes a power plane Ea and a ground plane Eb. Power plane Ea is, for example, the power plane for the phase-locked loop power supply pll_VDDHV, and ground plane Eb is, for example, the ground plane VSS. Power plane Ea and ground plane Eb are positioned opposite each other in a direction parallel to the main surface of the package substrate. Figure 14A illustrates the planar structure and relative positional relationship of a conventional power plane and ground plane in a comparative example. Figure 14B illustrates an enlarged view of the planar structure of the power plane and ground plane according to an embodiment of the present disclosure.

[0188] The embodiment of FIG14B improves the structure of the power plane Ea and the ground plane Eb based on the comparative example shown in FIG14A , so that the power plane Ea and the ground plane Eb form the fishbone-shaped interdigital capacitor structure described above with reference to capacitor structure 500. For the sake of simplicity, FIG14B only shows the portion of the interdigital capacitor structure formed by the power plane Ea and the ground plane Eb. The specific structural features of the fishbone-shaped interdigital capacitor structure formed by the power plane Ea and the ground plane Eb are similar to those of the fishbone-shaped interdigital capacitor structure formed by adjacent electrode plates in capacitor structure 500 described above and are not further described here.

[0189] In some examples, calculations show that improving the power plane Ea and the ground plane Eb shown in FIG. 14A to the fishbone capacitor structure shown in FIG. 14B can increase the parasitic capacitance between the power plane Ea and the ground plane Eb by 5 pF.

[0190] The power supply noise in the above comparative example and the embodiment can be compared by simulation testing. For example, a circuit is built to perform a power supply noise simulation test on the power supply pll_VDDHV of the power plane Ea, such as an AC noise simulation test. Figures 15A and 15B show the system circuit for the test, wherein VRM_VDDHV is an ideal voltage source, L is the estimated inductance on the package substrate, PKG is the package model (S parameter) of pll_VDDHV, R and C are the parasitic resistance and parasitic capacitance in the chip connected to the package substrate, IC_VDDHV is the CPM model of the phase-locked loop power supply, and C1 is the 5pF capacitance added to the improved power plane Ea and ground plane Eb compared to the traditional structure. The circuit of Figure 15A corresponds to the comparative example of Figure 14A in which the package substrate uses a traditional power plane and ground plane structure; the circuit of Figure 15B corresponds to the embodiment of Figure 14B in which the package substrate uses a power plane and ground plane with a fishbone-shaped interdigitated capacitor structure, that is, capacitor C1 is added.

[0191] The power supply noise of the phase-locked loop power supply pll_VDDHV in the conventional package substrate and the package substrate of the embodiment of the present disclosure is compared through the circuit simulation of Figures 15A and 15B. Figures 16A and 16B respectively show the simulation results of the test circuits of Figures 15A and 15B.

[0192] As shown in Figure 16A, the test results corresponding to the traditional packaging substrate show that its peak-to-peak voltage (Voltage Peak-Peak, VPP) is 7.829mV; as shown in Figure 16B, the test results corresponding to the packaging substrate of the embodiment of the present disclosure show that its VPP is 6.941mV. In other words, by adopting the power plane and ground plane with a fishbone-shaped interdigitated capacitor structure, VPP is reduced, that is, the voltage drop is reduced and the power supply noise is reduced. In this example, the 5pF parasitic capacitance added by the power plane and ground plane can bring an 11.34% optimization to the power supply pll_VDDHV in terms of AC noise. Therefore, the use of the power plane and ground plane with a fishbone-shaped interdigitated capacitor structure according to the embodiment of the present disclosure can effectively reduce power supply noise.

[0193] In the embodiment of the present disclosure, by optimizing the structure of the electrode plates in the capacitor structure and the arrangement of adjacent electrode plates, the capacitance per unit area of ​​the capacitor structure can be maximized; in the example of application to the packaging substrate, by forming the power plane, ground plane, etc. into the capacitor structure of the embodiment of the present disclosure, the parasitic capacitance between conductive planes such as the power plane and ground plane can be greatly improved, which is beneficial to the impedance in the circuit of the packaging substrate and the packaging structure, and is beneficial to reducing power supply noise and improving device performance.

[0194] It should be understood that, in addition to being applied to the power plane and ground plane in the package substrate, the capacitor structure disclosed herein can also be applied to any other electronic device based on product requirements to enhance the capacitance of the capacitor structure.

[0195] There are a few points to note:

[0196] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0197] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0198] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A capacitor structure comprising: At least one conductive plane, each conductive plane comprising a plurality of electrode plates, the plurality of electrode plates being arranged side by side and spaced apart from each other in a direction parallel to a major surface of the conductive plane, wherein each electrode plate comprises: a pad portion, comprising a pad body portion and a plurality of pad extension portions connected to each other, wherein the plurality of pad extension portions are arranged at sides of the pad body portion in a first direction parallel to a main surface of the conductive plane; and A connecting portion, comprising a connecting main body portion and a plurality of connecting extension portions connected to each other, wherein the plurality of connecting extension portions are arranged at sides of the connecting main body portion in the first direction, and the plurality of pad extension portions and the plurality of connecting extension portions constitute a plurality of extended electrodes; The pad body portion and the connecting body portion are arranged along a second direction and connected to each other, the second direction intersects the first direction, and the width of the pad body portion in the first direction is greater than the width of the connecting body portion in the first direction; The plurality of pad extensions and the plurality of connection extensions extend along the first direction and are arranged along the second direction at intervals from each other; Wherein in each conductive plane, the multiple electrode plates include a first electrode plate and a second electrode plate adjacent to each other in the first direction, the first electrode plate and the second electrode plate are opposite to each other and arranged at intervals in the first direction, and the multiple extended electrodes of the first electrode plate and the multiple extended electrodes of the second electrode plate overlap in the second direction and are arranged alternately with each other to form an interdigitated capacitor structure. 2 . The capacitor structure according to claim 1 , wherein an extension length of at least some of the plurality of pad extensions in the first direction is the same as an extension length of the plurality of connection extensions in the first direction. 3 . The capacitor structure according to claim 1 , wherein an overall width of the pad portion in the first direction is greater than an overall width of the connecting portion in the first direction.

4. The capacitor structure according to any one of claims 1 to 3, wherein The pad portion of the first electrode plate and the connecting portion of the second electrode plate are arranged opposite to each other in the first direction, and a plurality of pad extension portions of the first electrode plate and a plurality of connecting extension portions of the second electrode plate overlap and are alternately arranged with each other in the second direction; The connection portion of the first electrode plate and the pad portion of the second electrode plate are arranged opposite to each other in the first direction, and the plurality of connection extension portions of the first electrode plate and the plurality of pad extension portions of the second electrode plate overlap and are alternately arranged with each other in the second direction.

5. The capacitor structure according to any one of claims 1 to 4, wherein in each electrode plate, The pad portion includes a first pad portion and a second pad portion, the first pad portion and the second pad portion include a first pad body portion and a second pad body portion respectively, and the plurality of pad extension portions include a plurality of first pad extension portions and a plurality of second pad extension portions, which are respectively connected to the first pad body portion and the second pad body portion; The connecting part includes a first connecting part and a second connecting part, the first connecting part and the second connecting part respectively include a first connecting main body part and a second connecting main body part, and the multiple connecting extension parts include multiple first connecting extension parts and multiple second connecting extension parts, which are respectively connected to the first connecting main body part and the second connecting main body part. 6 . The capacitor structure according to claim 5 , wherein in the second direction, the first connection portion is located between the first pad portion and the second pad portion, and the second connection portion is located on a side of the second pad portion away from the first connection portion.

7. The capacitor structure according to claim 5, wherein the first electrode plate and the second electrode plate are inverted relative to each other in the second direction, so that the first pad portion, the first connecting portion, the second pad portion, and the second connecting portion of the first electrode plate are respectively arranged relative to the second connecting portion, the second pad portion, the first connecting portion, and the first pad portion of the second electrode plate in a direction parallel to the main surface of the conductive plane.

8. The capacitor structure according to any one of claims 1 to 7, wherein the plurality of electrode plates include a plurality of first electrode plates and a plurality of second electrode plates, and the plurality of first electrode plates and the plurality of second electrode plates are alternately arranged in at least one of the first direction and the second direction.

9. The capacitor structure according to claim 8, wherein the plurality of first electrode plates and the plurality of second electrode plates further comprise a first electrode plate and a second electrode plate adjacent to each other in the second direction; The first electrode plate further comprises a plurality of first additional extension electrodes, which are arranged on a side of the first electrode plate facing the second electrode plate; The second electrode plate further comprises a plurality of second additional extended electrodes, which are arranged on a side of the second electrode plate facing the first electrode plate; The plurality of first additional extending electrodes and the plurality of second additional extending electrodes overlap in the first direction and are alternately arranged with each other to form an additional interdigital capacitor structure.

10. The capacitor structure according to any one of claims 1 to 9, comprising a plurality of conductive planes stacked in a third direction perpendicular to the main surfaces of the plurality of electrode plates and a dielectric layer located between adjacent conductive planes, and comprising: A first capacitor stack structure includes first electrode plates and second electrode plates alternately stacked in the third direction; as well as The second capacitor stack structure comprises alternately stacking the second electrode plates and the first electrode plates in the third direction, The first capacitor stack structure and the second capacitor stack structure are alternately arranged along at least one of the first direction and the second direction.

11. The capacitor structure according to claim 10, wherein the plurality of conductive planes include at least one first conductive plane and at least one second conductive plane alternately stacked with each other in the third direction; Each first conductive plane includes a first electrode plate of the first capacitor stack structure and a second electrode plate of the second capacitor stack structure; Each second conductive plane includes a second electrode plate of the first capacitor stack structure and a first electrode plate of the second capacitor stack structure.

12. The capacitor structure according to claim 11, wherein the at least one first conductive plane comprises a plurality of first conductive planes, and the first capacitor stack structure and the second capacitor stack structure respectively comprise a plurality of first electrode plates and a plurality of second electrode plates located on the plurality of first conductive planes; In the first capacitor stack structure, the plurality of first electrode plates are electrically connected to each other through a first conductive through-hole structure, and the first conductive through-hole structure passes through a second electrode plate located between adjacent first electrode plates and is electrically isolated from the second electrode plate; In the second capacitor stack structure, the plurality of second electrode plates are electrically connected to each other via a second conductive through-hole structure, and the second conductive through-hole structure passes through a first electrode plate between adjacent second electrode plates and is electrically isolated from the first electrode plate.

13. The capacitor structure according to claim 11, wherein the at least one second conductive plane comprises a plurality of second conductive planes, and the first capacitor stack structure and the second capacitor stack structure respectively comprise a plurality of second electrode plates and a plurality of first electrode plates located on the plurality of second conductive planes; In the first capacitor stack structure, the plurality of second electrode plates are electrically connected to each other through a third conductive through-hole structure, and the third through-hole structure passes through a first electrode plate between adjacent second electrode plates and is electrically isolated from the first electrode plate; In the second capacitor stack structure, the plurality of first electrode plates are electrically connected to each other via a fourth through-hole structure, and the fourth through-hole structure passes through a second electrode plate between adjacent first electrode plates and is electrically isolated from the second electrode plate.

14. A packaging substrate comprising the capacitor structure according to any one of claims 1-13. 15 . The packaging substrate according to claim 14 , wherein among the plurality of electrode plates in each conductive plane, one of the first electrode plate and the second electrode plate is a power plane, and the other of the first electrode plate and the second electrode plate is a ground plane.

16. The packaging substrate according to claim 14 or 15, wherein At least one conductive plane of the capacitor structure is respectively arranged in at least one conductive layer of the packaging substrate, and one of the at least one conductive layer includes a conductive circuit and the conductive plane of the capacitor structure, and the conductive circuit is located on the side of the conductive plane in a direction parallel to the main surface of the packaging substrate; The thickness of the first electrode plate and the second electrode plate in the conductive plane in a third direction perpendicular to the main surface of the packaging substrate is greater than the thickness of the conductive line in the third direction. 17 . The package substrate according to claim 16 , further comprising a solder resist layer covering the one of the at least one conductive layer.

18. A method for forming a packaging substrate according to claim 16, comprising: Forming a conductive material layer, and performing a patterning process on the conductive material layer to form the conductive circuit and an initial conductive plane including a first initial electrode plate and a second initial electrode plate; as well as The initial conductive plane is subjected to a thickening process to form the conductive plane, wherein the thickening process includes forming additional conductive material on the first initial electrode plate and the second initial electrode plate to form thickened first electrode plate and second electrode plate.

19. The method for forming a package substrate according to claim 18, wherein the thickening process further comprises: Before forming the additional conductive material, a mask layer is formed on the conductive material layer, wherein the mask layer covers the conductive line and has a plurality of openings to expose the first initial electrode plate. and the second initial electrode plate; The additional conductive material is formed on the first preliminary electrode plate and the second preliminary electrode plate exposed by the plurality of openings of the mask layer.

20. A packaging structure, comprising the packaging substrate according to any one of claims 14 to 17; and The chip is electrically connected to the packaging substrate.

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