Semiconductor packaging structure, semiconductor power module, electronic device, and vehicle

Abstract

Disclosed are a vehicle, an electronic device, and a semiconductor power module, each comprising a semiconductor packaging structure. The semiconductor packaging structure comprises a substrate, at least one semiconductor power chip, and a source power terminal. The semiconductor power chip is arranged on the substrate, and the semiconductor power chip is provided with a source electrode.The source power terminal is arranged on a top surface of the semiconductor power chip and is electrically connected with the source electrode, and the source power terminal extends in the thickness direction of the semiconductor packaging structure and is vertically led out.

Description

Semiconductor packaging structure, semiconductor power module, electronic equipment and vehicle

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application with application number 202311269440.2, entitled “Semiconductor packaging structure, electronic device and vehicle”, filed with the State Intellectual Property Office of China on September 27, 2023, the Chinese patent application with application number 202322648112.5, entitled “Semiconductor packaging structure, electronic device and vehicle”, filed with the State Intellectual Property Office of China on September 27, 2023, the Chinese patent application with application number 202311264888.5, entitled “Semiconductor packaging structure, semiconductor module and vehicle”, and the Chinese patent application with application number 202322676957.5, entitled “Semiconductor packaging structure, semiconductor power module and device”, filed with the State Intellectual Property Office of China on September 27, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application belongs to the technical field of power semiconductor devices. Specifically, the present application relates to a semiconductor packaging structure, a semiconductor power module, an electronic device and a vehicle. Background Art

[0004] Power semiconductor devices are devices that convert electrical energy. However, current packaging structures have limited current flow capacity, and insulation and heat dissipation rely on external thermal interface materials, resulting in high thermal resistance, which limits their application in higher-power applications.

[0005] Public content

[0006] The purpose of this application is to provide a new technical solution for a semiconductor packaging structure, a semiconductor power module, an electronic device and a vehicle.

[0007] According to the semiconductor packaging structure of the embodiment of the first aspect of the present application, it is characterized in that it includes: a substrate; at least one semiconductor power chip, the semiconductor power chip is arranged on the substrate, and the semiconductor power chip has a source; and a source power terminal, the source power terminal is arranged on the top surface of the semiconductor power chip and forms an electrical connection with the source, and the source power terminal extends along the thickness direction of the semiconductor packaging structure.

[0008] Optionally, the semiconductor power chip has a drain, and a drain power terminal is provided on the substrate. The drain power terminal is electrically connected to the drain, and the drain power terminal extends along the thickness direction of the semiconductor package structure.

[0009] Optionally, the semiconductor package structure further includes a package shell, which covers a portion of the source power terminal and / or the drain power terminal, and the source power terminal and / or the drain power terminal are vertically led out from the top surface of the package shell.

[0010] Optionally, the semiconductor package structure further includes a gate drive terminal, the semiconductor power chip has a gate, and the gate drive terminal is electrically connected to the gate.

[0011] Optionally, the substrate includes an insulating layer, the insulating layer has a first surface, and a drain power conductive layer is provided on the first surface; the drain of the semiconductor power chip is electrically connected to the drain power conductive layer, and the drain power terminal is electrically connected to the drain of the semiconductor power chip through the drain power conductive layer.

[0012] Optionally, the source of the semiconductor power chip includes a power source electrode, the power source electrode is arranged on the top surface of the semiconductor power chip, and the source power terminal is electrically connected to the power source electrode.

[0013] Optionally, the semiconductor package structure further includes a source driving terminal, the source of the semiconductor power chip includes a driving source, and the source driving terminal is electrically connected to the driving source.

[0014] Optionally, the substrate includes an insulating layer having a first surface, a driving source conductive layer is provided on the first surface, the driving source is electrically connected to the driving source conductive layer, and the source driving terminal is electrically connected to the driving source conductive layer.

[0015] Optionally, the substrate includes an insulating layer having a first surface, a driving gate conductive layer is provided on the first surface, the gate is electrically connected to the driving gate conductive layer, and the gate driving terminal is electrically connected to the driving gate conductive layer.

[0016] Optionally, the driving source is electrically connected to the driving source conductive layer via a first bonding wire, and the driving source conductive layer is electrically connected to the source driving terminal via a third bonding wire.

[0017] Optionally, the gate is electrically connected to the driving gate conductive layer via a second bonding wire, and the driving gate conductive layer is electrically connected to the gate driving terminal via a fourth bonding wire.

[0018] Optionally, the source power terminal has a first connection end and a second connection end; wherein the first connection end is welded to the top surface of the semiconductor power chip, and the second connection end is vertically led out from the top surface of the packaging shell.

[0019] Optionally, the drain power terminal has a third connection end and a fourth connection end; wherein the third connection end is welded to the drain power conductive layer of the semiconductor power chip, and the fourth connection end is vertically led out from the top surface of the packaging shell.

[0020] Optionally, the semiconductor power chip is provided in plurality, the source of the semiconductor power chip includes a power source terminal, and the power source terminal of any semiconductor power chip is electrically connected to the source power terminal.

[0021] Optionally, the semiconductor package structure includes a plurality of source power terminals, and a source power terminal is provided on the top surface of each semiconductor power chip, and the source power terminals are electrically connected to the power source of the corresponding semiconductor power chip.

[0022] Optionally, a plurality of the semiconductor power chips are connected in parallel to form a target packaging unit.

[0023] Optionally, the semiconductor packaging structure includes multiple drain power terminals, the drain of each semiconductor power chip is electrically connected to one of the drain power terminals, or the drains of multiple semiconductor power chips are electrically connected to the same drain power terminal.

[0024] Optionally, the semiconductor package structure includes a gate drive terminal, the semiconductor power chip has a gate, and the gates of the plurality of semiconductor power chips are electrically connected to the gate drive terminal.

[0025] Optionally, the semiconductor packaging structure includes multiple gate drive terminals, and the gate of each semiconductor power chip is electrically connected to one of the gate drive terminals, or the gates of multiple semiconductor power chips are electrically connected to the same gate drive terminal.

[0026] Optionally, the semiconductor package structure includes a source driving terminal, the source of the semiconductor power chip includes a driving source, and the driving sources of the plurality of semiconductor power chips are electrically connected to the source driving terminal.

[0027] Optionally, the semiconductor packaging structure includes multiple source drive terminals, and the drive source of each semiconductor power chip is electrically connected to one source drive terminal, or the drive sources of multiple semiconductor power chips are electrically connected to the same source drive terminal.

[0028] Optionally, the substrate includes an insulating layer, the insulating layer having at least a first surface, and a drain power conductive layer is provided on the first surface; the multiple semiconductor power chips are all arranged on the drain power conductive layer, and the drains of the multiple semiconductor power chips are electrically connected to the drain power conductive layer, and the drain power terminal forms an electrical connection with the drain power conductive layer.

[0029] Optionally, a driving gate conductive layer is further provided on the first surface, the gates of the plurality of semiconductor power chips are electrically connected to the driving gate conductive layer, and the gate driving terminal is electrically connected to the driving gate conductive layer.

[0030] Optionally, a driving source conductive layer is further provided on the first surface, the driving sources of the plurality of semiconductor power chips are electrically connected to the driving source conductive layer, and the source driving terminal is electrically connected to the driving source conductive layer.

[0031] Optionally, the drain of the semiconductor power chip is arranged on the bottom surface, the drain of the semiconductor power chip is welded on the drain power conductive layer, and a first solder layer is formed between the bottom surface of the semiconductor power chip and the drain power conductive layer, or the bottom surface of the semiconductor power chip is sintered to the drain power conductive layer.

[0032] Optionally, the power source electrodes of the multiple semiconductor power chips are all arranged on the top surface, the source power terminal is welded to the power source electrode on the top surface of the semiconductor power chip, and a second solder layer is formed between the source power terminal and the top surface of the semiconductor power chip, or the source power terminal is sintered to the top surface of the semiconductor power chip.

[0033] Optionally, the drain power terminal is a copper sheet; one end of the copper sheet is electrically connected to the drain power conductive layer, and one end of the copper sheet facing away from the drain power conductive layer extends to the top surface of the package shell of the semiconductor package structure and is led out.

[0034] Optionally, the insulating layer further has a second surface, the second surface being opposite to the first surface; a copper layer is formed on the second surface, the copper layer being exposed from the package shell of the semiconductor package structure.

[0035] According to the semiconductor packaging structure of the embodiment of the second aspect of the present application, it includes: a plurality of semiconductor power chips; and a substrate, the plurality of semiconductor power chips are arranged on the substrate, and a driving conductor is also arranged on the substrate, the driving conductor is suitable for transmitting a driving signal to the plurality of semiconductor power chips, and the driving conductor is arranged between the plurality of semiconductor power chips.

[0036] Optionally, the substrate includes a drain power conductive layer and an insulating layer, the drain power conductive layer is arranged on the insulating layer, a plurality of the semiconductor power chips are arranged on the drain power conductive layer, the drain power conductive layer is provided with a first gap, the first gap is located between the plurality of the semiconductor power chips, and the driving conductor is arranged in the first gap.

[0037] Optionally, the semiconductor power chip includes a drain, and the drain is electrically connected to the drain power conductive layer.

[0038] Optionally, the first notch extends along a first direction, and the plurality of semiconductor power chips are arranged around a circumference of the first notch.

[0039] Optionally, the plurality of semiconductor power chips are arranged along a second direction, and the second direction is perpendicular to the first direction.

[0040] Optionally, the plurality of semiconductor power chips are respectively arranged on both sides of the first notch, and the plurality of semiconductor power chips on both sides of the first notch are arranged along a first direction.

[0041] Optionally, the plurality of semiconductor power chips are symmetrically arranged along the axis of the first notch.

[0042] Optionally, the distances from the semiconductor power chips on both sides of the first gap to the driving conductor are the same.

[0043] Optionally, the drain power conductive layer is further provided with a second gap extending along the second direction, the second gap is connected to the first gap, and the driving conductor is provided in the first gap and the second gap.

[0044] Optionally, an edge of the second notch extends to an edge of the substrate.

[0045] Optionally, the first gap is vertically connected to the second gap, and the shape of the driving conductor matches the overall shape of the first gap and the second gap.

[0046] Optionally, the drain power conductive layer is provided with a plurality of the first notches, and at least one semiconductor power chip is provided around each of the first notches.

[0047] Optionally, the semiconductor power chip includes a gate, the driving conductor includes a driving gate conductive layer, the driving gate conductive layer is electrically connected to the gate, and the driving gate conductive layer is led out through the first notch and / or the second notch.

[0048] Optionally, the semiconductor packaging structure includes a source power terminal, the semiconductor power chip includes a source, the source power terminal is electrically connected to the sources of multiple semiconductor power chips, the source of the semiconductor power chip includes a power source, and the source power terminal is electrically connected to the power source.

[0049] Optionally, the power source of the semiconductor power chip is arranged on the top surface, and the source power terminal covers the top surface of the semiconductor power chip to form an electrical connection with the power source.

[0050] Optionally, the source of the semiconductor power chip includes a driving source, the driving conductor includes a driving source conductive layer, the driving source conductive layer is electrically connected to the driving source, and the driving source conductive layer is led out through the first gap and / or the second gap.

[0051] Optionally, the driving source conductive layer and the driving gate conductive layer are arranged in parallel and spaced apart.

[0052] Optionally, the semiconductor package structure includes a source driving terminal, and the driving source conductive layer is electrically connected to the source driving terminal.

[0053] Optionally, a gate driving terminal is included, and the driving gate conductive layer is electrically connected to the gate driving terminal.

[0054] Optionally, the source drive terminal is electrically connected to the source power terminal.

[0055] Optionally, a drain power terminal is provided on the substrate, electrically connected to the drain power conductive layer. The semiconductor package structure further includes a source power terminal electrically connected to the source of the semiconductor power chip. The substrate has a first sidewall and a second sidewall disposed opposite each other. The drain power terminal is located on the first sidewall, and the source power terminal is located on the second sidewall; alternatively, both the drain power terminal and the source power terminal are located on the first sidewall.

[0056] Optionally, the substrate includes a heat-conducting layer, and the heat-conducting layer and the drain power conductive layer are located on both sides of the insulating layer.

[0057] Optionally, the substrate further includes a package body, the package body is made of insulating material, the semiconductor power chip, the insulating layer and the drain power conductive layer are packaged outside the package body, and the heat conductive layer is exposed outside the package body.

[0058] According to the semiconductor packaging structure of the embodiment of the third aspect of the present application, it includes: a substrate, the substrate including a drain power conductive layer, a source power conductive layer and a driving conductive layer arranged at intervals, the source power conductive layer and the driving conductive layer are respectively arranged on both sides of the drain power conductive layer; and at least one semiconductor power chip, the semiconductor power chip is arranged on the drain power conductive layer, the drain of the semiconductor power chip is electrically connected to the drain power conductive layer, the source of the semiconductor power chip is electrically connected to the source power conductive layer, and the driving electrode of the semiconductor power chip is electrically connected to the driving conductive layer.

[0059] Optionally, the drain power conductive layer, the source power conductive layer and the driving conductive layer are extended along a first direction on the substrate.

[0060] Optionally, the drain power conductive layer includes a drain power conductive layer body and an end drain power conductive portion, the end drain power conductive portion is connected to the drain power conductive layer body, and the at least one semiconductor power chip is provided in the drain power conductive layer body.

[0061] Optionally, the end drain power conductive portion protrudes from the drain power conductive layer body along the second direction, the drain power conductive layer body extends along the first direction, the drain power conductive layer body is located between the driving conductive layer and the source power conductive layer, and the first direction is perpendicular to the second direction.

[0062] Optionally, the source power conductive layer includes an end source power conductive portion and a source power conductive layer body, the end source power conductive portion is connected to one end of the source power conductive layer body, the source power conductive layer body extends along a first direction, and the end source power conductive portion protrudes from the source power conductive layer body.

[0063] Optionally, the end source power conductive portion is arranged opposite to the drain power conductive layer body, and the end source power conductive portion is spaced apart from and covers the extended end of the drain power conductive layer body.

[0064] Optionally, the end drain power conductive portion protrudes from both ends of the drain power conductive layer body, and is spaced apart from and covers the end of the source power conductive layer body and the end of the driving conductive layer.

[0065] Optionally, the driving conductive layer includes a driving gate conductive layer, and the driving gate conductive layer extends along a first direction; the driving electrode includes a driving gate, and the driving gate conductive layer is electrically connected to the driving gate.

[0066] Optionally, the driving conductive layer further includes: a driving source conductive layer, the driving source power conductive layer extending along the first direction; the driving electrode includes a driving source electrode, and the driving source electrode is electrically connected to the driving source conductive layer.

[0067] Optionally, the driving source conductive layer and the driving gate conductive layer are spaced apart in a second direction, the second direction is perpendicular to the first direction, and the driving source conductive layer and the driving gate conductive layer are parallel in the second direction.

[0068] Optionally, the semiconductor packaging structure includes: a drain power terminal, which is electrically connected to the drain power conductive layer; a source power terminal, which is electrically connected to the source power conductive layer; and a drive terminal, which is electrically connected to the drive conductive layer.

[0069] Optionally, the driving terminal includes: a gate driving terminal, the gate driving terminal being electrically connected to the driving gate conductive layer; and a source driving terminal, the source driving terminal being electrically connected to the driving source conductive layer.

[0070] Optionally, the source driving terminal and the driving source conductive layer are arranged opposite to each other along a first direction, and the gate driving terminal and the driving gate conductive layer are arranged opposite to each other along the first direction.

[0071] Optionally, the driving terminal and the source power terminal are located on the same side of the substrate.

[0072] Optionally, the drain of the semiconductor power chip is welded to the drain power conductive layer to form an electrical connection.

[0073] Optionally, there are a plurality of semiconductor power chips, and the plurality of semiconductor power chips are arranged on the drain power conductive layer at intervals along the first direction.

[0074] Optionally, the drain power conductive layer includes a plurality of drain power conductive layer bodies and at least one end drain power conductive part, the plurality of drain power conductive layer bodies are spaced apart along a second direction, each of the drain power conductive layer bodies is provided with at least one semiconductor power chip, and the second direction is perpendicular to the extension direction of the drain power conductive layer body.

[0075] Optionally, there are multiple semiconductor power chips, and the multiple semiconductor power chips include at least a first semiconductor power chip group and a second semiconductor power chip group, the first semiconductor power chip group includes multiple first semiconductor power chips, the second semiconductor power chip group includes multiple second semiconductor power chips, and the multiple drain power conductive layer bodies include at least a first drain power conductive layer body and a second drain power conductive layer body spaced apart along the second direction. The multiple first semiconductor power chips are spaced apart from each other along a first direction and are spaced apart from each other along the first direction and are spaced apart from each other along the first direction and are spaced apart from each other along the first direction.

[0076] Optionally, there are multiple source power conductive layers, and the multiple source power conductive layers include at least a first source power conductive layer and a second source power conductive layer, the first source power conductive layer is arranged adjacent to the first drain power conductive layer body, and the second source power conductive layer is arranged adjacent to the second drain power conductive layer body.

[0077] Optionally, the semiconductor package structure further includes: at least one source power terminal, wherein the source power terminal is electrically connected to the plurality of source power conductive layers.

[0078] Optionally, the source power terminal includes at least a first source power terminal portion and a second source power terminal portion, the first source power terminal portion is electrically connected to the first source power conductive layer, and the second source power terminal portion is electrically connected to the second source power conductive layer.

[0079] Optionally, one end of the driving conductive layer is located between the plurality of drain power conductive layer bodies, and is used for being electrically connected to the driving electrodes of the plurality of semiconductor power chips.

[0080] Optionally, the semiconductor package structure further includes a driving terminal, and the other end of the driving conductive layer is electrically connected to the driving terminal.

[0081] Optionally, the driving conductive layer includes: a driving conductive layer body and an end driving conductive portion, the driving conductive layer body is located between two adjacent drain power conductive layer bodies, and the end driving conductive portion is electrically connected to the driving terminal.

[0082] Optionally, the drain power terminal, the source power terminal and the driving terminal are located on the same side of the substrate, the driving conductive layer, the drain power conductive layer and the source power conductive layer are arranged in sequence along the second direction, the driving terminal, the drain power terminal and the source power terminal are arranged in sequence along the second direction, and the driving terminal, the drain power terminal and the source power terminal are respectively arranged corresponding to the driving conductive layer, the drain power conductive layer and the source power conductive layer.

[0083] According to the semiconductor packaging structure of the embodiment of the fourth aspect of the present application, it includes: a substrate, the substrate including a drain power conductive layer and a driving conductive layer arranged at intervals; at least one semiconductor power chip, the semiconductor power chip is arranged on the drain power conductive layer, the drain of the semiconductor power chip is electrically connected to the drain power conductive layer, and the driving electrode of the semiconductor power chip is electrically connected to the driving conductive layer; a plurality of power terminals, the plurality of power terminals are respectively electrically connected to the source of the semiconductor power chip and the drain power conductive layer; and at least one driving terminal, the driving terminal is electrically connected to the driving conductive layer, and the driving terminal and the power terminal are respectively located on different sides of the substrate.

[0084] Optionally, the driving terminal and the power terminal are respectively located on two sides of the substrate that are opposite to each other along the first direction.

[0085] Optionally, the drain power conductive layer and the driving conductive layer are arranged in sequence along a first direction.

[0086] Optionally, the driving terminal is located in the middle of a side edge of the substrate.

[0087] Optionally, the driving conductive layer includes a driving gate conductive layer extending along the second direction and disposed adjacent to the driving terminal. The driving electrode includes a driving gate electrically connected to the driving gate conductive layer.

[0088] Optionally, the driving conductive layer includes a driving source conductive layer, the driving source conductive layer extending along the second direction and disposed adjacent to the driving terminal. The driving electrode includes a driving source electrode, the driving source electrode being electrically connected to the driving source conductive layer.

[0089] Optionally, the driving source conductive layer and the driving gate conductive layer are parallel to each other, the driving source conductive layer and the driving gate conductive layer extend along the second direction, the power terminal and the driving terminal are arranged along the first direction, and the first direction is perpendicular to the second direction.

[0090] Optionally, the driving source conductive layer and the driving gate conductive layer are in a strip shape.

[0091] Optionally, the power terminal includes:

[0092] A drain power terminal and a source power terminal, wherein the drain power terminal and the source power terminal are both located on the same side of the substrate.

[0093] Optionally, the drain power terminal is electrically connected to the drain power conductive layer, the source power terminal is electrically connected to the source of the semiconductor power chip, and the power terminal is electrically connected to the drain power conductive layer and the source of the semiconductor power chip respectively through bonding wires.

[0094] Optionally, the width of the source power terminal is W, the width of the semiconductor package structure is L, and W and L satisfy: <W<L / ; and / or

[0095] The width of the drain power terminal is W, the width of the semiconductor package structure is L, and W and L satisfy: <W<L / .

[0096] Optionally, the driving terminal includes: a source driving terminal and a gate driving terminal, and the source driving terminal and the gate driving terminal are both located on the same side of the substrate.

[0097] Optionally, the source driving terminal is electrically connected to the driving source through the driving source conductive layer, and the gate driving terminal is electrically connected to the driving gate through the driving gate conductive layer.

[0098] Optionally, the width of the source driving terminal and the gate driving terminal are respectively H, and H satisfies: mm≤H≤mm.

[0099] Optionally, there are multiple semiconductor power chips, and the multiple semiconductor power chips are arranged at intervals along the second direction.

[0100] Optionally, the plurality of semiconductor power chips are divided into a plurality of semiconductor power chip groups, each of which includes at least two semiconductor power chips. The drain power terminal includes a plurality of drain power terminal portions, each of which is located on either side of the source power terminal, and each of which is electrically connected to the drain power conductive layer.

[0101] Optionally, the drain power terminal is electrically connected to the drain power conductive layer via a first connecting piece, and the source power terminal is electrically connected to the source via a second connecting piece.

[0102] Optionally, at least one through hole is formed on the second connecting piece, and the through hole is located between two adjacent semiconductor power chips, and ends of the two adjacent semiconductor power chips adjacent to each other are exposed from the through hole.

[0103] Optionally, the substrate further includes: a source power conductive layer, the source power conductive layer and the drain power terminal are spaced apart, the source power conductive layer is electrically connected to the source and the power terminal respectively, and the source power conductive layer is arranged between the drain power conductive layer and the power terminal.

[0104] A semiconductor power module according to an embodiment of the fifth aspect of the present application includes a semiconductor packaging structure according to any one embodiment of the first to fourth aspects of the present application.

[0105] An electronic device according to an embodiment of the sixth aspect of the present application includes a semiconductor packaging structure according to any one embodiment of the first to fourth aspects of the present application.

[0106] The vehicle according to the seventh aspect of the present application includes the semiconductor packaging structure according to any one of the first to fourth aspects of the present application.

[0107] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application.

[0108] Other features and advantages of the present application will become apparent from the following detailed description of exemplary embodiments of the present application with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the application and, together with the description, serve to explain the principles of the application.

[0110] FIG1 is a first cross-sectional view of a semiconductor package structure provided by an embodiment of the first aspect of the present application;

[0111] FIG2 is a top view of the semiconductor package structure shown in FIG1 ;

[0112] FIG3 is an equivalent circuit diagram of the semiconductor package structure provided in FIG1 and FIG2;

[0113] FIG4 is a second cross-sectional view of the semiconductor package structure provided by the embodiment of the first aspect of the present application;

[0114] FIG5 is a first top view of a semiconductor package structure provided by an embodiment of the first aspect of the present application;

[0115] FIG6 is a second top view of the semiconductor packaging structure provided by the embodiment of the first aspect of the present application.

[0116] FIG7 is a cross-sectional view of a semiconductor package structure according to an embodiment of the second aspect of the present application.

[0117] FIG8 is a schematic structural diagram of a semiconductor packaging structure according to an embodiment of the second aspect of the present application.

[0118] FIG9 is a connection diagram of a semiconductor package structure according to an embodiment of the second aspect of the present application.

[0119] FIG10 is a connection diagram of a semiconductor package structure according to another embodiment of the second aspect of the present application.

[0120] FIG11 is a connection diagram of a semiconductor package structure according to yet another embodiment of the second aspect of the present application.

[0121] FIG12 is a circuit diagram of a semiconductor package structure according to an embodiment of the second aspect of the present application.

[0122] FIG13 is a schematic diagram showing that the driving terminal and the power terminal are located on the same side wall of the base according to an embodiment of the second aspect of the present application.

[0123] FIG14 is a schematic diagram showing that the driving terminal and the power terminal are respectively located on different side walls of the base according to an embodiment of the second aspect of the present application.

[0124] FIG15 is a schematic diagram of a semiconductor package structure of multiple first portions according to an embodiment of the second aspect of the present application.

[0125] FIG16 is a schematic diagram of a semiconductor power chip extending along a first direction according to an embodiment of the second aspect of the present application.

[0126] FIG17 is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the third aspect of the present application.

[0127] FIG18 is a schematic diagram of a conductive layer and terminal arrangement according to an embodiment of the third aspect of the present application.

[0128] FIG19 is a schematic diagram of connection using bonding wires according to an embodiment of the third aspect of the present application.

[0129] FIG20 is a schematic diagram of connection using a CLIP connection method according to an embodiment of the third aspect of the present application.

[0130] FIG21 is a schematic diagram of an arrangement of multiple power chips according to an embodiment of the third aspect of the present application.

[0131] FIG22 is an equivalent circuit diagram of an embodiment according to the third aspect of the present application.

[0132] FIG23 is a schematic diagram of the conductive layer and terminal arrangement according to another embodiment of the third aspect of the present application.

[0133] FIG24 is a schematic diagram of the conductive layer and terminal arrangement according to another embodiment of the third aspect of the present application.

[0134] FIG. 25 is a diagram showing the temperature simulation effect of a semiconductor packaging structure in the prior art.

[0135] FIG. 26 is a temperature simulation cross-sectional effect diagram of a semiconductor packaging structure in the prior art.

[0136] Figure 27 is a temperature simulation effect diagram of a semiconductor packaging structure according to an embodiment of the third aspect of the present application.

[0137] Figure 28 is a temperature simulation cross-sectional rendering of a semiconductor packaging structure according to an embodiment of the third aspect of the present application.

[0138] Figure 29 is a cross-sectional schematic diagram of the power terminal of the semiconductor packaging structure according to the fourth embodiment of the present application.

[0139] Figure 30 is a schematic diagram of the distribution of the conductive layers and terminals of the semiconductor packaging structure according to the embodiment of the fourth aspect of the present application.

[0140] FIG31 is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention, wherein the internal structure of the semiconductor package structure is connected by bonding wires.

[0141] FIG32 is a schematic diagram showing a semiconductor package structure according to an embodiment of the present invention in which a CLIP connection method is used internally in the semiconductor package structure.

[0142] FIG33 is an equivalent circuit diagram of a semiconductor package structure according to an embodiment of the semiconductor package structure of the present application.

[0143] FIG34 is a schematic diagram showing a semiconductor package structure according to another embodiment of the present invention, in which a CLIP connection method is used internally in the semiconductor package structure.

[0144] Figure 35 is a schematic block diagram of a semiconductor power module according to an embodiment of the fifth aspect of the present application.

[0145] Figure 36 is a schematic block diagram of an electronic device according to an embodiment of the sixth aspect of the present application.

[0146] Figure 37 is a schematic block diagram of a vehicle according to an embodiment of the seventh aspect of the present application.

[0147] Description of reference numerals:

[0148] 1. 20. Semiconductor power chip; 101. Power source (source power lead terminal); 102. Gate (driving gate); 103. Driving source;

[0149] 2. 10, substrate; 201, drain power conductive layer; 2111, first notch; 2112, second notch; 132, driving source conductive layer; 131, driving gate conductive layer; 221, first conductor; 222, second conductor; 223, avoidance area; 24, insulating layer; 25, thermal conductive layer; 27, second surface;

[0150] 31. First solder layer; 32. Second solder layer; 33. Third solder layer; 301. Source power terminal; 302. Drain power terminal;

[0151] 61. First buffer metal layer; 62. Second buffer metal layer; 41. Source drive terminal; 42. Gate drive terminal;

[0152] 91. First bonding wire; 92. Second bonding wire; 93. Third bonding wire; 94. Fourth bonding wire; 50. Package casing.

[0153] 71. Source power terminal bonding wire; 72. Source drive bonding wire; 73. Gate drive bonding wire; 74. Drain power terminal bonding wire; 75. Source drive terminal bonding wire; 76. Gate drive terminal bonding wire; 77. Gate avoidance area bonding wire; 8. Package body; 81. First side wall; 82. Second side wall; 60. Solder layer,

[0154] 100. Semiconductor packaging structure; 111. Drain power conductive layer body; 1111. First drain power conductive layer body; 1112. Second drain power conductive layer body; 112. End drain power conductive portion; 12. Source power conductive layer; 121. Source power conductive layer body; 122. End source power conductive portion; 123. First source power conductive layer; 124. Second source power conductive layer; 130. Drive conductive layer; 133. Drive conductive layer body; 134. End drive conductive portion; 1 5. Second metal layer; 21. Driver; 28. First semiconductor power chipset; 220. First semiconductor power chip; 23. Second semiconductor power chipset; 231. Second semiconductor power chip; 321. First source power terminal; 322. Second source power terminal; 40. Driver terminal; 30. Power terminal; 351. Drain power terminal; 330. First connecting piece; 340. Second connecting piece; 341. First connecting sub-piece; 342. Second connecting sub-piece; 343. Through hole; DETAILED DESCRIPTION

[0155] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application.

[0156] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0157] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0158] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0159] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0160] The semiconductor packaging structure provided in the embodiment of the first aspect of the present application is described in detail below with reference to the accompanying drawings.

[0161] In related technologies, power semiconductor devices are devices that achieve electrical energy conversion. However, current packaging structures have limited current flow capacity, and insulation and heat dissipation rely on external thermal interface materials, resulting in high thermal resistance, which limits the application of power semiconductor devices in higher-power applications.

[0162] According to one embodiment of the present application, a semiconductor package structure is provided. Referring to Figures 1 to 3 , the semiconductor package structure 100 includes a substrate 2, at least one semiconductor power chip 1, and a source power terminal 301. The semiconductor power chip 1 is disposed on the substrate 2 and has a source electrode. The source power terminal 301 is disposed on the top surface of the semiconductor power chip 1 and is electrically connected to the source electrode. The source power terminal 301 extends through the thickness of the semiconductor package structure 100.

[0163] According to the above embodiments, the present application provides a single-tube packaging solution for a semiconductor power chip with vertical power terminals, wherein the number of semiconductor power chips 1 includes but is not limited to a single one, and the specific number can be adjusted as needed to meet high-power applications.

[0164] For example, in the semiconductor package structure 100 , two or more semiconductor power chips 1 may be designed to be connected in parallel and packaged using the single-tube packaging solution in the above embodiment.

[0165] According to the above embodiment, the semiconductor power chip 1 is, for example, a sheet-like structure having a certain thickness, and has two opposing large surfaces, namely a top surface and a bottom surface. The bottom surface of the semiconductor power chip 1 is connected to the substrate 2, so that the semiconductor power chip 1 is disposed on the substrate 2. The top surface of the semiconductor power chip 1 is, for example, provided with a source electrode, and the source power terminal 301 is also disposed on the top surface of the semiconductor power chip 1. This facilitates electrical connection between the source power terminal 301 and the source electrode of the semiconductor power chip 1, and allows the source power terminal 301 to extend along the thickness direction of the semiconductor package structure 100 and be vertically led out.

[0166] When the source power terminal 301 is extended along the thickness direction, the source power terminal 301 can be extended in a variety of ways, such as tilting or bending, without limitation. When the source power terminal 301 is extended vertically, the length of the source power terminal 301 can be shorter, which helps to shorten the power loop and thus minimize parasitic inductance. Moreover, after the source power terminal 301 is extended vertically, in addition to its short length, its cross-sectional area can be larger, which can significantly improve the current carrying capacity. In addition, after the source power terminal 301 in the present application is extended vertically, it can also play a certain role in heat dissipation.

[0167] It should be noted that the preferred solution in this application is to design the source power terminal 301 to be vertically extended. However, in actual applications, the source power terminal 301 can also be slightly bent and tilted, and does not necessarily have to be completely vertically extended. Or the source power terminal 301 itself may be bent and tilted, but this should also fall within the scope of protection of this application.

[0168] The semiconductor package structure 100 proposed in the present embodiment is a single-tube package structure with vertical power terminals. By designing the power terminals to extend vertically along the thickness of the entire device, the power terminals are short and have a large cross-sectional area. This design shortens the power loop, thereby minimizing parasitic inductance. Furthermore, the exposed power terminals provide a certain degree of heat dissipation. The resulting semiconductor package structure 100 has excellent flow capacity and reduced thermal resistance, enabling its application in higher-power applications.

[0169] In some examples of the present application, referring to Figures 1 to 3, the semiconductor power chip 1 has a drain, and a drain power terminal 302 is provided on the substrate 2. The drain power terminal 302 is electrically connected to the drain, and the drain power terminal 302 extends along the thickness direction of the semiconductor package structure 100 and is vertically led out.

[0170] According to the above example, the drain power terminal 302 on the substrate 2 is also designed to be vertically extended. On this basis, combined with the above embodiment, the source power terminal 301 is stacked on the top surface of the semiconductor power chip 1 and vertically extended. This makes the two power terminals of the semiconductor package structure 100 designed to be vertically extended, which is different from the traditional power terminal extension method.

[0171] The semiconductor packaging structure 100 provided in an embodiment of the present application is designed such that the power terminals therein, such as the source power terminal 301 and the drain power terminal 302, are designed to be vertically led out along the thickness direction of the entire device. This lead-out method allows the length of the power terminals to be designed to be shorter, for example, the length of the power terminals can be in the millimeter level, and this design achieves extremely low parasitic inductance.

[0172] Traditional packaged devices can only dissipate heat from the bottom. However, in the present invention, the source power terminal 301 and the drain power terminal 302 are vertically led out of the package structure and located at the top, which allows the top of the entire package structure to play a certain role in heat dissipation.

[0173] In addition, the source power terminal 301 and / or the drain power terminal 302 in the present application are located on the top surface of the semiconductor package structure 100 , and a variety of connection processes can be used with external circuits, such as welding, sintering, and laser welding.

[0174] In some examples of the present application, referring to Figures 1 to 3, the semiconductor package structure 100 further includes a package shell 50, which covers a portion of the source power terminal 301 and / or the drain power terminal 302, and the source power terminal 301 and / or the drain power terminal 302 are led out from the top surface of the package shell 50.

[0175] In the semiconductor packaging structure 100 provided in the embodiment of the present application, the substrate 2 provides mechanical support and insulation for each functional device. The packaging shell 50 is arranged on one side of the substrate 2 and can cover each functional device, thereby providing a certain degree of protection for each functional device and the substrate 2.

[0176] According to the above example, the package shell 50 covers the device supported on the insulating layer 24 and exposes the top surface of the source power terminal 301 and / or the drain power terminal 302 for connection with the outside. Under this design, the source power terminal 301 and / or the drain power terminal 302 can also play a certain heat dissipation role.

[0177] The packaging shell 50 is made of epoxy resin material, for example.

[0178] In some examples of the present application, referring to FIG. 2 and FIG. 3 , the semiconductor package structure 100 further includes a gate drive terminal 42 , the semiconductor power chip 1 has a gate 102 , and the gate drive terminal 42 is electrically connected to the gate 102 .

[0179] According to the above example, referring to FIG. 2 and FIG. 3 , the semiconductor package structure 100 is a single-tube package structure, and the entire package structure may have one gate driving terminal 42 .

[0180] Specifically, the gate driving terminal 42 can be separated from the substrate 2 and then electrically connected to the substrate 2 using a bonding wire.

[0181] Of course, the gate drive terminal 42 can also be directly welded on the surface of the substrate 2 .

[0182] It should be noted that the gate drive terminal 42 and the substrate 2 only need to be electrically connected. The specific connection methods are quite diverse and will not be described in detail in this application.

[0183] In some examples of the present application, referring to Figures 1 and 2 , substrate 2 includes an insulating layer 24 having a first surface on which a drain power conductive layer 201, such as a drain copper layer, is disposed. The drain of semiconductor power chip 1 is electrically connected to drain power conductive layer 201, and drain power terminal 302 is electrically connected to the drain of semiconductor power chip 1 via drain power conductive layer 201.

[0184] According to the above example, substrate 2 has an insulating layer 24, which is, for example, a ceramic material layer. Since substrate 2 has its own ceramic insulating layer 24, internal insulation of semiconductor package structure 100 can be achieved, eliminating the need for an additional external insulating layer, thereby improving the reliability and thermal conductivity of the entire semiconductor package structure 100.

[0185] For example, the substrate 2 is an AMB substrate or a DBC substrate.

[0186] Of course, the substrate 2 may also be other types of substrates with a ceramic insulating layer.

[0187] In some examples of the present application, referring to FIG1 and FIG2 , the source of the semiconductor power chip 1 includes a power source 101 . The power source 101 is disposed on the top surface of the semiconductor power chip 1 , and the source power terminal 301 is electrically connected to the power source 101 .

[0188] The source of the semiconductor power chip 1 is designed to be located on the top surface thereof. The source includes a power source 101 . The source power terminal 301 is used to form an electrical connection with the power source 101 .

[0189] In some examples of the present application, referring to FIG. 2 and FIG. 3 , the semiconductor package structure 100 further includes a source driving terminal 41 , the source of the semiconductor power chip 1 includes a driving source 103 , and the source driving terminal 41 is electrically connected to the driving source 103 .

[0190] 2 and 3 , the semiconductor package structure 100 is a single-tube package structure, and the entire package structure has not only a gate drive terminal 42 but also a source drive terminal 41. The source drive terminal 41 is used to form an electrical connection with the drive source 103 of the semiconductor power chip 1.

[0191] Specifically, the source driving terminal 41 can be separated from the substrate 2 and then electrically connected to the substrate 2 using a bonding wire.

[0192] Of course, the source driving terminal 41 can also be directly welded on the surface of the substrate 2 .

[0193] It should be noted that the source driving terminal 41 and the substrate 2 only need to be electrically connected. The specific connection methods are quite diverse and will not be described in detail in this application.

[0194] In some examples of the present application, referring to Figures 1 and 2, the substrate 2 includes an insulating layer 24, the insulating layer 24 has a first surface, and a driving source conductive layer 132 is provided on the first surface, such as a driving source copper layer. The driving source 103 is electrically connected to the driving source conductive layer 132, and the driving terminal 7 is electrically connected to the driving source conductive layer 132.

[0195] A copper layer is provided on the insulating layer of the substrate 2 , and a driving source conductive layer 132 of a predetermined shape can be formed on the copper layer by, for example, an etching process.

[0196] In some examples of the present application, referring to Figures 1 and 2, the substrate 2 includes an insulating layer 24, the insulating layer 24 has a first surface, a driving gate conductive layer 131 is provided on the first surface, such as a driving gate copper layer, the gate 102 is electrically connected to the driving gate conductive layer 131, and the gate driving terminal 42 is electrically connected to the driving gate conductive layer 131.

[0197] A copper layer is provided on the insulating layer of the substrate 2 , and a driving gate conductive layer 131 of a predetermined shape can be formed on the copper layer by, for example, an etching process.

[0198] The semiconductor power chip 1 has a gate 102 located on the top surface of the semiconductor power chip 1 . The gate 102 is electrically connected to the driving gate conductive layer 131 . The driving gate conductive layer 131 is also electrically connected to a gate driving terminal 42 of the semiconductor package structure 100 .

[0199] According to the semiconductor packaging structure 100 provided in an embodiment of the present application, for the substrate 2, for example, a copper layer is formed on the first surface of its insulating layer 24. After etching, the copper layer can form a drain power conductive layer 201, a driving source conductive layer 132 and a driving gate conductive layer 131 respectively. The drain power conductive layer 201, the driving source conductive layer 132 and the driving gate conductive layer 131 are arranged in blocks and at intervals, see Figure 2.

[0200] The top surface of the semiconductor power chip 1 is provided with a source and a gate 102, wherein the source comprises two parts, namely a power source 101 and a driving source 103. The bottom surface of the semiconductor power chip 1 is a drain, see FIG2 .

[0201] The bottom surface of the semiconductor power chip 1 is disposed on the drain power conductive layer 201 , and the drain thereof can be directly electrically connected to the drain power conductive layer 201 .

[0202] The power source 101 on the top surface of the semiconductor power chip 1 is electrically connected to the source power terminal 301. The gate 102 and the driving source 103 on the top surface of the semiconductor power chip 1 are electrically connected to the driving gate conductive layer 131 and the driving source conductive layer 132, respectively. In addition, a drain power terminal 302 is stacked on the drain power conductive layer 201, and the drain power terminal 302 is electrically connected to the drain power conductive layer 201.

[0203] In some examples of the present application, the driving source 103 is electrically connected to the driving source conductive layer 132 through a first bonding wire 91 , and the driving source conductive layer 132 is electrically connected to the source driving terminal 41 through a third bonding wire 93 , see FIG. 2 .

[0204] Since the driving source 103 is located on the top surface of the semiconductor power chip 1 and the driving source conductive layer 132 is located on the substrate 2, in order to facilitate electrical connection between the two, a bonding wire can be used to achieve electrical conduction between the two, such as the first bonding wire 91 in the above example.

[0205] Since the location of the source driving terminal 41 on the semiconductor package structure 100 is relatively flexible, in order to facilitate the electrical connection between the driving source conductive layer 132 and the source driving terminal 41, a bonding wire can be used to achieve electrical conduction between the two, such as the third bonding wire 93 in the above example.

[0206] That is to say, referring to FIG2 , the driving source 103 can be connected to the driving source conductive layer 132 on the surface of the substrate 2 through a first bonding wire 91 (source bonding wire), and further electrically connected to the source driving terminal 41 through a third bonding wire 93 to form a Kelvin connection, thereby eliminating the influence of the common source inductance on the switching performance of the semiconductor power chip 1.

[0207] In some examples of the present application, referring to FIG. 2 , the gate 102 is electrically connected to the driving gate conductive layer 131 through a second bonding wire 92 , and the driving gate conductive layer 131 is electrically connected to the gate driving terminal 42 through a fourth bonding wire 94 .

[0208] According to the above example, the gate 102 is electrically connected to the gate driving terminal 42 .

[0209] In some examples of the present application, referring to FIG1 , the source power terminal 301 has a first connection end and a second connection end, wherein the first connection end is welded to the top surface of the semiconductor power chip 1 , the source power terminal 301 is perpendicular to the top surface of the semiconductor power chip 1 , and the second connection end is vertically led out from the top surface of the packaging shell 50 .

[0210] The first connection end is used to form an electrical connection with the first semiconductor power chip 1 , and the second connection end can be led out to the outside to be used for electrical connection with an external device.

[0211] In some examples of the present application, referring to FIG1 , the drain power terminal 302 has a third connection end and a fourth connection end, wherein the third connection end is welded to the drain power conductive layer 201 of the semiconductor power chip 1 , and the fourth connection end is vertically led out from the top surface of the packaging shell 50 .

[0212] The drain power terminal 302 is perpendicular to the drain power conductive layer 201, and its fourth connection end is vertically extended from the top surface of the package housing 50. In other words, the drain power terminal 302 is arranged perpendicular to the substrate 2. In this application, the vertical power terminal design achieves 3D power current flow, making the power circuit plane perpendicular to the drive circuit plane, greatly reducing the coupling between the power circuit and the drive circuit, and preventing the impact of power current changes on the drive circuit.

[0213] In some examples of the present application, a plurality of semiconductor power chips 1 are provided, and the source of the semiconductor power chip 1 includes a power source 101 . The power source 101 of any semiconductor power chip 1 is electrically connected to the source power terminal 301 .

[0214] The semiconductor package structure 100 provided in the embodiment of the present application can be provided with two or more semiconductor power chips 1 in parallel, rather than being limited to packaging one semiconductor power chip 1 in a single tube. This makes the formed semiconductor package structure 100 suitable for high-power applications.

[0215] In some examples of the present application, the semiconductor packaging structure 100 includes multiple source power terminals 301, and a source power terminal 301 is provided on the top surface of each semiconductor power chip 1, and the source power terminals 301 are respectively electrically connected to the power source 101 of the corresponding semiconductor power chip 1.

[0216] In some examples of the present application, a plurality of semiconductor power chips 1 are connected in parallel to form a target packaging unit.

[0217] For example, two semiconductor power chips 1 are connected in parallel to form a target package unit.

[0218] Of course, three or more semiconductor power chips 1 may be connected in parallel to form a target packaging unit, which is not limited in the present application.

[0219] The semiconductor package structure 100 may include at least one target package unit as described above.

[0220] In the semiconductor package structure 100 , the target package unit may be one or more, where “more” means two or more than two.

[0221] It should be noted that in the semiconductor package structure 100, the number of target package units can be increased and is not limited to one. However, since a single-tube package solution is adopted, when two or more target package units are designed, all target package units share the gate drive terminal 42 and the source drive terminal 41, as shown in Figures 5 and 6.

[0222] In some examples of the present application, drains of a plurality of semiconductor power chips 1 are electrically connected to the drain power terminal 302 .

[0223] 2 and 3 , the drains of each semiconductor power chip 1 are electrically connected to the drain power terminal 302, and the power sources 101 of each semiconductor power chip 1 are electrically connected to the source power terminal 301. This allows multiple semiconductor power chips 1 to be connected in parallel and form a target package unit. The target package unit formed can provide an interface for connecting to an external circuit through the drain power terminal 302 and the source power terminal 301.

[0224] For example, the semiconductor package structure 100 includes a plurality of drain power terminals 302 , and the drain of each semiconductor power chip 1 is electrically connected to one drain power terminal 302 .

[0225] For example, the drains of the plurality of semiconductor power chips 1 are electrically connected to the same drain power terminal 302 .

[0226] In some examples of the present application, the semiconductor package structure 100 includes a gate drive terminal 42 , the semiconductor power chip 1 has a gate 102 , and the gates 102 of the plurality of semiconductor power chips 1 are electrically connected to the gate drive terminal 42 .

[0227] That is, the gates 102 of the plurality of semiconductor power chips 1 may be electrically connected together to the gate drive terminal 42 to provide a connection interface with an external drive circuit.

[0228] For example, the semiconductor package structure 100 includes a plurality of gate driving terminals 42 , and the gate 102 of each semiconductor power chip 1 is electrically connected to one gate driving terminal 42 .

[0229] For example, the gates 102 of the plurality of semiconductor power chips 1 are all electrically connected to the same gate driving terminal 42 .

[0230] In some examples of the present application, the semiconductor package structure 100 includes a source drive terminal 41 , the source of the semiconductor power chip 1 includes a drive source 103 , and the drive sources 103 of multiple semiconductor power chips 1 are electrically connected to the source drive terminal 41 .

[0231] The driving sources 103 of the plurality of semiconductor power chips 1 may be electrically connected together to the source driving terminal 41 . The source driving terminal 41 is used to provide an external connection interface, forming a Kelvin connection.

[0232] For example, the semiconductor package structure 100 includes a plurality of source driving terminals 41 , and the driving source 103 of each semiconductor power chip 1 is electrically connected to one source driving terminal 41 .

[0233] For example, the driving sources 103 of the plurality of semiconductor power chips 1 are all electrically connected to the same source driving terminal 41 .

[0234] The packaging structure provided by the embodiment of the present application can realize single-tube packaging of multiple semiconductor power chips 1, which can improve the current carrying capacity. Among them, multiple semiconductor power chips 1 are designed in parallel and then packaged in a single tube.

[0235] Figures 2 and 3 show two semiconductor power chips 1 connected in parallel and then packaged as a single chip. In fact, more than two semiconductor power chips 1 can also be connected in parallel and packaged as a single chip.

[0236] 2 , taking two semiconductor power chips 1 connected in parallel as an example, a top view of the internal layout structure of the packaging structure provided by an embodiment of the present application is shown. Specifically, the top copper layer of the substrate 2 (i.e., the copper layer on the first surface) is etched into a drain power conductive layer 201, a driving source conductive layer 132, and a driving gate conductive layer 131; the drain power terminal 302 is electrically connected to the drain power conductive layer 201, and the drain (bottom surface) of the semiconductor power chip 1 is electrically connected to the drain power conductive layer 201; the driving source 103 of the semiconductor power chip 1 is connected to the driving source conductive layer 132 through a first bonding wire 91, and is further connected to the source driving terminal 41 through a third bonding wire 93, forming a Kelvin connection to eliminate the influence of the common source inductance on the switching performance of the semiconductor power chip 1; the gate 102 of the semiconductor power chip 1 is connected to the driving gate conductive layer 131 through a second bonding wire 92, and is further connected to the gate driving terminal 42 through a fourth bonding wire 94; the above-mentioned parts are mechanically supported and insulated by the insulating layer 24 of the substrate 2 and are covered by the packaging shell 50.

[0237] Referring to FIG3 , which shows a circuit schematic diagram of the package structure shown in FIG2 , the drains and power sources 101 of the two semiconductor power chips 1 are connected to form a parallel structure, and an interface for connecting to an external circuit is provided through the drain power terminal 302 and the source power terminal 301. Furthermore, the gates 102 of the two semiconductor power chips 1 are interconnected, and a connection interface with an external drive circuit is provided through the gate drive terminal 42. The drive sources 103 of the two semiconductor power chips 1 are interconnected, and an external connection interface is provided through the source drive terminal 41, forming a Kelvin connection, thereby eliminating the impact of common source inductance on the switching performance of the semiconductor power chip 1.

[0238] It should be emphasized that the solution provided by the embodiments of this application, based on the parallel connection of multiple semiconductor power chips, allows for a larger cross-section of the source power terminal 301 and a larger cross-section of the drain power terminal 302. This shortens the length and increases the cross-sectional area of ​​the power terminals, thereby improving current carrying capacity.

[0239] In some examples of the present application, the substrate 2 includes an insulating layer 24, the insulating layer 24 has at least a first surface, and a drain power conductive layer 201 is provided on the first surface; multiple semiconductor power chips 1 are arranged on the drain power conductive layer 201, and the drains of the multiple semiconductor power chips 1 are electrically connected to the drain power conductive layer 201, and the drain power terminal 302 is electrically connected to the drain power conductive layer 201.

[0240] It should be noted that the drain of the semiconductor power chip 1 is located on its bottom surface. When the drain of the semiconductor power chip 1 is electrically connected to the drain power conductive layer 201, the bottom surface of the semiconductor power chip 1 can be directly electrically connected to the drain power conductive layer 201 on the substrate 2.

[0241] In some examples of the present application, a driving gate conductive layer 131 is further provided on the first surface, the gates 102 of multiple semiconductor power chips 1 are electrically connected to the driving gate conductive layer 131 , and the gate driving terminal 42 is electrically connected to the driving gate conductive layer 131 .

[0242] In some examples of the present application, a driving source conductive layer 132 is further provided on the first surface, the driving sources 103 of multiple semiconductor power chips 1 are electrically connected to the driving source conductive layer 132 , and the source driving terminal 41 is electrically connected to the driving source conductive layer 132 .

[0243] In some examples of the present application, the drain power conductive layer 201 , the driving source conductive layer 132 , and the driving gate conductive layer 131 extend in the same direction and are arranged in parallel and spaced apart.

[0244] Referring to Figure 5 , the first surface is provided with a drain power conductive layer 201, a driving source conductive layer 132, and a driving gate conductive layer 131. Each of the drain power conductive layer 201, the driving source conductive layer 132, and the driving gate conductive layer 131 is spaced apart and arranged parallel to one another. This layout increases the current carrying capacity of the device while reducing parasitic inductance.

[0245] Referring to FIG5 , when multiple target package units are provided on the substrate 2, the multiple target package units are collectively provided on the drain power conductive layer 201 and are sequentially spaced apart along the lateral direction of the first surface. The drain power conductive layer 201, the driver source conductive layer 132, and the driver gate conductive layer 131 are sequentially spaced apart and parallel along the longitudinal direction of the first surface. A first bonding wire 91 extending from each driver source 103 is connected to the driver source conductive layer 132, and a second bonding wire 92 extending from each gate 102 is connected to the driver gate conductive layer 131.

[0246] 5 , multiple target packaging units can be arranged laterally. In this case, the size of the substrate 2 is laterally expanded, and the source drive terminal 41 and the gate drive terminal 42 are drawn out from the middle of the device. The remaining features are consistent with those shown in FIG. 2 .

[0247] In some examples of the present application, referring to FIG6 , the drain power conductive layer 201 includes a first portion and a second portion. The first portion is arranged along a horizontal direction (i.e., an extension direction), and the second portion is arranged perpendicular to the horizontal direction (i.e., a longitudinal direction). The first and second portions form a T-shaped structure. Multiple semiconductor power chips 1 are disposed in the second portion of the drain power conductive layer 201.

[0248] 6 , a plurality of target package units are disposed on the drain power conductive layer 201 and are sequentially spaced apart along the longitudinal direction of the first surface.

[0249] That is to say, the multiple target packaging units can also be arranged in a longitudinal extension along the substrate 2 and are not limited to the horizontal layout in the aforementioned example, thereby improving the flexibility of the packaged chip layout.

[0250] In some examples of the present application, referring to FIG. 6 , the driving source conductive layer 132 and the driving gate conductive layer 131 are disposed around the second portion of the drain power conductive layer 201 .

[0251] Specifically, referring to Figure 6, multiple target packaging units can be arranged longitudinally, and the size of the substrate 2 is expanded longitudinally accordingly. On the first surface of the substrate 2, the driving source conductive layer 132 and the driving gate conductive layer 131 surround a portion of the drain power conductive layer 201 from both sides. At this time, the driving source 103 and the gate 102 of the semiconductor power chip 1 are connected to the driving copper layer (i.e., the driving source conductive layer 132 and the driving gate conductive layer 131) on the surface of the substrate 2 from both sides through bonding wires. This layout method can increase the number of semiconductor power chips 1 while maintaining the appropriate size of the single tube and avoiding excessive differences in the length and width of the single tube.

[0252] In some examples of the present application, referring to FIG1 , the drain of the semiconductor power chip 1 is arranged on the bottom surface, the drain of the semiconductor power chip is welded on the drain power conductive layer 201, and a first solder layer 31 is formed between the bottom surface of the semiconductor power chip 1 and the drain power conductive layer 201, or the bottom surface of the semiconductor power chip 1 is sintered to the drain power conductive layer 201.

[0253] In some examples of the present application, referring to FIG1 , the power source electrodes 101 of multiple semiconductor power chips 1 are all arranged on the top surface, the source power terminal 301 is welded on the power source electrode on the top surface of the semiconductor power chip 1, and a second solder layer 32 is formed between the source power terminal 301 and the top surface of the semiconductor power chip 1, or the source power terminal 301 is sintered to the top surface of the semiconductor power chip 1.

[0254] In some examples of the present application, referring to FIG. 1 , the drain power terminal 302 is soldered on the drain power conductive layer 201 , and a third solder layer 33 is formed between the drain power terminal 302 and the drain power conductive layer 201 , or the drain power terminal 302 is sintered to the drain power conductive layer 201 .

[0255] That is to say, the semiconductor power chip 1 can be electrically connected to the substrate 2 through the first solder layer 31 located at the bottom. Of course, the electrical connection between the two can also be achieved by sintering.

[0256] The drain power terminal 302 can be electrically connected to the substrate 2 via the third solder layer 33 at the bottom. Of course, the electrical connection between the two can also be achieved by sintering.

[0257] In some examples of the present application, referring to FIG. 1 , the source power terminal 301 includes a first buffer metal layer 61 , and the first buffer metal layer 61 is connected to the second solder layer 32 .

[0258] The material of the first buffer metal layer 61 includes metal molybdenum.

[0259] In some examples of the present application, referring to FIG. 1 , the drain power terminal 302 includes a second buffer metal layer 62 , and the second buffer metal layer 62 is connected to the third solder layer 33 .

[0260] The material of the second buffer metal layer 62 includes metal molybdenum.

[0261] The top surface of the semiconductor power chip 1 can be connected to the first buffer metal layer 61 via the second solder layer 32, and the substrate 2 can be connected to the second buffer metal layer 62 via the third solder layer 33. The first buffer metal layer 61 and the second buffer metal layer 62 are respectively connected to the source power terminal 301 and the drain power terminal 302. By adding the metal buffer layer, the reliability of the entire device can be improved.

[0262] Optionally, the source power terminal 301 and the drain power terminal 302 are made of copper.

[0263] Optionally, the first buffer metal layer 61 and the second buffer metal layer 62 may be made of molybdenum. This is because, in theory, welding metal can conduct electricity, but directly welding copper may cause a large difference in thermal expansion coefficient and damage the semiconductor power chip 1. Therefore, an additional metal layer is added to act as a buffer.

[0264] In some examples of the present application, as shown in FIG4 , the drain power terminal 302 is a copper sheet. One end of the copper sheet is electrically connected to the drain power conductive layer 201 , and the end of the copper sheet facing away from the drain power conductive layer 201 extends to and adheres to the top surface of the package housing 50 .

[0265] According to the above example, Figure 4 shows an implementation method of replacing the drain power terminal 302 in the solution of the present application. The drain power terminal 302 uses a copper sheet to replace the copper terminal, and can be electrically connected to the drain power conductive layer 201 on the first surface of the substrate 2 by ultrasonic welding, laser welding, etc., thereby reducing costs.

[0266] In some examples of the present application, referring to FIG. 1 , the insulating layer 24 further has a second surface 27 , which is opposite to the first surface. A copper layer is formed on the second surface 27 , and the copper layer is exposed from the package housing 50 .

[0267] The second surface 27 is a copper layer located at the bottom of the substrate 2 and can be used for bottom surface heat dissipation.

[0268] In the packaging solution of the present application, the top surfaces of the source power terminal 301 and the drain power terminal 302 are exposed from the packaging shell 50 and can also play a certain role in heat dissipation, so that the entire device can achieve double-sided heat dissipation on the top and bottom.

[0269] In related technologies, semiconductor packaging structures are typically equipped with semiconductor power chips. However, the dynamic current distribution of these chips is low, and the individual semiconductor power chips are not turned on or off synchronously. Therefore, a new technical solution is needed to address these technical issues. According to an embodiment of the second aspect of the present application, another semiconductor packaging structure 100 is provided.

[0270] As shown in Figures 7 to 16 , the package structure includes: multiple semiconductor power chips 1; and a substrate 2. The multiple semiconductor power chips 1 are disposed on the substrate 2. Drive conductors are also disposed on the substrate 2. The drive conductors are adapted to transmit drive signals to the multiple semiconductor power chips 1 and are disposed between the multiple semiconductor power chips 1.

[0271] Specifically, the semiconductor power chip 1 can be but is not limited to a metal-oxide-semiconductor field-effect transistor (i.e., a MOSFET chip) or an insulated gate bipolar transistor (i.e., an IGBT chip). The control electrode can control the on / off of the power semiconductor power chip 1. Take the MOSFET chip as an example for illustration. The MOSFET chip includes a source, a drain, and a gate. The gate controls the on / off of the source and the drain. The IGBT chip includes a collector, an emitter, and a gate. The emitter of the IGBT chip is connected to the source of the MOSFET chip. The collector of the IGBT chip is connected to the drain of the MOSFET chip. The substrate 2 is used to package the semiconductor power chip 1. The substrate 2 is provided with terminals for connecting to an external circuit, such as a drive terminal, a power terminal, etc. The above-mentioned terminals are electrically connected to the corresponding electrodes of the semiconductor power chip 1.

[0272] In this example, the substrate 2 is also used to secure the semiconductor power chips 1. For example, the substrate 2 further includes an insulating layer 24. Drive conductors are disposed on the insulating layer 24. The drive conductors are connected to the multiple semiconductor power chips 1 to transmit drive signals to the multiple semiconductor power chips 1. The drive signals are used to control the on and off operation of the semiconductor power chips 1.

[0273] In the present application, the driving conductor is located between the multiple semiconductor power chips 1. In this way, the distance between the driving conductor and the multiple semiconductor power chips is close or equal, thereby significantly improving the dynamic current sharing of the multiple semiconductor power chips 1 and significantly improving the synchronization of the opening and closing of each semiconductor power chip 1.

[0274] In one example, as shown in Figures 7-16, the substrate 2 includes a drain power conductive layer 201 and an insulating layer 24, the drain power conductive layer 201 is arranged on the insulating layer 24, and multiple semiconductor power chips 1 are arranged on the drain power conductive layer 201, the drain power conductive layer 201 is provided with a first notch 2111, the first notch 2111 is located between the multiple semiconductor power chips 1, and the driving conductor is arranged in the first notch 2111.

[0275] As shown in Figures 7 to 16, the substrate 2 is an AMB substrate. The material of the drain power conductive layer 201 is metal, such as gold, silver, copper, aluminum, nickel, zinc, iron, etc. The drain power conductive layer 201 is attached to the insulating layer 24. The insulating layer 24 is ceramic. For example, the drain power conductive layer 201 is arranged on the insulating layer 24 by active metal brazing. The insulating layer 24 is located on the side of the drain power conductive layer 201 away from the semiconductor power chip 1. The insulating layer 24 can play a heat conductive role, which significantly improves the heat dissipation effect of the packaging structure. In addition, the insulating layer 24 can also play an insulating role, thereby forming internal insulation of the packaging structure, without the need to set an external insulating layer 24, thereby improving the reliability of the packaging structure.

[0276] A first notch 2111 is formed by etching the drain power conductive layer 201. The shape of the first notch 2111 can be, but is not limited to, rectangular, circular, elliptical, trapezoidal, triangular, etc. The driving conductor is disposed within the first notch 2111, which ensures good insulation between the driving conductor and the drain power conductive layer 201, preventing interference between the two.

[0277] In addition, the first notch 2111 plays a positioning role, which makes the arrangement positions of the plurality of semiconductor power chips 1 and the driving conductors more accurate.

[0278] In one example, referring to Figures 7-16 , the semiconductor power chip 1 includes a drain, which is electrically connected to the drain power conductive layer 201. The drain power conductive layer 201 has a conductive function, and this arrangement facilitates the connection of the drain of the semiconductor power chip with an external circuit. Typically, the source and drain are located on two opposite surfaces of the semiconductor power chip 1. This arrangement enables the source of the semiconductor power chip to be away from the drain power conductive layer 201, thereby being exposed to the outside, which facilitates the connection of the source with an external circuit.

[0279] In one example, referring to FIG. 7 to FIG. 16 , the first notch 2111 extends along the first direction A, and the plurality of semiconductor power chips 1 are arranged around the first notch 2111 .

[0280] As shown in FIG8 , the substrate 2 is rectangular. The first direction A is, for example, the widthwise direction of the substrate 2. Multiple semiconductor power chips 1 are arranged relative to the periphery of the first notch 2111. For example, the multiple semiconductor power chips 1 are arranged on opposite sides of the first notch 2111 or around the first notch 2111. This allows the semiconductor power chips 1 to be more centrally located and the distance between the multiple semiconductor power chips 1 and the drive conductor to be closer.

[0281] In an example, a plurality of semiconductor power chips 1 are arranged along a second direction B, and the second direction B is perpendicular to the first direction A.

[0282] As shown in FIG8 , the second direction B is the long side direction of the substrate 2 . Multiple semiconductor power chips 1 are arranged along the long side direction. This approach fully utilizes the space in the second direction B of the substrate 2 .

[0283] In one example, referring to FIG. 8 , a plurality of semiconductor power chips 1 are respectively disposed on both sides of the first notch 2111 .

[0284] As shown in FIG8 , for example, two semiconductor power chips 1 are respectively arranged on both sides of the first notch 2111 along the second direction B. This approach brings the two semiconductor power chips 1 closer to the driving conductor and facilitates the connection between the driving conductor and the semiconductor power chips 1.

[0285] Of course, those skilled in the art can set the number of semiconductor power chips 1 according to actual needs, and this is not limited here.

[0286] In one example, the multiple semiconductor power chips 1 on both sides of the first notch 2111 are arranged along the first direction A. As shown in FIG16 , the two semiconductor power chips 1 on the same side of the first notch 2111 are arranged along the first direction A. In this way, the space of the substrate 2 along the first direction A is fully utilized. The multiple semiconductor power chips 1 on the same side are closer to the driving conductor. Of course, more semiconductor power chips 1 can be arranged on the same side of the first notch 2111, and those skilled in the art can select the number of semiconductor power chips 1 according to actual needs.

[0287] In one example, a plurality of semiconductor power chips 1 are symmetrically arranged along the axis of the first notch 2111. As shown in FIG8 , the two semiconductor power chips 1 are symmetrically arranged relative to the axis of the first notch, and the axis of the first notch is the axis of the center position of the notch along the extension direction in the figure. The symmetry can also be a mirror symmetry. The gates 102 of the two semiconductor power chips are both facing the first notch 2111. This arrangement makes it possible for the lengths of the bonding wires connecting the corresponding electrodes to be substantially equal during electrical connection, thereby achieving good dynamic flow uniformity of the plurality of semiconductor power chips 1 and good synchronization of opening and closing of each semiconductor power chip 1. When hot, the number of semiconductor power chips 1 is not limited thereto, and those skilled in the art can set it according to actual needs.

[0288] In one example, the distances from the drive conductors to the multiple semiconductor power chips 1 on both sides of the first notch 2111 are the same. As shown in FIG8 , the distances from the multiple semiconductor power chips 1 to the drive conductors are the same, which ensures that the lengths of the bonding wires connecting the drive conductors to the corresponding electrodes of the semiconductor power chips 1 are the same, thereby achieving good dynamic current balancing among the multiple semiconductor power chips 1 and good synchronization in turning on and off the semiconductor power chips 1.

[0289] In one example, the drain power conductive layer 201 further defines a second notch 2112 extending along the second direction B. The second notch 2112 communicates with the first notch 2111 . The driving conductor is disposed in the first notch 2111 and the second notch 2112 .

[0290] As shown in Figures 8 and 10, the shape of the second notch 2112 can be, but is not limited to, rectangular, circular, elliptical, triangular, or trapezoidal. The second notch 2112 is connected to the first notch 2111. The driving conductor is located within the first notch 2111 and the second notch 2112. The driving conductor is strip-shaped. The first notch 2111 and the second notch 2112 facilitate routing of the driving conductor and connection of the driving conductor to external circuits.

[0291] In one example, the edge of the second notch 2112 extends to the edge of the substrate 2. As shown in Figures 8 and 10, the first notch 2111 is located in the middle of the substrate 2, and the second notch 2112 is located at the edge of the substrate 2. The drive conductor extends from the middle of the substrate 2 to the edge. At the edge, the drive conductor is directly or indirectly connected to an external circuit. This facilitates electrical connection between the semiconductor power chip 1 and the external circuit.

[0292] In one example, the first notch 2111 and the second notch 2112 are vertically connected, and the shape of the driving conductor matches the overall shape of the first and second notches 2111 and 2112. As shown in Figures 8 to 10, the first and second notches 2111 and 2112 are both rectangular, with the long side of the first notch 2111 parallel to the first direction A. The long side of the second notch 2112 is parallel to the second direction B. The overall shape of the first and second notches 2111 and 2112 is L-shaped, and the overall shape of the driving conductor can be a matching L-shape, but they are spaced apart and not electrically connected. In some embodiments, matching can also mean that the shapes are not exactly the same, but the general outlines of the two are similar, except that they are spaced apart and not electrically connected. The driving conductor is located within the first and second notches 2111 and 2112. The portion of the driving conductor located within the first notch 2111 is used to connect to multiple semiconductor power chips 1. The portion of the driving conductor located within the second notch 2112 is used to connect to external circuits. This arrangement facilitates the connection of the driving conductor to multiple semiconductor power chips and external circuits.

[0293] In an example, the drain power conductive layer 201 is provided with a plurality of first notches 2111 , and at least one semiconductor power chip 1 is provided around each first notch 2111 .

[0294] As shown in FIG15 , the drain power conductive layer 201 is provided with two first notches 2111. Both first notches 2111 are parallel to the first direction A. Both first notches 2111 are connected to the second notch 2112. Two semiconductor power chips 1 are disposed around each first notch 2111. This arrangement enables the semiconductor package structure 100 to integrate more semiconductor power chips 1, thereby improving the operating efficiency of the semiconductor package structure 100.

[0295] Of course, the number of the first notches 2111 can also be 2, 3, 4, 5 or more, and 1, 3, 4, 5 or more semiconductor power chips can be arranged around each first notch 2111, without being limited to the above embodiments.

[0296] 15 , the driving conductor includes a first conductor 221 and a second conductor 222 for connecting to the plurality of semiconductor power chips 1. A clearance region 223 is formed between the first conductor 221 and the second conductor 222. The first conductor 221 and the second conductor 222 are connected via bonding wires (e.g., gate clearance region bonding wires 77).

[0297] In an example, the semiconductor power chip 1 includes a gate 102 , and the driving conductor includes a driving gate conductive layer 131 , i.e., a gate driving conductor. The driving gate conductive layer 131 is electrically connected to the gate 102 , and the driving gate conductive layer 131 is led out through the first notch 2111 and / or the second notch 2112 .

[0298] As shown in Figures 8 and 13, the driving gate conductive layer 131 is used to transmit driving signals and is L-shaped. One end of the driving gate conductive layer 131 is located within the first notch 2111 and is electrically connected to the gates 102 of the multiple semiconductor power chips 11. The other end of the driving gate conductive layer 131 is led out of the second notch 2112. In this example, the driving gate conductive layer 131 has a simple structure and is easily connected to the multiple semiconductor power chips 1 and external circuits.

[0299] Of course, the extraction position of the driving gate conductive layer 131 is not limited to the above embodiment, and those skilled in the art can determine the extraction position according to the positions of the first notch 2111 and the second notch 2112 .

[0300] In one example, the gate driving conductive layer 131 is electrically connected to the gate 102 via a bonding wire. As shown in FIG9 , one end of the gate driving conductive layer 131 located within the first notch 2111 is electrically connected to the gates 102 of the plurality of semiconductor power chips via gate driving bonding wires 73. Wire bonding offers a simple process and high connection stability.

[0301] Of course, the electrical connection method is not limited to the above embodiments, and those skilled in the art can make settings according to actual needs.

[0302] In one example, the semiconductor package structure 100 includes a source power terminal 301 , the semiconductor power chip 1 includes a source, and the source power terminal 301 is electrically connected to the sources of the plurality of semiconductor power chips 1 .

[0303] As shown in Figures 7 and 8 , source power terminal 301 is made of metal, such as a metal sheet. It is embedded in substrate 2 and electrically connected to an external circuit, for example, via bonding wires. Source power terminal 301 is electrically connected to the source terminals of multiple semiconductor power chips 1 via bonding wires. The provision of source power terminal 301 facilitates electrical connection between the package structure and external circuits.

[0304] In one example, the source of semiconductor power chip 1 includes a power source electrode 101, and source power terminal 301 is electrically connected to power source electrode 101. For example, as shown in FIG8 , power source electrode 101 is located within the largest rectangular region of the semiconductor power chip. Bonding wires are connected to power source electrode 101. The large area of ​​power source electrode 101 facilitates bonding wire connections.

[0305] In one example, the power source 101 of the semiconductor power chip 1 is disposed on the top surface, and the source power terminal 301 covers the top surface of the semiconductor power chip 1 and forms an electrical connection with the power source 101 .

[0306] As shown in Figures 8 and 10 , the top surface of the semiconductor power source 101 is the side of the semiconductor power source 101 facing away from the substrate 2. In this example, the source power terminal 301 covers the top surface of the semiconductor power chip and directly forms an electrical connection with the power source 101 of multiple semiconductor power chips 1, for example, by soldering. This configuration eliminates the need for bonding wires, thereby simplifying the processing and structure of the semiconductor package structure 100.

[0307] In one example, the power source 101 of the semiconductor power chip 1 is disposed on the top surface, and the source power terminal 301 is electrically connected to the power source 101 through a bonding wire.

[0308] As shown in Figure 9, unlike the above embodiment, in this example, the source power terminal 301 is electrically connected to the power source 101 via a source power terminal bonding wire 71. The electrical connection via the bonding wire can also form a stable electrical connection between the source power terminal 301 and the power source 101.

[0309] Of course, the manner in which the source power terminal 301 is electrically connected to the power source 101 is not limited to the above embodiment, and those skilled in the art can make settings according to actual needs.

[0310] In one example, the source of the semiconductor power chip 1 includes a driving source 103, the driving conductor includes a driving source conductive layer 132, i.e., a source driving conductor, the driving source conductive layer 132 is electrically connected to the driving source 103, and the driving source conductive layer 132 is led out through the first notch 2111 and / or the second notch 2112.

[0311] As shown in Figure 8, the driving source 103 is used to connect to the driving conductor. The driving source 103 is located in the larger rectangular area on the left side of the power source 101. It should be noted that the driving source 103 and the power source 101 are different areas of the source, and the two are at the same potential. The driving source 103 and the power source 101 are connected to different conductors and have different functions. The driving source 103 is connected to the driving conductor, such as the driving source conductive layer 132, which is used to transmit the driving signal to control the on and off of the power source 101 and the drain. The driving source conductive layer 132 is L-shaped. One end of the driving source conductive layer 132 is located in the first notch 2111, and this end is electrically connected to the driving source 103 of multiple semiconductor power chips 11. The other end of the driving source conductive layer 132 is led out from the second notch 2112. In this example, the structure of the driving source conductive layer 132 is simple and easy to connect to multiple semiconductor power chips 1 and external circuits.

[0312] Of course, the extraction position of the driving source conductive layer 132 is not limited to the above embodiment, and those skilled in the art can determine the extraction position according to the positions of the first notch 2111 and the second notch 2112 .

[0313] In one example, the driving source conductive layer 132 and the driving gate conductive layer 131 are arranged in parallel and spaced apart.

[0314] As shown in Figures 8, 9, and 12 to 16, the driving source conductive layer 132 and the driving gate conductive layer 131 are both strip-shaped, arranged in parallel with a gap between them. This effectively prevents interference between the signals transmitted by the driving source conductive layer 132 and the driving gate conductive layer 131.

[0315] In one example, the semiconductor package structure 100 includes a source driving terminal 41 , and the driving source conductive layer 132 is electrically connected to the source driving terminal 41 .

[0316] As shown in Figures 8, 9, and 10, the end of the driving source conductive layer 132 facing away from the driving source 103 is electrically connected to the source driving terminal 41. The source driving terminal 41 is used to electrically connect to an external circuit. In this way, the electrical connection between the semiconductor package structure 100 and the external circuit becomes easier.

[0317] In one example, the driving source conductive layer 132 is electrically connected to the source driving terminal 41 via a bonding wire. As shown in FIG9 , the driving source conductive layer 132 is electrically connected to the source driving terminal 41 via a source driving terminal bonding wire 75. The bonding wire has a simple structure, a simple processing process, and low cost, and enables the driving source conductive layer 132 to form a stable connection with the source driving terminal 41.

[0318] In one example, the semiconductor package structure 100 includes a gate driving terminal 42 , and the driving gate conductive layer 131 is electrically connected to the gate driving terminal 42 .

[0319] As shown in Figures 8, 9, and 10, the end of the gate driving conductive layer 131 facing away from the gate is electrically connected to the gate driving terminal 5. The gate driving terminal 42 is embedded in the substrate 2. This arrangement makes it easy to electrically connect the gate driving conductive layer 131 to the external circuit.

[0320] In one example, the gate drive conductive layer 131 is electrically connected to the gate drive terminal 42 via a bonding wire. As shown in FIG9 , the gate drive conductive layer 131 is electrically connected to the gate drive terminal 42 via a gate drive conductor bonding wire 76. The bonding wire has a simple structure, a simple processing process, and low cost, and enables a stable connection between the gate drive conductive layer 131 and the gate drive terminal 42.

[0321] It should be noted that in the embodiments shown in Figures 8, 9, 10, 13, 14, 15, and 16, the source drive terminal 41 is connected to the drive source 103 of multiple semiconductor power chips 1 through an independent line. Figure 12 shows a circuit diagram of the Kelvin connection. Multiple semiconductor power chips 1 are connected in parallel. The gates of multiple semiconductor power chips 1 are connected to the drive gate conductive layer 131, and are connected to the gate drive terminal 42 through the drive gate conductive layer 131. This connection method forms a Kelvin connection. The Kelvin connection can significantly reduce the impact of the common source inductance of the packaging structure on the switching performance of the semiconductor power chip 1.

[0322] In other examples, the Kelvin connection may not be formed. For example, the source driver terminal 41 is electrically connected to the source power terminal 301 .

[0323] In this example, the source driver terminal 41 and the source power terminal 301 are connected via a common circuit. For example, the source power terminal 301 is connected to the power sources 101 of multiple semiconductor power chips 1. This connection does not form a Kelvin connection. However, this connection method has a simple circuit and can still achieve the conduction and disconnection of multiple semiconductor power chips 1.

[0324] Optionally, in this example, the gate driving conductive layer 131 is connected to the gate driving terminal 42 via a gate driving terminal bonding wire 76. The gate driving terminal 42 and the source driving terminal 41 are both located at a corner of the substrate so that the source power terminal 301 has a larger area.

[0325] In one example, the source driver terminal 41 and the source power terminal 301 are integrally formed. For example, the source driver terminal 41 and the source power terminal 301 are formed into an integrally formed part by cutting a metal sheet. This makes the processing and connection of the two easier.

[0326] In one example, a drain power terminal 302 is provided on substrate 2 and is electrically connected to drain power conductive layer 201. As shown in FIG10 , drain power terminal 302 is embedded within substrate 2. Drain power terminal 302 is configured to electrically connect to an external circuit. This facilitates electrical connection between the drain terminals of multiple semiconductor power chips 1 and external circuits.

[0327] In one example, the drain power terminal 302 is electrically connected to the drain power conductive layer 201 via a bonding wire. As shown in FIG9 , the drain power terminal 302 is electrically connected to the drain power conductive layer 201 via a drain power terminal bonding wire 74. This bonding wire has a simple structure, a simple processing process, and low cost, and enables a stable connection between the drain power terminal 302 and the drain power conductive layer 201.

[0328] In another example, as shown in Figure 10, the drain power terminal 302 and the drain power conductive layer 201 partially overlap, and the drain power terminal 302 and the drain power conductive layer 201 are electrically connected by brazing. This method is simple to manufacture and saves the process of setting bonding wires.

[0329] In an example, the substrate 2 has a first side wall 81 and a second side wall 82 opposite to each other. The drain power terminal 302 is located on the first side wall 81 , and the source power terminal 301 is located on the second side wall 82 .

[0330] As shown in FIG8 and FIG9 , the drain power terminal 302 and the source power terminal 301 are relatively arranged on two side walls of the substrate 2 , so both can have a larger area, thereby significantly improving the current carrying capacity of the semiconductor package structure 100 .

[0331] In an example, the substrate 2 has a first sidewall 81 and a second sidewall 82 opposite to each other, and the drain power terminal 302 and the source power terminal 301 are located on the same sidewall, such as the first sidewall 81 or the second sidewall 82 .

[0332] As shown in FIG13 , the drain power terminal 302 and the source power terminal 301 are disposed on the second sidewall 82. As shown in FIG14 , the drain power terminal 302 and the source power terminal 301 are disposed on the first sidewall 81. In this arrangement, the drain power terminal 302 and the source power terminal 301 are located on the same side of the substrate 2, which facilitates connection of the drain power terminal 302 and the source power terminal 301 to external circuits.

[0333] In one example, substrate 2 includes a thermally conductive layer 25. Thermally conductive layer 25 and drain power conductive layer 201 are located on either side of insulating layer 24. For example, as shown in FIG7 , thermally conductive layer 25 is made of metal, such as copper, aluminum, or stainless steel. Thermally conductive layer 25 is secured to insulating layer 24 by bonding, deposition, or other methods. Thermally conductive layer 25 acts as a heat dissipator, dissipating heat from the insulating layer.

[0334] In one example, the substrate 2 further includes a package body 8 , which is made of insulating material. The semiconductor power chip 1 , the insulating layer 24 and the drain power conductive layer 201 are packaged in the package body 8 , and the thermal conductive layer 25 is exposed outside the package body 8 .

[0335] For example, package 8 is made of epoxy resin. Package 8 effectively protects substrate 2 and semiconductor power chip 1. For example, thermal conductive layer 25 is exposed at the bottom of package 8. Thermal conductive layer 25 dissipates heat from the bottom of package 8 to the outside, thereby not affecting the normal operation of other parts of package 8.

[0336] Of course, the material of the packaging shell 8 is not limited to epoxy resin, and can also be other insulating glue.

[0337] In one example, the drain power conductive layer 201 can be connected to the drain power terminal 302 via a first bonding wire or welding. The source is connected to the source power terminal 301 via a second bonding wire. The source and / or gate are connected to the driving conductor via a third bonding wire. At least one of the first bonding wire and the second bonding wire is perpendicular to the third bonding wire.

[0338] As shown in Figure 9, the first bonding wire is, for example, a drain power terminal bonding wire 74. The second bonding wire is, for example, a source power terminal bonding wire 71. The third bonding wire includes, for example, a source drive bonding wire 72 and a gate drive bonding wire 73. In this example, the drain power terminal bonding wire 74 is perpendicular to the source drive bonding wire 72 and the gate drive bonding wire 73. The source power terminal bonding wire 71 is perpendicular to the source drive bonding wire 72 and the gate drive bonding wire 73. The gate driving conductive layer 131 is connected to the gate drive terminal 42 through the gate drive terminal bonding wire 76. The source driving conductive layer 132 is connected to the source drive terminal 41 through the source drive terminal bonding wire 75. In this way, the coupling between the power circuit and the drive circuit can be effectively reduced, mutual interference between the two circuits is avoided, and the sensitivity of the semiconductor power chip 1 is improved.

[0339] Current single-tube transistors are typically packaged from a single power chip, offering greater flexibility. However, conventional single-tube packages have small pins and limited current capacity. Furthermore, the source power terminal is bonded to the source terminal on the power chip, with insulation and heat dissipation relying on external thermal interface materials or a plastic package. However, after bonding, the power chip experiences a significant temperature rise, resulting in unsatisfactory heat dissipation. The following describes a semiconductor package structure 100 according to an embodiment of the third aspect of the present application, with reference to Figures 17-28 , comprising: a substrate 10 and at least one semiconductor power chip 20.

[0340] Specifically, as shown in Figures 17 to 28, the substrate 10 includes a drain power conductive layer 201, a source power conductive layer 12 and a driving conductive layer 13 that are spaced apart. The source power conductive layer 12 and the driving conductive layer 13 are respectively arranged on both sides of the drain power conductive layer 201. The semiconductor power chip 20 is arranged on the drain power conductive layer 201. The drain of the semiconductor power chip 20 is electrically connected to the drain power conductive layer 201, the source of the semiconductor power chip 20 is electrically connected to the source power conductive layer 12, and the driving electrode 21 of the semiconductor power chip 20 is electrically connected to the driving conductive layer 13.

[0341] The substrate 10 includes a first metal layer, a second metal layer 15, and an insulating layer 12 disposed between the first and second metal layers 15. The first metal layer is constructed as a drain power conductive layer 201. The insulating layer 12 may be a ceramic layer that can be used to achieve internal insulation of the substrate 10 and ensure good heat dissipation capability of the substrate 10. The substrate 10 may be an AMB (Active Metal Brazing) substrate. The drain power conductive layer 201, the source power conductive layer 12, and the drive conductive layer 13 are disposed on a side of the insulating layer 12 away from the second metal layer 15. The semiconductor power chip 20 can be connected to the side of the drain power conductive layer 201 away from the insulating layer 12 through a sintering process, and the semiconductor power chip 20 is placed in the middle of the semiconductor package structure 100 to facilitate packaging of the semiconductor power chip 20 on the peripheral side of the semiconductor power chip 20.

[0342] In the semiconductor package structure 100, the drain power conductive layer 201 and the source power conductive layer 12 are spaced apart. The semiconductor power chip 20 has a source electrode, a drain electrode, and a driver electrode 21. The source electrode, drain electrode, and driver electrode 21 are part of the semiconductor power chip 20 and are functionally defined regions on the surface of the semiconductor power chip 20. The source electrode is electrically connected to the source power conductive layer 12, the drain electrode is electrically connected to the drain power conductive layer 201, and the driver electrode 21 is electrically connected to the driver conductive layer 13. The one-to-one correspondence between the electrodes of the semiconductor power chip 20 and the distributed conductive layers effectively prevents misconnections and improves the packaging efficiency of the semiconductor package structure 100.

[0343] The semiconductor package structure 100 includes a package housing 50 (e.g., a plastic package) to protect and support the semiconductor package structure 100. During the molding process, at least a portion of the substrate 10, such as the second metal layer 15, leaks out of the bottom of the package housing 50, so that the second metal layer 15 can be used to increase heat dissipation for the semiconductor package structure 100. The semiconductor power chip 20 is a SiC MOSFET semiconductor power chip.

[0344] According to the semiconductor package structure 100 of the embodiment of the present application, by providing a source power conductive layer 12 on the substrate 10, the source of the semiconductor power chip 20 is electrically connected to the source power conductive layer 12 on other components leading to the semiconductor package structure 100. This can optimize the layout of the semiconductor package structure 100 and improve the flexibility of the connection between the semiconductor power chip 20 and the various conductive layers. Furthermore, because the driving conductive layer 13 and the source power conductive layer 12 are positioned on either side of the drain power conductive layer 201, the semiconductor power chip 20 can be electrically connected to different conductive layers in different directions, thereby improving the heat dissipation of the semiconductor package structure 100 and enabling the semiconductor power chip 20 to operate stably and efficiently.

[0345] In some embodiments, as shown in FIG18 , the drain power conductive layer 201, the source power conductive layer 12, and the driving conductive layer 13 are extended along a first direction A on the substrate 10, and the source power conductive layer 12 and the driving conductive layer 13 are disposed on both sides of the drain power conductive layer 201 along the first direction A. Thus, the drain power conductive layer 201, the source power conductive layer 12, and the driving conductive layer 13 extend along the first direction A, which can reduce their width in a second direction B perpendicular to the first direction A. This facilitates reducing the width of the semiconductor package structure 100 in the second direction B, reduces the length of the connectors between the semiconductor power chip 20 disposed on the drain power conductive layer 201 and the source power conductive layer 12 and the driving conductive layer 13, and optimizes the space within the semiconductor package structure 100, thereby making the directions of the connectors between the conductive layers clearer.

[0346] In some embodiments, referring to FIG18 , the drain power conductive layer 201 includes a drain power conductive layer body 111 and an end drain power conductive portion 112. The end drain power conductive portion 112 is connected to the drain power conductive layer body 111. At least one semiconductor power chip 20 is disposed on the drain power conductive layer body 111. Thus, by disposing the semiconductor power chip 20 on the drain power conductive layer body 111, the distances between the semiconductor power chip 20 and different conductive layers are shortened. This optimizes the electrical connection between the semiconductor power chip 20 and different conductive layers while allowing heat from the semiconductor power chip 20 to be dissipated in different directions, thereby improving the heat dissipation capability of the semiconductor package structure 100.

[0347] 18 and 19 , the end drain power conductive portion 112 protrudes from the drain power conductive layer body 111 along the second direction B. The drain power conductive layer body 111 extends along the first direction A. The drain power conductive layer body 111 is located between the driving conductive layer 13 and the source power conductive layer 12. The first direction A is perpendicular to the second direction B. That is, the end drain power conductive portion 112 is provided on both sides of the drain power conductive layer body 111 along the second direction B at one end along the first direction A. The drain power conductive layer body 111 is located between the source power conductive layer 12 and the driving conductive layer 13 and is spaced apart from the source power conductive layer 12 and the driving conductive layer 13 along the second direction B. The semiconductor power chip 20 is arranged on the drain power conductive layer body 111, the source power conductive layer 12 is electrically connected to the source of the semiconductor power chip 20 on one side of the drain power conductive layer body 111 along the second direction B, and the driving conductive layer 13 is electrically connected to the driving electrode 21 of the semiconductor power chip 20 on the other side of the drain power conductive layer body 111 along the second direction B.

[0348] Therefore, the source power conductive layer 12 and the driving conductive layer 13 are arranged on both sides of the drain power conductive layer body 111 along the second direction B, and the semiconductor power chip 20 is arranged on the drain power conductive layer body 111, so that the distance between the semiconductor power chip 20 and the driving conductive layer 13 and the source power conductive layer 12 is close or equal, and the connectors for connecting the source power conductive layer 12 and the connectors for connecting the driving conductive layer 13 are distributed on both sides of the drain power conductive layer body 111 along the second direction B, which can reduce the mutual interference between the source power conductive layer 12 and the driving conductive layer 13, and optimize the semiconductor packaging structure 100.

[0349] In some embodiments, as shown in FIG18 , the source power conductive layer 12 includes an end source power conductive portion 122 and a source power conductive layer body 121. The end source power conductive portion 122 is connected to one end of the source power conductive layer body 121. The source power conductive layer body 121 extends along a first direction A, and the end source power conductive portion 122 protrudes from the source power conductive layer body 121. Specifically, the source power conductive layer body 121 extends along the first direction A and is disposed on one side of the drain power conductive layer body 111 along a second direction B. The end source power conductive portion 122 is disposed along the first direction A at an end of the source power conductive layer body 121 away from the end drain power conductive portion 112, and extends toward the driving conductive layer 13 along the second direction B. Thus, the configuration of the source power conductive layer 12 facilitates electrical connection with the semiconductor power chip 20 while fully utilizing the space within the semiconductor package structure 100.

[0350] For example, the end source power conductive portion 122 is disposed opposite the drain power conductive layer body 111, and is spaced apart from and covers the extended end of the drain power conductive layer body 111. The end source power conductive portion 122 is opposite and spaced apart from the drain power conductive layer body 111 in the first direction A. The end of the end source power conductive portion 122, which is away from the source power conductive layer body 121 along the second direction B, is flush with a side of the drain power conductive layer body 111 away from the source power conductive layer body 121 along the first direction A. The source power conductive layer 12 covers the drain power conductive layer body 111 on one side in the first direction A and on one side in the second direction B, and is spaced apart from the drain power conductive layer body 111.

[0351] Therefore, the source power conductive layer body 121 is arranged on one side of the drain power conductive layer body 111, which can facilitate the electrical connection between the source power conductive layer body 121 and the drain power conductive layer body 111, and facilitate the arrangement of the source power conductive layer 12 on the substrate 10, so that the structure of the semiconductor packaging structure 100 is more compact after the source power conductive layer 12 and the drain power conductive layer 201 arranged on the substrate 10 are arranged.

[0352] In some embodiments, as shown in FIG18 , the end drain power conductive portion 112 protrudes from both ends of the drain power conductive layer body 111, is spaced apart from and covers the ends of the source power conductive layer body 121 and the end of the driving conductive layer 13. In this embodiment, there are two end drain power conductive portions 112 . The two end drain power conductive portions 112 are disposed at one end of the drain power conductive layer body 111 away from the end source power conductive portion 122 along the first direction A, and are respectively disposed on either side of the drain power conductive layer body 111 along the second direction B, extending away from each other.

[0353] One end of the driving conductive layer 13 is opposite to one of the end drain power conductive portions 112 along the first direction A. The one end drain power conductive portion 112 and the drain power conductive layer body 111 form a covering for the one end of the driving conductive layer 13. One end of the source power conductive layer body 121, away from the end source power conductive portion 122, is opposite to the other end drain power conductive portion 112 along the first direction A. The other end drain power conductive portion 112 and the drain power conductive layer body 111 form a covering for the one end of the source power conductive layer body 121.

[0354] Thus, the source power conductive layer 12, the drain power conductive layer 201 and the driving conductive layer 13 are reasonably arranged on the substrate 10, the space on the substrate 10 is fully utilized, the length of the drain power conductive layer 201 in the second direction B and the length of the end source power conductive portion 122 in the second direction B are increased, and the source power conductive layer 12 and the drain power conductive layer 201 are conveniently electrically connected to other components.

[0355] In some embodiments, as shown in Figures 18-20, the driving conductive layer 13 includes a driving gate conductive layer 131, which extends along a first direction A. The driving electrode 21 includes a gate 102, i.e., the driving gate 102, and the driving gate conductive layer 131 is electrically connected to the driving gate 102. Therefore, the arrangement of the driving gate 102 facilitates electrical connection with the driving gate conductive layer 131, ensuring the accuracy of the connection between the driving conductive layer 13 and the driving electrode 21, and controlling the on and off of the semiconductor package structure 100.

[0356] 19 and 20 , the driving conductive layer 13 further includes a driving source conductive layer 132, which extends along a first direction A. The driving electrode 21 includes a driving source electrode 103, which is electrically connected to the driving source conductive layer 132. That is, the driving electrode 21 includes a driving gate 102 and a driving source electrode 103, and the driving conductive layer 13 includes a driving gate conductive layer 131 and a driving source conductive layer 132. The driving gate 102 is electrically connected to the driving gate conductive layer 131, and the driving source electrode 103 is electrically connected to the driving source conductive layer 132. Thus, different regions of the driving electrode 21 are electrically connected to different driving conductive layers 13, facilitating precise connections within the semiconductor package structure 100 and improving the installation speed of the semiconductor package structure 100.

[0357] In some embodiments, the driving source conductive layer 132 and the driving gate conductive layer 131 are spaced apart in a second direction B, and the second direction B is perpendicular to the first direction A. Thus, the driving source conductive layer 132 and the driving gate conductive layer 131 are spaced apart, so that interference between the driving gate conductive layer 131 and the driving source conductive layer 132 can be avoided.

[0358] In some embodiments, the driving source conductive layer 132 and the driving gate conductive layer 131 are arranged in parallel in the second direction B. Therefore, the driving source conductive layer 132 and the driving gate conductive layer 131 are arranged in parallel, which can facilitate the arrangement of the driving gate conductive layer 131 and the driving source conductive layer 132, reduce the inductance effect between the driving source conductive layer 132 and the driving gate conductive layer 131, optimize the structure of the driving conductive layer 13, and facilitate the arrangement of the driving conductive layer 13 on the substrate 10.

[0359] In some embodiments, as shown in Figures 19 and 20 , the semiconductor package structure 100 includes a drain power terminal 302, which is electrically connected to the drain power conductive layer 201. The drain power terminal 302 is disposed along a first direction A at an end of the drain power conductive layer 201 away from the end source power conductive portion 122, and is mounted on the substrate 10.

[0360] Thus, the source power terminal 301 is electrically connected to the drain power conductive layer 201, and the source power terminal 301 is arranged adjacent to the drain power conductive layer 201, which can shorten the length of the connector for electrically connecting the source power terminal 301 and the drain power conductive layer 201, optimize the arrangement of the drain power terminal 302 and the drain power conductive layer 201, and avoid the connector for electrical connection from crossing or contacting the connectors between other conductive layers to cause coupling mutual inductance.

[0361] In some embodiments, as shown in FIG19 , the semiconductor package structure 100 includes a source power terminal 301, which is electrically connected to the source power conductive layer 12. The source power terminal 301 is disposed at one end of the source power conductive layer 12 along a first direction A away from the drain power terminal 302. In this case, the source power terminal 301 and the drain power terminal 302 are respectively disposed at two ends of the substrate 10 along the first direction A. The connector extending from the drain power conductive layer 201 extends toward and is electrically connected to the drain power terminal 302, and the connector extending from the source power conductive layer 12 extends toward and is electrically connected to the source power terminal 301. Thus, interference between the connector connecting the source power terminal 301 and the source power conductive layer 12 and the connector connecting the drain power terminal 302 and the drain power conductive layer 201 can be effectively avoided, thereby improving the accuracy of the connectors connecting the corresponding conductive layers. At the same time, the distance between the connectors connecting different conductive layers can be increased, thereby reducing the possibility of coupling mutual inductance between the connectors connecting different conductive layers.

[0362] In some embodiments, the semiconductor package structure 100 further includes a driving terminal 40 electrically connected to the driving conductive layer 13. In the embodiments shown in Figures 19, 20, 21, and 23, the driving terminal 40 is disposed at one end of the substrate 10 and is located at the same end of the substrate 10 along the first direction A as the source power terminal 301. The driving terminal 40 and the source power terminal 301 are spaced apart along the second direction B, and the driving terminal 40 is opposite to the driving conductive layer 13 in the first direction A.

[0363] Furthermore, the driving terminal 40 includes a gate driving terminal 42, which is electrically connected to the driving gate conductive layer 131. The driving terminal 40 includes a source driving terminal 41, which is electrically connected to the driving source conductive layer 132. The source driving terminal 41 and the driving source conductive layer 132 are arranged opposite to each other along the first direction A, and the gate driving terminal 42 and the driving gate conductive layer 131 are arranged opposite to each other along the first direction A.

[0364] That is, the driving terminal 40 includes a gate driving terminal 42 and a source driving terminal 41, and the gate driving terminal 42 and the source driving terminal 41 are located on the same side of the substrate 10 and are spaced apart along the second direction B. To facilitate the correspondence between the driving terminal 40 and the corresponding driving conductive layer 13, the gate driving terminal 42 is opposite to the driving gate conductive layer 131 along the first direction A, and the source driving terminal 41 is opposite to the driving source conductive layer 132 along the first direction A. This ensures that the connector connecting the gate driving terminal 42 and the driving gate conductive layer 131 and the connector connecting the source driving terminal 41 and the driving source conductive layer 132 are parallel to each other, avoiding the cross-coupling mutual inductance between the two connectors, reducing the influence between the circuits where the gate driving terminal 42 and the source driving terminal 41 are located, ensuring the performance of the circuit, improving stability, and avoiding circuit failure.

[0365] Optionally, as shown in Figures 18-23, the driving terminal 40 and the source power terminal 301 are located on the same side of the substrate 10. The driving conductive layer 13 and the source power conductive layer 12 both extend along the first direction A and are spaced apart along the second direction B. The driving terminal 40 and the source power terminal 301 are located on the same side. This facilitates the placement of the driving terminal 40 adjacent to and electrically connected to the driving conductive layer 13, and the placement of the source power terminal 301 adjacent to and electrically connected to the source power conductive layer 12. This optimizes the internal space of the semiconductor package structure 100 and the arrangement of the conductive layers and terminals therein, thereby facilitating a miniaturized design of the semiconductor package structure 100.

[0366] In some embodiments, the drain electrode of the semiconductor power chip 20 is welded to the drain power conductive layer 201 to form an electrical connection. That is, the semiconductor power chip 20 can be mounted on the drain power conductive layer 201 by welding, thereby forming an electrical connection between the drain electrode of the semiconductor power chip 20 and the drain power conductive layer 201. As a result, the welding process is simple and has good reliability.

[0367] In some embodiments, the source electrode of the semiconductor power chip 20 is electrically connected to the source power conductive layer 12 via a bonding wire. Thus, the bonding wire connection method is simple and direct, which can improve the connection efficiency. Furthermore, the bonding wire has stable chemical properties and is not likely to form intermetallic compounds that may affect the semiconductor power chip 20. Furthermore, the bonding wire connection between the source electrode and the source power conductive layer 12 can provide a strong bonding force and good plasticity, allowing the source electrode and the source power conductive layer 12 to maintain a certain geometric shape during the bonding process, thereby improving the stability and reliability of the semiconductor package structure 100.

[0368] In some embodiments, as shown in Figures 18 and 19, the source includes a power source 101 (or source power lead-out terminal 101), and the source of the semiconductor power chip 20 is electrically connected to the source power conductive layer 12 through the source power lead-out terminal 101 (or power source 101). For example, the source includes two source power lead-out terminals 101, which are spaced apart at the source, and the two source power lead-out terminals 101 are respectively electrically connected to the source power conductive layer 12, and form a loop through the arrangement of bonding wires. Therefore, the arrangement of the source lead-out terminals ensures the accuracy of the bonding wire bonding position and the bonding quality when the source is connected to the source power terminal 301.

[0369] In some embodiments, referring to Figures 18-20 , the driving electrode 21 of the semiconductor power chip 20 is electrically connected to the driving conductive layer 13 via a bonding wire. Thus, by bonding the driving electrode 21 to the corresponding driving conductive layer 13 via a bonding wire, the stability of the electrical connection between the driving electrode 21 and the driving conductive layer 13 can be ensured.

[0370] In some embodiments, as shown in Figures 18-21 , there are multiple semiconductor power chips 20, and the multiple semiconductor power chips 20 are spaced apart on the drain power conductive layer 201 along a first direction A. The multiple semiconductor power chips 20 are spaced apart on the drain power conductive layer body 111 along the first direction A. The arrangement direction of the semiconductor power chips 20 is the same as the extension direction of the drain power conductive layer body 111. This increases the utilization of the space of the drain power conductive layer 201 by the semiconductor power chips 20, facilitates the parallel design of multiple semiconductor power chips 20, and improves the current carrying capacity of the semiconductor package structure 100.

[0371] In some embodiments, as shown in Figure 23, the drain power conductive layer 201 includes a plurality of drain power conductive layer bodies 111 and at least one end drain power conductive portion 112, the plurality of drain power conductive layer bodies 111 are spaced apart along the second direction B, and each drain power conductive layer body 111 is provided with at least one semiconductor power chip 20, and the second direction B is perpendicular to the extension direction of the drain power conductive layer body 111.

[0372] In this embodiment, to increase the number of semiconductor power chips 20 that can be provided, reduce the volume of the semiconductor package structure 100 (e.g., reduce the length of the drain power conductive layer body 111 in the first direction A), and facilitate the use of the semiconductor package structure 100 in specific scenarios, the drain power conductive layer 201 includes a plurality of drain power conductive layer bodies 111. The plurality of drain power conductive layer bodies 111 are spaced apart along the second direction B and extend along the first direction A. At least one semiconductor power chip 20 is provided on each drain power conductive layer body 111. If multiple semiconductor power chips 20 are provided on each drain power conductive layer body 111, the plurality of semiconductor power chips 20 are spaced apart along the length direction of the drain power conductive layer body 111.

[0373] Furthermore, as shown in FIG23 , there are multiple semiconductor power chips 20, and the multiple semiconductor power chips 20 include at least a first semiconductor power chip group 28 and a second semiconductor power chip group 23. The first semiconductor power chip group 28 includes multiple first semiconductor power chips 220, and the second semiconductor power chip group 23 includes multiple second semiconductor power chips 231. The multiple drain power conductive layer bodies 111 include at least a first drain power conductive layer body 111 and a second drain power conductive layer body 111 spaced apart along a second direction B. The multiple first semiconductor power chips 220 are spaced apart from each other along a first direction A on the first drain power conductive layer body 111, and the multiple second semiconductor power chips 231 are spaced apart from each other along the first direction A on the second drain power conductive layer body 111. The first direction A is the same as the direction in which the drain power conductive layer body 111 extends. The number of drain power conductive layer bodies 111 spaced apart along the second direction B is not specifically limited. For example, it includes but is not limited to two. The number of semiconductor power chips 20 disposed on each drain power conductive layer body 111 includes but is not limited to one, and may be two or more. A reasonable selection can be made based on the location and usage conditions of the semiconductor package structure 100 and the power required.

[0374] Therefore, the setting of multiple semiconductor power chip groups can enable multiple semiconductor power chips 20 to be expanded and arranged in the second direction B of the substrate 10, increase the number of semiconductor power chips 20, improve the current carrying capacity of the semiconductor packaging structure 100, avoid mutual interference between the bonding wires used for electrical connection between multiple semiconductor power chips 20, and reduce parasitic inductance and resistance introduced when packaging semiconductors.

[0375] As shown in Figure 23, there are multiple source power conductive layers 12, and the multiple source power conductive layers 12 include at least a first source power conductive layer 123 and a second source power conductive layer 124. The first source power conductive layer 123 is arranged adjacent to the first drain power conductive layer body 111, and the second source power conductive layer 124 is arranged adjacent to the second drain power conductive layer body 111.

[0376] For example, the first source power conductive layer 123 and the second source power conductive layer 124 are spaced apart along the second direction B, and the first source power conductive layer 123 is opposite to the first drain power conductive layer body 111, while the second source power conductive layer 124 is opposite to the second drain power conductive layer body 111. The first source power conductive layer 123 includes a first source power conductive layer body 121 and a first end source power conductive portion 122 connected to each other. The first source power conductive layer body 121 is disposed along the second direction B on a side of the first drain power conductive layer body 111 away from the second drain power conductive layer body 111, and the first end source power conductive portion 122 is disposed along the first direction A on a side of the first drain power conductive layer body 111 away from the end drain power conductive portion 112. The second source power conductive layer 124 includes a second source power conductive layer body 121 and a second end source power conductive portion 122 connected to each other. The second source power conductive layer body 121 is arranged on a side of the second drain power conductive layer body 111 away from the first drain power conductive layer body 111 along the second direction B, and the second end source power conductive portion 122 is arranged on a side of the second drain power conductive layer body 111 away from the end drain power conductive portion 112 along the first direction A.

[0377] Therefore, the arrangement of the first and second source power conductive layers 124 facilitates the first and second source power conductive layers 124 to be opposite to the first and second drain power conductive layer bodies 111, and facilitates the bonding wires led out from the semiconductor power chips 20 arranged on the first and second drain power conductive layer bodies 111 to be electrically connected to the corresponding source power conductive layer bodies 121 along the second direction B in a direction away from each other, thereby avoiding mutual inductance caused by the proximity or crossing of the bonding wires used for electrical connection, reducing mutual interference between the circuit where the first source power conductive layer 123 is located and the circuit where the second source power conductive layer 124 is located, effectively improving the heat dissipation of the semiconductor packaging structure 100, and avoiding bonding wire confusion when connected through bonding wires.

[0378] Each drain power conductive layer body 111 is provided with multiple semiconductor power chips 20. The multiple semiconductor power chips 20 are connected in parallel in the substrate 10. The bonding wires on two adjacent semiconductor power chips 20 are arranged at intervals to avoid mutual interference between the inductances on the bonding wires connecting different semiconductor power chips 20.

[0379] Optionally, in an embodiment of the present application, in combination with Figure 21, there can be more than two semiconductor power chips 20, such as four, and the four semiconductor power chips 20 are arranged on the drain power conductive layer body 111 at intervals along the first direction A. At this time, the size of the drain power conductive layer body 111 can be increased to meet the arrangement requirements of a larger number of semiconductor power chips 20, thereby realizing a parallel design of multiple semiconductor power chips 20 to improve the current carrying capacity of the semiconductor packaging structure 100.

[0380] As shown in FIG22 , according to the equivalent circuit diagram of the embodiment of the present application, the drain power conductive layer 201 and the source power conductive layer 12 of the multiple semiconductor power chips 20 are respectively connected to form a parallel structure between the multiple semiconductor power chips 20, and the drain power terminal 302 electrically connected to the drain power conductive layer 201 and the source power terminal 301 electrically connected to the source power conductive layer 12 provide an interface for connecting to an external circuit. The gates of the multiple semiconductor power chips 20 are electrically connected to the driving gate conductive layer 131 and are connected to the connection interface of the external driving circuit through the gate driving terminal 42. The sources of the multiple semiconductor power chips 20 are electrically connected to the driving source conductive layer 132 and are provided with an external connection interface through the source driving terminal 41, forming a Kelvin connection to eliminate the influence of the common source inductance on the switching performance of the semiconductor power chip 20. Among them, the Kelvin connection is a simple method for eliminating the influence of the voltage drop generated on the wire in the circuit.

[0381] In some embodiments, as shown in Figures 18-24, the semiconductor package structure 100 further includes at least one source power terminal 301, which is electrically connected to multiple source power conductive layers 12. Specifically, the source power terminal 301 is disposed on one side of the substrate 10, electrically connected to the source power conductive layer 12, and the source power conductive layer 12 is electrically connected to the semiconductor power chip 20. Thus, the provision of the source power conductive layer 12 enables the source power terminal 301 to be electrically connected to the source electrode of the semiconductor power chip 20 through the source power conductive layer 12, avoiding direct bonding between the source power terminal 301 and the semiconductor power chip 20. Furthermore, the contact between the source power terminal 301 and the substrate increases the heat dissipation capability of the source power terminal 301, reduces the heat generated by the semiconductor power chip 20, improves the heat dissipation capability of the semiconductor power chip 20, and ensures the performance of the semiconductor power chip 20. At the same time, the arrangement of the bonding wires electrically connecting the source power terminal 301 and the semiconductor power chip 20 is more free and flexible, thereby avoiding coupling mutual inductance with the bonding wires of other circuits.

[0382] In some embodiments, referring to FIG23 , the source power terminal 301 includes at least a first source power terminal portion 321 and a second source power terminal portion 322. The first source power terminal portion 321 is electrically connected to the first source power conductive layer 123, and the second source power terminal portion 322 is electrically connected to the second source power conductive layer 124. The first source power terminal portion 321 and the second source power terminal portion 322 are opposite to the first source power conductive layer 123 and the second source power conductive layer 124, respectively. The first source power terminal portion 321 and the second source power terminal portion 322 are spaced apart along the second direction B so that the source power terminal 301 can be electrically connected to two source power conductive layers 12 simultaneously. This allows the bonding wires used to connect different source power conductive layers 12 to the source power terminal 301 to be reasonably distributed within the semiconductor package structure 100, avoiding cross-interference between the bonding wires.

[0383] In some embodiments, referring to Figures 23-24 , one end of the driving conductive layer 13 is located between multiple drain power conductive layer bodies 111 and is configured to electrically connect to the driving electrodes 21 of multiple semiconductor power chips 20. The driving conductive layer 13 is disposed between two drain power conductive layer bodies 111 along the second direction B and is spaced apart from the drain power conductive layer bodies 111. The drain power conductive layer body 111 is disposed between the source power conductive layer 12 and the driving conductive layer 13 along the second direction B. The bonding wires extending from the source electrode of the semiconductor power chip 20 and the bonding wires extending from the driving electrode 21 extend away from each other along the second direction B to the source power conductive layer 12 and the driving conductive layer 13 in corresponding directions.

[0384] Therefore, the driving conductive layer 13 and the source power conductive layer 12 are arranged on both sides of the drain power conductive layer body 111 along the second direction B, that is, on both sides of the semiconductor power chip 20, so that the bonding wires led out from the source of the semiconductor power chip 20 and the bonding wires led out from the driving electrode 21 can extend in different directions, increasing the distance between the driving circuit where the driving conductive layer 13 is located and the power circuit where the source power conductive layer 12 is located, avoiding the bonding wires connecting the source and the bonding wires connecting the driving electrode 21 from being close to or intersecting, which can greatly reduce the coupling mutual inductance between the power circuit where the source power conductive layer 12 is located and the driving circuit where the driving conductive layer 13 is located, and reduce the impact of the current change in the power circuit on the driving circuit.

[0385] Furthermore, as shown in FIG. 23 and in conjunction with FIG. 18 , the semiconductor package structure 100 further includes a drive terminal 40, to which the other end of the drive conductive layer 13 is electrically connected. The drive terminal 40 is disposed on one side of the substrate 10 along the first direction A. The drive terminal 40 is electrically connected to the drive conductive layer 13 to enable communication with an external circuit or device. The drive terminal 40 disposed on the substrate can improve heat dissipation of the drive terminal 40.

[0386] The driving conductive layer 13 includes a driving conductive layer body 133 and an end driving conductive portion 134. The driving conductive layer body 133 is located between two adjacent drain power conductive layer bodies 111, and the end driving conductive portion 134 is electrically connected to the driving terminal 40. Specifically, the driving conductive layer 13 includes the driving conductive layer body 133 and the end driving conductive portion 134. The driving conductive layer body 133 is located between two adjacent drain power conductive layer bodies 111, and the end driving conductive portion 134 is located at one end of the driving conductive layer body 133 away from the end drain power conductive portion 112 along the first direction A, extending toward the driving terminal 40, and capable of achieving electrical connection to the driving terminal 40 via bonding wires. In this embodiment, the end driving conductive portion 134 is located between the source power conductive layer 12 and the driving terminal 40. Thus, the design of the driving conductive layer 13 facilitates the use of space on the substrate 10, allowing for clear routing of bonding wires within the semiconductor package structure 100 and avoiding mutual inductance between bonding wires.

[0387] In some embodiments, as shown in FIG24 , the drain power terminal 302 , the source power terminal 301 , and the driver terminal 40 are located on the same side of the substrate 10 . The driver terminal 40 and the source power terminal 301 are spaced apart along the second direction B. Thus, the driver terminal 40 and the source power terminal 301 are located on the same side of the substrate 10 , which can increase space utilization on the substrate 10 on the side where the source power terminal 301 is located, thereby preventing the power terminals from being connected reversely or connected to the same conductive layer, which could affect the quality of the semiconductor package structure 100 .

[0388] In this embodiment, the source power terminal 301, the drain power terminal 302, and the driving terminal 40 are disposed on the same side of the substrate 10 along the first direction A. The source power terminal 301 is disposed adjacent to the source power conductive layer 12, the drain power terminal 302 is disposed adjacent to the drain power conductive layer 201, and the driving terminal 40 is disposed adjacent to the driving conductive layer 13. The source power conductive layer 12, the drain power conductive layer 201, and the driving conductive layer 13 are spaced apart along the second direction B, and the source power conductive layer 12 and the driving conductive layer 13 are respectively disposed on either side of the drain power conductive layer 13.

[0389] That is, the driving conductive layer 13, the drain power conductive layer 201 and the source power conductive layer 12 are arranged in sequence along the second direction B, and the driving terminal 40, the drain power terminal 302 and the source power terminal 301 are arranged in sequence along the second direction B. The driving terminal 40, the drain power terminal 302 and the source power terminal 301 are respectively arranged corresponding to the driving conductive layer 13, the drain power conductive layer 201 and the source power conductive layer 12.

[0390] Thus, multiple terminals are electrically connected to the corresponding conductive layers. The above arrangement can shorten the distance between the terminals and the corresponding conductive layers and the length of the bonding wires for achieving electrical connection, optimize the semiconductor packaging structure 100, effectively avoid the influence between adjacent bonding wires, and improve the power of the semiconductor packaging structure 100 while enhancing the current carrying capacity of the semiconductor packaging structure 100.

[0391] In the above embodiment, as shown in FIG19 , electrical connections can be achieved between the semiconductor power chip 20 and the source power conductive layer 12 and the driver conductive layer 13, between the source power terminal 301 and the source power conductive layer 12, between the drain power terminal 302 and the drain power conductive layer 201, and between the driver terminal 40 and the driver conductive layer 13 via bonding wires. Bonding wires can be used to connect the drain power terminal 302 and the drain power conductive layer 201, the semiconductor power chip 20 and the source power conductive layer 12, and further connect to the source power terminal 301. The driver electrode 21 is connected to the driver conductive layer 13 via bonding wires, and further connected to the driver terminal 40. The source electrode is connected to the source power conductive layer 12 via bonding wires, forming a Kelvin connection, and further connected to the source driver terminal 41 via bonding wires.

[0392] In the above embodiment, as shown in Figures 20, 21, 23 and 24, the semiconductor power chip 20 and the source power conductive layer 12, the drain power terminal 302 and the drain power conductive layer 201, and the source power terminal 301 and the source power conductive layer 12 can all be electrically connected by copper sheets, and the drive circuits formed between other conductive layers and terminals can be connected by a bonding wire process, so that this embodiment adopts a CLIP connection method. The drain power terminal 302 is directly connected to the drain power conductive layer 201, and preferably, ultrasonic welding is used for the connection. The connection between the semiconductor power chip 20 and the source power conductive layer 12 is achieved by CLIP, and preferably, sintering is used for the connection. The source power terminal 301 is directly connected to the source power conductive layer 12, and preferably, ultrasonic welding is used for the connection.

[0393] As shown in FIG22 , according to the equivalent circuit diagram of the embodiment of the present application, the drain power conductive layer 201 and the source power conductive layer 12 of the multiple semiconductor power chips 20 are respectively connected to form a parallel structure between the multiple semiconductor power chips 20, and the drain power terminal 302 electrically connected to the drain power conductive layer 201 and the source power terminal 301 electrically connected to the source power conductive layer 12 provide an interface for connecting to an external circuit. The gates of the multiple semiconductor power chips 20 are electrically connected to the driving gate conductive layer 131 and are connected to the connection interface of the external driving circuit through the gate driving terminal 42. The sources of the multiple semiconductor power chips 20 are electrically connected to the driving source conductive layer 132 and are provided with an external connection interface through the source driving terminal 41, forming a Kelvin connection to eliminate the influence of the common source inductance on the switching performance of the semiconductor power chip 20. Among them, the Kelvin connection is a simple method for eliminating the influence of the voltage drop generated on the wire in the circuit.

[0394] Combined with Figures 25 and 26, it shows the thermal simulation of existing products, and the simulation conditions are typical operating conditions (current 200A, loss of a single semiconductor power chip 20 200W, surface temperature of the second metal layer 15 at the bottom of the substrate 10 90°C, and heat transfer coefficient of the remaining surfaces 5W / (m2K)). For the internal heat conduction of the Peninsula's packaged structure, the SiC semiconductor power chip 20 and the AMB substrate have extremely high thermal conductivity, and the thermal conductivity of the plastic packaging material is much lower than that of the AMB substrate. For external heat dissipation, the bottom surface in contact with the radiator is the main heat dissipation path, and the remaining surfaces are in contact with the air, and the heat dissipation efficiency is extremely low.

[0395] From the partial view of the terminal shown in FIG25 , it can be seen that since the source power terminal 301 is in direct contact with the SiC semiconductor power chip 20 and the temperature of the SiC semiconductor power chip 20 is relatively high during operation, the heat generated by the current flowing through the terminal cannot be conducted to the AMB substrate through the SiC semiconductor power chip 20 and can only be conducted through the packaging shell 50. Therefore, the source power terminal 301 has a very high temperature rise, and the overall temperature exceeds 130°C.

[0396] In addition, due to the influence of the high temperature of the source power terminal 301 , the overall temperature rise of the package casing 50 is also high, as shown in FIG. 26 .

[0397] As shown in Figures 27 and 28, they are the simulation results of this application under the same conditions. It can be seen from the partial view of the terminal shown in Figure 27 that in this embodiment, the source power terminal 301 is in direct contact with the AMB substrate, and the heat generated by the flow can be directly conducted to the heat dissipation bottom surface through the AMB substrate, with higher heat dissipation efficiency and extremely low temperature rise. The overall temperature of the terminal is about 93°C, which is only about 3°C ​​higher than the temperature rise of the heat dissipation bottom surface. The thermal simulation results show that in high-power applications, the solution of this embodiment has a greater flow capacity when the terminal cross-sectional area is the same. In addition, as shown in Figure 28, the area of ​​the package shell 50 affected by high temperature in this embodiment is smaller, which is conducive to improving reliability.

[0398] In related art, the power terminals of semiconductor packaging structures have poor current-carrying capacity. Furthermore, the CLIPs / bonding wires connecting the power terminals and the bonding wires of the driver terminals are too close and arranged in parallel, which introduces significant mutual coupling inductance. This can cause current changes in the power circuit where the power terminals are located to affect the driver circuit. The following describes a semiconductor packaging structure 100 according to an embodiment of the fourth aspect of the present application with reference to Figures 29-34 . The semiconductor packaging structure 100 includes: a substrate 10, at least one semiconductor power chip 20, a plurality of power terminals 30, and at least one driver terminal 40.

[0399] Specifically, as shown in Figures 29 to 34, the substrate 10 includes a drain power conductive layer 201 and a driving conductive layer 130 that are arranged at intervals. The semiconductor power chip 20 is arranged on the drain power conductive layer 201. The drain of the semiconductor power chip 20 is electrically connected to the drain power conductive layer 201. The driving electrode of the semiconductor power chip 20 is electrically connected to the driving conductive layer 130. A plurality of power terminals 30 are respectively electrically connected to the source and drain power conductive layer 201 of the semiconductor power chip 20. The driving terminal 40 is electrically connected to the driving conductive layer 130. The driving terminal 40 and the power terminal 30 are respectively located on different sides of the substrate 10.

[0400] The substrate 10 includes a first metal layer, a second metal layer 15, and an insulating layer 12 disposed between the first and second metal layers 15. The first metal layer is configured as the drain power conductive layer 201, and the second metal layer 15 is configured as a thermally conductive layer for the semiconductor package structure 100, serving as the primary heat dissipation channel for the semiconductor package structure 100. The insulating layer 12 may be a ceramic layer, which provides internal insulation for the substrate 10 and ensures good heat dissipation. The substrate 10 may be an AMB (Active Metal Brazing) substrate. The semiconductor power chip 20 is connected to the side of the drain power conductive layer 201 away from the thermally conductive layer 13 through a sintering process. The semiconductor power chip 20 is positioned in the center of the semiconductor package structure 100. A solder layer 60 is disposed between the semiconductor power chip 20 and the drain power conductive layer 201 to facilitate soldering of the semiconductor power chip 20 to the substrate 10.

[0401] On the semiconductor packaging structure 100, the drain power conductive layer 201 and the driving conductive layer 130 are arranged at intervals along the first direction A, and the drain power conductive layer 201 and the driving conductive layer 130 are arranged between the power terminal 30 and the driving terminal 40, and the power terminal 30 is arranged adjacent to the drain power conductive layer 201, and the driving terminal 40 is arranged adjacent to the driving conductive layer 130.

[0402] The fact that the drive terminal 40 and the power terminal 30 are located on different sides of the substrate 10 can be understood as meaning that the drive terminal 40 and the power terminal 30 are located on both sides of the substrate 10 along the first direction A, or that the drive terminal 40 and the power terminal 30 are located on adjacent sides of the substrate 10, thereby increasing the distance between the power terminal 30 and the drive terminal 40 and avoiding interference between the circuits of the power terminal 30 and the drive terminal 40. The drain power terminal 302 is directly connected to the drain power conductive layer 201, preferably by ultrasonic welding; the semiconductor power chip 20 is connected to the source power terminal 301, preferably by sintering.

[0403] A packaging shell 50 is formed on the semiconductor packaging structure 100 to achieve sealing of the semiconductor packaging structure 100, thereby providing protection and support for the semiconductor packaging structure 100. During the molding process, at least a portion of the substrate 10, such as the second metal layer 15, leaks out of the bottom of the packaging shell 50 to achieve heat dissipation of the semiconductor packaging structure 100. Moreover, both the power terminal 30 and the drive terminal 40 at least partially extend out of the plastic package shell to achieve connection with an external circuit. The shape of the portion extending out of the packaging shell 50 can be processed into different shapes as required to facilitate connection with an external circuit in the form of various different processes such as socket welding, surface mount welding, or laser welding. The semiconductor power chip 20 can be connected to the power terminal 30 or the drive terminal 40 by bonding wires or by CLIP (copper sheet plus bonding wire). The semiconductor power chip 20 is a SiC MOSFET semiconductor power chip.

[0404] According to the semiconductor packaging structure 100 of the embodiment of the present application, by locating the drive terminal 40 and the power terminal 30 on different sides of the substrate 10, the width of the power terminal 30 can be increased under the same device size, the current carrying capacity of the power terminal 30 is improved, and the influence of parasitic inductance on the operation of the semiconductor packaging structure 100 is reduced. In addition, the drive terminal 40 and the power terminal 30 are located on different sides, resulting in a longer distance between the power terminal 30 and the drive terminal 40, which can effectively reduce the possibility of coupling mutual inductance between the drive circuit where the drive terminal 40 is located and the power circuit where the power terminal 30 is located, thereby reducing the interference of the power circuit on the drive circuit.

[0405] Preferably, as shown in Figures 30 to 33, in this embodiment, the drive terminal 40 and the power terminal 30 are respectively located on opposite sides of the substrate 10 along the first direction A. That is, the drive terminal 40 and the power terminal 30 are located on opposite sides of the substrate 10 along the arrangement direction of the drain power conductive layer and the drive conductive layer 130, that is, the first direction A. In this case, the distance between the drive terminal 40 and the power terminal 30 is maximized, and the distance between the drive circuit where the drive terminal 40 is located and the power circuit where the power terminal 30 is located is maximized. This can prevent the drive circuit and the power circuit from crossing, effectively avoid coupling mutual inductance between the drive circuit and the power circuit, and reduce the impact of current changes in the power circuit on the drive circuit.

[0406] In some embodiments, as shown in FIG31 and FIG32 and in conjunction with FIG30 , the drain power conductive layer 201 and the driving conductive layer 130 are arranged sequentially along a first direction A. The drain power conductive layer 201 and the driving conductive layer 130 are arranged sequentially along a direction from the power terminal 30 toward the driving terminal 40. Along the first direction A, the drain power conductive layer 201 and the driving conductive layer 130 are arranged sequentially in a direction away from the power terminal 30, so that the drain power conductive layer 201 is disposed adjacent to the power terminal 30 and the driving conductive layer 130 is disposed adjacent to the driving terminal 40. This avoids electrical connection between the power terminal 30 and the drain power conductive layer 201, while also facilitating electrical connection between the driving conductive layer 130 and the driving terminal 40. This allows the power terminal 30, the driving terminal 40, the drain power conductive layer 201, and the driving conductive layer 130 to be rationally arranged on the substrate 10, thereby increasing space utilization on the substrate 10 and avoiding interference between the driving circuit and the power circuit.

[0407] In some embodiments, as shown in FIG34 and in conjunction with FIG29-30 , the drive terminal 40 is located in the middle of a side edge of the substrate 10. For example, the drive terminal 40 is provided on a side of the substrate 10 opposite the power terminal 30. The drive terminal 40 is provided on a side edge of the substrate 10 away from the power terminal 30 along a first direction A, and the drive terminal 40 is provided near the center of the substrate 10 on the side edge of the first direction A. In other words, the drive terminal 40 is provided on one side of the substrate 10 along the first direction A, and the power terminals 30 are provided on both sides of the drive terminal 40 along a second direction B. This ensures that when the drive terminal 40 is electrically connected to different semiconductor power chips 20, the bonding wires or copper sheets used for electrical connection between the drive terminal 40 and the different semiconductor power chips 20 are at equal distances. This ensures that the drive circuits between the different semiconductor power chips 20 are symmetrical about the first direction A, reduces differences between the drive circuits of the different semiconductor power chips 20, and reduces the impact of the drive circuits on the performance of the semiconductor power chips 20.

[0408] In some embodiments, as shown in Figures 30 and 31, the driving conductive layer 130 includes a driving gate conductive layer 131. The driving conductive layer 130 extends along the second direction B, and the driving gate conductive layer 131 is disposed adjacent to the driving terminal 40. The driving electrode includes a gate 102, i.e., a driving gate 102, which is electrically connected to the driving gate conductive layer 131. The driving terminal 40 is adjacent to the driving gate conductive layer 131 disposed on the substrate 10, which can shorten the length of the bonding wire between the driving terminal 40 and the driving gate conductive layer 131, thereby optimizing the space within the semiconductor package structure 100. At the same time, the driving gate 102 corresponds to the driving gate conductive layer 131 to facilitate electrical connection. The provision of the driving gate 102 helps achieve a precise connection between the semiconductor power chip 20 and the driving conductive layer 130, thereby improving the connection speed of the semiconductor package structure 100.

[0409] Furthermore, in conjunction with Figures 30 and 31 , the driving conductive layer 130 includes a driving source conductive layer 132, which extends along the second direction B and is disposed adjacent to the driving terminal 40. The driving electrode includes a driving source 103, which is electrically connected to the driving source conductive layer 132. That is, the driving conductive layer 130 includes a driving source conductive layer 132 and a driving gate conductive layer 131, and the driving electrode includes a driving gate 102 and a driving source 103. When the driving conductive layer 130 is electrically connected to the driving electrode of the semiconductor power chip 20, the driving source conductive layer 132 is electrically connected to the driving source 103, and the driving gate conductive layer 131 is electrically connected to the driving gate 102. This prevents cross-inductance between bonding wires used for connection when the semiconductor power chip 20 is electrically connected to the driving conductive layer 130, thereby improving the installation efficiency of the semiconductor package structure 100.

[0410] In some embodiments, as shown in Figures 30 to 34 , the driving source conductive layer 132 and the driving gate conductive layer 131 are parallel to each other in the first direction A. Therefore, the driving source conductive layer 132 and the driving gate conductive layer 131 are arranged in parallel, which can facilitate the arrangement of the driving gate conductive layer 131 and the driving source conductive layer 132 , reduce the inductance effect between the driving source conductive layer 132 and the driving gate conductive layer 131 , optimize the structure of the driving conductive layer 130 , and facilitate the arrangement of the driving conductive layer 130 on the substrate 10 .

[0411] Optionally, as shown in FIG30 , the driving source conductive layer 132 and the driving gate conductive layer 131 extend along the second direction B, and the power terminals 30 and the driving terminals 40 are arranged along the first direction A, with the first direction A being perpendicular to the second direction B. Thus, the position and arrangement of the driving conductive layer 130, the driving terminals 40, and the power terminals 30 on the substrate 10 can increase the utilization of the space within the substrate 10, optimize the space within the semiconductor package structure 100, and facilitate the miniaturization and integrated design of the semiconductor package structure 100.

[0412] In some embodiments, referring to FIG. 30 , the driving source conductive layer 132 and the driving gate conductive layer 131 are in the shape of long strips extending along the second direction B, thereby increasing the utilization of the space within the substrate 10 and avoiding cross-inductance between the driving source conductive layer 132 and the driving gate conductive layer 131 , which affects the flow of current.

[0413] As shown in FIG30 , the power terminal 30 includes a drain power terminal 302 and a source power terminal 301. Both the drain power terminal 302 and the source power terminal 301 are located on the same side of the substrate 10. In this embodiment, the drain power terminal 302 and the source power terminal 301 are located on the same side of the substrate 10 in the first direction A of the substrate 10. The drain power terminal 302 is electrically connected to the drain power conductive layer 201, which is electrically connected to the drain of the semiconductor power chip 20. The source power terminal 301 is electrically connected to the source 101 (i.e., the power source 101) of the semiconductor power chip 20.

[0414] Optionally, if a source power conductive layer is provided between the source power terminal 301 and the source 101 of the semiconductor power chip 20 , the source power conductive layer is electrically connected to the source power terminal 301 and the source 101 of the semiconductor power chip 20 through bonding wires or copper sheets.

[0415] In the embodiment of FIG31 , the power terminal 30 is electrically connected to the drain power conductive layer 201 and the source 101 of the semiconductor power chip 20 via bonding wires. Specifically, the power terminal 30 includes a source power terminal 301 and a drain power terminal 302. The source power terminal 301 is connected to the source 101 via bonding wires, and the drain power terminal 302 is connected to the drain power conductive layer 201 via bonding wires. Thus, the bonding wire connection facilitates electrical connection between the power terminal 30 and the semiconductor power chip 20 and the drain power conductive layer 201. Furthermore, the bonding wires can be flexibly arranged within the semiconductor package structure 100, simplifying the connection structure and ensuring connection reliability.

[0416] In some embodiments, referring to FIG. 30 , the width of the source power terminal 301 is W1, the width of the semiconductor package structure 100 is L, and W1 and L satisfy the relationship: 0 < W1 < L / 2; or the width of the drain power terminal 302 is W2, the width of the semiconductor package structure 100 is L, and W2 and L satisfy the relationship: 0 < W2 < L / 2. In this embodiment, the widths of the source power terminal 301 and the drain power terminal 302 in the second direction B are equal. Thus, the widths of the source power terminal 301 and the drain power terminal 302 are limited to facilitate the placement of the power terminal 30 on one side of the substrate 10 in the first direction A, avoiding contact between the source power terminal 301 and the drain power terminal 302, while maximizing the width of the power terminal 30 to improve its current carrying capacity.

[0417] In some embodiments, the driving terminal 40 includes a source driving terminal 41 and a gate driving terminal 42. The source driving terminal 41 and the gate driving terminal 42 are both located on the same side of the substrate 10 and are spaced apart along the second direction B. To facilitate the correspondence between the driving terminal 40 and the corresponding driving conductive layer 130, the gate driving terminal 42 is opposite to the driving gate conductive layer 131 along the first direction A, and the source driving terminal 41 is opposite to the driving source conductive layer 132 along the first direction A. This ensures that the connector connecting the gate driving terminal 42 and the driving gate conductive layer 131 and the connector connecting the source driving terminal 41 and the driving source conductive layer 132 are parallel to each other, avoiding the cross-coupling mutual inductance between the two connectors, reducing the impact between the circuits where the gate driving terminal 42 and the source driving terminal 41 are located, ensuring circuit performance, improving stability, and avoiding circuit failure.

[0418] 30-31 , the source driving terminal 41 is electrically connected to the driving source 103 through the driving source conductive layer 132 , and the gate driving terminal 42 is electrically connected to the driving gate 102 through the driving gate conductive layer 131 .

[0419] In some embodiments, referring to Figures 30 and 31 , the widths of the source drive terminal 41 and the gate drive terminal 42 are H, respectively, where H satisfies the following: 1 mm ≤ H ≤ 2 mm. For example, H = 1.5 mm. Thus, limiting the widths of the source drive terminal 41 and the gate drive terminal 42 in the second direction B facilitates positioning the drive terminal 40 on one side of the substrate 10 in the first direction A, thereby reducing the possibility of mutual inductance between the source drive terminal 41 and the gate drive terminal 42.

[0420] The semiconductor power chip 20 is provided with a source electrode 101, a driving source electrode 103, and a driving gate electrode 102. When connections are required between the devices, the source electrode 101 on the semiconductor power chip 20 is electrically connected to the source power terminal 301, the driving source electrode 103 is electrically connected to the driving source electrode conductive layer 132, and the driving gate electrode 102 is electrically connected to the driving gate electrode conductive layer 131. Furthermore, the driving source electrode conductive layer 132 is electrically connected to the source driving terminal 41, and the driving gate electrode conductive layer 131 is electrically connected to the gate driving terminal 42. The semiconductor power chip 20 is connected to the driving terminal 40 via the driving conductive layer 130 to achieve connectivity of the driving circuit. At the same time, the drain power terminal 302 provided on the substrate 10 is electrically connected to the drain power conductive layer 201, and the source power terminal 301 is electrically connected to the driving source 103, so that the source driving terminal 41 is directly electrically connected to the semiconductor power chip 20, which can reduce the resistance and parasitic inductance introduced by the semiconductor packaging structure 100 during the packaging process and improve the current carrying capacity of the source power terminal 301.

[0421] In some embodiments, as shown in FIG. 30 to FIG. 32 , there are multiple semiconductor power chips 20 , and the multiple semiconductor power chips 20 are spaced apart along a direction perpendicular to the arrangement direction of the drain power conductive layer 201 and the driving conductive layer 130 , that is, the second direction B.

[0422] In this embodiment, there are two semiconductor power chips 20, including a first semiconductor power chip 220 and a second semiconductor power chip 231. The driving source 103 and the driving gate 102 provided on the first semiconductor power chip 220 and the second semiconductor power chip 231 can be respectively provided at ends of the first semiconductor power chip 220 and the second semiconductor power chip 231 that are away from each other along the second direction B, so as to facilitate electrical connection between the first semiconductor power chip 220 and the second semiconductor power chip 231 and the driving terminal 40. The arrangement direction of the multiple semiconductor power chips 20 is perpendicular to the arrangement direction of the drain power conductive layer 201 and the driving conductive layer 130, which can increase the utilization of the space within the substrate 10, making the structure of the semiconductor package structure 100 more compact, and facilitating the miniaturization and integrated design of the semiconductor package structure 100.

[0423] The first semiconductor power chip 220 and the second semiconductor power chip 231 are arranged on the drain power conductive layer 201, the source power terminal 301 and the drain power terminal 302 are arranged on one side of the substrate 10, the drain power terminal 302 is electrically connected to the drain power conductive layer 201, the source power terminal 301 is electrically connected to the semiconductor power chip 20, and the driving source conductive layer 132 and the driving gate conductive layer 131 are respectively electrically connected to the semiconductor power chip 20 on the side of the semiconductor power chip 20 away from the power terminal 30.

[0424] Referring to Figure 33, which is an equivalent circuit diagram of this embodiment, the driving source electrodes 103 and source electrodes 101 of multiple semiconductor power chips 20 are respectively connected to form a parallel structure between the multiple semiconductor power chips 20, and an interface for connecting to an external circuit is provided through a drain power terminal 302 electrically connected to the drain power conductive layer 201 and a source power terminal 301 electrically connected to the source electrode 101 of the semiconductor power chip 20. The driving gates 102 of the multiple semiconductor power chips 20 are respectively connected to the driving gate conductive layer 131, and a connection interface with an external driving circuit is provided through a gate driving terminal 42. The driving source electrodes 103 of the multiple semiconductor power chips 20 are interconnected and connected to the driving source conductive layer 132, and an external connection interface is provided through the source driving terminal 41, forming a Kelvin connection, eliminating the influence of common source inductance on the switching performance of the semiconductor power chip 20. Among them, the Kelvin connection is a simple method for eliminating the influence of voltage drop generated on the wire in the circuit.

[0425] As shown in FIG34 , the plurality of semiconductor power chips 20 are divided into a plurality of semiconductor power chip groups, each of which includes two semiconductor power chips 20. The drain power terminal 302 includes a plurality of drain power terminal portions 351, which are located on both sides of the source power terminal 301 along the second direction B. The plurality of drain power terminal portions 351 are electrically connected to the drain power conductive layer 201.

[0426] In this embodiment, the number of semiconductor power chip groups and the number of semiconductor power chips 20 corresponding to each semiconductor power chip group are selected based on actual needs. Here, a case is taken where the multiple semiconductor power chip groups include a first semiconductor power chip group 28 and a second semiconductor power chip group 23, each of which includes two semiconductor power chips 20. A source power terminal 301 is disposed between two drain power terminal portions 351. The source power terminal 301 is electrically connected to each of the multiple semiconductor power chips 20, and the two drain power terminal portions 351 are electrically connected to the drain power conductive layer 201. The multiple semiconductor power chips 20 are spaced apart along the second direction B. To facilitate electrical connection between each semiconductor power chip 20 and the driving conductive layer 130, the two semiconductor power chips 20 included in the first semiconductor power chip group 28 and the second semiconductor power chip group 23 are symmetrically arranged along the first direction A. This avoids intersecting bonding wires between the semiconductor power chips 20 and the driving conductive layer 130, thereby reducing parasitic inductance between the bonding wires.

[0427] Thus, the drain power terminal 302 includes two drain power terminal portions 351, which are arranged on either side of the source power terminal 301. This allows multiple semiconductor power chips 20 to be close to the drain power terminal portions 351, facilitating the layout of multiple semiconductor power chips 20 on the substrate and the placement of multiple semiconductor power chips 20, thereby improving current flow capacity. Furthermore, this layout improves device current flow capacity while reducing parasitic inductance and ensuring current sharing among semiconductor power chips 20 at different locations.

[0428] In some embodiments, as shown in FIG34 , the drain power terminal 302 is electrically connected to the drain power conductive layer 201 via a first connecting piece 330, and the source power terminal 301 is electrically connected to the semiconductor power chip 20 via a second connecting piece 340. The first connecting piece 330 is used to connect the drain power terminal 302 and the drain power conductive layer 201, and the second connecting piece 340 is used to connect the source power terminal 301 and the semiconductor power chip 20. The first connecting piece 330 and the second connecting piece 340 may be conductive copper pieces.

[0429] In this embodiment, the first connecting piece 330 can be integrally formed with the drain power terminal 302 or be a part of the drain power terminal 302, and the second connecting piece 340 can be integrally formed with the source power terminal 301 or be a part of the source power terminal 301. In this case, the drain power terminal 302 is directly electrically connected to the drain power conductive layer 201, and the source power terminal 301 is electrically connected to the semiconductor power chip 20. Therefore, the provision of the first connecting piece 330 and the second connecting piece 340 facilitates the electrical connection between the drain power terminal 302 and the drain power conductive layer 201 and the electrical connection between the source power terminal 301 and the semiconductor power chip 20, simplifying the internal structure of the semiconductor package structure 100.

[0430] In some embodiments, as shown in FIG. 34 , at least one through hole 343 is formed on the second connection sheet 340 . The through hole 343 is located between two adjacent semiconductor power chips 20 , and a portion of the two adjacent semiconductor power chips 20 is exposed from the through hole 343 .

[0431] The second connecting piece 340 includes a first connecting sub-piece 341 and a second connecting sub-piece 342. The first connecting sub-piece 341 is connected to the first semiconductor power chip group 28, and the second connecting sub-piece 342 is connected to the second semiconductor power chip group 23. The first connecting sub-piece 341 and the second connecting sub-piece 342 are each provided with a through hole 343. The through hole 343 passes through the portion of the first connecting sub-piece 341 and the second connecting sub-piece 342 opposite the semiconductor power chips 20, so that the two semiconductor power chips 20 included in the first semiconductor power chip group 28 and the second semiconductor power chip group 23 form a parallel structure. In other words, taking the first semiconductor power chip group 28 as an example, in this case, the two semiconductor power chips 20 included in the first semiconductor power chip group 28 are respectively electrically connected to the source power terminal 301.

[0432] Thus, the arrangement of the through hole 343 facilitates the parallel connection between the plurality of semiconductor power chips 20 in the semiconductor power chip group, thereby improving the flow capacity of the semiconductor package structure 100.

[0433] In some embodiments, as shown in Figures 30-34, the driving conductive layer 130 is electrically connected to the driving electrode of the semiconductor power chip 20 via a first bonding wire, and the driving conductive layer 130 is electrically connected to the driving terminal 40 via a second bonding wire. The conductive layer and the terminal within the semiconductor package structure 100 can be electrically connected via a bonding wire connection or a CLIP (copper sheet plus bonding wire) connection.

[0434] For example, as shown in FIG31 , the drain power conductive layer 201 is electrically connected to the power terminal 30 and the semiconductor power chip 20, and the driving conductive layer 130 is electrically connected to the semiconductor power chip 20 and the driving terminal 40 via bonding wires. As shown in FIG32 and FIG34 , the power terminal 30 and the semiconductor power chip 20, and the power terminal 30 and the drain power conductive layer 201 can be directly connected via copper sheets, while the remaining portions, such as the driving conductive layer 130 and the semiconductor power chip 20, and the driving terminal 40, are electrically connected using bonding wires, thereby making the internal structure of the semiconductor package structure 100 more rational and improving production efficiency.

[0435] Therefore, the driving conductive layer 130 and the semiconductor power chip 20, and the driving conductive layer 130 and the driving terminal 40 are electrically connected through bonding wires, which can optimize the connection structure and avoid mutual interference between the first bonding wire and the second bonding wire. Especially for the semiconductor packaging structure 100 connected using the CLIP connection method, it can save space inside the semiconductor packaging structure 100, optimize the layout structure, reduce the resistance and parasitic inductance introduced by the package, and improve the current flow capacity.

[0436] In some embodiments, substrate 10 further includes a source power conductive layer, which is spaced apart from drain power terminal 302 and electrically connected to source 101 and power terminal 30, respectively. Specifically, substrate 10 further includes a source power conductive layer disposed adjacent to source power terminal 301. Source power terminal 301 is electrically connected to source 101 of semiconductor power chip 20 via the source power conductive layer. This effectively prevents heating of semiconductor power chip 20 caused by direct electrical connection between source power terminal 301 and source 101, thereby improving the heat dissipation capability of semiconductor power chip 20. Furthermore, this facilitates electrical connection between source power terminal 301 and source 101, increasing flexibility in positioning source power terminal 301 on substrate 10.

[0437] Furthermore, the source power conductive layer is disposed between the drain power conductive layer 201 and the power terminal 30, and the source power conductive layer is disposed adjacent to the power terminal 30. Thus, the source power terminal 301 is disposed between the drain power conductive layer 201 and the power terminal 30, which facilitates the connection between the power terminal 30 and the source power conductive layer and the drain power conductive layer 201, shortens the length of the bonding wire between the source power conductive layer and the source power terminal 301, and helps reduce parasitic inductance and the resistance of the source power terminal 301.

[0438] According to an embodiment of the fifth aspect of the present application, as shown in Figure 35, a semiconductor power module 1000 is provided, wherein the semiconductor power module includes a semiconductor packaging structure 100 according to any embodiment of the first to fourth aspects above or having similar technical features.

[0439] For example, a semiconductor power module according to an embodiment of the fifth aspect of the present application includes a semiconductor package structure 100 according to any of the above embodiments of the third aspect of the present application. According to the semiconductor power module of the embodiment of the present application, a source power conductive layer 12 is provided on the substrate 10 of the semiconductor package structure 100, so that the source power terminal 301 and the source of the semiconductor power chip 20 are respectively electrically connected to the source power conductive layer 12 by bonding wires, which can improve the heat dissipation capability of the semiconductor package structure 100, achieve lower parasitic inductance, and enhance the current carrying capacity of the semiconductor power module. Moreover, since the drive terminal 40 and the source power terminal 301 are all provided on the substrate 10, combined with the insulation and heat dissipation capabilities inside the substrate 10, the semiconductor power chip 20 and the semiconductor power module can maintain good performance.

[0440] An embodiment of the sixth aspect of the present application, as shown in FIG36 , provides an electronic device 2000 , wherein the device includes a semiconductor packaging structure 100 according to any embodiment of the first to fourth aspects described above or having similar technical features.

[0441] According to an embodiment of the seventh aspect of the present application, as shown in FIG37 , a vehicle 3000 is provided, comprising a semiconductor package structure 100 according to any one of the embodiments of the first to fourth aspects or having similar technical features. The vehicle according to the present application utilizes the semiconductor package structure 100 described above, thereby enabling the vehicle to have good performance.

[0442] The above embodiments focus on the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. Considering the simplicity of the text, they will not be repeated here.

[0443] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0444] In the description of the present application, "first feature" and "second feature" may include one or more of the features. In the description of the present application, "plurality" means two or more. In the description of the present application, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them. In the description of the present application, the first feature being "above", "above" and "above" the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.

[0445] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0446] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A semiconductor packaging structure (100), characterized in that: include: base(2); at least one semiconductor power chip (1), the semiconductor power chip (1) being arranged on the substrate (2), the semiconductor power chip (1) having a source electrode; as well as A source power terminal (301), the source power terminal (301) is arranged on the top surface of the semiconductor power chip (1) and is electrically connected to the source, and the source power terminal (301) is extended along the thickness direction of the semiconductor packaging structure (100).

2. The semiconductor package structure (100) according to claim 1, characterized in that: The semiconductor power chip (1) has a drain, and a drain power terminal (302) is provided on the substrate (2). The drain power terminal (302) is electrically connected to the drain, and the drain power terminal (302) extends along the thickness direction of the semiconductor packaging structure (100).

3. The semiconductor package structure (100) according to claim 2, characterized in that: The semiconductor packaging structure (100) further comprises a packaging shell (10); The package shell (50) covers a portion of the source power terminal (301) and / or the drain power terminal (302), and the source power terminal (301) and / or the drain power terminal (302) are vertically led out from the top surface of the package shell (50).

4. The semiconductor package structure (100) according to claim 2 or 3, characterized in that: The semiconductor package structure (100) further comprises a gate drive terminal (42); the semiconductor power chip (1) has a gate (102); and the gate drive terminal (42) is electrically connected to the gate (102).

5. The semiconductor packaging structure (100) according to any one of claims 2 to 4, characterized in that: The substrate (2) comprises an insulating layer (24), the insulating layer (24) having a first surface, and a drain power conductive layer (201) is provided on the first surface; The drain of the semiconductor power chip (1) is electrically connected to the drain power conductive layer (201), and the drain power terminal (302) is electrically connected to the drain of the semiconductor power chip (1) through the drain power conductive layer (201).

6. The semiconductor package structure (100) according to claim 4, characterized in that: The source of the semiconductor power chip (1) comprises a power source (101), the power source (101) is arranged on the top surface of the semiconductor power chip (1), and the source power terminal (301) is electrically connected to the power source (101).

7. The semiconductor package structure (100) according to claim 6, characterized in that: The semiconductor package structure (100) further comprises a source driving terminal (41), the source of the semiconductor power chip (1) comprises a driving source (103), and the source driving terminal (41) is electrically connected to the driving source (103).

8. The semiconductor package structure (100) according to claim 7, characterized in that: The substrate (2) comprises an insulating layer (24), the insulating layer (24) has a first surface, a driving source conductive layer (132) is provided on the first surface, the driving source (103) is electrically connected to the driving source conductive layer (132), and the source driving terminal (41) is electrically connected to the driving source conductive layer (132).

9. The semiconductor package structure (100) according to any one of claims 4 and 6-8, characterized in that: The substrate (2) comprises an insulating layer (24), the insulating layer (24) having a first surface, a driving gate conductive layer (131) being provided on the first surface, the gate (102) being electrically connected to the driving gate conductive layer (131), and the gate driving terminal (42) being electrically connected to the driving gate conductive layer (131).

10. The semiconductor package structure (100) according to claim 8, characterized in that: The driving source electrode (103) is electrically connected to the driving source electrode conductive layer (132) via a first bonding wire (91), and the driving source electrode conductive layer (132) is electrically connected to the source driving terminal (41) via a third bonding wire (93).

11. The semiconductor package structure (100) according to claim 9, characterized in that: The gate (102) is electrically connected to the driving gate conductive layer (131) via a second bonding wire (92), and the driving gate conductive layer (131) is electrically connected to the gate driving terminal (8) via a fourth bonding wire (94).

12. The semiconductor package structure (100) according to any one of claims 1 to 11, characterized in that: The source power terminal (301) has a first connection end and a second connection end; The first connection end is welded to the top surface of the semiconductor power chip (1), and the second connection end is vertically led out from the top surface of the packaging shell (50).

13. The semiconductor package structure (100) according to claim 5, characterized in that: The drain power terminal (302) has a third connection terminal and a fourth connection terminal; The third connection end is welded to the drain power conductive layer (201) of the semiconductor power chip (1), and the fourth connection end is vertically led out from the top surface of the packaging shell (50).

14. The semiconductor package structure (100) according to claim 7, 8 or 10, characterized in that: The semiconductor power chip (1) is arranged in plurality, the source of the semiconductor power chip (1) comprises a power source electrode (101), and the power source electrode (101) of any semiconductor power chip (1) is electrically connected to the source power terminal (301).

15. The semiconductor package structure (100) according to claim 14, characterized in that: The semiconductor packaging structure (100) comprises a plurality of source power terminals (301), wherein a source power terminal (301) is provided on the top surface of each semiconductor power chip (1), and the source power terminals (301) are respectively electrically connected to the power source (101) of the corresponding semiconductor power chip (1).

16. The semiconductor package structure (100) according to claim 14, characterized in that: A plurality of the semiconductor power chips (1) are connected in parallel to form a target packaging unit.

17. The semiconductor package structure (100) according to claim 14, 15 or 16, characterized in that: The semiconductor packaging structure (100) comprises a plurality of drain power terminals (302), the drain of each of the semiconductor power chips (1) being electrically connected to one of the drain power terminals (302), or the drains of a plurality of the semiconductor power chips (1) being electrically connected to the same drain power terminal (5).

18. The semiconductor package structure (100) according to any one of claims 14 to 17, characterized in that: The semiconductor packaging structure (100) comprises a gate drive terminal (42), the semiconductor power chip (1) has a gate (102), and the gates (102) of a plurality of semiconductor power chips (1) are electrically connected to the gate drive terminal (42).

19. The semiconductor package structure (100) according to claim 18, characterized in that: The semiconductor packaging structure (100) comprises a plurality of gate drive terminals (8), the gate (102) of each of the semiconductor power chips (1) being electrically connected to one of the gate drive terminals (42), or the gates (102) of a plurality of the semiconductor power chips (1) being electrically connected to the same gate drive terminal (42).

20. The semiconductor package structure (100) according to any one of claims 14 to 19, characterized in that: The semiconductor packaging structure (100) comprises a source driving terminal (41), the source of the semiconductor power chip (1) comprises a driving source (103), and the driving sources (103) of a plurality of the semiconductor power chips (1) are all electrically connected to the source driving terminal (41).

21. The semiconductor package structure (100) according to claim 20, characterized in that: The semiconductor packaging structure (100) comprises a plurality of source drive terminals (7), and the drive source (103) of each semiconductor power chip (1) is electrically connected to one of the source drive terminals (41), or the drive source (103) of a plurality of semiconductor power chips (1) are electrically connected to the same source drive terminal (41).

22. The semiconductor package structure (100) according to any one of claims 17 to 19, characterized in that: The substrate (2) comprises an insulating layer (24), the insulating layer (24) having at least a first surface, and a drain power conductive layer (201) is provided on the first surface; The plurality of semiconductor power chips (1) are all arranged on the drain power conductive layer (201), the drains of the plurality of semiconductor power chips (1) are all electrically connected to the drain power conductive layer (201), and the drain power terminal (302) is electrically connected to the drain power conductive layer (201).

23. The semiconductor package structure (100) according to claim 22, characterized in that: A driving gate conductive layer (131) is also provided on the first surface, the gates (102) of the plurality of semiconductor power chips (1) are electrically connected to the driving gate conductive layer (131), and the gate driving terminal (42) is electrically connected to the driving gate conductive layer (131).

24. The semiconductor package structure (100) according to claim 23, characterized in that: A driving source conductive layer (132) is also provided on the first surface, and the driving sources (103) of the plurality of semiconductor power chips (1) are all electrically connected to the driving source conductive layer (132), and the source driving terminal (41) is electrically connected to the driving source conductive layer (132).

25. The semiconductor package structure (100) according to any one of claims 22 to 24, characterized in that: The drain of the semiconductor power chip (1) is arranged on the bottom surface, the drain of the semiconductor power chip is soldered on the drain power conductive layer (201), a first solder layer (31) is formed between the bottom surface of the semiconductor power chip (1) and the drain power conductive layer (201), or the bottom surface of the semiconductor power chip (1) is sintered to the drain power conductive layer (201).

26. The semiconductor package structure (100) according to any one of claims 14 to 25, characterized in that: The power source electrodes (101) of the plurality of semiconductor power chips (1) are all arranged on the top surface, the source power terminal (301) is welded to the power source electrode on the top surface of the semiconductor power chip (1), and a second solder layer (32) is formed between the source power terminal (301) and the top surface of the semiconductor power chip (1), or the source power terminal (301) is sintered to the top surface of the semiconductor power chip (1).

27. The semiconductor package structure (100) according to claim 5 or 13, characterized in that: The drain power terminal (302) is a copper sheet; One end of the copper sheet is electrically connected to the drain power conductive layer (201), and one end of the copper sheet facing away from the drain power conductive layer (201) extends to the top surface of the packaging shell (50) of the semiconductor packaging structure (100) and is led out.

28. The semiconductor package structure (100) according to claim 5, 13 or 27, characterized in that: The insulating layer (24) further has a second surface (27), and the second surface (27) is opposite to the first surface; A copper layer is formed on the second surface (27), and the copper layer exposes the packaging shell (50) of the semiconductor packaging structure (100).

29. A semiconductor packaging structure (100), characterized in that: include: A plurality of semiconductor power chips (1); as well as A substrate (2), a plurality of the semiconductor power chips (1) are arranged on the substrate (2), a driving conductor is also arranged on the substrate (2), the driving conductor is suitable for transmitting a driving signal to the plurality of the semiconductor power chips (1), and the driving conductor is arranged between the plurality of the semiconductor power chips (1).

30. The semiconductor package structure (100) according to claim 29, characterized in that: The substrate (2) comprises a drain power conductive layer (201) and an insulating layer (24); the drain power conductive layer (201) is arranged on the insulating layer (24); a plurality of semiconductor power chips (1) are arranged on the drain power conductive layer (201); the drain power conductive layer (201) is provided with a first notch (2111); the first notch (2111) is located between the plurality of semiconductor power chips (1); and the driving conductor is arranged in the first notch (2111).

31. The semiconductor package structure (100) according to claim 30, characterized in that: The semiconductor power chip (1) comprises a drain electrode, and the drain electrode is electrically connected to the drain power conductive layer (201).

32. The semiconductor package structure (100) according to claim 31, characterized in that: The first notch (2111) extends along a first direction, and the plurality of semiconductor power chips (1) are arranged relative to the peripheral side of the first notch (2111).

33. The semiconductor package structure (100) according to claim 32, characterized in that: The plurality of semiconductor power chips (1) are arranged along a second direction, and the second direction is perpendicular to the first direction.

34. The semiconductor package structure (100) according to claim 33, characterized in that: The plurality of semiconductor power chips (1) are respectively arranged on both sides of the first notch (2111), and the plurality of semiconductor power chips (1) on both sides of the first notch (2111) are arranged along a first direction.

35. The semiconductor package structure (100) according to claim 34, characterized in that: The plurality of semiconductor power chips (1) are symmetrically arranged along the axis of the first notch.

36. The semiconductor package structure (100) according to claim 34 or 35, characterized in that: The distances between the plurality of semiconductor power chips (1) on both sides of the first notch and the driving conductor are the same.

37. The semiconductor package structure (100) according to any one of claims 33 to 36, characterized in that: The drain power conductive layer (201) is further provided with a second notch (2112) extending along the second direction, the second notch (2112) is connected to the first notch (2111), and the driving conductor is arranged in the first notch (2111) and the second notch (2112).

38. The semiconductor package structure (100) according to claim 37, characterized in that: The edge of the second notch (2112) extends to the edge of the substrate (2).

39. The semiconductor package structure (100) according to claim 37 or 38, characterized in that: The first notch (2111) is vertically connected to the second notch (2112), and the shape of the driving conductor matches the overall shape of the first notch (2111) and the second notch (2112).

40. The semiconductor package structure (100) according to any one of claims 30 to 39, characterized in that: The drain power conductive layer (201) is provided with a plurality of the first notches (2111), and at least one semiconductor power chip (1) is provided on the periphery of each of the first notches (2111).

41. The semiconductor package structure (100) according to any one of claims 37 to 39, characterized in that: The semiconductor power chip (1) comprises a gate (102), the driving conductor comprises a driving gate conductive layer (131), the driving gate conductive layer (131) is electrically connected to the gate (102), and the driving gate conductive layer (131) is led out through the first notch (2111) and / or the second notch (2112).

42. The semiconductor package structure (100) according to claim 41, characterized in that: The semiconductor power chip (1) comprises a source electrode, the source power terminal (301) is electrically connected to the source electrodes of a plurality of the semiconductor power chips (1), the source electrode of the semiconductor power chip (1) comprises a power source electrode (101), and the source power terminal (301) is electrically connected to the power source electrode (101).

43. The semiconductor package structure (100) according to claim 42, characterized in that: The power source (101) of the semiconductor power chip (1) is arranged on the top surface, and the source power terminal (301) covers the top surface of the semiconductor power chip (1) to form an electrical connection with the power source (101).

44. The semiconductor package structure (100) according to claim 42 or 43, characterized in that: The source electrode of the semiconductor power chip (1) comprises a driving source electrode (103), the driving conductor comprises a driving source electrode conductive layer (132), the driving source electrode conductive layer (132) is electrically connected to the driving source electrode (103), and the driving source electrode conductive layer (132) is led out through the first notch (2111) and / or the second notch (2112).

45. The semiconductor package structure (100) according to claim 44, characterized in that: The driving source conductive layer (132) and the driving gate conductive layer (131) are arranged in parallel and spaced apart.

46. ​​The semiconductor package structure (100) according to claim 44 or 45, characterized in that: It comprises a source driving terminal (41), and the driving source conductive layer (132) is electrically connected to the source driving terminal (41).

47. The semiconductor package structure (100) according to any one of claims 41 to 46, characterized in that: It comprises a gate drive terminal (42), and the drive gate conductive layer (131) is electrically connected to the gate drive terminal (42).

48. The semiconductor package structure (100) according to claim 47, characterized in that: The source driving terminal (6) is electrically connected to the source power terminal (301).

49. The semiconductor package structure (100) according to any one of claims 31 to 48, characterized in that: A drain power terminal (302) is provided on the substrate (2), and the drain power terminal (302) is electrically connected to the drain power conductive layer (201). The semiconductor packaging structure (100) further comprises a source power terminal (301) electrically connected to the source of the semiconductor power chip (1); the substrate (2) comprises a first side wall (81) and a second side wall (82) arranged opposite to each other; The drain power terminal (302) is located on the first side wall (81), and the source power terminal (301) is located on the second side wall (82); or the drain power terminal (302) and the source power terminal (301) are located on the first side wall (81).

50. The semiconductor package structure (100) according to any one of claims 30 to 49, characterized in that: The substrate (2) comprises a heat-conducting layer (25), and the heat-conducting layer (25) and the drain power conductive layer (201) are located on both sides of the insulating layer (24).

51. The semiconductor package structure (100) according to claim 50, characterized in that: The substrate (2) further comprises a packaging body (8), the packaging body (8) is made of insulating material, the semiconductor power chip (1), the insulating layer (24) and the drain power conductive layer (201) are packaged in the packaging body (8), and the heat conductive layer (25) is exposed outside the packaging body (8).

52. A semiconductor packaging structure (100), characterized in that: include: A substrate (10), the substrate (10) comprising a drain power conductive layer (201), a source power conductive layer (12) and a driving conductive layer (130) which are arranged at intervals, the source power conductive layer (12) and the driving conductive layer (130) being arranged on both sides of the drain power conductive layer (201) respectively; and At least one semiconductor power chip (20), the semiconductor power chip (20) being arranged on the drain power conductive layer (201), the drain of the semiconductor power chip (20) being electrically connected to the drain power conductive layer (201), the source of the semiconductor power chip (20) being electrically connected to the source power conductive layer (12), and the driving electrode (21) of the semiconductor power chip (20) being electrically connected to the driving conductive layer (130).

53. The semiconductor package structure (100) according to claim 52, characterized in that: The drain power conductive layer (201), the source power conductive layer (12) and the driving conductive layer (130) are arranged on the substrate (10) in an extending manner along a first direction.

54. The semiconductor package structure (100) according to claim 53, characterized in that: The drain power conductive layer (201) comprises a drain power conductive layer body (111) and an end drain power conductive portion (112), the end drain power conductive portion (112) is connected to the drain power conductive layer body (111), and the at least one semiconductor power chip (20) is arranged on the drain power conductive layer body (111).

55. The semiconductor package structure (100) according to claim 54, characterized in that: The end drain power conductive portion (112) protrudes from the drain power conductive layer body (111) along a second direction, the drain power conductive layer body (111) extends along a first direction, the drain power conductive layer body (111) is located between the driving conductive layer (130) and the source power conductive layer (12), and the first direction is perpendicular to the second direction.

56. The semiconductor package structure (100) according to claim 55, characterized in that: The source power conductive layer (12) comprises an end source power conductive portion (122) and a source power conductive layer body (121); the end source power conductive portion (122) is connected to one end of the source power conductive layer body (121); the source power conductive layer body (121) extends along a first direction; and the end source power conductive portion (122) protrudes from the source power conductive layer body (121).

57. The semiconductor package structure (100) according to claim 56, characterized in that: The end source power conductive portion (122) is arranged opposite to the drain power conductive layer body (111), and the end source power conductive portion (122) is spaced apart from the extended end of the drain power conductive layer body (111) and covers the extended end of the drain power conductive layer body (111).

58. The semiconductor package structure (100) according to claim 57, characterized in that: The end drain power conductive portion (112) protrudes from both ends of the drain power conductive layer body (111), and is spaced apart from and covers the end of the source power conductive layer body (121) and the end of the driving conductive layer (130).

59. The semiconductor package structure (100) according to any one of claims 52 to 58, characterized in that: The driving conductive layer (130) comprises a driving gate conductive layer (131), and the driving gate conductive layer (131) extends along a first direction; The driving electrode (21) comprises a driving gate (102), and the driving gate conductive layer (131) is electrically connected to the driving gate (102).

60. The semiconductor package structure (100) according to claim 59, characterized in that: The driving conductive layer (130) further comprises: a driving source conductive layer (132), wherein the driving source power conductive layer (12) extends along a first direction; The driving electrode (21) comprises a driving source electrode (103), and the driving source electrode (103) is electrically connected to the driving source electrode conductive layer (132).

61. The semiconductor package structure (100) according to claim 60, characterized in that: The driving source conductive layer (132) and the driving gate conductive layer (131) are arranged at intervals in a second direction, the second direction is perpendicular to the first direction, and the driving source conductive layer (132) and the driving gate conductive layer (131) are arranged in parallel in the second direction.

62. The semiconductor package structure (100) according to claim 60 or 61, characterized in that: include: A drain power terminal (302), the drain power terminal (302) being electrically connected to the drain power conductive layer (201); A source power terminal (301), the source power terminal (301) being electrically connected to the source power conductive layer (12); and A driving terminal (40), wherein the driving terminal (40) is electrically connected to the driving conductive layer (130).

63. The semiconductor package structure (100) according to claim 62, characterized in that: The driving terminal (40) comprises: a gate drive terminal (42), the gate drive terminal (42) being electrically connected to the drive gate conductive layer (131); and A source driving terminal (41), wherein the source driving terminal (41) is electrically connected to the driving source conductive layer (132).

64. The semiconductor package structure (100) according to claim 63, characterized in that: The source driving terminal and the driving source conductive layer (132) are arranged opposite to each other along a first direction, and the gate driving terminal (42) and the driving gate conductive layer (131) are arranged opposite to each other along the first direction.

65. The semiconductor package structure (100) according to any one of claims 62-64, characterized in that: The driving terminal (40) and the source power terminal (301) are located on the same side of the substrate (10).

66. The semiconductor package structure (100) according to any one of claims 52 to 63, characterized in that: The drain electrode of the semiconductor power chip (20) is welded to the drain power conductive layer (201) to form an electrical connection.

67. The semiconductor package structure (100) according to any one of claims 52 to 66, characterized in that: There are a plurality of semiconductor power chips (20), and the plurality of semiconductor power chips (20) are arranged on the drain power conductive layer (201) at intervals along a first direction.

68. The semiconductor package structure (100) according to any one of claims 52 to 67, characterized in that: The drain power conductive layer (201) comprises a plurality of drain power conductive layer bodies (111) and at least one end drain power conductive portion (112), the plurality of drain power conductive layer bodies (111) being spaced apart along a second direction, each drain power conductive layer body (111) being provided with at least one semiconductor power chip (20), and the second direction being perpendicular to an extension direction of the drain power conductive layer body (111).

69. The semiconductor package structure (100) according to claim 68, characterized in that: There are a plurality of semiconductor power chips (20), the plurality of semiconductor power chips (20) at least comprising a first semiconductor power chip group (28) and a second semiconductor power chip group (23), the first semiconductor power chip group (28) comprising a plurality of first semiconductor power chips (220), the second semiconductor power chip group (23) comprising a plurality of second semiconductor power chips (231), and the plurality of drain power conductive layer bodies (111) at least comprising a first drain power conductive layer body (1111) and a second drain power conductive layer body (1112) arranged at intervals along the second direction; A plurality of the first semiconductor power chips (220) are arranged on the first drain power conductive layer body (1111) at intervals from each other along a first direction, and a plurality of the second semiconductor power chips (231) are arranged on the second drain power conductive layer body (1112) at intervals from each other along the first direction, and the first direction is the same as the direction in which the drain power conductive layer body (111) extends.

70. The semiconductor package structure (100) according to claim 69, characterized in that: The source power conductive layer (12) is multiple, and the multiple source power conductive layers (12) at least include a first source power conductive layer (123) (12) and a second source power conductive layer (124) (12), wherein the first source power conductive layer (123) (12) is arranged adjacent to the first drain power conductive layer body (1111), and the second source power conductive layer (124) (12) is arranged adjacent to the second drain power conductive layer body (1112).

71. The semiconductor package structure (100) according to claim 70, characterized in that: Also includes: At least one source power terminal (301), the source power terminal being electrically connected to the plurality of source power conductive layers (12).

72. The semiconductor package structure (100) according to claim 70 or 71, characterized in that: The source power terminal (301) comprises at least a first source power terminal portion (321) and a second source power terminal portion (322), wherein the first source power terminal portion (321) is electrically connected to the first source power conductive layer (123) (12), and the second source power terminal portion (322) is electrically connected to the second source power conductive layer (124) (12).

73. The semiconductor package structure (100) according to any one of claims 68721, characterized in that: One end of the driving conductive layer (130) is located between the plurality of drain power conductive layer bodies (111) and is used for being electrically connected to the driving electrodes (21) of the plurality of semiconductor power chips (20).

74. The semiconductor package structure (100) according to claim 73, characterized in that: Also includes: A driving terminal (40), the other end of the driving conductive layer (130) being electrically connected to the driving terminal.

75. The semiconductor package structure (100) according to claim 73 or 74, characterized in that: The driving conductive layer (130) comprises: a driving conductive layer (130) body and an end driving conductive portion (134); the driving conductive layer (130) body is located between two adjacent drain power conductive layer bodies (111); and the end driving conductive portion (134) is electrically connected to the driving terminal (40).

76. The semiconductor package structure (100) according to any one of claims 62 to 64, characterized in that: The drain power terminal (302), the source power terminal (301) and the driving terminal (40) are located on the same side of the substrate (10); the driving conductive layer (130), the drain power conductive layer (201) and the source power conductive layer (12) are arranged in sequence along the second direction; the driving terminal (40), the drain power terminal (302) and the source power terminal (301) are arranged in sequence along the second direction; and the driving terminal (40), the drain power terminal (302) and the source power terminal (301) are respectively arranged corresponding to the driving conductive layer (130), the drain power conductive layer (201) and the source power conductive layer (12).

77. A semiconductor packaging structure (100), characterized in that: include: A substrate (10), the substrate (10) comprising a drain power conductive layer (201) and a driving conductive layer (130) which are arranged at intervals; At least one semiconductor power chip (20), the semiconductor power chip (20) being arranged on the drain power conductive layer (201), the drain of the semiconductor power chip (20) being electrically connected to the drain power conductive layer (201), and the driving electrode of the semiconductor power chip (20) being electrically connected to the driving conductive layer (130); A plurality of power terminals (30), wherein the plurality of power terminals (30) are electrically connected to the source (101) and the drain power conductive layer (201) of the semiconductor power chip (20) respectively; and At least one driving terminal (40), the driving terminal (40) being electrically connected to the driving conductive layer (130), and the driving terminal (40) and the power terminal (30) being respectively located on different sides of the substrate (10).

78. The semiconductor package structure (100) according to claim 77, characterized in that: The driving terminal (40) and the power terminal (30) are respectively located on two sides of the substrate (10) that are opposite to each other along a first direction.

79. The semiconductor package structure (100) according to claim 77 or 78, characterized in that: The drain power conductive layer (201) and the driving conductive layer (130) are arranged in sequence along a first direction.

80. The semiconductor package structure (100) according to any one of claims 77 to 79, characterized in that: The driving terminal is located in the middle of the side of the substrate (10).

81. The semiconductor package structure (100) according to any one of claims 77 to 80, characterized in that: The driving conductive layer (130) comprises: a driving gate (102) conductive layer (131), the driving gate (102) conductive layer (131) extending along the second direction, and the driving gate (102) conductive layer (131) being arranged adjacent to the driving terminal (40); The driving electrode comprises: a driving gate (102), and the driving gate (102) and the driving gate (102) conductive layer (131) are electrically connected.

82. The semiconductor package structure (100) according to claim 81, characterized in that: The driving conductive layer (130) comprises: a driving source electrode (103) conductive layer (132), the driving source electrode (103) conductive layer (132) extending along the second direction, and the driving source electrode (103) conductive layer (132) being arranged adjacent to the driving terminal (40); The driving electrode comprises: a driving source electrode (103), and the driving source electrode (103) and the driving source electrode (103) conductive layer (132) are electrically connected.

83. The semiconductor package structure (100) according to claim 82, characterized in that: The driving source (103) conductive layer (132) and the driving gate (102) conductive layer (131) are parallel to each other, the driving source (103) conductive layer (132) and the driving gate (102) conductive layer (131) extend along a second direction, the power terminal (30) and the driving terminal (40) are arranged along a first direction, and the first direction is perpendicular to the second direction.

84. The semiconductor package structure (100) according to claim 82 or 83, characterized in that: The driving source electrode (103) conductive layer (132) and the driving gate electrode (102) conductive layer (131) are in the shape of long strips.

85. The semiconductor package structure (100) according to any one of claims 82-84, characterized in that: The power terminal (30) comprises: A drain power terminal (302) and a source power terminal (301), wherein the drain power terminal (302) and the source power terminal (301) are both located on the same side of the substrate (10).

86. The semiconductor package structure (100) according to claim 85, characterized in that: The drain power terminal is electrically connected to the drain power conductive layer (201), the source power terminal (301) is electrically connected to the source (101) of the semiconductor power chip (20), and the power terminal (30) is electrically connected to the drain power conductive layer (201) and the source (101) of the semiconductor power chip (20) respectively through bonding wires.

87. The semiconductor package structure (100) according to claim 85 or 86, characterized in that: The width of the source power terminal (301) is W1, the width of the semiconductor package structure (100) is L, and W1 and L satisfy: 0<W1<L / 2; and / or The width of the drain power terminal (302) is W2, the width of the semiconductor package structure (100) is L, and W2 and L satisfy: 0<W2<L / 2.

88. The semiconductor package structure (100) according to any one of claims 82 to 87, characterized in that: The driving terminal (40) comprises: A source driving terminal (41) and a gate driving terminal (42), wherein the source driving terminal (41) and the gate driving terminal (42) are both located on the same side of the substrate (10).

89. The semiconductor package structure (100) according to claim 88, characterized in that: The source driving terminal (41) is electrically connected to the driving source (103) through the driving source (103) conductive layer (132), and the gate driving terminal (42) is electrically connected to the driving gate (102) through the driving gate (102) conductive layer (131).

90. The semiconductor package structure (100) according to claim 88 or 89, characterized in that: The widths of the source driving terminal (41) and the gate driving terminal (42) are respectively H, and H satisfies: 1 mm≤H≤2 mm.

91. The semiconductor package structure (100) according to any one of claims 82 to 90, characterized in that: There are a plurality of semiconductor power chips (20), and the plurality of semiconductor power chips (20) are arranged at intervals along the second direction.

92. The semiconductor package structure (100) according to any one of claims 85 to 87, characterized in that: The plurality of semiconductor power chips (20) are divided into a plurality of semiconductor power chip groups, each of the semiconductor power chip groups comprising at least two semiconductor power chips (20); The drain power terminal (302) comprises a plurality of drain power terminal parts (351), the plurality of drain power terminal parts (351) are respectively located on both sides of the source power terminal (301), and the plurality of drain power terminal parts are all electrically connected to the drain power conductive layer (201).

93. The semiconductor package structure (100) according to any one of claims 85 to 87 and 92, characterized in that: The drain power terminal (301) is electrically connected to the drain power conductive layer (201) via a first connecting piece (330), and the source power terminal (301) is electrically connected to the source (101) via a second connecting piece (340).

94. The semiconductor package structure (100) according to claim 93, characterized in that: At least one through hole (343) is formed on the second connecting sheet (340), the through hole (343) is located between two adjacent semiconductor power chips (20), and one end of the two adjacent semiconductor power chips (20) that is adjacent to each other is exposed from the through hole (343).

95. The semiconductor package structure (100) according to any one of claims 77 to 94, characterized in that: The substrate (10) further comprises: a source power conductive layer, the source power conductive layer and the drain power terminal (302) are arranged at intervals, the source power conductive layer is electrically connected to the source (101) and the power terminal (30) respectively, and the source power conductive layer is arranged between the drain power conductive layer (201) and the power terminal (30).

96. A semiconductor power module, characterized in that: A semiconductor package structure (100) comprising any one of claims 1 to 95.

97. An electronic device, characterized in that: A semiconductor package structure (100) comprising any one of claims 1 to 95.

98. A vehicle, characterized in that: Comprising the semiconductor package structure (100) as claimed in any one of claims 1 to 95.

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