Multi-chip packaging structure and radio frequency front-end module

Abstract

The present application relates to the technical field of chip-scale packaging, and particularly provides a multi-chip packaging structure and a radio frequency front-end module. The multi-chip packaging structure specifically comprises: a substrate, wherein first pads and second pads are arranged on a first surface of the substrate; a filter chip arranged upside down on the first surface and connected to the first pads; a non-filter chip arranged on the first surface, and by means of bonding leads, connected to the second pads; an adhesive material part, wherein a first adhesive material part comprised therein at least surrounds the filter chip and is arranged on the first surface, and a cavity is formed between the filter chip, the first adhesive material part, and the substrate; and a filler filled on the first surface and covering the filter chip, the non-filter chip, and the adhesive material part. The present application can arrange, on the same side of a substrate, a filter chip and a non-filter chip which is provided with bonding leads, and meets the requirement of a cavity of the filter chip by arranging an adhesive material part, thereby meeting the reliability requirement for a package while realizing miniaturization of the package.

Description

A multi-chip packaging structure and radio frequency front-end module

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 28, 2023, with application number CN202322658137.3 and application name “A multi-chip packaging structure and RF front-end module”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip-level packaging technology, and in particular to a multi-chip packaging structure and a radio frequency front-end module. Background Art

[0003] In chip-scale packaging, multiple chips are mounted on the surface of a packaging substrate and then encapsulated with materials such as thermosetting resin to protect the chips from moisture. Some specialized chips, such as surface acoustic wave (SAW) and bulk acoustic wave (BAW) filter chips, require a cavity between them and the substrate during the packaging process to meet their functional, performance, or other special requirements.

[0004] To create a sealed cavity and shield chip components from external environmental influences, a protective film is typically applied to the chip surface, creating a sealed cavity between the chip and substrate. This cavity is then filled with plastic encapsulation material. However, in practice, some chips are not suitable for this packaging method. Therefore, the film-coated packaging process cannot meet the packaging requirements of multi-chip scenarios.

[0005] Application Contents

[0006] The embodiments of the present application provide a multi-chip packaging structure and a radio frequency front-end module, which can reduce the packaging size and meet the packaging requirements in multi-chip scenarios.

[0007] A first aspect of an embodiment of the present application provides a multi-chip package structure, including:

[0008] The substrate comprises a first surface, wherein the first surface is provided with a first solder pad and a second solder pad;

[0009] a filter chip, flip-chip mounted on the first surface and connected to the first pad;

[0010] a non-filter chip, comprising a bonding wire, wherein the non-filter chip is disposed on the first surface, and the bonding wire is connected to the second pad;

[0011] A glue portion, the glue portion including a first glue portion, the first glue portion being disposed on the first surface at least surrounding the filter chip, and a cavity being formed between the filter chip, the first glue portion, and the substrate;

[0012] The filler is filled on the first surface and covers the filter chip, the non-filter chip and the adhesive portion.

[0013] A second aspect of an embodiment of the present application provides a multi-chip package structure, including:

[0014] The substrate comprises a first surface, wherein the first surface is provided with a first solder pad and a second solder pad;

[0015] a filter chip, flip-chip mounted on the first surface and connected to the first pad;

[0016] a non-filter chip, comprising a bonding wire, wherein the non-filter chip is disposed on the first surface, the bonding wire is connected to the second pad, and a first distance exists between the non-filter chip and the filter chip;

[0017] A first chip is disposed on the first surface, wherein a second distance exists between the first chip and the filter chip or the non-filter chip, and the first distance is smaller than the second distance;

[0018] The adhesive portion includes a first adhesive portion, the first adhesive portion is provided on the first surface at least surrounding the filter chip, and a cavity is formed between the filter chip, the first adhesive portion, and the substrate;

[0019] The filler is filled on the first surface and covers the filter chip, the non-filter chip, the first chip and the adhesive portion.

[0020] A third aspect of the embodiments of the present application provides a multi-chip package structure, including:

[0021] A substrate comprising a first surface, wherein the first surface is provided with a solder resist layer, a first pad and a second pad, the solder resist layer having at least a first opening and a second opening, the first pad and the second pad being located in the first opening and the second opening respectively;

[0022] a filter chip, flip-chip mounted in the first opening and connected to the first pad;

[0023] a non-filter chip, comprising a bonding wire, wherein the non-filter chip is disposed in the second opening, and the bonding wire is connected to the second pad;

[0024] an adhesive portion, the adhesive portion including a third adhesive portion, the third adhesive portion being disposed on the first surface to cover the solder resist layer, the filter chip, and the non-filter chip, with a cavity formed between the filter chip, the third adhesive portion, and the substrate;

[0025] The filler fills the first surface and covers the adhesive portion.

[0026] A fourth aspect of an embodiment of the present application provides a radio frequency front-end module, comprising the multi-chip packaging structure provided by any of the above aspects.

[0027] Through the multi-chip packaging structure provided by the present application, the filter chip and the non-filter chip with bonding leads can be arranged on the same side of the substrate, and the filter chip cavity requirement can be realized by setting the glue part, thereby not only achieving the miniaturization of the package but also meeting the reliability requirements of the package. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] FIG1 is a schematic diagram of a multi-chip package structure according to at least one embodiment of the present application;

[0030] FIG2 is a second schematic diagram of a multi-filter packaging structure provided by at least one embodiment of the present application;

[0031] FIG3 is a third schematic diagram of a multi-filter packaging structure provided by at least one embodiment of the present application;

[0032] FIG4 is a fourth schematic diagram of a multi-filter packaging structure provided by at least one embodiment of the present application;

[0033] FIG5 is a fifth schematic diagram of a multi-filter packaging structure provided by at least one embodiment of the present application;

[0034] FIG6 is a sixth schematic diagram of a multi-filter packaging structure provided by at least one embodiment of the present application;

[0035] FIG7 is a seventh schematic diagram of a multi-filter packaging structure provided by at least one embodiment of the present application.

[0036] Reference numerals:

[0037] 10. Substrate; 11. First surface; 12. Second surface; 13. Trace; 14. First pad; 15. Second pad; 16. Solder mask;

[0038] 20. Filter chip; 21. Upper surface of filter chip; 22. Lower surface of filter chip; 23. Connecting bump of first filter chip; 24. Chip element of filter chip; 25. Cavity of filter chip;

[0039] 30. Non-filter chip; 31. Top surface of non-filter chip; 32. Adhesion layer; 33. Bonding wire;

[0040] 41. Adhesive material section; 41. First adhesive material section; 42. Second adhesive material section; 43. Third adhesive material section; 44. Fourth adhesive material section;

[0041] 50. Filling material;

[0042] 60. The first chip. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0044] It should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present application to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0045] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to," "connected to," or "connected to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present application.

[0046] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] In order to fully understand the present application, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0049] In chip-level packaging technology, in order to meet the cavity requirements of the filter chip, a protective film is usually covered on the outer surface of the chip. During the process, the protective film is generally laid on the upper surface of the chip first, and then pressure is applied to the protective film facing the substrate to make the protective film fit the upper surface, side and substrate of the chip. A closed cavity is formed between the chip, the protective film and the substrate to meet the functional requirements of the chip. Finally, the chip is plastic-sealed with filling materials such as sealing resin. Since the sealing resin has a high hardness after cooling and is not easily deformed by temperature changes, it can protect the chip from external moisture erosion and mechanical stress after plastic sealing. Therefore, it is widely used in chip-level packaging technology. Since the lamination process involves laying a protective film on the surface of the structure to be packaged and applying pressure toward the substrate, in a multi-chip scenario, if the filter chip is packaged by lamination, the lamination process will affect the chips with special structures. For example, it may cause the bonding wires in the wire-bonded structure chip to break. Of course, in order to avoid this situation, the relevant technology generally places the filter chip and the wire-bonded structure chip on different sides of the substrate, but this will increase the package size and does not meet the needs of miniaturization.

[0050] In order to solve the above problems, the present application provides a multi-chip packaging structure, specifically including: a substrate, including a first surface, the first surface is provided with a first solder pad and a second solder pad; a filter chip, flipped on the first surface and connected to the first solder pad; a non-filter chip, including a bonding wire, the non-filter chip is provided on the first surface, and the bonding wire is connected to the second solder pad; a first adhesive portion, at least around the filter chip is provided on the first surface, and a cavity is formed between the filter chip, the first adhesive portion and the substrate; a filler, filled on the first surface, and covering the filter chip, the non-filter chip and the first adhesive portion. In other words, the present application can set the filter chip and the non-filter chip (wire bonding structure chip) with bonding wires on the same side of the substrate, and realize the filter chip cavity requirement by setting the adhesive, thereby not only achieving miniaturization of the package but also meeting the reliability requirements of the package. The present application will be specifically illustrated by the following embodiments:

[0051] It should be noted that the filter chip in the embodiment of the present application refers to a chip with a filtering function, which can be a surface acoustic wave filter chip or a bulk acoustic wave filter chip; the non-filter chip is a chip other than a filtering function, which can be a power amplifier chip, a low-noise amplifier chip, a switch, a coupler, a matching circuit, etc., and is not limited in the implementation of this application.

[0052] In one embodiment, please refer to FIG1 , which is a schematic diagram of a multi-chip package structure according to at least one embodiment of the present application. The multi-chip structure shown in FIG1 includes a substrate 10, a filter chip 20, a non-filter chip 30, an adhesive portion 40, and a filler 50. The adhesive portion 40 includes a first adhesive portion 41 disposed at least around the filter chip 20. The filler 50 is filled in the substrate 10 and covers the filter chip 20, the non-filter chip 30, and the first adhesive portion 41.

[0053] Among them, the substrate 10 can be a substrate such as resin, ceramic, quartz, etc., or the substrate 10 can be a single-layer substrate or a multi-layer substrate, which is not limited in this application. In this embodiment, the substrate 10 is a multi-layer substrate. The material of the filler 50 can be an insulating material, such as a sealing resin, or other insulating materials with weaker fluidity, such as a sealing resin containing particulate matter. Specifically, the material of the filler 50 can be a thermosetting resin, or a thermosetting resin containing particulate matter. Among them, the particulate matter can be silicon dioxide (SiO2) particles, or aluminum oxide (Al2O3) particles, which is not limited in this application. Optionally, the filler 50 can also be an insulating resin material or other conventional plastic packaging materials. It can be understood that the filler 50 can also be other materials that can achieve a sealing function, which will not be repeated in this application. The setting of the filler 50 can provide physical support protection, and can also block substances such as water vapor, salt, fog, etc. in the external environment, thereby protecting the packaged chip. The adhesive portion 40 may be a fast-curing adhesive. In one embodiment, the adhesive portion 40 may be a UV-curing adhesive. In other embodiments, the adhesive portion 40 may be an adhesive with lower fluidity than the filler. This application does not limit this.

[0054] Specifically, the substrate 10 includes a first surface 11, a second surface 12, a plurality of traces 13, and a first solder pad 14 and a second solder pad 15, wherein the first surface 11 and the second surface 12 are arranged opposite to each other; the first solder pad 14 and the second solder pad 15 are arranged on the first surface 11. In one embodiment, the first solder pad 14 and the second solder pad 15 can also be embedded in the substrate 10, and the upper surfaces of the first solder pad 14 and the second solder pad 15 can be flush with the first surface 11 or slightly higher than the first surface 11, which is not limited in this application; a plurality of traces 13 can be arranged on the first surface 11, the second surface 12, and within the substrate 10 to achieve internal circuit connection and connection between the multi-chip module and the external circuit. The first solder pad 14 and the second solder pad 15 and the traces 13 can be metal or alloys doped with multiple metals, specifically nickel, palladium, molybdenum, tungsten, ruthenium, gold, magnesium, aluminum, copper, chromium, titanium, osmium, iridium, etc.

[0055] In the embodiment shown in FIG. 1 , the first pad 14 , the second pad 15 , and the trace 13 disposed on the first surface 11 have substantially the same height and can be manufactured in the same process.

[0056] Specifically, the filter chip 20 includes a connecting bump 23 and a chip component 24, which is flip-chip mounted on the first surface 11 and is specifically connected to the first pad 14 via the connecting bump 23. The connecting bump 23 may be made of tin, gold, copper, etc., which is not limited in this application. The flip-chip filter chip 20 has an upper surface 21 and a lower surface 22 opposite to the upper surface 21, wherein the lower surface 22 is closer to the substrate 10 than the upper surface 21. The connecting bumps 23 and chip components 24 of the filter chip 20 are arranged on the lower surface 22. Specifically, the connecting bumps 23 and chip components 24 are generally arranged in the middle area of ​​the lower surface 22. The edge of the lower surface 22 is the area surrounding the middle area, and generally no components related to the working performance of the filter are provided.

[0057] Specifically, the non-filter chip 30 includes an upper surface 31 facing away from the substrate 10 and a lower surface, wherein the lower surface is adhered to the first surface 11 via an adhesive layer 32. The non-filter chip 30 includes a bonding wire 33, one end of which is connected to the upper surface 31 of the non-filter chip 30 and the other end is connected to the second pad 15, thereby achieving electrical connection with the trace 13 of the substrate 10, and achieving electrical connection with the filter chip 20 and external circuitry through the trace 13.

[0058] Furthermore, the non-filter chip 30 further includes a first solder joint and a second solder joint, wherein the first solder joint is a solder joint connecting the bonding wire 33 to the upper surface 31 of the non-filter chip 30, and the second solder joint is a solder joint connecting the bonding wire 33 to the second solder pad 15. The bonding wire 33 is connected to the solder pad on the upper surface 31 of the non-filter chip 30 via the first solder joint, and is connected to the second solder pad 15 via the second solder joint. The first and second solder joints are not shown in the drawings of this application.

[0059] For example, in the embodiment shown in Figure 1, the glue portion 40 includes a first glue portion 41, which is arranged on the first surface 11 around the filter chip 20. A portion of the first glue portion 41 is arranged below the filter chip 20, opposite to the edge area of ​​the lower surface 22, and the other portion is arranged on the outside of the filter chip 20, so that the cavity 25 of the filter chip 20 is enclosed between the lower surface 22 of the filter chip 20, the first surface 11 of the substrate 10 and the first glue portion 41.

[0060] In one embodiment, the portion of the first adhesive portion 41 located below the filter chip 20 may abut against the lower surface 22 of the filter chip 20 , with a certain gap therebetween.

[0061] In another embodiment, the thickness of the portion of the first adhesive portion 41 located outside the filter chip 20 may be slightly less than the height of the distance between the lower surface 22 of the filter chip 20 and the first surface 11, or may be greater than the height of the distance. If the thickness of the portion of the first adhesive portion 41 located outside the filter chip 20 is greater than the height of the distance, the portion may abut against the side surface of the filter chip 20 or may have a certain gap therebetween, and this application does not impose any specific restrictions.

[0062] In the embodiments of the present application, there is no limitation on the shape of the first adhesive portion 41. For example, the surface of the first adhesive portion 41 facing away from the substrate 10 may have multiple vertices or a top surface, with adjacent vertices or top surfaces forming a "concave" shape, or may be a substantially flat surface.

[0063] It is understandable that the first adhesive portion 41 may partially contact the first pad 14 to protect the first pad 14 , or may be spaced apart from each other, which is not specifically limited in this application.

[0064] Through the embodiments of the present application, the filter chip 20 and the non-filter chip 30 with a wire-bonded structure can be packaged on the same side of the substrate, shortening the connection line between the filter chip and the non-filter chip, reducing the negative impact on operating performance caused by excessively long connection lines. This not only meets the requirements for operating performance, but also reduces the package size and saves packaging costs. Furthermore, the provision of the first adhesive portion 41 meets the filter chip 20's requirement for a sealed cavity, thereby improving packaging reliability.

[0065] In some embodiments, the distance between the filter chip 20 and the non-filter chip 30 is smaller than a first threshold.

[0066] It is understandable that the spacing between the filter chip 20 and the non-filter chip 30 can be the minimum spacing between the two chips in the arrangement direction of the two chips, or the average spacing, or the maximum spacing, which is not limited in this application.

[0067] It can be understood that the filter chip 20 and the non-filter chip 30 can be arranged in a line along a specific direction, with the two chips basically overlapping in this direction; they can also be staggered along this direction, with the two chips partially overlapping in this direction; they can also be arranged diagonally, with the two chips almost not overlapping in this direction. This application does not make specific restrictions on this.

[0068] In this embodiment, when the first adhesive portion 41 is set around the filter chip 20, the distance between the two chips can also be set to be less than the first threshold value. Compared with the filter chip 20 and the non-filter chip with a non-wire-bonded structure using a film package, the distance between the two chips can be further reduced, thereby greatly reducing the package size and saving packaging costs.

[0069] In some embodiments, the first threshold is 150 μm, 100 μm or 50 μm. Specifically, the distance between the filter chip 20 and the non-filter chip 30 may be less than 150 μm, or less than 100 μm, or less than 80 μm, or less than 50 μm.

[0070] For example, the spacing between the filter chip 20 and the non-filter chip 30 may be 30 μm, 40 μm, 50 μm, 75 μm, 80 μm, 90 μm, 99 μm, 130 μm, etc., which is not limited in this application.

[0071] In this embodiment, a first adhesive portion 41 is provided around the filter chip 20, which can shorten the distance between the filter chip 20 and the non-filter chip 30 to 150 μm or below 100 μm, or even below 50 μm, thereby greatly shortening the distance between the two chips while ensuring packaging reliability.

[0072] In some embodiments, the thickness of a portion of the first adhesive portion 41 close to the side surface of the filter chip 20 is greater than the minimum distance from the lower surface 22 of the filter chip 20 to the first surface 11 .

[0073] Specifically, referring again to Figure 1 , the portion of the first adhesive portion 41 near the side of the filter chip 20 can be understood as the portion of the first adhesive portion located on the outside of the filter chip 20 facing the side of the filter chip 20 in a top view (the direction from the filter chip 20 to the substrate 10). The minimum distance between the lower surface 22 of the filter chip 20 and the first surface 11 can be understood as the distance between the lower surface 22 and the first surface 11 in a top view.

[0074] In this embodiment, by limiting the thickness of the portion of the first adhesive portion 41 close to the side surface of the filter chip 20, on the one hand, a certain stress buffering effect can be exerted on the side surface of the filter chip 20. On the other hand, it is also beneficial to form a cavity of the filter chip 20, effectively preventing the filler 50 from entering the cavity 25 of the filter chip 20 through the gap between the lower surface 22 of the filter chip 20 and the first surface 11, thereby improving the packaging reliability.

[0075] In some embodiments, there is a gap between at least a portion of the first adhesive portion 41 near the filter chip 20 and the side surface of the filter chip 20; or, at least a portion of the first adhesive portion 41 near the filter chip 20 is in contact with the side surface of the filter chip 20. This approach can buffer the external stress on the side surface of the filter chip 20.

[0076] Specifically, the first adhesive portion 41 close to the filter chip 20 can be a portion having a gap with the side surface of the filter chip 20, and a portion being adhered to the side surface of the filter chip 20; or, the first adhesive portion 41 close to the filter chip 20 has a gap with the side surface of the filter chip 20; or, the first adhesive portion 41 close to the filter chip 20 is all adhered to the side surface of the filter chip 20, which is not limited in this application.

[0077] In one embodiment, the gap between the first adhesive portion 41 disposed on the solder resist layer 16 and the side surface of the filter chip 20 at a position close to the side surface of the filter chip 20 is no more than 15 μm, 10 μm, or 5 μm, so as to prevent the filler 50 from entering the cavity 25 of the filter chip 20 through the gap between the first adhesive portion 41 and the filter chip 20 and the gap between the solder resist layer 16 and the filter chip 20. In other words, the first adhesive portion 41 does not cover the side surface of the filter chip 20.

[0078] In one specific embodiment, the first adhesive portion 41 disposed on the solder resist layer 16 is attached to the side of the filter chip 20 at a position close to the side of the filter chip 20, so that a small portion of the side of the filter chip 20 close to the solder resist layer 16 is covered by the first adhesive portion 41, which can, to a certain extent, buffer the stress on the side of the filter chip 20. In other words, the majority of the side of the filter chip 20 (i.e., the upper half) is not covered by the first adhesive portion 41.

[0079] In some embodiments, the first adhesive portion 41 may also be located on the upper surface 21 of the filter chip 20 to at least partially cover the upper surface 21 of the filter chip 20. Specifically, the first adhesive portion 41 located on the upper surface 21 of the filter chip 20 may cover only the edge region of the upper surface 21, or only the middle region of the upper surface 21, or may be intermittently disposed on the upper surface 21, or may completely cover the upper surface 21, so as to buffer the stress borne by the upper surface 21 of the filter chip 20.

[0080] In some embodiments, the first adhesive portion 41 can be formed by a dispensing process. In a specific embodiment, the first adhesive portion 41 surrounding the filter chip 20 shown in FIG1 can be formed by multiple dispensing and curing processes. For example, after printing a first layer of adhesive, it is cured with ultraviolet light, and then a second layer of adhesive is printed and cured. Multiple printing and curing processes are performed to ultimately form the first adhesive portion 41 shown in FIG1 .

[0081] In at least one embodiment, the substrate 10 includes a solder resist layer 16, the solder resist layer 16 has at least a first opening 161 and a second opening 162, the first solder pad 14 is located in the first opening 161, the second solder pad 15 is located in the second opening 162, and the first adhesive portion 41 arranged around the filter chip 20 is at least partially located on the solder resist layer 16.

[0082] Specifically, in the case where the solder resist layer 16 is present, the solder resist layer 16 located at the edge of the first opening 161 at least faces the edge of the lower surface 22 of the filter chip 20 .

[0083] In one embodiment, please refer to FIG. 2 , which is a second schematic diagram of a multi-chip package structure provided by at least one embodiment of the present application. The structure shown in FIG. 2 differs from FIG. 1 in that: the substrate 10 includes a solder resist layer 16 , the solder resist layer 16 having at least a first opening 161 and a second opening 162 , the first solder pad 14 is located within the first opening 161 , the second solder pad 15 is located within the second opening 162 , and the first adhesive portion 41 disposed around the filter chip 20 is entirely located on the solder resist layer 16 . In the embodiment shown in FIG. 1 , the substrate 10 does not include the solder resist layer 16 , and the first adhesive portion 41 disposed around the filter chip 20 is directly disposed on the first surface 11 .

[0084] Specifically, the number of first openings 161 can be multiple or one. When there are multiple first openings 161, one or more first solder pads 14 are disposed within each first opening 161, meaning that a portion of solder resist 16 (not shown) is present within the cavity formed by the filter chip 20. When there is only one first opening 161, all first solder pads 14 connected to the connection bumps 23 of the filter chip 20 are located within the first opening 161, as shown in FIG2 . Furthermore, a portion of traces 13 may be disposed on the first surface 11 of the substrate 10 within the first opening 161 to meet the operational or performance requirements of the filter chip 20.

[0085] Specifically, the number of second openings 162 can be multiple or one. When there are multiple second openings 162, one or more second pads 15 are provided in each second opening 162, and the non-filter chip 30 can be located on the solder resist layer 16 or in the second opening 162, as shown in FIG2 ; when there is only one second opening 162, all second pads 15 connected to the bonding wires 33 of the non-filter chip 30 and the non-filter chip 30 are located in the second opening 161 (not shown in the figure).

[0086] In another embodiment, please refer to Figure 3, which is a third schematic diagram of a multi-chip package structure provided by at least one embodiment of the present application. The structure shown in Figure 3 differs from that in Figure 2 in that a portion of the first adhesive portion 41 disposed around the filter chip 20 is located on the solder resist layer 16, while another portion is located within the first opening 161.

[0087] In some embodiments, the thickness of the solder resist layer 16 is greater than the thickness of the first pad 14 or the second pad 15 exposed on the first surface 11 .

[0088] It is understood that the first pad 14, the second pad 15, and the trace 13 can be manufactured in the same process and have substantially the same height. The thickness of the first pad 14 or the second pad 15 exposed on the first surface 11 can also be understood as the thickness of the trace 13 exposed on the first surface 11. If the three are manufactured in different processes or have different heights, the thickness of the solder resist layer 16 can be greater than the maximum thickness of the three exposed on the first surface 11.

[0089] In the structures shown in Figures 2 and 3, the first pad 14, the second pad 15, and the trace 13 are all disposed on the first surface 11 of the substrate 10. The thickness of the first pad 14 or the second pad 15 exposed above the first surface 11 can be understood as the height of the first pad 14 or the second pad 15. In other embodiments, if the first pad 14 or the second pad 15 is fully embedded in the substrate 10 and the upper surface of the first pad 14 or the second pad 15 is substantially flush with the first surface 11, the thickness of the first pad 14 or the second pad 15 exposed above the first surface 11 can be almost negligible. In yet another embodiment, if the first pad 14 or the second pad 15 is partially embedded in the substrate 10 and the upper surface of the first pad 14 or the second pad 15 is slightly higher than the first surface 11, the thickness of the first pad 14 or the second pad 15 exposed above the first surface 11 can be understood as the minimum distance from the upper surface of the first pad 14 or the second pad 15 to the first surface 11.

[0090] In this embodiment, the thickness of the solder resist layer 16 is greater than or slightly greater than the thickness of the first pad 14 or the second pad 15 exposed on the first surface 11 to protect the traces and pads within the opening. The provision of the solder resist layer 16 can reduce the distance between the filter chip 20 and the substrate 10. Combined with the provision of the first adhesive portion 41, it is more conducive to preventing the filler 50 from entering the cavity 25 of the filter chip 20.

[0091] In some embodiments, when the substrate 10 includes a solder resist layer 16, the thickness of the first adhesive portion 41 close to the side of the filter chip 20 is greater than the minimum distance from the lower surface 22 of the filter chip 20 to the first surface 11. It can be understood that the thickness of the first adhesive portion 41 close to the side of the filter chip 20 is greater than the minimum distance from the lower surface 22 of the filter chip 20 to the solder resist layer 16.

[0092] In the structures shown in FIG. 2 and FIG. 3 , the first adhesive portion 41 surrounding the filter chip 20 can be formed by a dispensing process.

[0093] In at least one embodiment, the adhesive portion 40 may further include a second adhesive portion 42 , and the second adhesive portion 42 at least covers at least one of the first welding point and the second welding point.

[0094] For example, in one embodiment, the second adhesive portion 42 only covers the second welding point; in another embodiment, the second adhesive portion 42 only covers the first welding point; in yet another embodiment, please continue to refer to FIG. 3 , in which the second adhesive portion 42 covers the first welding point and the second welding point.

[0095] In some embodiments, the second adhesive portion 42 may only cover the second welding point, or may cover the second welding pad 15 while covering the second welding point, which is not limited in this application.

[0096] In this embodiment, the second adhesive portion 42 can be formed at the first solder joint and / or the second solder joint by a dispensing process. It covers at least one of the first solder joint and the second solder joint, thereby protecting the solder joint of the non-filter chip and preventing the solder joint from falling off and causing a short circuit in the non-filter chip.

[0097] In some embodiments, the second adhesive portion 42 further covers at least a portion of a side surface of the non-filter chip 30 and at least one of a top surface of the non-filter chip 30 .

[0098] In this embodiment, the second adhesive portion 42 can cover the first solder joint on the upper surface 31 of the non-filter chip 30 while also covering other parts of the upper surface 31 of the non-filter chip 30. Specifically, it can cover the entire upper surface 31, or it can cover part of the upper surface 31. Specifically, it can cover the edge area and / or the middle area of ​​the upper surface 31 of the non-filter chip 30. It can be intermittent or continuous, and this application does not limit it. The second adhesive portion 42 covering at least part of the side of the non-filter chip 30 can be understood as covering only the side of the non-filter chip 30 near the second solder joint, or covering all sides of the non-filter chip 30. Specifically, it can cover only the part of the side near the substrate, or it can cover the entire side, and this application does not limit it.

[0099] In this embodiment, the second glue dispensing portion 42 covers the side surface and / or the upper surface 31 of the non-filter chip 30 , which can buffer external stress to a certain extent and protect the non-filter chip 30 .

[0100] In one embodiment, the second adhesive portion 42 may be formed by an adhesive dispensing process to cover at least a portion of a side surface of the non-filter chip 30 and at least one of an upper surface of the non-filter chip 30 .

[0101] In at least one embodiment, please refer to Figure 4 , which is a fourth schematic diagram of a multi-chip package structure provided by at least one embodiment of the present application. In Figure 4 , the solder mask layer 16 , the upper surface 21 of the filter chip 20 , the second solder pad 15 , and the upper surface 31 of the non-filter chip 30 are all covered by an adhesive portion 40 . The adhesive portion 40 on the solder mask layer 16 between the filter chip 20 and the non-filter chip 30 can be considered either the first adhesive portion 41 or the second adhesive portion 42 .

[0102] In some embodiments, a thickness difference between any two locations on the surface of the glue portion 40 (including the first glue portion 41 and / or the second glue portion 42 ) facing away from the substrate 10 is smaller than a second threshold.

[0103] Exemplarily, the adhesive portion 40 (including the first adhesive portion 41 and / or the second adhesive portion 42 ) may be formed by a full spraying process.

[0104] In some embodiments, the second threshold is 25 μm, 20 μm, or 15 μm.

[0105] In some embodiments, the fourth threshold is 10 μm or 5 μm.

[0106] In this embodiment, the difference in thickness between any two locations of the adhesive portion 40 is less than the second threshold, which can be understood as indicating that the thickness of the adhesive portion 40 ultimately formed through, for example, the full spraying process is substantially uniform. Specifically, the difference in thickness between any two locations of the adhesive portion 40 is within this range, resulting in a relatively uniform thickness of the adhesive portion 40 and improved packaging efficiency.

[0107] It is understandable that the thickness formed by the full spraying process is theoretically to form a glue part with uniform thickness, but there will be errors in the actual process. Therefore, the thickness difference between the thickest part and the thinnest part of the glue part 40 will be around 20μm, specifically within the range of 25μm, or within the range of 20μm, or within the range of 15μm.

[0108] For example, since there are multiple structures on the surface of the substrate 10 and the heights of the structures are different, when performing the full spraying process, the spraying time or direction for each position will also be different, so the thickness of the adhesive portion 40 finally formed on the surface of each structure will also be different. Specifically, for example, the thickness of the adhesive formed on the solder mask layer 15 is roughly uniform, with a small thickness difference, while the thickness of the adhesive formed on the upper surfaces of the two chips (filter chip 20 and / or non-filter chip 30) is roughly uniform, with a small thickness difference, but the thickness of the adhesive portion 40 on the solder mask layer 16 may be significantly different from the thickness of the adhesive portion 40 on the upper surfaces of the two chips (filter chip 20 and / or non-filter chip 30).

[0109] For example, due to the need for packaging reliability, the solder resist layer 16 needs to have a thicker glue material near the two chips (filter chip 20 and / or non-filter chip 30), or based on the need to relieve stress, the upper surface or side of one of the two chips needs to be covered with a thicker glue material. Therefore, when performing the full spraying process, the spraying time may be extended or the spraying direction may be adjusted at the corresponding position, so that the thickness of the glue material part 40 formed at this position will be greater than the thickness of the glue material part 40 at other positions. Therefore, even if the glue material part 40 is formed by the full spraying process, there will be a thickness difference in the range of 15μm, 20μm or even 25μm.

[0110] Furthermore, the thickness formed by the full spraying process is theoretically to form a glue portion with uniform thickness, but there will be errors in the actual process. Therefore, the thickness difference between any two positions of the glue portion 40 may be within the range of 10μm, or even within the range of 5μm.

[0111] In some embodiments, the adhesive portion 40 (including the first adhesive portion 41 and / or the second adhesive portion 42 ) may be formed by a dispensing process, as shown in FIG. 1 to FIG. 3 .

[0112] In this embodiment, the glue portion 40 is formed by a dispensing process, which can accurately place the glue at the required position, saving the amount of glue used. Reducing the amount of glue used can also reduce the impact of volatile gases of the glue on the packaged chip to a certain extent.

[0113] In the packaging scenario where the filter chip 20 and the non-filter chip 30 with a wire-bonding structure are on the same side of the substrate 10, one implementation method is to form a first glue portion 41 with a relatively uniform thickness through a full spraying process, which can not only meet the requirements of the closed cavity of the filter chip 20 and perform stress buffering on the upper surface of the filter chip 20, but also improve the packaging efficiency; the second glue portion is formed only at the required position through a dispensing process, which can reduce the use of glue and save process costs.

[0114] In another embodiment, a second glue portion 42 with a relatively uniform thickness is formed by a full spraying process, which can not only protect the solder joints and buffer the stress of the upper surface of the non-filter chip 300, but also improve the process efficiency; the first glue portion 41 is formed only at the required position through a dispensing process, which can meet the requirements of the closed cavity of the filter chip 20.

[0115] In another embodiment, a glue portion 40 with a relatively uniform thickness is formed by a full spraying process (the first glue portion 41 and the second glue portion 42 can be regarded as a whole), such as Figure 4, which can be formed in one step, reducing the process flow, greatly improving the packaging efficiency, reducing the process cost, and also buffering the stress borne by the filter chip 20 and the non-filter chip 30, thereby improving the packaging reliability.

[0116] It is understood that the thickness of the adhesive portion 40 formed by the full spraying process is the minimum distance from the position of the adhesive portion 40 on the upper surface facing away from the substrate 10 to the lower surface close to the substrate 10. This thickness is at least greater than the distance between the lower surface 22 of the filter chip 20 and the gap between the solder resist layer 16, so as to relieve stress on the side of the filter chip at and near the gap and block the filler 50 at the gap.

[0117] In at least one embodiment, please refer to Figures 5 and 6. Figure 5 is a fifth schematic diagram of a multi-chip package structure provided in at least one embodiment of the present application, and Figure 6 is a sixth schematic diagram of a multi-chip package structure provided in at least one embodiment of the present application. In the structures shown in Figures 5 and 6, the multi-chip package structure further includes a first chip 60. The substrate 10 includes a second surface 12 opposite to the first surface 11. The first chip 60 is disposed on the first surface 11 and / or the second surface 12.

[0118] Specifically, there may be one or more first chips 60. When there are multiple first chips 60, they may all be disposed on the first surface 11, or on the second surface 12, or some may be disposed on the first surface 11 and others on the second surface 12. The multiple first chips 60 may all be flip-chip mounted on the substrate 10, or all may be wire-bonded to the substrate 10, or some may be flip-chip mounted and others wire-bonded, and this application does not impose any specific limitations.

[0119] Exemplarily, FIG. 5 shows only one first chip 60 , which is flip-chip mounted on the second surface 12 , and the filler 50 is used to encapsulate the first chip 60 and fill the space between the first chip 60 and the second surface 12 .

[0120] For example, Figure 6 shows only one first chip 60, which is flip-chip mounted on the first surface 11, specifically on the side near the filter chip 20. The top surfaces of the first chip 60, the filter chip 20, and the non-filter chip 30 are all sprayed with the adhesive portion 40. However, a larger gap exists between the adhesive portion 40 and the first chip 60, allowing the filler 50 to enter the space between the first chip 60 and the first surface 11 through this gap.

[0121] In some embodiments, the first chip 60 may also be disposed on a side close to the non-filter chip 30 .

[0122] In some embodiments, the spacing between the first chip and the adjacent chip may be greater than or less than the first threshold. Preferably, the spacing between the first chip and the adjacent chip is less than the first threshold, thereby further reducing the package size of the multi-chip package structure by providing adhesive around at least the filter chip 20.

[0123] In some embodiments, the first chip 30 is a filter chip, a non-filter chip, or a passive component.

[0124] It can be understood that when the number of the first chip 30 is one, the first chip 30 can be a filter chip, a non-filter chip or a passive component. When the number of the first chips 30 is multiple, each first chip 30 can be a filter chip, a non-filter chip or a passive component. Among the multiple first chips 30, there can be chips of the same type or chips of different types, which is not limited in this application. The non-filter chip can be a low-noise amplifier chip, a power amplifier chip, a switch, a coupler, a matching circuit, etc. The passive component can be a capacitor or an inductor. Figure 5 only shows that the first chip 30 is a non-filter chip structure.

[0125] In at least one embodiment, a multi-chip package structure includes: a substrate 10, a filter chip 20, a non-filter chip 30, a first chip 60, an adhesive portion 40 (including a first adhesive portion 41), and a filler 50, wherein:

[0126] The substrate 10 includes a first surface 11, which is provided with a first solder pad 14 and a second solder pad 15. The filter chip 20 is flip-chip mounted on the first surface 11 and connected to the first solder pad 14. The non-filter chip 30 includes a bonding wire 33, the non-filter chip 30 is provided on the first surface 11, and the bonding wire 33 is connected to the second solder pad 15, and a first distance D1 is provided between the non-filter chip 30 and the filter chip 20. The first chip 60 is provided on the first surface 11, and a second distance D2 is provided between the first chip 60 and the filter chip 20 or the non-filter chip 30, and the first distance D1 is less than the second distance D2. The first glue portion 41 is provided on the first surface 11 around at least the filter chip 20, and a cavity 25 is formed between the filter chip 20, the first glue portion 41 and the substrate 10. The filler 50 is filled on the first surface 11 and covers the filter chip 20, the non-filter chip 30, the first chip 60 and the glue portion 40.

[0127] Please continue to refer to FIG. 6 . In the structure shown in FIG. 6 , the first chip 60 is disposed on the first surface 11 . For the description of the first chip 60 , reference may be made to the relevant description of the above embodiments, and this application will not elaborate on it any further.

[0128] It can be understood that the first distance D1 between the filter chip 20 and the non-filter chip 30 can be the minimum distance between the two chips, specifically the minimum distance between the sides of the two chips, or the minimum distance between the side of the filter chip 20 and the bonding lead 33 of the non-filter chip 30, or the minimum distance between the second pad 15 connected to the bonding lead 33 as shown in Figure 6, which is not limited in this application.

[0129] In this embodiment, in a multi-chip scenario, the filter chip's requirement for a sealed cavity can be met by providing an adhesive portion. The provision of the adhesive portion enables the filter chip and the non-filter chip with a wire bonding structure to be packaged on the same side of the substrate, shortening the connection line between the filter chip and the non-filter chip, and reducing the negative impact on operating performance caused by an excessively long connection line. This not only meets the operating performance requirements, but also reduces the package size and saves packaging costs. Furthermore, providing the adhesive portion around the filter chip can also shorten the first distance between the filter chip and the non-filter chip with a wire bonding structure, so that the first distance is less than the second distance between the first chip and the filter chip or the non-filter chip with a wire bonding structure. Compared to the use of a film package for the filter chip 20 and the non-filter chip with a non-wire bonding structure, the package size can be further reduced, saving packaging costs.

[0130] It should be noted that other structures and corresponding effects of this embodiment can refer to the relevant descriptions in the above embodiments, and this application will not go into details here.

[0131] In at least one embodiment, a multi-chip package structure includes: a substrate 10, a filter chip 20, a non-filter chip 30, an adhesive portion 40 (including a third adhesive portion 43), and a filler 50, wherein:

[0132] The substrate 10 includes a first surface 11 , on which a solder resist layer 16 , a first pad 14 and a second pad 15 are provided. The solder resist layer 16 has at least a first opening and a second opening. The first pad 14 and the second pad 15 are located in the first opening and the second opening respectively.

[0133] The filter chip 20 is flip-chip mounted in the first opening and connected to the first pad 14 . The non-filter chip 30 includes a bonding wire 33 . The non-filter chip 20 is disposed in the second opening, and the bonding wire 33 is connected to the second pad 15 .

[0134] The adhesive portion 40 includes a third adhesive portion 43 disposed on the first surface 11 to cover the solder mask 16, the filter chip 20, and the non-filter chip 30. A cavity is formed between the filter chip 20, the third adhesive portion 43, and the substrate 10. A filler 50 is filled on the first surface 11 and covers the adhesive portion 40.

[0135] In a specific embodiment, the third glue part 43 can be formed on the solder mask layer 16, the upper surface 21 of the filter chip 20 and the upper surface 31 of the non-filter chip 30 by a full spraying process or a dispensing process. The relevant description and effects can be referred to the relevant contents of the above embodiments, and this application will not repeat them.

[0136] In some embodiments, the thickness of the third adhesive portion 43 is relatively uniform, and the thickness difference between any two positions thereof is within a range of 25 μm, or within a range of 20 μm, or within a range of 15 μm.

[0137] In some embodiments, the thickness of the third adhesive portion 43 is relatively uniform, and the thickness difference between any two positions thereof is within 10 μm or within 5 μm. For related descriptions, reference may be made to the corresponding contents of the above embodiments, and the embodiments of this application will not be repeated here.

[0138] In some embodiments, the non-filter chip 30 also includes a first solder joint and a second solder joint, and the glue part 40 also includes a fourth glue part 44. The fourth glue part 44 is arranged on the surface of the third glue part 43 facing away from the substrate 10 through a dispensing process to cover at least one of the first solder joint and the second solder joint; wherein the first solder joint is a solder joint connecting the bonding lead 33 and the upper surface 31 of the non-filter chip 30, and the second solder joint is a solder joint connecting the bonding lead 33 and the second pad 15.

[0139] In the embodiment of the present application, on the basis of setting the third glue part 43, a fourth glue part 44 is further set on at least one of the first solder joint and the second solder joint through a dispensing process, which can better protect the first solder joint and the second solder joint, effectively prevent the solder joints of the non-filter chip 30 from falling off, and further improve the reliability of the multi-chip packaging structure.

[0140] In at least one embodiment, a fourth adhesive portion 44 may be pre-disposed on at least one of the first solder joint and the second solder joint, and then a third adhesive portion 43 may be disposed to cover the fourth adhesive portion 44 , the solder resist layer 16 , the filter chip 20 , and the non-filter chip 30 .

[0141] In one embodiment, a radio frequency front-end module is provided. The packaging structure of the radio frequency front-end module includes the multi-chip packaging structure provided in this application, such as the multi-chip packaging structure provided in the above-mentioned embodiments. In addition, the radio frequency front-end module also includes components such as antennas, amplifiers, inductors, and capacitors, which are not limited in this embodiment.

[0142] The RF front-end module provided in the present application includes the above-mentioned multi-chip packaging structure, which can reduce the overall packaging size of the module to a certain extent and improve the module packaging reliability.

[0143] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A multi-chip packaging structure, wherein: A substrate, comprising a first surface, wherein the first surface is provided with a first pad and a second pad; A filter chip, flipped on the first surface and connected to the first pad; A non-filter chip, comprising a bonding wire, wherein the non-filter chip is disposed on the first surface, and the bonding wire is connected to the second pad; A glue part, the glue part includes a first glue part, the first glue part is at least arranged around the filter chip on the first surface, and a cavity is formed between the filter chip, the first glue part and the substrate; The filler is filled on the first surface and covers the filter chip, the non-filter chip and the adhesive part.

2. The multi-chip package structure according to claim 1, wherein: The distance between the filter chip and the non-filter chip is smaller than a first threshold.

3. The multi-chip package structure according to claim 2, wherein: The first threshold is 100 μm or 50 μm.

4. The multi-chip package structure according to claim 1, wherein: A thickness of a portion of the first adhesive portion close to a side surface of the filter chip is greater than a minimum distance from a lower surface of the filter chip to the first surface.

5. The multi-chip package structure according to claim 1, wherein: The substrate comprises a solder resist layer having at least a first opening and a second opening, the first solder pad and the second solder pad are respectively located in the first opening and the second opening, and a first glue portion arranged around the filter chip is at least partially located on the solder resist layer.

6. The multi-chip package structure according to claim 5, wherein: The thickness of the solder resist layer is greater than the thickness of the first pad or the second pad exposed on the first surface.

7. The multi-chip package structure according to claim 1, wherein: The glue part further includes a second glue part, the non-filter chip further includes a first solder joint and a second solder joint, and the second glue part at least covers at least one of the first solder joint and the second solder joint; The first solder joint is a solder joint where the bonding wire is connected to the upper surface of the non-filter chip, and the second solder joint is a solder joint where the bonding wire is connected to the second pad.

8. The multi-chip package structure according to claim 7, wherein: The second adhesive portion further covers at least a portion of a side surface of the non-filter chip and at least one of an upper surface of the non-filter chip.

9. The multi-chip package structure according to claim 1, wherein: The thickness difference between any two positions of the adhesive portion is smaller than a second threshold value, and the second threshold value is 25 μm, 20 μm or 15 μm.

10. The multi-chip package structure according to claim 1, wherein: There is a gap between at least a portion of the first adhesive portion close to the filter chip and the side surface of the filter chip; or at least a portion of the first adhesive portion close to the filter chip is attached to the side surface of the filter chip.

11. The multi-chip package structure according to claim 1 or 10, wherein: The first adhesive portion covers at least a portion of the upper surface of the filter chip.

12. The multi-chip package structure according to claim 1, wherein: The multi-chip packaging structure further includes a first chip, the substrate includes a second surface opposite to the first surface, and the first chip is disposed on the first surface and / or the second surface.

13. The multi-chip package structure according to claim 12, wherein: The first chip is a filter chip, a non-filter chip or a passive component.

14. A multi-chip packaging structure, wherein: A substrate, comprising a first surface, wherein the first surface is provided with a first pad and a second pad; A filter chip, flipped on the first surface and connected to the first pad; A non-filter chip, comprising a bonding wire, wherein the non-filter chip is disposed on the first surface, and the bonding wire is connected to the second pad, and a first distance exists between the non-filter chip and the filter chip; A first chip is disposed on the first surface, a second distance exists between the first chip and the filter chip or the non-filter chip, and the first distance is smaller than the second distance; The adhesive part includes a first adhesive part, wherein the first adhesive part is at least arranged around the filter chip and on the first surface, and a cavity is formed between the filter chip, the first adhesive part and the substrate; The filler is filled on the first surface and covers the filter chip, the non-filter chip, the first chip and the adhesive part.

15. A multi-chip packaging structure, wherein: A substrate, comprising a first surface, the first surface being provided with a solder resist layer, a first pad and a second pad, the solder resist layer having at least a first opening and a second opening, the first pad and the second pad being located in the first opening and the second opening respectively; A filter chip is flipped in the first opening and connected to the first pad; a non-filter chip, comprising a bonding wire, wherein the non-filter chip is disposed in the second opening, and the bonding wire is connected to the second pad; A glue part, the glue part includes a third glue part, the third glue part is arranged on the first surface to cover the solder resist layer, the filter chip and the non-filter chip, and a cavity is formed between the filter chip, the third glue part and the substrate; The filling material is filled on the first surface and covers the adhesive material portion.

16. The multi-chip package structure according to claim 15, wherein: The non-filter chip further includes a first solder joint and a second solder joint, and the glue part further includes a fourth glue part, which is disposed on a surface of the third glue part away from the substrate through a dispensing process to cover at least one of the first solder joint and the second solder joint; The first solder joint is a solder joint where the bonding wire is connected to the upper surface of the non-filter chip, and the second solder joint is a solder joint where the bonding wire is connected to the second pad.

17. A radio frequency front-end module, wherein: Comprising the multi-chip packaging structure as described in any one of claims 1-16.

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