Method for forming electrodes and semiconductor device

Abstract

Disclosed is a method forming an electrode and a transistor device. The transistor device comprises a gate runner (41) and a drain runner (43) that are spaced apart from each other. The gate runner and the drain runner comprise a respective first device electrode layer and a second device electrode layer (421, 423), wherein, in the gate runner (41), the first device electrode layer (411) protrudes for a first distance (p11) in a direction facing away from the drain runner (43) and protrudes less than the first distance (p11) below the second device electrode layer (421) in the direction of the drain runner (43), and, in the drain runner (43), the first device electrode layer (413) protrudes for a second distance (p31) different from zero below the second device electrode layer (423) in the direction of the gate runner (41).

Description

METHOD FOR FORMING ELECTRODES AND SEMICONDUCTOR DEVICE

[0001] This disclosure relates in general to a method for forming electrically conducting electrodes, above a semiconductor body.

[0002] Dependent on the specific type of semiconductor device implemented in a semiconductor body, various kinds of electrodes may be formed above the semiconductor body. The electrodes are connected to active device regions of the semiconductor device and may provide for an external connection to the active device regions. Electrodes formed above a semiconductor body of a vertical transistor device, for example, include a source electrode connected to source regions of the transistor device, a gate runner and a gate pad connected to gate electrodes of the transistor device, and a drain runner, for example.

[0003] One example relates to a transistor device. The transistor device includes a gate runner and a drain runner that are spaced apart from each other. Each of the gate runner and the drain runner includes a respective first device electrode layer and a second device electrode layer. In the gate runner, the first device electrode layer protrudes for a first distance different from zero below the second device electrode layer in a direction facing away from the drain runner and protrudes less than the first distance below the second device electrode layer in the direction of the drain runner. In the drain runner, the first device electrode layer protrudes for a second distance different from zero below the second device electrode layer in the direction of the gate runner.

[0004] Another example relates to a method that includes patterning an electrically conducting layer. Patterning the electrically conducting layer includes forming an etch mask having an opening on top of the electrically conducting layer, wherein the opening includes beveled sidewalls, and etching portions of the electrically conducting layer exposed at a bottom of the opening and portions of the etch mask, so that the opening widens during the etching process and an opening with beveled edge surface is formed in the first electrically conducting layer.

[0005] Yet another example relates to a method that includes forming an electrically conducting via. The method includes forming a via trench, forming a first tungsten layer in a first the deposition process such that the first tungsten layer lines sidewalls and a bottom of the via trench, and forming a second tungsten layer in a second deposition process on top of the first tungsten layer such that the second tungsten layer closes the via trench. Each of the first and second deposition processes uses WFe as a precursor gas, and at least one of the first and second deposition processes additional uses nitrogen gas. The nitrogen gas flow in the first deposition process is lower than in the second deposition process.

[0006] Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like features.

[0007] Figures 1 A-1F illustrate one example of a method for forming an electrode that includes a portion of a first electrically conducting layer and a portion of a second electrically conducting layer;Figure 2 illustrates the electrode formed in the method according to Figures 1A-1F in greater detail;Figures 3 A-3B each illustrate a top view of a transistor device according to one example;Figure 4 illustrates a vertical cross-sectional view of one portion of a source electrode, a gate runner, and a drain runner of a transistor device;Figure 5 illustrates a portion of the source electrode and the gate runner in greater detail, Figure 6 illustrates a portion of the gate runner and the drain runner in greater detail;Figure 7 illustrates one example of transistor cells that each include a gate electrode;Figure 8 illustrates one example of the gate electrodes in greater detail;Figure 9 illustrates one example of an edge region of a transistor device;Figure 10 illustrates one example of the edge region illustrated in Figure 9 in a section plane different from the section plane illustrated in Figure 9;Figures 11 A and 1 IB each illustrate a void that may occur in the second electrically conducting layer formed in the method according to Figures 1A-1B;Figures 12A-12E illustrate one example of a method for patterning the first electrically conducting layer in order to avoid the formation of voids in the second electrically conducting layer; andFigures 13A-13C illustrate one example of a method for forming an electrically conducting via.In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and for the purpose of illustration show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

[0008] Figures 1 A-1F illustrate one example of a method for forming an electrode 41 above a semiconductor body 100. Figures 1 A-1F each illustrate a vertical cross-sectional view of one portion of the semiconductor body 100 during the process of forming the electrode 41. The vertical cross-sectional views illustrated in Figures 1A-1F are cross-sectional views in vertical section planes of the semiconductor body 100. Vertical section planes are section planes that are perpendicular to a first surface 101 of the semiconductor body 100, for example.

[0009] The electrode 41 formed in the process according to Figures 1A-1F is an electrode of a semiconductor device, for example. The electrode 41 may therefore also be referred to as device electrode. The semiconductor device may have active device regions integrated in the semiconductor body 100. The semiconductor device is a transistor device, for example. A more detailed example of a transistor device is explained herein further below.

[0010] According to one example, the semiconductor body 100 includes a monocrystalline semiconductor material. The monocrystalline semiconductor material may be a conventional monocrystalline semiconductor material such as, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or the like.

[0011] In Figures 1 A-1F only those features of the semiconductor body 100 are shown that relate to forming the device electrode 41. That is, device regions that may have been formed in the semiconductor body 100 before forming the electrode 41 are not illustrated.

[0012] It should be noted that the manufacturing process explained in the following may take place on a wafer level. That is, the manufacturing processes may be applied at the same time to a plurality of semiconductor bodies that are part of a wafer, which is finally separated into individual semiconductor bodies (chips, dies).

[0013] Figures 1A-1F illustrate forming one electrode 41. This, however, is only for illustration purposes. The same process may be used to form several electrodes above the semiconductor body 100.

[0014] Referring to Figure 1 A, the method includes forming a first electrically conducting layer 410 on top of an insulating layer 5 formed above the semiconductor body 100. More specifically, the insulating layer 5 is formed on top of a first surface 101 of the semiconductor body 100. The insulating layer 5 may include an oxide, a nitride, or the like. The first electrically conducting layer 410 is formed on top of a surface 501 of the insulating layer 5.

[0015] According to one example, the first electrically conducting layer 410 comprises a metal such as tungsten (W) or titanium (Ti). According to one example, the first electrically conducting layer 410 is a homogeneous layer of the same material such as tungsten or titanium. According to another example, the first electrically conducting layer 410 includes two or more partial layers. According to one example, one of the partial layers is a tungsten layer and the thickness of each of the one or more other partial layers is less than 10% or less than 5% of the thickness of the tungsten layer.

[0016] According to one example, the first electrically conducting layer 410 includes a first partial layer including titanium (Ti), a second partial layer including titanium nitride (TiN), and a third partial layer including tungsten (W).

[0017] According to one example, the first partial layer including Ti is formed on top of the insulating layer 5, the second partial layer including TiN is formed on top of the first partial layer, and the third partial layer including W is formed on top of the second partial layer. According to one example, each of the first, second and third partial layers is formed in a deposition process, so that the first partial layer ist deposited on the insulating layer 5, the second partial layer is deposited on the first partial layer, and the third partial layer is deposited on the second partial layer. According to another example, for forming the first and second partial layers, a Ti layer is deposited on the insulating layer 5, and the Ti layer is annealed in a nitrogen (N) containing ambient, so that a portion of the Ti layer is transformed into a TiN layer. A Ti layer remaining after the annealing process forms the first partial layer, and a TiN layer formed from portions of the Ti layer and nitrogen forms the second partial layer. The third partial layer may be deposited after the annealing process. In addition to the Ti containing first partial layer and the TiN containing second partial layer the layer stack resulting from the Ti layer and the annealing processing may include an intermediate layer between Ti layer and the TiN layer. The intermediate layer includes Ti and TiN, wherein the TiN concentration increases towards the second partial layer.

[0018] According to one example, a thickness of each of the first and second partial layers is less than 10% or even less than 5% of the thickness of the third partiallayer. According to one example, the thickness of the optional intermediate layer between the first and second partial layers is less than 10%, less than 5%, or less than 3% of the thickness of the third partial layer. One example of a first electrically conducting layer 410 that includes three partial layers is explained herein further below.

[0019] A thickness d410 of the first electrically conducting layer 410 is between 0.8 micrometers and 1.5 micrometers, in particular, between 0.8 micrometers and 1.2 micrometers, for example. The thickness d410 of the first electrically conducting layer 410 is the dimension of the first electrically conducting 410 layer in a direction perpendicular to the first surface 501 of the insulating layer 5.

[0020] Referring to Figure IB, the method further includes patterning the first electrically conducting layer 410 to form a first device electrode layer 411. Patterning the first electrically conducting layer 410 may include forming a first etch mask 310 above the first electrically conducting layer 410 and etching the first electrically conducting layer 410 with the etch mask 310 in place. The etch mask 310 protects certain regions of the electrically conducting layer 410 from being etched and, therefore, essentially defines the size and the position of the first device electrode layer 411. According to one example, the etching process for patterning the first electrically conducting layer 410 is an anisotropic etching process, such as a plasma matching process. Figure IB shows the semiconductor body 100 after the etching process and with the first etch mask 310 still in place.

[0021] Referring to Figure 1C, the method further includes removing the first etch mask 310 and forming a second electrically conducting layer 420. Forming the second electrically conducting layer 420 includes forming the second electrically conducting layer on top of portions of the insulating layer 5 not covered by the first electrode layer 411 and on top of the first electrode layer 411.

[0022] The second electrically conducting layer 420 includes a metal such as aluminum (Al) or copper (Cu), or a metal alloy such as AICu or AlSiCu, for example. AlSiCu is an alloy including aluminum, copper, and silicon. According to one example, the second electrically conducting layer 420 is a homogeneous layer including only onematerial. According to another example, the second electrically conducting layer includes two or more partial layers including different electrically conducting materials.

[0023] According to one example, the second electrically conducting layer 420 is thicker than the first electrically conducting layer 410. That is, a thickness d420 of the second electrically conducting layer 420 is greater than the thickness d410 of the first electrically conducting layer 410. According to one example, the thickness d420 of the second electrically conducting layer 420 is between 3 micrometers and 10 micrometers. According to one example, the second electrically conducting layer 420 is thicker than 5 micrometers (d420 > 5 pm) and thinner than 8 micrometers (d420 < 8 pm). According to one example, the thickness d420 of the second electrically conducting layer 420 is between 5.5 micrometers and 7.5 micrometers or between 5.5 micrometers and 6.5 micrometers.

[0024] According to one example, the thickness d410 of the first electrically conducting layer 410 is less than 30% of the thickness d420 of the second electrically conducting layer 420.

[0025] The method for forming the device electrode 41 further includes patterning the second electrically conducting layer 420 to form a second device electrode layer 412 at least partially on top of the first device electrode layer 411. Patterning the second electrically conducting layer 420 may include forming a second etch mask 320 above the second electrically conducting layer 420 and etching the second electrically conducting layer 420 with the second etch mask 320 in place.

[0026] Figure ID illustrates the second electrically conducting layer 420 after forming the etch mask 320. The etch mask 320 protects certain regions of the second electrically conducting layer 420 from being etched and, therefore, essentially defines the size and the position of the second device electrode layer 421. According to one example, the etching process for patterning the second electrically conducting layer 420 is an isotropic etching process, such as a wet etching process. In this type of process, portions of the second electrically conducting layer 420 below edge regions of the etch mask 320 are also etched.

[0027] According to one example, the etching process for patterning the second electrically conducting layer 420 etches the second electrically conducting layer 420 selectively relative to the first electrode layer 411, so that the first electrode layer 411 remains in place. Figure IE illustrates the semiconductor body 100 after the etching process for patterning the second electrically conducting layer 420.

[0028] The device electrode 41 includes the first device electrode layer 411 obtained by patterning the first electrically conducting layer 410 and the second device electrode layer 421 obtained by patterning the second electrically conducting layer 420. This is illustrated in Figure IF that shows the semiconductor body 100 after removing the etch mask 320 for patterning the second electrically conducting layer 420.

[0029] In the method explained herein before, the size of the first device electrode layer 411 can be adjusted rather precisely based on the size of the first etch mask 310. In the process of forming the second device electrode layer 421, however, there are certain restrictions and process fluctuations so that the size of the second device electrode layer 421 cannot be adjusted as precisely as the size of the first device electrode layer 411. This is explained with reference to Figure 2, which illustrates a detailed view of the device electrode 41 after forming the second device electrode layer 421 and with the second etch mask 320 still in place.

[0030] Referring to the above, forming the second device electrode layer 421 may include an isotropic etching process in which portions of the second electrically conducting layer 420 below the second etch mask 320 are removed. This type of etching process results in beveled edge surfaces of the second device electrode layer 421. The edge surfaces terminate the device electrode layer 421 in lateral directions. Just for the purpose of illustration, the edge surfaces of the second device electrode layer 421 illustrated in Figure 2 are straight. However, other shapes of the edge surfaces, such as curved edge surfaces may occur as well as a result of the etching process.

[0031] Referring to Figure 2, the second device electrode layer 421 has a bottom surface 521, which is a surface facing the first device electrode layer 411, and a top sur-face 621, which is a surface facing the second etch mask 320. Due to the isotropic etching process, a width w521 of the bottom surface 521 is larger than a width w621 of the top surface 621. The width w621 of the top surface 621 is also referred to as top width, and the width of the bottom surface 521 is also referred to as bottom width in the following.

[0032] Basically, the etching process is stopped, when the second electrically conducting layer 420 has been removed down to the first device electrode layer 41 land the insulating layer 5 to form the second device electrode layer 421. How much of the second electrically conducting layer 420 is removed below the second etch mask 320 before the second electrically conducting layer 420 has been etched down to the first device electrode layer 411 and the insulating layer 5 is dependent on the thickness d420 of the second electrically conducting layer 420. In Figure 2, u denotes distances between edges of the second etch mask 320 and the top surface 621 after the etching process has been finished. This distance u is referred to as undercut in the following.

[0033] There is a predefined relationship between the thickness d420 of the second electrically conducting layer 420 and the undercut u, which is dependent on the type of material of the second electrically conducting layer 420 and the etchant used in the etching process, for example. According to one example, the undercut u is essentially given by the thickness of the second electrically conducting layer 420, u « d420. In this example, when the etching process stops as soon as the second electrically conducting layer d420 has been edged down to the first device electrode layer 411 and the insulating layer 5 the undercut u (on both sides of the second etch mask 320) essentially equals the thickness d420.

[0034] When the etching process stops as soon as the second electrically conducting layer 420 has been edged down to the first device electrode layer 411 and the insulating layer 5, the bottom width w521 essentially equals the width w320 of the second etch mask 320. It should be noted that the widths explained herein before are dimensions of the respective electrically conducting device layers 411, 421 and the etch mask 320 in a first lateral direction xl.

[0035] One possible fluctuation in the process of forming the second device electrode layer 421 is the duration of the etching process. If, for example, the etching process continues after the second electrically conducting layer 420 has been edged down to the first device electrode layer 411 and the insulating layer 5, the bottom width 521 may become smaller than the width w320 of the second etch mask 320. That is, the second electrically conducting layer 420 continues to be etched in lateral directions after the second electrically conducting layer 420 has already been completely removed in sections not covered by the second etch mask 320.

[0036] Furthermore, in order to prevent the second etch mask 320 from being lifted off during the etching process, the width w320 of the second etch mask should not be smaller than 3 times the undercut u, w320 > 3u. Considering the process fluctuations explained above, the second etch mask 320 may be selected such that its width w320 is not smaller than 3.5 times the thickness d420 of the second electrically conducting layer, w320 > 3.5 d420. Thus, the thicker the second electrically conducting layer 420, the wider the second etch mask 320 and the larger the minimum of the bottom width w521 that can be obtained. Furthermore, due to the process fluctuations, the bottom width w521 may vary within a certain range, such as, for example, between 0.8 times and 1 time the width w320 of the second etch mask 320.

[0037] Referring to the above, the semiconductor device that has its active device regions integrated in the semiconductor body 100 is a transistor device, for example. According to one example, the device electrode 41 explained herein before is a gate runner of the transistor device. The transistor device is a power transistor device, which is a transistor device that may be used as an electronic switch, for example. A voltage blocking capability of the power transistor device is in the range of several hundred volts, for example.

[0038] Top views of two different transistor devices that each include the first device electrode 41 as a gate runner are illustrated in Figures 3A and 3B. Each of Figures 3 A and 3B illustrates a top view of the respective overall transistor device.

[0039] Referring to Figures 3 A and 3B, the transistor device further includes a source electrode 42 and a drain runner 43. The gate runner 41 surrounds the source electrode 42 in lateral directions of the semiconductor body 100. Lateral directions are directions that are essentially parallel to the first surface 101 of the semiconductor body 100. The drain runner 43 is arranged above a region of the semiconductor body 100 that is terminated by sidewalls 103-106 of the semiconductor body 100. Furthermore, the drain runner 43 surrounds the gate runner 41 and the source electrode 42 in lateral directions.

[0040] Referring to Figures 3 A and 3B, the transistor device may further include a gate pad 44 that is connected to the gate runner 44. The gate pad 44 forms a gate node G or is connected to a gate node G of the transistor device. The gate pad 44 may adjoin the gate runner 42, as illustrated in Figures 3A and 3B. Alternatively, the gate pad 44 is spaced apart from the gate runner 42, and a resistor (gate resistor) is connected between the gate pad 44 and the gate runner 42. The source electrode 42 forms a source node S of the transistor device. This is explained herein further below.

[0041] The source electrode 42, the gate pad 44, and the drain runner 43 are device electrodes that may be formed by the same process as the gate runner 41. In the example in which the gate pad 44 adjoins the gate runner 41, the gate pad 44 and the gate runner 41 are formed as one contiguous device electrode.

[0042] In the example illustrated in Figure 3 A, the gate pad 44 is arranged at a position that is essentially in the middle between two opposing sidewalls 103, 106 of the semiconductor body 100. In the example according to Figure 3B, the gate pad 44 is arranged at a position that is close to a corner formed by two adjacent sidewalls 105, 106 of the semiconductor body 100. The sidewalls 103-106 of the semiconductor body 100 result from separating a wafer including a plurality of semiconductor bodies into the individual semiconductor bodies, such as the semiconductor body 100 illustrated in Figures 3 A and 3B.

[0043] Figure 4 illustrates a vertical cross-sectional view of one portion of the source electrode 42, the gate runner 41, and the drain runner 43 according to one example. The vertical cross-sectional view illustrated in Figure 4 corresponds to a vertical cross-sectional view in a section plane A-A illustrated in Figures 3 A-3B, for example. In Figure 4, however, the semiconductor body 100 is only schematically illustrated. Active device regions of the transistor device are not shown.

[0044] Referring to Figure 4, each of the source electrode 42 and the drain runner 43 includes a respective first device electrode layer 412, 413 resulting from patterning the first electrically conducting layer 410, and a second device electrode layer 422, 423 resulting from patterning the second electrically conducting layer 420.

[0045] The first device electrode layers, in particular, the first device electrode layers 411, 412 of the gate runner 41 and the source electrode 42 may each act as a barrier layer that serves to prevent or at least reduce a diffusion of impurity atoms into the insulating layer 5 and the semiconductor body 100. According to one example, impurity atoms are atoms from a mold compound (illustrated in dashed lines) that may be formed on top of the semiconductor device after the wafer 1 has been separated into the individual devices. Such impurity atoms may negatively affect the functionality of the semiconductor devices. A diffusion of impurity atoms into the semiconductor body 100 is, in particular, an issue in regions close to the source electrode 42 and may be less critical in regions more distant to the source electrode 42, such as in regions between the gate runner 41 and the drain runner 43.

[0046] It is therefore desirable to reduce a size of a gap between the first device electrode layers 411, 412 of the gate runner 41 and the source electrode 42. This can be achieved by the method explained before, in which the first and second electrically conducting layers 410, 420 are patterned by separated processes. Patterning the first electrically conducting layer 410 using an anisotropic etching process, for example, makes it possible to produce smaller gaps between the first device electrode layers 411, 412 than between the second device electrode layers 421, 422 that are formed by patterning the second electrically conducting layer 420 using an isotropic etching process, for example.

[0047] In order to ensure that the transistor device is capable of withstanding the voltage between the gate runner 41 and the source electrode 42, it is desirable to precisely adjust the distance between the source electrode 42 and the gate runner 41. According to one example, this distance is defined by the first device electrode layers 411, 412. That is, in the direction of the source electrode 42 the first device electrode layer 411 of the gate electrode 41 protrudes from the second device electrode layer 421. Equivalently, in the direction of the gate runner 41, the first device electrode layer 412 of the source electrode 42 protrudes from the second device electrode layer 422.

[0048] The gap between the first and second device electrode layers 411, 412 of the gate runner 41 and the source electrode 42 is dependent on a voltage that may occur between the gate runner 41 and the source electrode 42 when the transistor device is in operation. Basically, the higher the voltage that may occur, the larger the distance. According to one example, the distance is selected from between 1.5 micrometers and 5 micrometers, in particular, between 1.6 micrometers and 3 micrometers, for example.

[0049] In order to reduce an overall size of the transistor device it may be desirable to reduce a width of the gate runner 41 is much as possible. The width of the gate runner 41 is essentially given by the width w411 of the first device electrode layer 411. Referring to the above the width w411 of the first device electrode layer 411 can be adjusted rather precisely in the first etching process. Given the process fluctuations explained above, the bottom width w521 and the top width w621 of the second device electrode layer 421 of the gate runner 41 cannot be adjusted as precisely as the width w411 of the first device electrode layer 411.

[0050] Given that the bottom width w521 explained above of the second device electrode layer 421 is limited towards small values; a small width w411 of the first device electrode layer 411 is desired; the distance between the gate runner 41 and the source electrode 42 should be defined by the first device electrode layer 411, 412; and, in particular, a certain cross-sectional area of the second device electrode layer 421 of the gate runner 41 is desired in order to obtain a low resistance of the gate runner 41, the gate runner 41 according to Figure 4 is implemented as an asymmetric gate runner 41. This is explained in detail with reference to Figure 5.

[0051] Figure 5 shows an enlarged view of the gate runner 41 according to Figure 4 and an adjacent portion of the source electrode 42. As explained above, the first device electrode layer 411 of the gate runner 41, in the direction of the source electrode 42, protrudes below the second device electrode layer 421. Such protrusion of the first device electrode layer 411 below the second device electrode layer 421 is labeled with pl 1 in Figure 5 and is referred to as first protrusion in the following. Implementing an asymmetric gate runner 41 includes that a second protrusion p21 of the first device electrode layer 411 of the gate runner 41 below the second device electrode layer 421 in the opposite direction, that is, in the direction of the gate runner 43 (not illustrated in Figure 5) is smaller than the first protrusion p 11 , p21 < p 11.

[0052] Referring to the above, the second device electrode layer 421 of the gate runner 41 is formed such that, even considering process fluctuations, the first device electrode layer 421 does not extend beyond the first device electrode layer 411 in the direction of the source electrode 43, so that the first device electrode layer 411 protrudes from the second device electrode layer 421 and the distance between the gate runner 41 and the source electrode 42 is defined by the distance between the first device electrode layers 411, 421.

[0053] The second protrusion p21 of the gate runner 41 being smaller than the first protrusion pl 1 includes that, in the direction of the drain runner 43, the second device electrode layer 421 may completely cover the first device electrode layer 411 or may even extend beyond the first device electrode layer 411 (as illustrated in dashed lines in Figure 5). According to one example, the first protrusion pl 1 is at least 100 nm, at least 500 nm, or at least 1 micrometer. According to one example, the first protrusion pl 1 is at least 2 times, at least 3 times, at least 5 times, or at least 10 times the second protrusion p21.

[0054] Figure 6 illustrates an enlarged view of the drain runner 43 and a portion of the gate runner 41 according to one example. In the example illustrated in Figure 6, the drain runner 43 is implemented such that the first device electrode layer 413 of the drain runner 43, in the direction of the gate runner 41, protrudes from the second device electrode layer 423 of the drain runner 43. The protrusion of the first device electrodelayer 413 of the drain runner 43 in the direction of the gate runner 41 is labeled with p31 in Figure 6 and is referred to as first protrusion in the following. According to one example, the first protrusion p31 is at least 100 nm, at least 500 nm, or at least 1 micrometer.

[0055] In the transistor device, a relatively high voltage may occur between the gate runner 41 and the drain runner 43, so that a distance between the gate runner 41 and the drain runner 43 is suitably selected in order to avoid a voltage breakdown. As illustrated in Figure 6, the process fluctuations in manufacturing the second device electrode layer 421 of the gate runner 41 may cause a variation in the distance between the gate runner 41 and the drain runner 43, dependent on whether or not the second device electrode layer 421 of the gate runner 41 extends beyond the first device electrode layer 411 in the direction of the drain runner 43. In the event that the second device electrode layer 421 does not extend beyond the first device electrode layer 411, the distance is given by the distance between the first device electrode layers 411, 413 of the gate runner 41 and the drain runner 43. In the event that the second device electrode layer 421 of the gate runner 41 extends beyond the first device electrode layer 411 in the direction of the drain runner 43, the distance is shorter.

[0056] However, it has been found that the breakdown voltage between the gate runner 41 and the drain runner 43 is not only dependent on the distance between the gate runner 41 and the drain runner 43, but is also dependent on the lateral position of that edge of the drain runner 43 that faces the gate runner 41. Thus, shifting the edge of the drain runner 43 in the direction of the gate runner, for example, by the second device electrode layer 423 extending beyond the first device electrode layer 413, may have a more negative effect on the breakdown voltage as shifting the edge of the gate runner 41 in the direction of the drain runner 43, for example, by the second device electrode layer 421 extending beyond the first device electrode layer.

[0057] According to one example, the drain runner 43 is asymmetric. That is, a second protrusion p32 of the first device electrode layer 413 from below the second device electrode layer 423 in a direction facing away from the gate runner 41 is smallerthan the first protrusion p31. Everything explained hereinabove with regard to the relationship between the first and second protrusions pl 1, p21 of the gate runner 41 applies to the first and second protrusions p31, p32 of the drain runner 43 as well.

[0058] The semiconductor body 100 of each of the transistor devices illustrated in Figures 3 A and 3B may include an inner region and an edge region. The inner region is essentially the region of the semiconductor body 100 that is arranged below the source electrode 42. The edge region surrounds the inner region and is arranged between the inner region and the sidewalls 103-106. In the inner region of the semiconductor body 100 a plurality of transistor cells are integrated.

[0059] One example of the transistor cells 10 that may be arranged in the inner region are illustrated in Figure 7. Figure 7 shows a vertical cross-sectional view of one portion of the semiconductor body 100, the insulating layer 5 and the source electrode 42. The vertical cross-sectional view illustrated in Figure 7 is a vertical sectional view in section plane B-B illustrated in Figures 3 A and 3B, for example.

[0060] Referring to Figure 7, each transistor cell 10 includes a source region 11 of a first doping type, a body region 12 of a second doping type complementary to the first doping type, and a gate electrode 21. The gate electrode 21 is adjacent to the body region 12, is dielectrically insulated from the body region 12 by a gate dielectric 22, and is arranged in a gate trench 120 extending from the first surface 101 of the semiconductor body 100 into the semiconductor body 100.

[0061] Referring to Figure 7, source and body regions 11, 12 of two neighboring transistor cells 10 may be arranged in a mesa region between neighboring gate trenches 120. In this example, the body regions 12 of the two neighboring transistor cells 10 may be formed by one contiguous doped region of the second doping type. Furthermore, two (other) neighboring transistor cells may share the gate electrode 21. That is, the gate electrodes 21 of two neighboring transistor cells may be formed by one contiguous electrode arranged in one gate trench 120.

[0062] The gate electrodes 21 include an electrically conducting material. Examples of the electrically conducting material include doped poly silicon, or a metal such as tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), or the like. The gate dielectric 22 includes an oxide, for example. According to one example, the oxide is silicon oxide (SiO2).

[0063] The source electrode 42 either forms the source node S or is connected to the source node S of the transistor device. The source electrode 42 is only schematically illustrated in Figure 7, so that the first and second device electrode layers 411, 412 are not shown.

[0064] The source electrode 42 is electrically connected to the source and body regions 11, 12 of the transistor cells 10. Connections between the source electrode 42 and the source and body regions 11, 12 are only schematically illustrated in Figure 7. Such connections may be implemented using electrically conducting vias that extend from the source electrode 42 through the insulating layer 5 down to the source and body regions 11, 12. Examples of such vias are explained herein further below.

[0065] The insulating layer 5 is formed on top of the first surface 101 and on top of the gate electrodes 21 and separates the source electrode 42 from the semiconductor body 100 and the gate electrodes 21.

[0066] Referring to Figure 7, the transistor device further includes a drift region 14 of the first doping type. The drift region 14 adjoins the body regions 12 of the transistor cells 10 so that the PN junctions are formed between the body regions 12 and the drift region 14. Furthermore, in the vertical direction, the drift region 14 is arranged between the body regions 12 and a drain region 13 of the first doping type. The drain region 13 may adjoin a second surface 102 opposite the first surface 101.

[0067] Optionally, a buffer region 16 of the first doping type and having a doping concentration that is higher than the doping concentration of the drift region 14 and lower than the doping concentration of the drain region 13 is arranged between the drift region 14 and the drain region 13.

[0068] Referring to Figure 7 and as explained above, the gate trenches with the gate electrodes 21 may be spaced apart from each other in the first lateral direction x. According to one example, the gate electrodes 21 are implemented as stripe electrodes (elongated electrodes). In this example, longitudinal directions of the gate electrodes 21 correspond to a second lateral direction perpendicular to the first lateral direction x.

[0069] One example of elongated gate electrodes 21 is illustrated in Figure 8. Figure 8 illustrates one portion of the semiconductor body 100 in a first horizontal section plane C-C shown in Figure 7 that cuts through the gate trenches 120 with the gate electrodes 21 and the gate dielectrics 22. The horizontal sectional plane C-C is essentially parallel to the first surface 101. In the example illustrated in Figure 8, the gate electrodes 21 longitudinally extend in the second lateral direction y.

[0070] According to one example, the transistor device is implemented as a superjunction transistor device. In this example, the transistor device includes a plurality of compensation regions 15 (illustrated in dashed lines) that are spaced apart from each other in a lateral direction of the semiconductor body 100. Each of the compensation regions 15 is adjacent to a respective portion of the drift region 14.

[0071] Just for the purpose of illustration, in the example illustrated in Figure 7, the compensation regions 15 are spaced apart from each other in the first lateral direction x. According to another example (not illustrated) the compensation regions 15 are spaced apart from each other in the second lateral direction y.

[0072] The transistor device can be operated in an on-state or an off-state. In the on-state, there are conducting channels in the body regions 12 along the gate dielectrics 22 between the source regions 11 and the drift region 14. For this, the drift region 14 adjoins the gate dielectric 22 and the body region 12 of at least one of the transistor cells 10.

[0073] Furthermore, each of the optional compensation regions 15 is adjacent to at least one of the portions of the drift region 14 and is connected to the source electrode 42. In the example illustrated in Figure 7, each of the compensation regions 15 adjoinsthe body region 12 of at least one transistor cell and is connected to the source electrode 42 via the respective body region 12.

[0074] The transistor device can be operated in a conventional way by applying a drive voltage (gate-source voltage) between the gate electrodes 21 and the source electrode 42. The transistor device is in the on-state (conducting state) when the drive voltage is such that conducting channels are generated in the body regions 12 along the gate dielectrics 22 between the source regions 11 and the drift region 14. The transistor device is in the off-state (blocking state) when the electrically conducting channels are interrupted.

[0075] The transistor device can be implemented as an N-type transistor device or as a P-type transistor device. An N-type transistor device, for example, is in the on- state, when the drive voltage is higher than a predefined positive threshold voltage and in the off-state, when the drive voltage is below the threshold voltage.

[0076] In an N-type transistor device, the doped regions of the first doping type are N-type regions and the doped regions of the second doping type are P-type regions. In a P-type transistor device, the doped regions of the first doping type are P-type regions and the doped regions of the second doping type are N-type regions.

[0077] The source regions 11, the body regions 12, the drift and compensation regions 14, 15, the buffer region 16, and the drain region 13 may also be referred to as (active) device regions of the transistor device.

[0078] Figure 9 shows a more detailed view of one example of the transistor devices in section plane A-A. Figure 9, in addition to the gate runner 41, the source electrode 42, and the drain runner 43 illustrates transistor cells arranged in the inner region 130 of the semiconductor body 100 below the source electrode 42, and an edge termination structure arranged in the edge region 140 below the gate runner 41 and the drain runner 43.

[0079] The transistor device illustrated in Figure 9 is a superjunction transistor device, which, in addition to the drift region 14, includes compensation regions 15. According to one example, illustrated in Figure 9, drift and compensation regions are not only arranged in the inner region 130 but are also arranged in the edge region 140. Drift regions arranged in the edge region 140 may be referred to as edge drift regions 14', and compensation regions arranged in the edge region 140 may be referred to as edge compensation regions 15'.

[0080] Referring to the above, the source and body regions 11, 12 of the transistor cells are connected to the source electrode 41. According to one example illustrated in Figure 9, the source and body regions 11, 12 are connected to the source electrode 41 through electrically conducting vias 45 that extend from the source electrode 41 through the insulating layer 5 to the source and body regions 11, 12 in the semiconductor body 100. Optionally, each transistor cell 10 includes a body contact regions 17 of the second doping type that provides for an ohmic contact between the body region 12 and the respective electrically conducting via 45. The body contact regions 17 have a higher doping concentration than the body regions 12.

[0081] In the edge region, the transistor device may include an edge termination structure. Optionally, the edge termination structure includes an edge trench 6 (illustrated in dashed lines) extending from the first surface 101 into the edge region 140 of the semiconductor body 100 and filled with an electrically insulating layer 51. The optional edge trench 6 with the insulating layer 51 may surround the inner region 130 in lateral directions.

[0082] Referring to Figure 9, the edge termination structure may include a field electrode 31 arranged above the edge trench 6 and electrically connected to the gate runner 41 through an electrically conducting via 46. The field electrode 31 includes doped polysilicon, for example.

[0083] Referring to Figure 9, the transistor device further includes a field stop region 71 of the first doping type extending from the drain regions 13 or the buffer re-gion 16 along the sidewalls 103-106 to the first surface 101. The drain runner 43 is electrically connected to the field stop region 51. According to one example, the drain runner 43 is connected to the field stop region 51 through an electrically conducting via 48. According to one example, the drain runner 46 is connected to the field stop region 73 only in regions of the four corners of the semiconductor body 100.

[0084] Referring to the above, each of the transistor cells 10 includes a gate electrode 21. The transistor cells are out of view in Figures 3 A and 3B. For the purpose of illustration, the position of some of the gate electrodes 21 relative to the source electrode 42, the gate runner 41, and the gate pad 44 is illustrated by bold lines in Figures 3A and 3B. In the example illustrated in Figures 3A and 3B, the gate electrodes 21 are elongated electrodes which are spaced apart from each other in a first lateral direction x. Longitudinal directions of the gate electrodes 21 correspond to a second lateral direction y perpendicular to the first lateral direction x, for example.

[0085] The gate electrode 21 of each transistor cell is electrically connected to the gate runner 41 at least at one longitudinal end of the respective gate electrode 21. Connections between the gate electrodes 21 and the gate runner 41 are not illustrated in Figures 3 A and 3B. One example for connecting the gate electrodes 21 to the gate runner 42 is illustrated in Figure 10.

[0086] Figure 10 shows a vertical cross-sectional view of the transistor device in a section plane D-D illustrated in Figures 3 A-3B that is essentially parallel to the longitudinal directions of the gate electrodes 21 and that cuts through one of the gate electrodes 21. Figure 10 shows a portion of the inner region 130 and the edge region 140 of the semiconductor body 100, a portion of the source electrode 42 and the gate runner 41. The drain runner 43 and the field stop region 71 are not illustrated in Figure 10.

[0087] In the example illustrated in Figure 10, the gate electrode 21 is connected to the gate runner 42 via the field electrode 31. For this, a contact finger 32 extends, in the insulating layer 5, from the field electrode 31 to the gate electrode 21 and is connected to the gate electrodes 21 at a longitudinal end of the gate electrode 21.

[0088] The field electrode 31 and the contact finger can be formed by the same process, so that the field electrode 31 and the contact finger 32 can formed by one contiguous electrode layer. The electrode layer is an electrically conducting layer such as a doped polysilicon layer, for example.

[0089] Forming the second electrically conducting layer 420 in the method illustrated in Figures 1 A-1F may include a deposition process. In the process of forming the second electrically conducting layer 420 growth disturbances may occur. Such growth disturbances may result in voids formed in the second electrically conducting layer 420. Figures 11 A and 1 IB illustrate a second electrically conducting layer 420 including a void V according to different examples. In the example illustrated in Figure 11 A, the void V is open towards the surface of the second electrically conducting layer 420, in the example illustrated in Figure 1 IB, the void V is closed and entirely surrounded by sections of the second electrically conducting layer 420. Any type of void V that may occur in the second electrically conducting layer 420 is undesirable as it may result in an uncontrolled etching of the second electrically conducting layer 420 in the region of the void V when the second electrically conducting layer 420 is patterned to form the second device electrode layers 421, 422, 423.

[0090] Voids may occur, in particular, in those regions in which the second electrically conducting layer 420 is grown on top of first device electrode layers, such as device electrode layer 411, 412 illustrated in Figures 11 A and 1 IB, and when a distance between neighboring first device electrode layers 411, 421 is short, such as less than 3 micrometers.

[0091] It has been found that the occurrence of growth disturbances resulting in a void V occurs, in particular, at sharp edges of the first device electrode layers 411, 421.

[0092] Figures 12A-12E illustrate one example of a method for forming edges of two neighboring device electrode layers, such as device electrode layers 411, 421 illustrated in Figures 11 A and 1 IB, such that growth disturbances in a second electricallyconducting layer 420 (not illustrated in Figures 12A-12E) formed on top of the first electrically conducting layer are reduced, so that voids are less likely to occur.

[0093] Figure 12A shows a vertical cross-sectional view of one portion of the insulating layer 5, the first electrically conducting layer 410 formed on top of the insulating layer 5, and the first etch mask 310. The first etch mask 310 is a photoresist, for example. A thickness of the first etch mask 320 is between 3 micrometers and 5 micrometers, for example.

[0094] Just for the purpose of illustration, the first electrically conducting layer 410 according to Figures 12A -12E includes three partial layers, a first partial layer 4101, a second partial layer 4102, and a third partial layer 4103. The first partial layer 4101 is a titanium (Ti) layer, the second partial layer 4102 is a titanium nitride (TiN) layer, and the third partial layer is a tungsten layer (W), for example. The thickness of each of the first and second partial layers 4101, 4102 is less than 5% of the thickness of the third partial layer 103, for example. According to one example, the thickness of the third partially or 4103 is between 0.8 micrometers and 1.2 micrometers, for example.

[0095] Figure 12A illustrates the first etch mask 310 after forming an opening 311 in the first etch mask 310. According to one example, the opening 311 of the first etch mask 310 has beveled sidewalls 312 such that the trench 311 narrows towards a trench bottom which is formed by the first electrically conducting layer 410. According to one example, an angle of the sidewalls 312 relative to the surface of the first electrically conducting layer is between 70° and 80°.

[0096] Figure 12D illustrates the first electrically conducting layer 410 after the third partial layer 4103 has been etched down to the second partial layer. 102. Figures 12B and 12C illustrate the first electrically conducting layer 410 at different stages of the etching process. As can be seen from Figures 12B-12D, the etchant used in the etching process is such that it not only etches the first electrically conducting layer 410, but also etches away portions of the etch mask 310. At first, as illustrated in Figure 12B, the first electrically conducting layer 410 is mainly etched in regions adjoining a bottom of the opening 311 in the etch mask 310. Furthermore portions of the sidewall 312 of theopening in the etch mask 310 are etched, which results in a decrease of the angle between the sidewalls and the surface of the first electrically conducting layer 410 below the etch mask 310.

[0097] As illustrated in Figure 12C, as the etching process continues, portions of the etch mask 310 are removed from above the surface of the electrically conducting layer 410, so that exposed portions of the surface of the electrically conducting layer 410 are etched.

[0098] In the first part of the etching process illustrated in Figure 12B, a first portion 431 of an opening (trench) 430 is formed in the first electrically conducting layer 410. This first portion 431 extends from the bottom of the opening 311 of the etch mask 310 into the first electrically conducting layer 410 and has sidewalls that have a first angle a relative to the horizontal plane. The first a angle is between 70° and 85°, for example. The horizontal plane is parallel to the surface 501 of the insulating layer 5, for example.

[0099] In the second part of the etching process illustrated in Figure 12C, the first portion 431 of the opening 430 extends further down into the first electrically conducting layer 410. Furthermore, the opening formed in the first electrically conducting layer 410 is widened by etching the first electrically conducting layer 410 in those regions that were covered by the etch mask 310 at the beginning of the etching process. In Figure 12C, reference number 432 denotes a widened portion of the trench 430 that is formed in the second part of the etching process. A second angle 0 between sidewalls of the widened portion 432 is lower than the first angle a. According to one example, the second angle is between 20° and 30°, in particular between 21° and 25°.

[0100] The trench 430 at the end of the etching process of etching the third partial layer 4103 has a first trench portion 431 having sidewalls with the first angle a relative to the horizontal plane and a widened second trench portion 432 with the smaller second angle 0 relative to the horizontal plane. The overall surface of the second portion432 is greater than the overall surface of the second portion 431, so that the second electrically conducting layer 420 (not illustrated in Figures 12A-12C) is mainly grown on the second portion 432 having the relatively small second angle 0 relative to the horizontal plane. As compared to growing the second electrically conducting layer 420 on essentially perpendicular sidewalls that may result from a conventional etching process, the risk that growth disturbances occur in the second electrically conducting layer 420 formed on top of the first electrically conducting layer 410 is significantly reduced.

[0101] According to one example, illustrated in Figures 12A-12D, the first and second sidewalls portions are essentially straight resulting in an edge between the first and second sidewall portions, wherein an angle in the edge region is significantly greater than 90°. According to another example illustrated in dashed lines in Figure 12D, the etching process may result in first and second side-wall portions 431, 432 with a smooth transition from the sidewalls of the first trench portion 431 to the sidewalls of the second trench portion 432. In each case, the sidewalls of the second trench portion 432 have a portion in which the angle 0 relative to the horizontal plane is smaller than the first angle a and is between 20° and 30°, for example.

[0102] The etchant used in the etching process includes chlorine, oxygen, and / or argon, for example.

[0103] According to one example, the etchant used in the process for etching the third partial layer 4103 does not etch the first and second partial layers 4101, 4102. In this case, after the third partial layer 4103 has been etched, another etchant is used to etch the first and second partial layers 4101, 4102 down to the insulating layer 5. The previously etched third partial layer 4103 may act as an etch mask in this etching process.

[0104] Figure 12E illustrates the arrangement shown in Figure 12D after etching the first and second partial layers 4101, 4102 using the third partial layer 4103 as an etch mask.

[0105] Referring to the above, the transistor device may include a plurality of electrically conducting via, such as vias 45 connecting the source electrode 42 to the source and body regions 11, 12, vias 46 connecting the gate runner 41 to the first field electrode 31, vias 47 connecting the drain runner 43 to the second field electrode 32, or vias 48 connecting the drain runner 43 to the field stop region 71.

[0106] According to one example, these vias 45, 46, 47, 48 are formed by the first electrically conducting layer 410 portions of which form the first device electrode layers 411, 412, 413. One example of a method for forming the vias 45, 46, 47, 48 based on the first electrically conducting layer 410 is explained in the following with reference to Figures 13A-13C. Each of these figures shows one via during the manufacturing process.

[0107] Referring to Figure 13 A, the method includes forming a via trench 81 in the surface 501 of the insulating layer 5. The vertical dimension of the via trench is dependent on the type of via that is to be formed. That is, for forming vias 45 connecting the source electrode 42 to the source and body regions 11, 12 or for forming vias 48 that connect the drain runner 43 to the field stop region 71, the via trench 81 may extend through the insulating layer 5 into the semiconductor body 100. For forming vias 46, 47 that connect the gate runner 41 and the drain runner 43 to field electrodes 31, 32, the via trench 81 may extend into the insulating layer 5 and to the respective field electrode 31, 32. In Figures 13A-13C, only the surface 501 of the insulating layer 5 is illustrated. The semiconductor body or field electrodes are not illustrated in these drawings.

[0108] Referring to Figure 13B, the method includes a first deposition process in which a first layer 4110 of the second electrically conducting layer 410 is deposited on the sidewalls and the bottom of the via trench 81 and the surface 501 of the insulating layer 5. According to one example, the first layer 4110 is a layer of a partial layer including tungsten (W), such as the third partial layer 4103 illustrated in Figures 12A- 12E. The first and second partial layers 4101, 4102 are optional and, in the process according to Figures 13A-13C, may have been formed before forming the first layer 4110 or may be omitted.

[0109] Process parameter in the deposition process for forming the first layer 4110 are selected such that the first layer 4110 has a high tendency to line the sidewalls and the bottom of the via trench 81 and the surface 501 of the insulating layer 5. A thickness of the first layer 4110 (on top of the surface 501) is between 100 nanometers and 300 nanometers, in particular, between 200 nanometers and 300 nanometers, for example. Forming the first layer 4110 may include using WFe gas as a precursor. Forming the entire via based on the process that forms the first layer 4110 may result in a less mechanical robust first electrically conducting layer 410.

[0110] Thus, referring to Figure 13C, a second layer 4120 of the first electrically conducting layer 410 is formed using process parameters that are different from the process according to Figure 13B such that second layer 4120 has a high tendency to grow on horizontal planes and fill the trench 81. The second process, in addition to WFe may include nitrogen (N2) gas. Basically the first and second processes are different in the nitrogen flow during the deposition process. In the first process that forms the first layer 110, the nitrogen flow is lower than in the second process. According to one example, the nitrogen flow in the first process is even zero.[OlH] The thickness of the second layer 4120 above the surface 501 of the insulating layer 5, is between 600 nanometers and 900 nanometers, for example. An overall thickness of the first electrically conducting layer 410 is as explained herein further above.

[0112] Portions of the first and second layers 4110, 4120 in the trench 81 form the electrically conducting via 8. After forming the second layer 4120 a void VI may remain of the trench 81. The void VI may help to reduce mechanical stress that may result from depositing the first electrically conducting layer 410 in the via trench 81.

Claims

CLAIMS1. A transistor device, comprising: a gate runner (41) and a drain runner (43) that are spaced apart from each other, wherein each of the gate runner (41) and the drain runner (43) comprises a respective first device electrode layer (411, 413) and a second device electrode layer (421, 423), wherein, in the gate runner (41), the first device electrode layer (411) protrudes for a first distance (pl 1) different from zero below the second device electrode layer (421) in a direction facing away from the drain runner (43) and protrudes less than the first distance (pl 1) below the second device electrode layer (421) in the direction of the drain runner (43), and wherein, in the drain runner (43), the first device electrode layer (413) protrudes for a second distance (p31) different from zero below the second device electrode layer (423) in the direction of the gate runner (41).

2. The transistor device of claim 1, wherein the first distance (pl 1) is at least 100 nanometers.

3. The transistor device of claim 1, wherein the second distance (p31) is at least 100 nanometers.

4. The transistor device of any one of the preceding claims, wherein each of the first device electrode layers (411, 413) comprises at least one of tungsten and titanium.

5. The transistor device of any one of the preceding claims, wherein a thickness of each of the first device electrode layers (411, 413) is between 0.8 micrometers and 1.2 micrometers.

6. The transistor device of any one of the preceding claims, wherein each of the second device electrode layers (421, 423) comprises at least one of aluminum and copper.

7. The transistor device of any one of the preceding claims, wherein a thickness of each of the first and second device electrode layers (421, 423) is between 6 micrometers and 8 micrometers.

8. The transistor device of any one of the preceding claims, further comprising: a source electrode (42) spaced apart from the gate runner (41) in a direction facing away from the drain run (43), wherein the source electrode (42) comprises a first device electrode layer (412) and a second device electrode layer (422), and wherein the first device electrode layer (412) of the source electrode (42) protrudes below the second device electrode layer (422) of the source electrode (42) in the direction of the gate runner (41).

9. The transistor device of any one of the preceding claims, wherein a distance between the first device electrode layers (411, 412) of the gate runner (41) and the source electrode (42) is between 1.5 micrometers and 3 micrometers.

10. The transistor device of any one of the preceding claims, further comprising: a plurality of transistor cells (10) each comprising a source region (11) connected to the source electrode (21) and a gate electrode (21) connected to the gate runner (41).

11. The transistor device of claim 10, wherein the transistor cells (10) are at least partially integrated in a semiconductor body (100), and wherein the gate runner (41), the source electrode (42), and the drain runner (43) are formed above an insulating layer (5) formed above a surface (101) of the semiconductor body (100).

12. The transistor device of claim 10 or 11, wherein the semiconductor body (100) includes an inner region (130) and an edge region (130) surrounding the inner region (130) in lateral directions, wherein the transistor cells (10) are integrated in the inner region (130), andwherein the transistor device further comprises an edge termination structure arranged in and above the edge region (140).

13. The transistor device of claim 12, wherein the edge termination structure comprises an edge trench (6) extending from the first surface (101) into the edge region (140) of the semiconductor body (100) and filed with an insulating material (51).

14. A method, comprising: patterning an electrically conducting layer (410), wherein patterning the electrically conducting layer (410) comprises: forming an etch mask (310) having an opening (311) on top of the electrically conducting layer (410), wherein the opening (311) comprises beveled sidewalls (312); etching portions of the electrically conducting layer (410) exposed at a bottom of the opening (311) and portions of the etch mask (310), so that the opening (311) widens during the etching process and an opening (430) with a beveled edge surface is formed in the first electrically conducting layer (410).

15. The method according to claim 14, wherein the opening (430) in the electrically conducting layer (410) is formed to have a first portion (431) and a second portion (432), wherein a first angle (a) between sidewalls of the first portion (431) and a horizontal plane is larger than a second angle (0) between sidewalls of the second portion (432) and the horizontal plane.

16. The method according to claim 15, wherein the first angle (a) is between 70° and 85°.

17. The method according to claim 15 or 16, wherein the second angle (0) is between 20° and 30°.

18. The method according to any one of claims 14 to 17, wherein the first electrically conducting layer ( 10) comprises at least one of tungsten and titanium.

19. The method according to any one of claims 14 to 18, wherein a thickness of the first electrically conducting layer (410) is between 0.8 micrometers and 1.2 micrometers.

20. The method according to any one of claims 14 to 19, wherein the first electrically conducting layer (410) comprises a first partial layer (4101) comprising titanium, a second partial layer (4102) comprising titanium nitride, and a third partial layer (4103) comprising tungsten, wherein a thickness of each of the first and second partial layers (4101, 4102) is less than 5% of the thickness of the third partial layer (4103), wherein patterning the electrically conducting layer (410) comprises patterning the third partial layer (4103), and wherein the method further comprises etching the first and second partial layers (4101, 4102) below a bottom of the opening formed in the third partial layer (4103).

21. The method according to any one of claims 14 to 20, wherein the etch mask (310) comprises a photoresist.

22. The method according to any one of claims 14 to 21, further comprising: depositing a second electrically conducting layer (420) on top of the first electrically conducting layer (410) after removing the etch mask (310).

23. The method according to claim 22, wherein the second electrically conducting layer (420) comprises at least one of aluminum and copper.24 The method according to claim 23, wherein a thickness of the second electrically conducting layer (420) is between 6 micrometers and 8 micrometers.

25. A method, comprising: forming an electrically conducting via (8), wherein the method comprises: forming a via trench (81), forming a first tungsten layer (4110) in a first the deposition process such that the first tungsten layer (4110) lines sidewalls and a bottom of the via trench (81), and forming a second tungsten layer (4120) in a second deposition process on top of the first tungsten layer (4110) such that the second tungsten layer (4120) closes the via trench, wherein each of the first and second deposition processes uses WFe as a precursor gas, and wherein at least one of the first and second deposition processes additionally uses nitrogen gas, wherein a nitrogen gas flow in the first deposition process is lower than in the second deposition process.

26. The method according to claim 25, wherein the first layer (4110) is formed to have a thickness of between 100 nm and 300 nm.

27. The method according to claim 25 or 26, wherein the second layer (4120) is formed to have a thickness of between 600 nm and 900 nm.

28. The method according to any one of claims 25 to 27, wherein the via trench (81) is formed in a surface (501) of an insulating layer.

29. The method according to claim 28, wherein the insulating layer is an oxide layer.

30. The method according to claim 28 or 29, wherein the via trench (81) is formed to extend through the insulating layer (5) into a semiconductor body (100) on top of which the insulating layer (5) is formed.

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