A semiconductor die

Abstract

The disclosure relates to a semiconductor die, comprising a semiconductor body; a semiconductor device in an active area of the semiconductor body; an edge termination structure arranged laterally between the active area and a lateral edge of the die; a chipping stopper trench; the chipping stopper trench arranged laterally between the edge termination structure and the lateral edge of the die, wherein the chipping stopper trench is unfilled.

Description

[0001] A SEMICONDUCTOR DIE

[0002] TECHNICAL FIELD

[0003] The present application relates to a semiconductor die.

[0004] BACKGROUND

[0005] The semiconductor die may comprise a semiconductor body and a semiconductor device in an active area of the semiconductor body.

[0006] SUMMARY

[0007] Examples of the present application are directed at an advantageous semiconductor die.

[0008] In an embodiment, the application relates to the semiconductor die of claim 1. The semiconductor die may comprise a chipping stopper trench which is arranged laterally outward of an edge termination structure, i.e. laterally between the edge termination structure and a lateral edge of the die. In an embodiment, the chipping stopper trench is unfilled, e.g. not provided with a filler made of metal or the like.

[0009] In other words, the chipping stopper trench is left open. Generally, the chipping stopper may reduce or stop a crack or chipping propagation inwards (in direction to the edge termination structure / active area), e.g. in a sewing process during singulation of the die. In addition to reducing or stopping a crack propagation, the unfilled chipping stopper trench may optionally be used to introduce an implantation, e.g. to tune or improve a device behavior. In more general words, it may have advantages in terms of mechanical and electrical device properties.

[0010] Particular and / or alternative embodiments are provided in the remaining claims and the following description. Therein, the individual features shall be disclosed independently of a specific claim category, the disclosure relates to apparatus and device aspects but also to method and use aspects. If for instance a die manufactured in a specific way is described, this is also a disclosure of a respective manufacturing process, and vice versa. Any embodiment may for instance relate to the die, to a die set, or to a method or use.

[0011] As discussed in further detail below, one single or a plurality of laterally staggered chipping stopper trenches may be provided. A respective chipping stopper trench may be etched into the semiconductor body. As viewed for instance in a vertical cross-section, the sectional plane lying perpendicular to the lateral edge of the die or semiconductor body, a respective chipping stopper trench may extend from the first side of the semiconductor body into the semiconductor body.

[0012] The chipping stopper trench(es) may extend along the lateral edge or edges of the semiconductor die or body. Therein, a respective chipping stopper trench may extend continuously between adjacent lateral edges or may be interrupted in a comer between two lateral edges. As seen for instance in a vertical top view, a respective chipping stopper trench may form a closed line around the active area or may be interrupted locally, e.g. at one or some or of the corners between the lateral edges.

[0013] The edge termination structure may be arranged between the lateral edge of the die or semiconductor body and an active area of the die. In the active area, a device structure may be formed in the semiconductor body, for instance a transistor device structure. Generally, when elements are discussed with respect to the relative position, e.g. when viewed in a vertical cross-section, these elements are for instance arranged on the same side of the active area, i. e. at the same lateral edge of the semiconductor die or body (“outwards” meaning for instance closer to / towards the respective lateral edge, and “inwards” meaning closer to / towards the active area).

[0014] As viewed for instance in a vertical cross-section, the sectional plane lying perpendicular to the lateral edge of the die or semiconductor body, the edge termination structure may be arranged outward of the active area but inward of the chipping stopper trench or trenches (see below). In other words, the chipping stopper trench(es) may be arranged outward of the edge termination structure which, in turn, is arranged outward of the active area. "Vertical" or "vertically" may refer to a vertical direction which lies for instance perpendicular to a surface of the die, e. g. a surface of the semiconductor body. A first side and a second side of the semiconductor body may lie vertically opposite. "Above" may mean vertically aligned and closer to the first side of the semiconductor body or frontside of the die, "below" may mean vertically aligned and closer to the second side of the semiconductor body or the backside of the die. "Lateral" or "laterally" may refer to the lateral directions perpendicular to the vertical direction, in which for instance an area of the semiconductor body or die may be taken.

[0015] The semiconductor body may comprise a semiconductor substrate, for instance in combination with one or a plurality of epitaxial layers thereon. The semiconductor body may, for instance, be a silicon (Si), a silicon carbide (SiC), gallium nitride (GaN) or gallium arsenide (GaAs) semiconductor body.

[0016] A device structure or semiconductor device arranged in the active area may comprise a first load terminal arranged at a first side of the semiconductor body. In addition, it may comprise a second load terminal, which may be arranged at a vertically opposite second side of the semiconductor body. The device or device structure can for instance be a FET having a source terminal / region and a drain terminal / region in the semiconductor body, e.g. the source region at the first side of the semiconductor body and the drain region at the second side thereof.

[0017] In addition to the source region and the drain region, the device may comprise a body region to which a gate electrode capacitively couples. By way of example, the device may be a superjunction transistor device. In the semiconductor body, first regions made of a first doping type and second regions made of a second doping type may be formed. The first regions may be drift regions, and the second regions may be compensation regions. By way of example, the first doping type may be n-type and the second doping type may be p-type.

[0018] In an embodiment, a doping is introduced at a sidewall and / or bottom of the chipping stopper trench or trenches. The doping may, for instance, be implanted via the unfilled chipping stopper trench into the semiconductor body. In other words, the side wall and / or bot- tom, which define the respective chipping stopper trench laterally and downwards, may be formed by the semiconductor body.

[0019] In an embodiment, the chipping stopper trench has a lateral width of at most 0.8 pm, further upper limits being for instance at most 0.7 pm or 0.6 pm. Possible lower limits may be at least 0.1 pm or 0.2 pm. When a plurality of chipping stopper trenches are provided, each may have a respective lateral width, by way of example. Independently of these details, the lateral width may, for instance, be taken at the bottom of the respective chipping stopper trench, e.g. in a lateral transverse direction which lies perpendicular to a length extension of the respective chipping stopper trench.

[0020] When a plurality of chipping stopper trenches are provided, they may for instance be arranged with a pitch of not more than 3.5 pm, 3 pm, 2.5 pm, 2.0 pm or 1.5 pm. The pitch may be taken as a lateral center-to-center-distance, e.g. in the transverse direction. Possible lower limits of the pitch may for instance be at least 0.8 pm or 1.0 pm.

[0021] The semiconductor device may comprise a gate electrode arranged in a gate trench. In other words, the gate region may be arranged laterally aside the body region in a trench. In an embodiment, the gate trench extends deeper into the semiconductor body than the chipping stopper trench. In other words, a lower and of the chipping stopper trench is arranged at a larger vertical height (closer to the first side) than a lower end of the gate trench.

[0022] The semiconductor device may comprise a contact plug in a contact trench, the contact plug being for instance electrically connected to a load terminal of the device. The load terminal may for instance be a source terminal, the contact plug being a source contact, e.g. combined body / source contact. The contact plug may, for instance, intersect an insulation layer (interlayer dielectric) arranged on first side of the semiconductor body, e.g. may electrically connect the load terminal to a metallization above (e.g. source pad in case of the source contact). Independently of these details, the contact plaque may extend vertically into the semiconductor body.

[0023] In an embodiment, the contact trench, in which the contact plug is arranged, and the chipping stopper trench extends to the same vertical depth. In other words, the lower ends of the contact trench and the chipping stopper trench are arranged on the same vertical height in the semiconductor body. By way of example, the contact trench(es) and the chipping stopper trench(es) may be etched simultaneously.

[0024] In an embodiment, the contact trench and the chipping stopper trench have the same lateral width. As discussed above, the lateral width may, for instance, be taken at a lower end of the respective trench, e.g. in a respective transverse direction.

[0025] In an embodiment, the edge termination structure comprises a channel stopper in a channel stopper trench. The channel stopper trench may extend deeper into the semiconductor body than the chipping stopper trench. In other words, a lower end of the channel stopper trench may be arranged at a larger vertical depth (larger distance from the first side of the semiconductor body) than the chipping stopper trench. By way of example, the channel stopper trench may extend to the same vertical depth like a gate trench of the device.

[0026] The channel stopper trench may be filled with an insulating liner and a conductive filler, e.g. made of metal or polysilicon. By way of example, the channel stopper may be made of the same materials like a gate region arranged in the gate trench, the gate region and the channel stopper may for instance be manufactured in the same processing steps. Alternatively or in addition, the gate trench and the channel stopper trench may be etched simultaneously.

[0027] In an embodiment, the edge termination structure comprises at least two channel stoppers, each provided in a respective channel stopper trench. In other words, it may comprise a first channel stopper in a first channel stopper trench and a second channel stopper in a second channel stopper trench. The second channel stopper trench with the second channel stopper may be arranged laterally outside of the first channel stopper trench with the first channel stopper, e.g. as viewed in a vertical cross-section perpendicular to the lateral edge of the semiconductor die or body.

[0028] At least one channel stopper may be electrically connected to a runner, e.g. to a load contact runner. The load contact runner may be formed in the metallization in an area of the edge termination structure. It may, for example, run in parallel to a respective side of the active area and / or a respective lateral edge of the semiconductor body or die. By way of example, the load contact runner may surround the active area at least partly, e.g. form a load contact ring. The load contact runner may be on an electrical potential of a load terminal of the device, e.g. be electrically connected to the respective load terminal, for instance drain terminal. In other words, the load contact runner may be a drain runner, e.g. drain ring.

[0029] In an embodiment, which relates to the first and the second channel stopper, only one of these channel stoppers is electrically connected to the load contact runner. By way of example, the first channel stopper, which may be arranged laterally inside of the second channel stopper, may be electrically connected to the load contact runner. The second channel stopper may be left floating, e.g. the electrical conductive filler of the second channel stopper being not electrically contacted.

[0030] In an embodiment, an insulation layer is arranged on the semiconductor body. The insulation layer may serve as an interlayer dielectric and be arranged on the first side of the semiconductor body, e.g. directly on the first side. In an embodiment, the edge termination structure comprises a diffusion stopper trench which intersects the insulation layer vertically. As seen in a vertical top view, the diffusion stopper trench may extend around the active area, e.g. surround it at least partly or form a closed line around the active area. Independently of these details, the diffusion stopper trench may for instance reduce or prevent a diffusion from the lateral edge of the semiconductor die or body towards the active area, for instance a sodium diffusion.

[0031] In an embodiment, the chipping stopper trench or trenches extend(s) through the insulation layer down into the semiconductor body. In the semiconductor body, the chipping stopper trench(es) may have a vertical extension of, for example, at least 0.2 pm, a further lower limit being for instance at least 0.4 pm. Possible upper limits of the vertical extension in the semiconductor body may, for example, be at most 1.0 pm or 0.7 pm. The vertical extension may respectively be taken between the lower end of the respective chipping stopper trench and the first side of the semiconductor body. In an embodiment, the edge termination structure comprises a shallow trench which is filled with a dielectric material. The shallow trench with a field dielectric may form a shallow trench isolation, e.g. for a shielding of a device arranged in the active area from an electrical potential at the lateral edge of the semiconductor body or die (which may reach up from the backside there, for instance). In more general word, the field dielectric in the shallow trench can, for instance, provide for an electrical isolation or field reduction.

[0032] In an embodiment, a bottom of the shallow trench is arranged at a greater vertical depth (larger distance from the first side of the semiconductor body) than a bottom of the chipping stopper trench or trenches. In other words, the shallow trench may extend deeper into the semiconductor body than the chipping stopper trench or trenches.

[0033] As discussed above, the semiconductor device or device structure may comprise a plurality of superjunction transistor cells.

[0034] As discussed above, a plurality of chipping stopper trenches may be provided, e.g. laterally staggered as viewed in a vertical cross-section perpendicular to the lateral edge of the semiconductor die or body. Therein, at least one of the chipping stopper trenches may surround the active area completely, e.g. form a closed line. By way of example, all chipping stopper trenches may surround the active area completely, e.g. form respectively closed rings which are nested one in the other. Alternatively, however, at least one of the chipping stopper trenches may be interrupted, e.g. in some or all of the corners. By way of example, all chipping stopper trenches may respectively be interrupted in some or all of the corners.

[0035] In an embodiment, the chipping stopper trenches are arranged with a pitch of not more than 3.5 pm, further upper limits being 3.0 pm, 2.5 pm, 2.0 pm or 1.5 pm. Possible lower limits may for instance be at least 0.8 pm or 1.0 pm. The pitch may be taken as a center-to-cen- ter-distance, e.g. in a transverse direction perpendicular to the length extension of trenches.

[0036] In an embodiment, a die set is provided, which comprises a first semiconductor die and a second semiconductor die. The dies may differ in their respective area, the first semiconductor die having for instance a large die area than the second semiconductor die. Further, the first die may have a greater number of chipping stopper trenches between its edge ter- mination structure and the lateral edge than the second die. In other words, the second die, which has a smaller die area, may have n chipping stopper trenches, where n > 1, whereas the first semiconductor die has (n + m) chipping stopper trenches, where m > 1. In case of a smaller the die area, a cracking or chipping risk may be smaller, and a reduced number of chipping stopper trenches may allow for saving area.

[0037] In an embodiment, a die set comprising a first and a second semiconductor die is provided. Therein, the first semiconductor die may have a lateral edge with a greater length and a greater number of chipping stopper trenches between the edge termination structure and the lateral edge than the second semiconductor die. In other words, the second semiconductor die, which has a shorter lateral edge, may have n chipping stopper trenches, where n > 1, whereas the first semiconductor die may have (n + m) chipping stopper trenches, were m > 1.

[0038] Generally, when reference is made to a die set, the first and second semiconductor die may for instance have the same type of device or device structure in the active area. By way of example, the first and second semiconductor die may comprise the same type of transistor cell, e.g. transistor cells being identical in construction. Therein, the first and second semiconductor die may, however, differ in their number of device cells.

[0039] In an embodiment, a method of designing a semiconductor die may comprise choosing the number of chipping stopper trenches in dependence of the die area. In case of a larger die area, more chipping stopper trenches may be provided. In case of a smaller die area, less chipping stopper trenches may be provided.

[0040] In an embodiment, a method of manufacturing a semiconductor die may comprise: forming the semiconductor die; forming the edge termination structure; etching the chipping stopper trench or trenches.

[0041] As discussed above, the chipping stopper trench(es) and a contact trench, in which a contact plug is formed subsequently, may be etched simultaneously. Alternatively or in addition, the chipping stopper trench(es) and contact trench may be filled simultaneously. In an embodiment, prior to manufacturing the semiconductor die, the number of chipping stopper trenches is chosen in dependence of the die area, more chipping stopper trenches being provided in case of a larger die area.

[0042] Parts of the application may be summarized by the following aspects:

[0043] 1. A semiconductor die (1), comprising: a semiconductor body (2); a semiconductor device (110) in an active area (2a) of the semiconductor body (2); an edge termination structure (10) arranged laterally between the active area (2a) and a lateral edge (1.1) of the die (1); a chipping stopper trench (40); the chipping stopper trench (40) arranged laterally between the edge termination structure (10) and the lateral edge (1.1) of the die (1).

[0044] 2. The semiconductor die (1) of aspect 1, the semiconductor device (110) comprising a gate trench (115) with a gate electrode (116), wherein the gate trench (115) extends deeper into the semiconductor body (2) than the chipping stopper trench (40).

[0045] 3. The semiconductor die (1) of aspect 1 or 2, the semiconductor device (110) comprising a contact plug (126) in a contact trench (125), the contact plug (126) electrically connected to a load terminal (111) of the semiconductor device (110), wherein the contact trench (125) and the chipping stopper trench (40) extend to the same vertical depth (45).

[0046] 4. The semiconductor die (1) of any one of the preceding aspects, the semiconductor device (110) comprising a contact plug (126) in a contact trench (125), the contact plug (126) electrically connected to a load terminal (111) of the semiconductor device (110), wherein the contact trench (125) and the chipping stopper trench (40) have a same lateral width (46). The semiconductor die (1) of any one of the preceding aspects, the edge termination structure (10) comprising a channel stopper (51) in a channel stopper trench (50), wherein the channel stopper trench (50) extends deeper into the semiconductor body (2) than the chipping stopper trench (40). The semiconductor die (1) of aspect 5, the semiconductor device (110) comprising a gate trench (115) with a gate electrode (116), wherein the gate trench (115) and the channel stopper trench (50) extend to a same vertical depth (55). The semiconductor die (1) of any one of the preceding aspects, comprising: an insulation layer (20) arranged on the semiconductor body (2); the edge termination structure (10) comprising a diffusion stopper trench (60) which intersects the insulation layer (20) vertically and extends around the active area (2a). The semiconductor die (1) of any one of the preceding aspects, comprising: an insulation layer (20) arranged on the semiconductor body (2); wherein the chipping stopper trench (40) extends through the insulation layer (20) down into the semiconductor body (2). The semiconductor die (1) of aspect 8, the chipping stopper trench (40) in the semiconductor body (2) having a vertical extension (47) of at least 0.2 pm and / or not more than 1.0 pm. The semiconductor die (1) of any one of the preceding aspects, the edge termination structure (10) comprising a shallow trench (25) filled with a dielectric material (26), wherein a bottom (25.1) of the shallow trench (25) is arranged at a greater vertical depth (45) than a bottom (40.1) of the chipping stopper trench (40). The semiconductor die (1) of any one of the preceding aspects, wherein the chipping stopper trench (40) is unfilled. The semiconductor die (1) of any one of aspects 1 to 10, wherein the chipping stopper trench (40) is filled, in particular with a metal material. The semiconductor die (1) of any one of the preceding aspects, wherein a doping (48) is introduced at a sidewall (40.2) and / or a bottom (40.1) of the chipping stopper trench (40). The semiconductor die (1) of any one of the preceding aspects, wherein the chipping stopper trench (40) has a lateral width (46) of at least 0.1 pm and / or not more than 0.8 pm. The semiconductor die (1) of any one of the preceding aspects, the semiconductor device (110) comprising a plurality of superjunction transistor cells (110.1). The semiconductor die (1) of any one of the preceding aspects, wherein a plurality of chipping stopper trenches (40) are arranged laterally between the edge termination structure (10) and the lateral edge (1.1) of the die (1). The semiconductor die (1) of aspect 16, wherein at least one of the chipping stopper trenches (40) surrounds the active area (2a) completely. The semiconductor die (1) of aspect 16 or 17, wherein at least one of the chipping stopper trenches (40) surrounds the active area (2a) only partly. The semiconductor die (1) of any one of aspects 16 to 18, wherein the plurality of chipping stopper trenches (40) are arranged with a pitch (49) of not more than 3.5 pm. A die set, comprising: a first semiconductor die (1) according to any one of the aspects 16 to 19; a second semiconductor die (1) according to any one of the aspects 16 to 19; the first semiconductor die (1) having a larger die area, and having a greater number of chipping stopper trenches (40) laterally between the edge termination structure (10) and the lateral edge (1.1), than the second semiconductor die (1). A die set, comprising: a first semiconductor die (1) according to any one of the aspects 16 to 19; a second semiconductor die (1) according to any one of the aspects 16 to 19; the first semiconductor die (1) having the lateral edge (1.1) with a greater length, and having a greater number of chipping stopper trenches (40) laterally between the edge termination structure (10) and the lateral edge (1.1), than the second semiconductor die (1). A method of designing a semiconductor die (1) of any one of aspects 16 to 19, wherein the number of chipping stopper trenches (40) is chosen in dependence of the die area, more chipping stopper trenches (40) being provided in case of a larger die area. A method of manufacturing a semiconductor die (1) of any one of aspects 1 to 19, comprising: forming the semiconductor device (110); forming the edge termination structure (10); etching the chipping stopper trench (40). The method of aspect 23 for manufacturing the semiconductor die (1) of aspect 3 or 4, wherein the chipping stopper trench (40) and the contact trench (125) are etched simultaneously. The method of aspect 23 or 24 for manufacturing the semiconductor die (1) of aspect 3 or 4, wherein the chipping stopper trench (40) and the contact trench (125) are filled simultaneously. 26. The method of manufacturing a semiconductor die (1) according to any one of aspects 23 to 25, wherein the semiconductor die (1) is designed in advance in a method according to aspect 22.

[0047] BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Below, the die and further details are explained by means of exemplary embodiments. Therein, the individual features can also be relevant for the application in a different combination.

[0049] Figure 1 shows an edge termination of a die in a vertical cross-section; figure 2 shows a more detailed view; figure 3 shows an alternative embodiment; figure 4 shows a detailed view at a corner of a die; figure 5 shows a cross-section in an active area.

[0050] PARTICULAR EMBODIMENT

[0051] Figure 1 shows a semiconductor die 1 with a semiconductor body 2 in a vertical cross-section. In an active area 2a of the semiconductor body 2, a semiconductor device is arranged (not shown in figure 1, see figure 4 in further detail). Laterally between the active area 2a and a lateral edge 1.1 of the die 1, an edge termination structure 10 is formed. Laterally outside of the edge termination structure 10, namely between the edge termination structure 10 and the lateral edge 1.1, a chipping stopper trench 40 is arranged, e.g. three chipping stopper trenches 40 in the embodiment as illustrated in figure 1.

[0052] The edge termination structure 10 may comprise a shallow trench 25, which is an optional feature. In the example shown, the shallow trench 25 is filled with a dielectric material 26, for instance silicon oxide. The shallow trench 25 with the dielectric material 26 may serve as a frontside isolation between the active area 2a and the lateral edge 1.1, for instance to shield the active area 2a from a backside potential reaching up to the frontside at the lateral edge 1.1. On the frontside of the semiconductor body 2, an insulation layer 20 is arranged which may in particular comprise a plurality of sublayers 20a-c.

[0053] The chipping stopper trench or trenches 40 may extend through the insulation layer 20 down into semiconductor body 2, see also figures 2 and 3 for illustration. Generally in this disclosure, the like reference numerals indicate the like elements or elements having the like function, and reference is made to the respective other figures as well. The chipping stopper trench or trenches 40 may in the semiconductor body 2 have a vertical extension 47 of for instance at least 0.2 pm, in particular at least 0.4 pm, possible upper limits being for example 1.0 pm or in particular 0.7 pm. The vertical extension 47 may be taken from the frontside (“first side” 2.1) of the semiconductor body 2.

[0054] In the embodiments shown, the shallow trench 25 extends deeper into the semiconductor body 2 than the chipping stopper trench or trenches 40. In other words, a bottom 25.1 of the shallow trench 25 is arranged at a greater vertical depth 45 than a bottom 40.1 of the chipping stopper trench 40. At a "greater depth" means for instance at a larger vertical distance from the frontside of the semiconductor body 2.

[0055] Figures 2 and 3 illustrates further optional details of the edge termination structure 10. It may additionally comprise a channel stopper trench 50 with a channel stopper 51, the channel stopper trench 50 extending down into the semiconductor body 2. In the embodiments shown, the channel stopper trench 51 extends deeper than the chipping stopper trench or trenches 40, e.g. to a vertical depth 55 lying deeper than a vertical depth 45 of the chipping stopper trench or trenches 40.

[0056] The channel stopper 51 may in particular surround the active area 2a, e.g. form a closed line when viewed in a vertical top view. As a part of the edge termination structure 10, the channel stopper 51 may be arranged laterally inside of the chipping stopper trench or trenches 40, for instance closer to the active area 2a. The edge termination structure 10 may comprise a plurality of channel stoppers 51, for instance two channel stoppers 51 as illustrated in figures 2 and 3, e.g. a first channel stopper 51.1 and a second channel stopper 51.2. At least one of them may be electrically connected, for instance to drain potential. In the example shown, the first channel stopper is electrically connected to a load contact runner 400, e.g. drain ring 401. The channel stopper or stoppers 51 may prevent ions from entering the active area 2a, for instance via the lateral edge 1.1 of the die 1. This may for example be achieved by applying a defined potential to the channel stopper or stoppers 51, for instance drain potential.

[0057] In the embodiment shown, the channel stopper trench or trenches 50 extend to the same vertical depth 55 like a gate trench or trenches 115 of the semiconductor device 110 in the active area, see figure 4 for illustration. In particular, the channel stopper trench 50 and the gate trench 115 may be etched and / or filled simultaneously, for instance with a polysilicon electrode material.

[0058] Alternatively or in addition to the channel stopper or stoppers 51, the edge termination structure 10 may comprise a diffusion stopper trench 60. The diffusion stopper trench 60 may intersect the insulation layer 20 vertically and extend around the active area 2a, for instance form a closed line when viewed in a vertical top view. The interruption of the isolation layer 20 may for instance prevent a sodium diffusion from the lateral edge 1.1 via the insulation layer 20 into the active area 2a.

[0059] In the embodiments shown, the diffusion stopper trench 60 stops on the first side 2.1 of the semiconductor body 2. In another embodiment, it may extend deeper into the semiconductor body 2, for instance to the same depth like the chipping stopper trench or trenches 40. The diffusion stopper trench 60 may be provided with a filler 61, for instance made of metal, for example tungsten. Independently of these details, the diffusion stopper trench 60 may in particular be the outermost element of the edge termination structure 10.

[0060] In the embodiment of figure 2, the chipping stopper trench or trenches 40 are unfilled. In other words, they are not filled, namely left open. In the embodiments of figures 1 and 3, the chipping stopper trench or trenches 40 are filled, for instance with a metal material.

[0061] At a bottom 40.1 and / or a sidewall 40.2 of the chipping stopper trench(es) 40, a doping 48 may be introduced (referenced only exemplary in figure 2). This additional doping 48 may for instance "attract" electrons or holes (depending on whether n- or p-region). This may in particular be combined with a metal filler in the chipping stopper trench or trenches 40, which may serve as a recombination center and reduce the plasma concentration towards the lateral edge 1.1.

[0062] Figures 2 and 3 illustrate a lateral width 46 of a respective chipping stopper trench 40, which may in particular be taken at the bottom 40.1 of the respective chipping stopper trench 40. The lateral width 46 may for instance be at least 0.1 pm, in particular at least 0.2 pm, possible upper limits being for instance 0.8 pm or 0.6 pm. When a plurality of chipping stopper trenches 40 are provided, they may for instance be arranged with a pitch 49 of not more than 3.5 pm, 3.0 pm, 2.5 pm or 2.0 pm, in particular not more than 1.5 pm. Possible lower limits of the pitch 49 may for instance be 0.8 pm or in particular 1.0 pm.

[0063] In general, only one chipping stopper trench 40 may be provided (not shown in the figures). In particular, a plurality of chipper stopping trenches 40 may be arranged laterally between the edge termination structure 10 and the lateral edge 1.1 of the die 1. For instance, at least 2, 5, 10 or 15 chipping stopper trenches 40 may be provided, possible upper limits being for example 40, 30 or 25 chipping stopper trenches. Referring to a vertical cross-section perpendicular to the lateral edge 1.1 of the die 1, these numbers may in particular relate to one side of the active area 2a, namely at at least one lateral edge 1.1 of the die 1. On the laterally opposite side, e.g. between the active area and the laterally opposite lateral edge of the die, a different or the same number of chipping stopper trenches may be provided.

[0064] Independently of these details, at least one of the chipping stopper trenches 40 may surround the active area 2a completely, for instance form a closed line (circumferential trench) when viewed in a vertical top view. Alternatively or in addition, at least one of the chipping stopper trenches 40 may surround the active area only partly, for instance form an interrupted line when viewed in a vertical top view.

[0065] The number of chipping stopper trenches 40 may in particular be chosen in dependence of a die area and / or length of the lateral edge. With increasing die area or edge length, the likelihood of a crack propagation or introduction may increase, for instance from the kerf. Vice versa, the additional area required for additional chipping stopper trenches may be less relevant or significant in relation to the die area in case of a larger die. An embodiment relates to a die set, namely to a plurality of semiconductor dies, e.g. at least two semiconductor dies. Therein, a first semiconductor die 1 may have a larger die area than a second semiconductor die and may be provided with a greater number of chipping stopper trenches between the edge termination structure 10 and the lateral edge 1.1.

[0066] Alternatively or in addition, a first semiconductor die of a die set may have a lateral edge 1.1 with a greater length compared to a lateral edge 1.1 of a second semiconductor die, wherein the first semiconductor die may be provided with a greater number of chipping stopper trenches 40 between the edge termination structure 10 and the lateral edge 1.1 than the second semiconductor die 1.

[0067] In a method of designing a semiconductor die 1, the number of chipping stopper trenches 40 may be chosen in dependence of a die area and / or edge length, more chipping stopper trenches 40 being provided in case of a larger die area / greater edge length.

[0068] Figure 4 shows another detailed view. In contrast to figures 2 and 3, the cross-section of figure 4 is arranged at a corner of the semiconductor die 1 (the sectional plane does not lie perpendicular to the lateral edge, but runs along a bisecting line through the corner). In this example, no chipping stopper trenches are provided in the comer of the die 1, the chipping stopper trenches are interrupted there. The load contact runner 400, namely drain ring 401 in the example shown, extends further outward in the comer. There, it makes an electrical contact to the filler 61 in the diffusion stopper trench 60, see figures 2 and 3 in comparison (the filler 61 is not connected to the load contact runner in these sectional views). The crosssection of figure 4, which is arranged at the corner, can refer to both embodiments according to figures 2 and 3.

[0069] Figure 5 shows a schematic cross-section in the active area 2a and illustrates the semiconductor device 110 which may in particular be a superjunction transistor device. In the semiconductor body 2, first regions 211 made of a first doping type and second regions 212 made of a second doping type are formed, wherein the first regions 211 may be drift regions in this semiconductor device 110. The second regions 212 may be compensation regions. The numeral 110.1 indicates one superjunction transistor cell. The first regions 211 and the second regions 212 may have the form of columns extending into the semiconductor body. Above the first and second regions 211, 212, a body region 112 and source region 111 (load terminal) may be formed. The source region 111 is arranged at the first side 2.1 of the semiconductor body 2, a drain region 113 of the device 110 is arranged at the vertically opposite second side 2.2 (“backside”) of the semiconductor body 2. The source and drain region 111, 113 may be made of the first doping type, the body region 112 of the second doping type. The first doping type may in particular be n-type, the second doping type p-type.

[0070] In an embodiment not shown, the body region may be arranged aside the source region, for instance combined with a planar gate formed above. In figure 5, a gate trench or trenches 115 extend from the first side 2.1 into the semiconductor body, the gate electrode 116 arranged laterally aside the body region 112. The gate trench or trenches 115 extend to the same vertical depth 55 like the channel stopper trench or trenches 50, see figures 2 and 3 for comparison. In other words, the gate trench or trenches 115 extend deeper into the semiconductor body 2 than the chipping stopper trench or trenches 40. Therein, the depth is taken from the first side 2.1 of the semiconductor body 2, "deeper" meaning a larger distance from the first side 2.1.

[0071] The source and body region 111, 112 are contacted by a contact plug 126 (on the semiconductor body 2, an insulation layer may be arranged, which is not shown here). The contact plug or plugs 126 may extend to the same vertical depth 45 like the chipping stopper trench or trenches 40 and / or may have the same lateral width 46 like the chipping stopper trench or trenches 40. Here, the width is taken in a width or transverse direction, in a length or longitudinal direction the trenches and the plugs can have a different extension. In other words, the width comparison may in particular apply in a vertical cross-section perpendicular to the lateral edge of the die.

Claims

Claims1. A semiconductor die (1), comprising: a semiconductor body (2); a semiconductor device (110) in an active area (2a) of the semiconductor body (2); an edge termination structure (10) arranged laterally between the active area (2a) and a lateral edge (1.1) of the die (1); a chipping stopper trench (40); the chipping stopper trench (40) arranged laterally between the edge termination structure (10) and the lateral edge (1.1) of the die (1), wherein the chipping stopper trench (40) is unfilled.

2. The semiconductor die (1) of claim 1, wherein a doping (48) is introduced at a sidewall (40.2) and / or a bottom (40.1) of the chipping stopper trench (40).

3. The semiconductor die (1) of any one of the preceding claims, wherein the chipping stopper trench (40) has a lateral width (46) of at least 0.1 pm and / or not more than 0.8 pm.

4. The semiconductor die (1) of any one of the preceding claims, the semiconductor device (110) comprising a gate trench (115) with a gate electrode (116), wherein the gate trench (115) extends deeper into the semiconductor body (2) than the chipping stopper trench (40).

5. The semiconductor die (1) of any one of the preceding claims, the semiconductor device (110) comprising a contact plug (126) in a contact trench (125), the contact plug (126) electrically connected to a load terminal (111) of the semiconductor device (110), wherein the contact trench (125) and the chipping stopper trench (40) extend to the same vertical depth (45).

6. The semiconductor die (1) of any one of the preceding claims, the semiconductor device (110) comprising a contact plug (126) in a contact trench (125), the contactplug (126) electrically connected to a load terminal (111) of the semiconductor device (110), wherein the contact trench (125) and the chipping stopper trench (40) have a same lateral width (46).

7. The semiconductor die (1) of any one of the preceding claims, the edge termination structure (10) comprising a channel stopper (51) in a channel stopper trench (50), wherein the channel stopper trench (50) extends deeper into the semiconductor body (2) than the chipping stopper trench (40).

8. The semiconductor die (1) of claim 7, the semiconductor device (110) comprising a gate trench (115) with a gate electrode (116), wherein the gate trench (115) and the channel stopper trench (50) extend to a same vertical depth (55).

9. The semiconductor die (1) of claim 7 or 8, the edge termination structure (10) comprising a first channel stopper (51.1) in a first channel stopper trench (50.1) and a second channel stopper (51.2) in a second channel stopper trench (50.2) arranged laterally outside of the first channel stopper trench (50.1).

10. The semiconductor die (1) of claim 9, the edge termination structure (10) comprising a load contact runner (400), wherein only the first channel stopper (51.1) is electrically connected to the load contact runner (400).

11. The semiconductor die (1) of any one of the preceding claims, comprising: an insulation layer (20) arranged on the semiconductor body (2); the edge termination structure (10) comprising a diffusion stopper trench (60) which intersects the insulation layer (20) vertically and extends around the active area (2a).

12. The semiconductor die (1) of any one of the preceding claims, comprising: an insulation layer (20) arranged on the semiconductor body (2); wherein the chipping stopper trench (40) extends through the insulation layer (20) down into the semiconductor body (2).

13. The semiconductor die (1) of claim 12, the chipping stopper trench (40) in the semiconductor body (2) having a vertical extension (47) of at least 0.2 pm and / or not more than 1.0 pm.

14. The semiconductor die (1) of any one of the preceding claims, the edge termination structure (10) comprising a shallow trench (25) filled with a dielectric material (26), wherein a bottom (25.1) of the shallow trench (25) is arranged at a greater vertical depth (45) than a bottom (40.1) of the chipping stopper trench (40).

15. The semiconductor die (1) of any one of the preceding claims, the semiconductor device (110) comprising a plurality of superjunction transistor cells (110.1).

16. The semiconductor die (1) of any one of the preceding claims, wherein a plurality of chipping stopper trenches (40) are arranged laterally between the edge termination structure (10) and the lateral edge (1.1) of the die (1).

17. The semiconductor die (1) of claim 16, wherein at least one of the chipping stopper trenches (40) surrounds the active area (2a) completely.

18. The semiconductor die (1) of claim 16 or 17, wherein at least one of the chipping stopper trenches (40) surrounds the active area (2a) only partly.

19. The semiconductor die (1) of any one of claims 16 to 18, wherein the plurality of chipping stopper trenches (40) are arranged with a pitch (49) of not more than 3.5 pm.

20. A die set, comprising: a first semiconductor die (1) according to any one of the claims 16 to 19; a second semiconductor die (1) according to any one of the claims 16 to 19; the first semiconductor die (1) having a larger die area, and having a greater number of chipping stopper trenches (40) laterally between the edge termination structure (10) and the lateral edge (1.1),than the second semiconductor die (1).

21. A die set, comprising: a first semiconductor die (1) according to any one of the claims 16 to 19; a second semiconductor die (1) according to any one of the claims 16 to 19; the first semiconductor die (1) having the lateral edge (1.1) with a greater length, and having a greater number of chipping stopper trenches (40) laterally between the edge termination structure (10) and the lateral edge (1.1), than the second semiconductor die (1).

22. A method of designing a semiconductor die (1) of any one of claims 16 to 19, wherein the number of chipping stopper trenches (40) is chosen in dependence of the die area, more chipping stopper trenches (40) being provided in case of a larger die area.

23. A method of manufacturing a semiconductor die (1) of any one of claims 1 to 19, comprising: forming the semiconductor device (110); forming the edge termination structure (10); etching the chipping stopper trench (40).

24. The method of claim 23 for manufacturing the semiconductor die (1) of claim 5 or 6, wherein the chipping stopper trench (40) and the contact trench (125) are etched simultaneously.

25. The method of manufacturing a semiconductor die (1) according to any one of claims 23 to 24, wherein the semiconductor die (1) is designed in advance in a method according to claim 22.

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