Signal processing device

Abstract

The present technology relates to a signal processing device capable of suppressing leakage occurring between two ports of a vector network analyzer. The signal processing device according to the present technology is provided with a first directional coupler comprising: a first circuit to which a first test signal from among differential signals configured from a first test signal and a second test signal is input and which includes at least an impedance element; a second circuit to which a second test signal from among the differential signals is input and which includes at least a circuit to be measured; and an adder circuit for calculating the sum of the output from the first circuit and the output from the second circuit. The present technology can be applied to, for example, a vector network analyzer.

Description

signal processing device

[0001] The present technology relates to a signal processing device, and more particularly to a signal processing device that can suppress leakage that occurs between two ports of a vector network analyzer.

[0002] A vector network analyzer includes a signal source, three receivers for R, A, and B channels, and a directional coupler for separating incident and reflected waves. Known directional couplers include those that use a transmission line formed on a substrate and those that use a waveguide (see, for example, Patent Document 1).

[0003] JP 2011-61440 A

[0004] In a vector network analyzer, in order to accurately measure S parameters, it is necessary to suppress leakage that occurs between the two ports to which the circuit under test is connected.

[0005] The present technology has been made in view of such circumstances, and makes it possible to suppress leakage occurring between two ports of a vector network analyzer.

[0006] A signal processing device according to one aspect of the present technology includes a first directional coupler including: a first circuit that receives as input a first test signal of a differential signal formed of a first test signal and a second test signal and that includes at least an impedance element; a second circuit that receives as input the second test signal of the differential signals and that includes at least a circuit under measurement; and an adder circuit that calculates the sum of an output from the first circuit and an output from the second circuit.

[0007] In one aspect of the present technology, a first directional coupler is configured with a first circuit that receives as input a first test signal of a differential signal formed of a first test signal and a second test signal and that includes at least an impedance element, a second circuit that receives as input the second test signal of the differential signals and that includes at least a circuit under measurement, and an adder circuit that calculates the sum of an output from the first circuit and an output from the second circuit.

[0008] 7 is a diagram illustrating an example of a vector network analyzer according to an embodiment of the present technology. FIG. 8 is a block diagram illustrating an example of the configuration of a VNA according to a first embodiment. FIG. 9 is a first diagram illustrating S-parameters measured by the VNA. FIG. 10 is a second diagram illustrating S-parameters measured by the VNA. FIG. 11 is a circuit diagram illustrating an example of the configuration of the directional coupler of FIG. 2. FIG. 12 is a diagram illustrating an example of leakage between ports in the first embodiment. FIG. 13 is a block diagram illustrating an example of the configuration of a VNA according to a second embodiment. FIG. 14 is a circuit diagram illustrating an example of the configuration of the directional coupler of FIG. 7. FIG. 15 is a diagram for explaining the operation of a directional coupler. FIG. 16 is a diagram illustrating an example of leakage between ports in the second embodiment. FIG. 17 is a circuit diagram illustrating a first modified example of the configuration of a directional coupler. FIG. 18 is a circuit diagram illustrating a second modified example of the configuration of a directional coupler.

[0009] Hereinafter, embodiments of the present technology will be described in the following order: 1. First embodiment of VNA 2. Second embodiment of the present technology 3. Modification

[0010] 1. First Embodiment of VNA> FIG. 1 is a diagram illustrating an example of a vector network analyzer 1 (hereinafter referred to as VNA 1) according to an embodiment of the present technology.

[0011] The VNA 1 in FIG. 1 is a signal processing device that measures the S-parameters (reflection and transmission characteristics) of a circuit under test 2 (hereinafter referred to as a DUT (Device Under Test) 2) connected between two ports P1 and P2.

[0012] FIG. 2 is a block diagram showing an example of the configuration of the VNA 1 according to the first embodiment.

[0013] As shown in FIG. 2, the VNA 1 includes a VNA chip 21, which is a semiconductor chip in which a reference signal generating circuit 11, a transmitting circuit 12, a directional coupler 13, an Rch (R channel) receiving circuit 14, an Ach (A channel) receiving circuit 15, a Bch (B channel) receiving circuit 16, and a plurality of input / output terminals 17 are integrated into one chip.

[0014] Of the multiple input / output terminals 17 of the VNA chip 21, input / output terminal 17-1 is a terminal that outputs a test signal and is connected to port P1. Input / output terminal 17-2 is a terminal that inputs a power supply voltage VDD, and input / output terminal 17-3 is a terminal that is connected to ground (GND). Input / output terminals 17-4 and 17-5 are connected to port P2 via the balun 22 and are terminals that input a signal that has passed through DUT2 (transmitted signal).

[0015] The reference signal generating circuit 11 is composed of a PLL (Phase Locked Loop) circuit and the like, and generates a reference signal that serves as a reference for the circuits within the chip, and supplies it to each of the transmitting circuit 12, directional coupler 13, Rch receiving circuit 14, Ach receiving circuit 15, and Bch receiving circuit 16.

[0016] The transmitting circuit 12 receives the reference signal from the reference signal generating circuit 11 and transmits the reference signal at a predetermined frequency f b and supplies the test signal to the directional coupler 13. For example, the transmission circuit 12 may generate a test signal of any frequency f within the range of 1 GHz to 9 GHz. b A sine wave of the above is generated and output as a test signal.

[0017] The directional coupler 13 divides the input signal, which is a test signal supplied from the transmitting circuit 12 and input to the DUT 2, and separates the reflected signal, which is a test signal reflected by the DUT 2. Specifically, the directional coupler 13 outputs a portion of the test signal supplied from the transmitting circuit 12 to the input / output terminal 17-1, and supplies the remaining divided test signal to the Rch receiving circuit 14. The directional coupler 13 also extracts the reflected signal reflected by the DUT 2 and input to the Ach receiving circuit 15.

[0018] The Rch receiving circuit 14 receives the input signal supplied from the directional coupler 13 .

[0019] The Ach receiving circuit 15 receives the reflected signal supplied from the directional coupler 13 .

[0020] The Bch receiving circuit 16 receives the transmitted signal that has passed through the DUT 2 and is input via the port P2.

[0021] The S parameters measured by the VNA 1 will be described with reference to FIGS.

[0022] As shown in FIG. 3, a sine wave output as a test signal from a signal source passes through a directional coupler 51 and is input to a DUT 52 .

[0023] The directional coupler 51 includes a directional coupler on the R channel side (hereinafter referred to as the Rch directional coupler) and a directional coupler on the A channel side (hereinafter referred to as the Ach directional coupler). The Rch directional coupler separates a part of the test signal, which is an incident wave input from the source (signal source) side, and outputs it to the Rch receiving circuit. The Ach directional coupler separates the reflected signal that is reflected by the DUT 52 and input from the test port side, and outputs it to the Ach receiving circuit. Meanwhile, the test signal that has passed through the DUT 52 is input to the Bch receiving circuit.

[0024] The VNA 1 measures the reflectance as a transfer characteristic from the directional coupler 51 side to the Bch receiving circuit side of the DUT 52 by observing the reflected signal received by the Ach receiving circuit with reference to the test signal received by the Rch receiving circuit. In other words, the VNA 1 can measure the reflectance = Ach signal / Rch signal.

[0025] Furthermore, the VNA 1 measures the transmittance as the transfer characteristic from the directional coupler 51 side to the Bch receiving circuit side of the DUT 52 by observing the transmitted signal received by the Bch receiving circuit with reference to the test signal received by the Rch receiving circuit. In other words, the VNA 1 can measure the transmittance = Bch signal / Rch signal.

[0026] Ideally, the test signal from the signal source would be distributed only to the Rch receiving circuit, and the reflected signal from the DUT 52 would be distributed only to the Ach receiving circuit, but in reality, leakage (isolation) exists. A larger ratio of the desired signal to the leakage indicates higher directivity, which is desirable.

[0027] 4, the port to which the signal source is connected is the first port 71, the port to which the DUT 52 is connected is the second port 72, the port to which the Rch receiving circuit is connected is the third port 73, and the port to which the Ach receiving circuit is connected is the fourth port 74. The insertion loss of the directional coupler 51 is S21, the coupling degree of the test signal is S31, the isolation of the test signal is S32, the coupling degree of the reflected signal is S42, and the isolation of the reflected signal is S41. In this case, the directivity D of the Rch side is Rch is D Rch = S31-S21-S32, and the directionality of Ach side D Ach is D Ach = S21 + S42 - S41. Directivity D on the Rch side Rch For the insertion loss S21, the directivity D Rch However, the directionality of the Ach side D Ach Regarding the insertion loss S21, only the directivity D Ach Since the directivity of Ach side D Ach It is more difficult to raise the

[0028] Fig. 5 is a circuit diagram showing an example of the configuration of the directional coupler 13 in Fig. 2. In Fig. 5, the circuit configuration of the Rch directional coupler is not shown, but the circuit configuration of the Ach directional coupler is shown.

[0029] The directional coupler 13 (Ach directional coupler) is realized by resistive elements 101 to 103 and a subtraction circuit 121. The subtraction circuit 121 is formed, for example, as part of the Ach receiving circuit 15. The resistive elements 101 and 103 and the subtraction circuit 121 are formed inside the VNA chip 21, but the resistive element 102 is formed outside the VNA chip 21. The input / output terminal 17-1 is a terminal from which a test signal is output, and the input / output terminal 17-6 is a terminal for connecting the resistive element 101 formed inside the chip with the resistive element 102 formed outside the chip.

[0030] The resistance values ​​of the resistor elements 101 to 103 are R １ ~R ３ The resistor element 103 is a termination resistor inside the Ach directional coupler.

[0031] The resistor elements 101 to 103 and the subtraction circuit 121 output the test signal input from the transmission circuit 12 to the DUT 2 via the input / output terminal 17-1, and also extract the reflected signal reflected by the DUT 2 and output it to the Ach reception circuit 15.

[0032] The input / output terminal 17-1 is connected to the DUT 2 when measuring S parameters, but when adjusting the VNA chip 21, for example, when adjusting the VNA chip 21 before shipping, a reference resistance element having a reference resistance value is connected. The reference resistance value is generally 50 Ω. The resistance value R of the resistance element 102 ２ is the resistance value R of the reference resistor element ４ In the example of FIG. 5, the reference resistance is 50Ω, and the resistance R ２ The total is set to 50 Ω.

[0033] The resistor elements 101 to 103 form a resistor bridge circuit together with the reference resistor element, and the resistance values ​​of the resistor elements 101 and 103 are adjusted so that the balance condition of the resistor bridge circuit is established when adjusting the VNA chip 21. That is, in a resistor bridge circuit in which the resistor element 101 and the resistor element 102 connected in series are connected in parallel with the resistor element 103 and the reference resistor element connected in series, １ / R ３ =R ２ / R ４ The resistance values ​​R of the resistor elements 101 and 103 are set so that １ , R ３ is adjusted.

[0034] When adjusting the resistance values ​​of the resistor elements 101 and 103, the resistance value R of the resistor element 101 is set on the upper side of the resistor bridge circuit. １ (and the resistance value R of the resistor element 102 ２ = 50Ω) flows through the resistor bridge circuit, and the resistance value R of the resistor element 103 flows through the resistor bridge circuit. ３ (and the resistance value R of the reference resistor element ４= 50Ω) flows. The subtraction circuit 121 calculates the difference between the voltage applied to the resistance element 102 and the voltage applied to the reference resistance element, and outputs the difference signal. When the balance condition of the resistance bridge circuit is met, the currents flowing on the upper and lower sides of the resistance bridge circuit become equal, and the voltage difference calculated by the subtraction circuit 121 becomes zero. Therefore, the resistance values ​​R of the resistance elements 101 and 103 are adjusted so that the voltage difference calculated by the subtraction circuit 121 becomes zero. １ , R ３ is adjusted.

[0035] When measuring S parameters after adjusting the resistance values ​​of the resistor elements 101 and 103, if the DUT 2 is connected to the input / output terminal 17-1, the resistance value R of the resistor element 102 is displayed on the upper side of the resistor bridge circuit. ２ A current flows in accordance with the impedance of the DUT 2 (the resistance value R of the load resistor 111) at the bottom of the resistor bridge circuit. Ｌ The difference signal output by the subtraction circuit 121 is a current according to the resistance value R of the resistor element 102. ２ is used as a reference and becomes a signal related to the impedance of the DUT 2, so the Ach receiving circuit 15 can detect the reflected signal.

[0036] As described above, by using a resistor bridge circuit, the directional coupler 13 can be made compact and incorporated into a semiconductor chip while still being compatible with a wide frequency band. By implementing the directional coupler 13 on a semiconductor chip, it is possible to provide a VNA 1 with a wide frequency band and a small area at low cost.

[0037] Furthermore, since the DUT 2 is arranged outside the VNA chip 21 and connected to the directional coupler 13 via the input / output terminal 17-1, the resistive element 102 corresponding to the DUT 2 is also arranged outside the VNA chip 21 and connected via the input / output terminal 17-6. By matching the arrangement conditions of the upper and lower sides of the resistive bridge circuit in this way and ensuring symmetry, degradation of directivity is prevented and the performance of the directional coupler 13 is improved.

[0038] 2. Second Embodiment of the Present Technology An important aspect of the performance of the VNA 1 is the isolation characteristics between the port P1 and the port P2 to which the DUT 2 is connected. If the leakage between the ports is large, the transmittance cannot be measured accurately. An example of the leakage between the ports is leakage via an IO ring (not shown in FIG. 6 ) formed at a position overlapping with multiple input / output terminals 17 of the VNA chip 21, as indicated by the bold white arrow in FIG. 6 . A portion of the test signal output to port P1 reaches the input / output terminals 17-4 and 17-5 corresponding to port P2 via the IO ring within the chip, which is a path other than between port P1 and port P2.

[0039] A second embodiment of the present technology has been conceived in light of the above points, and is configured to suppress leakage occurring between two ports of a VNA1 by configuring a directional coupler using a first circuit that receives an inverted signal of a differential signal composed of a positive-phase signal and a negative-phase signal and that includes at least an impedance element, a second circuit that receives an inverted signal of the differential signal and that includes at least a DUT2, and an adder circuit that calculates the sum of the output from the first circuit and the output from the second circuit.

[0040] Fig. 7 is a block diagram showing an example of the configuration of a VNA 1 according to the second embodiment. In Fig. 7, the same components as those in Fig. 2 are denoted by the same reference numerals. Duplicate explanations will be omitted where appropriate.

[0041] 7 differs from the VNA chip 21 in Fig. 2 in that a transmitter circuit 151, a directional coupler 152, and an input / output terminal 153 are provided instead of the transmitter circuit 12, the directional coupler 13, and the input / output terminal 17-1. In the first embodiment described above, a single-ended signal is used as the test signal, but in the second embodiment, a differential signal is used as the test signal.

[0042] The transmission circuit 151 transmits a signal at a predetermined frequency f b The transmission circuit 151 generates a test signal of the same frequency f as a differential signal and supplies it to the directional coupler 152. bA positive-phase signal (second test signal) and a negative-phase signal (first test signal) that are in an opposite phase relationship are generated and supplied to the directional coupler 152 .

[0043] The directional coupler 152 outputs, for example, a portion of the negative-phase signal out of the positive-phase signal and negative-phase signal supplied from the transmitting circuit 151 to the input / output terminal 153, and outputs the remaining divided negative-phase signal to the Rch receiving circuit 14. Furthermore, the directional coupler 152 outputs, for example, the positive-phase signal out of the positive-phase signal and negative-phase signal supplied from the transmitting circuit 151 to the input / output terminal 153, and outputs the positive-phase signal (reflected signal) reflected by and input to the DUT 2 to the Ach receiving circuit 15.

[0044] The input / output terminal 153 is a terminal that outputs a test signal and is connected to the port P1 via the balun 161. The balun 161 converts a differential signal serving as the test signal into a single-ended signal and outputs the signal to the port P1.

[0045] FIG. 8 is a circuit diagram showing an example of the configuration of the directional coupler 152 shown in FIG.

[0046] The directional coupler 152 has resistive elements 201 to 203, an R-channel output terminal 204, resistive elements 205 to 208, and resistive elements 211 to 213 and an A-channel output terminal 214. The resistive elements 201 to 203, the R-channel output terminal 204, the resistive elements 205 to 208, and the resistive elements 211, 213 and the A-channel output terminal 214 are formed inside the VNA chip 21, but the resistive element 212 is formed outside the VNA chip 21.

[0047] The input / output terminal 153-1 is a terminal for connecting the resistive element 211 formed inside the chip with the resistive element 212 formed outside the chip, and the input / output terminal 153-2 is a terminal from which a positive phase signal is output.

[0048] The resistor elements 201 to 203 constitute an Rch directional coupler, and the voltage V －and outputs a portion of the negative-phase signal to the Rch receiving circuit 14 via the R channel output terminal 204. That is, the negative-phase signal input from the transmitting circuit 12 is distributed to the resistive element 211 and the resistive element 202, and the negative-phase signal that flows through the resistive element 202 is output to the Rch receiving circuit 14 via the R channel output terminal 204. The resistive element 203 is a termination resistor inside the Rch directional coupler.

[0049] Resistor elements 205 to 208 constitute a circuit corresponding to the Rch directional coupler. Resistor elements 205 to 207 correspond to resistor elements 201 to 203. Resistor elements 205 to 208 are provided to maintain symmetry between the negative-phase signal input to the Ach directional coupler via the Rch directional coupler and the positive-phase signal input to the Ach directional coupler.

[0050] The resistor elements 211 to 213 constitute an Ach directional coupler and correspond to the resistor elements 101 to 103 described with reference to Fig. 5. The resistance values ​​of the resistor elements 211 to 213 are respectively R １１ ~R １３ Let's say.

[0051] The resistive elements 211 to 213 output the positive-phase signal input from the transmitting circuit 12 to the DUT 2 via the input / output terminal 153-2, and also extract the reflected signal reflected by the DUT 2 and output it to the A-channel output terminal 214. The reflected signal output to the A-channel output terminal 214 is supplied to the A-ch receiving circuit 15.

[0052] Here, the first circuit configured by connecting a resistor element 211 (first impedance element) and a resistor element 212 (second impedance element) in series and the Rch directional coupler are connected in series, and a voltage V － A second circuit configured by connecting a resistor element 213 (third impedance element) and DUT2 (load resistor 221) in series and a circuit corresponding to the Rch directional coupler are connected in series, and a voltage V ＋ A positive phase signal is input.

[0053] Fig. 9 is a diagram for explaining the operation of the directional coupler 152. In Fig. 9, the circuit configuration of the Rch directional coupler is not shown, but the circuit configuration of the Ach directional coupler is shown.

[0054] The directional coupler 152 (Ach directional coupler) is realized by resistor elements 211 to 213 and an adder circuit 251, and has a circuit configuration similar to a resistor bridge circuit. The adder circuit 251 is formed as part of the Ach receiving circuit 15, for example. In the example of FIG. 9, the resistance values ​​R １１ ~R １３ is set to 50 Ω.

[0055] When the DUT 2 is connected to the input / output terminal 153-2 during S-parameter measurement, the resistance value R １２ = 50Ω, and the current in accordance with the impedance of DUT2 (resistance value R of load resistor 221) flows in the circuit below the Ach directional coupler. Ｌ ) flows. Adder circuit 251 calculates the sum of the voltage applied to resistor element 212 and the voltage applied to load resistor 221, and outputs the sum signal.

[0056] The sum of the voltages calculated by the adder circuit 251 is V － = -V ＋ Then, it is expressed by the following equation (1).

[0057]

[0058] That is, the sum signal output by the adder circuit 251 is the resistance value R of the resistor element 212. １２ is used as a reference and becomes a signal related to the impedance of the DUT 2, so the Ach receiving circuit 15 can detect the reflected signal.

[0059] As described above, in the second embodiment, the test signal is differentiated, and the positive-phase signal of the differential signal serving as the test signal is output to the input / output terminal 153-2, and the negative-phase signal is output to the input / output terminal 153-2. As a result, even if a leak occurs between port P1 and port P2, the leak signal passing through the IO ring is also a differential signal, so the leak signal is essentially canceled.

[0060] 10, it is possible to reduce the leakage signals that reach the input / output terminals 17-4 and 17-5 via the IO ring, which means that the isolation characteristics between the ports can be improved, thereby improving the performance of the VNA 1.

[0061] In the second embodiment, too, by using two circuits, a first circuit in which two resistors are connected in series and a second circuit in which a resistive element and the DUT 2 are connected in series, the directional coupler 152 can be made compact while still supporting a wide bandwidth, and can be incorporated into a semiconductor chip. By realizing the directional coupler 152 on a semiconductor chip, it is possible to provide a VNA with a wide frequency band and a small area at low cost.

[0062] Furthermore, since DUT 2 is arranged outside the VNA chip 21 and connected to directional coupler 152 via input / output terminal 153-2, resistive element 212 corresponding to DUT 2 is also arranged outside the VNA chip 21 and connected via input / output terminal 153-1. By matching the layout conditions of the two circuits and ensuring symmetry in this way, degradation of directivity is prevented and the performance of directional coupler 152 is improved.

[0063] 3. Modifications In the second embodiment described above, the directional coupler 152 is configured only with a plurality of resistive elements. However, the directional coupler 152 can also be configured with a circuit including at least one of resistive elements, capacitive elements, inductors, and semiconductor elements, for example.

[0064] Fig. 11 is a circuit diagram showing a first modified example of the configuration of the directional coupler 152. In Fig. 11, the same components as those in Fig. 8 are assigned the same reference numerals. Duplicate explanations will be omitted where appropriate. Note that Fig. 11 does not show the circuit configuration of the Rch directional coupler, but shows the circuit configuration of the Ach directional coupler.

[0065] The directional coupler 152 in Fig. 11 differs from the directional coupler 152 in Fig. 8 in that variable resistance elements 301 and 303 are provided instead of the resistance elements 211 and 213. The directional coupler 152 in Fig. 11 also differs from the directional coupler 152 in Fig. 8 in that a variable capacitance element 302 is provided between the variable resistance element 301 and the input / output terminal 153-1, and a variable capacitance element 304 is provided between the variable resistance element 303 and the input / output terminal 153-2.

[0066] The variable resistance elements 301 and 303 are resistance elements whose resistance value can be changed, and the variable capacitance elements 302 and 304 are capacitance elements whose capacitance can be changed. The variable resistance elements 301 and 303 and the variable capacitance elements 302 and 304 are provided as variable impedance elements for adjusting the balance between the (upper) circuit to which a negative phase signal is input and the (lower) circuit to which a positive phase signal is input.

[0067] Fig. 12 is a circuit diagram showing a second modified example of the configuration of the directional coupler 152. In Fig. 12, the same components as those in Fig. 8 are assigned the same reference numerals. Duplicate explanations will be omitted where appropriate. Note that Fig. 12 does not show the circuit configuration of the Rch directional coupler, but shows the circuit configuration of the Ach directional coupler.

[0068] The directional coupler 152 in FIG. 12 differs from the directional coupler 152 in FIG. 8 in that an inductor 311 is provided between the resistive element 211 and the input / output terminal 153-1, and an inductor 312 is provided between the resistive element 213 and the input / output terminal 153-2.

[0069] By providing the inductors 311 and 312, the parasitic capacitance can be cancelled and the test signal can be made wider in bandwidth.

[0070] As described above, the directional coupler 152 can be configured using at least one impedance element such as a resistor, a capacitor, an inductor, or a semiconductor element.

[0071] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0072] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present technology.

[0073] <Examples of Combinations of Configurations> The present technology can also have the following configurations.

[0074] (1) A signal processing device comprising: a first directional coupler configured with: a first circuit receiving an input of a first test signal among differential signals formed by a first test signal and a second test signal and including at least an impedance element; a second circuit receiving an input of the second test signal among the differential signals and including at least a circuit under measurement; and an adder circuit that calculates the sum of an output from the first circuit and an output from the second circuit. (2) The signal processing device described in (1), wherein the first circuit includes a first impedance element and a second impedance element corresponding to the circuit under measurement, and the second circuit includes a third impedance element and the circuit under measurement. (3) The signal processing device described in (2), wherein the first circuit is configured by connecting the first impedance element and the second impedance element in series, and the second circuit is configured by connecting the third impedance element and the circuit under measurement in series. (4) The signal processing device described in (2) or (3), wherein a portion of the first directional coupler is formed within a semiconductor chip. (5) The signal processing device according to (4), wherein the second impedance element is formed outside the semiconductor chip. (6) The signal processing device according to any of (2) to (6), wherein the adder circuit calculates the sum of a voltage applied to the second impedance element as an output from the first circuit and a voltage applied to the circuit under measurement as an output from the second circuit. (7) The signal processing device according to any of (1) to (6), further comprising a second directional coupler connected in series to the first circuit and distributing the first test signal. (8) The signal processing device according to (1) to (7), further comprising a transmission circuit that generates the differential signal of a predetermined frequency and supplies it to the first directional coupler. (9) The signal processing device according to any of (1) to (8), wherein the first circuit and the second circuit include, as the impedance elements, a variable resistance element whose resistance value is changeable and a variable capacitance element whose capacitance is changeable. (10) The signal processing device according to any one of (1) to (8), wherein the first circuit and the second circuit include a resistive element and an inductor as the impedance elements.

[0075] 1 Vector network analyzer (VNA), 2 Device under test (DUT), 11 Reference signal generation circuit, 14 Rch receiving circuit, 15 Ach receiving circuit, 16 Bch receiving circuit, 17-2 to 17-6 Input / output terminals, 21 VNA chip, 22 Balun, 151 Transmitting circuit, 152 Directional coupler, 153 Input / output terminal, 161 Balun, 201 to 203 Resistive elements, 204 R channel output terminal, 211 to 213 Resistive elements, 214 A channel output terminal, 251 Adding circuit, 301 Variable resistive element, 302 Variable capacitance element, 303 Variable resistive element, 304 Variable capacitance element, 311, 312 Inductor

Claims

1. A signal processing device comprising: a first directional coupler configured with: a first circuit to which a first test signal of a differential signal composed of a first test signal and a second test signal is input and which includes at least an impedance element; a second circuit to which the second test signal of the differential signal is input and which includes at least a circuit under measurement; and an adder circuit that calculates the sum of the output from the first circuit and the output from the second circuit.

2. The signal processing device according to claim 1, wherein the first circuit includes a first impedance element and a second impedance element corresponding to the circuit under measurement, and the second circuit includes a third impedance element and the circuit under measurement.

3. The signal processing device according to claim 2, wherein the first circuit is configured by connecting the first impedance element and the second impedance element in series, and the second circuit is configured by connecting the third impedance element and the circuit under test in series.

4. The signal processing device according to claim 2, wherein a portion of the first directional coupler is formed within a semiconductor chip.

5. The signal processing device according to claim 4, wherein the second impedance element is formed outside the semiconductor chip.

6. The signal processing device according to claim 2, wherein the adder circuit calculates the sum of a voltage applied to the second impedance element as an output from the first circuit and a voltage applied to the circuit under measurement as an output from the second circuit.

7. The signal processing device according to claim 1, further comprising a second directional coupler connected in series with the first circuit and distributing the first test signal.

8. The signal processing device according to claim 1, further comprising a transmission circuit that generates the differential signal of a predetermined frequency and supplies it to the first directional coupler.

9. The signal processing device according to claim 1, wherein the first circuit and the second circuit include, as the impedance elements, a variable resistance element whose resistance value is changeable and a variable capacitance element whose capacitance is changeable.

10. The signal processing device according to claim 1, wherein the first circuit and the second circuit include a resistive element and an inductor as the impedance elements.

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