Stacked memory component

Abstract

An assembly comprises a single face up base die (a.k.a., logic die) that is shared by one or more (e.g., two) memory device stacks disposed thereon. The base die also extends out from underneath the memory device stacks to allow a portion of a processing die (e.g., CPU, GPU, etc.) to also be disposed on, and connected to, the base die. The base die interconnects the processing die to the memory device stacks. The base die may includes active circuitry to buffer / relay signals communicated between the processing die and the memory device stacks. The base die may include serializer / deserializer circuitry to allow the processing die to communicate with multiple memory device stacks using a similar number of data and / or command / address connections as is required for communicating with a single memory device stack (e.g., HBM3).

Description

STACKED MEMORY COMPONENTBRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure 1 is a diagram illustrating a first example stacked memory system.

[0002] Figure 2 is a diagram illustrating a second example stacked memory system.

[0003] Figures 3A-3B are diagrams illustrating overlapping communication for stacked memory accesses.

[0004] Figures 4A-4B are diagrams illustrating interleaved communication for stacked memory accesses.

[0005] Figure 5 is a flowchart illustrating a method of accessing multiple memory’ stacks disposed on a base die.

[0006] Figure 6 is a flowchart illustrating a method of communicating signals to multiple memory stacks disposed on a base die.

[0007] Figure 7 is a flowchart illustrating a method of communicating data signals between a processor and multiple memory stacks disposed on a base die.

[0008] Figure 8 is a flowchart illustrating a method of communicating data signals from a processor to multiple memory stacks disposed on a base die.

[0009] Figure 9 is a flowchart illustrating a method of concurrently accessing multiple memory stacks disposed on a base die.

[0010] Figure 10 is a flowchart illustrating a method of interleaving data communication of concurrent accesses to multiple memory stacks disposed on a base die.

[0011] Figure 1 1 is a block diagram of a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] In an embodiment, an assembly comprises a single face up base die (a.k.a., logic die) that is shared by one or more (e.g., two) memory device stacks disposed thereon. The base die also extends out from underneath the memory device stacks to allow a portion of a processing die (e.g., CPU, GPU, etc.) to also be disposed on, and connected to, the base die. The base die interconnects the processing die to the memory device stacks. In an embodiment, the base die includes active circuitry to buffer / relay signals communicated between the processing die and the memory device stacks. In an embodiment, the base die may include serializer / deserializer circuitry to allow the processing die to communicate with multiple memory device stacks using a similar number of data and / or command / address connections as is required for communicating with a single memory’ device stack (e.g.. HBM3). In another embodiment, the base die may communicate with the processing dieusing multiple sets of data and / or command / address connections dedicated to each communicating with one of the memory device stacks - e.g., two sets of data (DQ) signals each communicating with a one of two memory device stacks on the base die.

[0013] Figure 1 is a diagram illustrating a first example stacked memory system. In Figure 1, memory system 100 comprises base (a.k.a., logic) die 110, processor 120, memory device stack 130a, memory device stack 130b, and substrate 140. Base die 110 comprises stack “A” CA interface circuitry I l la, stack "B CA interface circuitry 11 lb, stack “A?’ data interface circuitry 112a, stack “B” data interface circuitry 112b, processor CA interface circuitry 113, processor stack “A” data interface circuitry 114a, stack “B” data interface circuitry 114b, stack “A"’ bidirectional buffer circuitry 115aa, stack “B"’ bidirectional buffer circuitry 115ba-l 15bc. stack “A” CA buffer circuitry 116aa, stackL‘B?’ CA buffer circuitry 116ba-116bc, control circuitry 117, and serializer / deserializer (SERDES) circuitry 119.

[0014] Processor 120 comprises command / address (CA) interface 123, stack “A” data interface 124a, stack “B” data interface 124b, and controller 125. Base die 110 is disposed on substrate / package 140. Memory device stack 130a and memory device stack 130b are disposed (e.g., active circuitry down) on base die 110 (e.g.. active circuitry up). Processor 120 is at least partially disposed (e.g., active circuitry down) on base die 110. In Figure 1, memory device stack 130a is disposed closer to processor 120 than memory7device stack 130b. Thus, signal lines coupling processor 120 with memory device stack 130b may be routed underneath memory- device stack 130a.

[0015] CA interface 123 of processor 120 is operatively coupled to CA interface 1 13 of base die 110. Stack “A” data interface 124a of processor 120 is operatively coupled to stack “A"’ data interface 114a of base die 110. Stack “B” data interface 124b of processor 120 is operatively coupled to stack “B” data interface 114b of base die 110. CA interface 113 and data interfaces 114a- 114b of base die 110 are operatively coupled to SERDES circuitry 119. SERDES circuitry 119 is operatively coupled to bidirectional buffer circuitry- 115aa 115ba- 115bc and buffer circuitry 116aa 116ba- 116bc.

[0016] Data signals to and from SERDES circuitry 119 are operatively coupled to data interface I32a of memory device stack 130a via bidirectional buffer circuitry 115aa, and data interface 112a. Data signals to and from SERDES circuitry7119 are operatively coupled to data interface 132b of memory- device stack 130b via bidirectional buffer circuitry7115ba- 115bc, and data interface 112b. Command / address signal from SERDES circuitry 119 are operatively coupled to CA interface 131a of memory device stack 130a via buffer circuitry 116aa and CA interface I l la. Command / address signal from SERDES circuitry 1 19 areoperatively coupled to CA interface 131b of memory device stack 130b via buffer circuitry 116ba-l 16bc, and CA interface 11 lb.

[0017] Processor 120 is at least partially disposed on base die 1 10 to allow command / address and data signals communicated via CA interface 123 and data interfaces 124a-124b, respectively, (a.k.a., memory' channel signals) to be communicated via base die 110 with memory device stacks 130a-130b. Memory device stack 130a is disposed on base die 110 to allow command / address signals and data signals (a.k.a., memory channel signals) communicated via CA interface 131a and data interface 132a to be communicated via base die 110 with processor 120 (and controller 125, in particular) via CA interface 123 and data interface 124a, respectively. Memory device stack 130b is disposed on base die 110 to allow command / address signals and data signals communicated via CA interface 131b and data interface 132b to be communicated via base die 110 with processor 120 (and controller 125, in particular) via CA interface 123 and data interface 124b, respectively.

[0018] CA interface 123 and data interfaces 124a-124b of processor 120 may be electrically and / or physically connected to base die 110 via conductive connections such as, for example, solder balls, bumps, copper fusion etc. CA interfaces 131a- 131b and data interfaces 132a- 132b of memory device stacks 130a- 130b, respectively, may be electrically and / or physically connected to base die 110 via conductive connections such as, for example, solder balls, bumps, copper fusion, etc. In an embodiment. CA interface 113 of base die 110 is disposed directly underneath CA interface 123 of processor 120. Likewise, data interface 1 14a and data interface 114b of base die 1 10 are respectively disposed directly underneath data interface 124a and data interface 124b of processor 120. By positioning CA interface 113 and data interfaces 114a-l 14b directly beneath their counterpart interfaces on processor 120, the signaling channel between processor 120 and base die 110 may be made as short as is practicably possible - thereby possibly decreasing power consumption and / or increasing signaling bandwidth.

[0019] Processor 120 and memory device stacks 130a-130b may comprise integrated circuit type devices, such as those commonly referred to as “chips”. In an embodiment, memory device stacks 130a- 130b may be. or comprise a stack of dynamic random access memory (DRAM) integrated circuit die co-packaged together and coupled to each other via wired bonds and / or through-silicon vias (TSVs) and / or copper fusion. Examples of a stacked die component comprising DRAM integrated circuit dies include High Bandwidth Memory (HBM) type components. However, rather than each memory device stack 130a- 130b having a dedicated, and separate, base die, memory device stack 130a and memorydevice stack 130b may be HBM compatible DRAM memory die stacks, without base logic dies, that “share” base die 110. Thus, memory’ device stacks 130a- 130b may share some or all of the functions (e.g., memory built-in self-test - MBIST and / or direct Access test circuitry) performed by the circuitry’ (e.g., control circuitry 117, and / or interface circuitry’ 11 la-1 l ib, 112a-112b of base die 110).

[0020] A memory controller, such as controller 125 of processor 120, manages the flow of data going to and from memory devices. Functionality of a memory controller may be included on a single die with the processing circuitry of processor 120, or included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or included as a chiplet separate from processor 120. Processor 120 may include, for example, northbridge functionality, an application specific functionality, a load-reduction memory buffer functionality’, a graphics processor unit (GPU), a system-on-chip (SoC) or an integrated circuit device that includes many circuit blocks such as ones selected from graphics cores, processor cores, and MPEG encoder / decoders, etc.

[0021] It should be understood that disposing processor 120 and memory device stacks 130a-130b on base die 110 may result in the signal coupling between processor 120 and memory device stacks 130a- 130b being shorter, and therefore allowing for faster communication and lower power consumption than if those couplings were made via a separate interposer, or substrate 140, and / or system component (e.g., host printed circuit board). In an embodiment, the distance between the base die 110 connections to processor 120 (e g., CA interface 121 and data interface 122a) and the base die connections to memory’ device stack 130a (e.g., CA interface 131a and data interface 132a) may be, for example, in the neighborhood of 2.5 mm. Similarly, the distance between the base die 110 connections to processor 120 (e.g., CA interface 121 and data interface 122b) and the base die connections to memory device stack 130b (e.g., CA interface 131b and data interface 132b) may be, for example, in the neighborhood of 15mm.

[0022] It should also be understood that more than one (e.g., 4, 6, 8, etc.) base die with two or more memory device stacks disposed on them may be disposed on substrate 140 and also partially disposed under processor 120 and interconnected with processor 120 via their respective base die. Processor 120, base die 110, memory’ device stacks 130a-130b may be viewed or referred to as, for example, part of an assembly and / or a component that includes substrate 140. The component comprising memory system 100 may be further disposed on, for example, a printed circuit (PC) board of a host system.

[0023] In an embodiment, base die 110 interconnects processor 120 and memory device stacks 130a-130b. In particular, base die 110 functions to communicate signals (e.g., data - DQ, and command / address - CA, signals) transmitted or received via CA interface 123 and data interfaces 124a-124b of processor 120. These signals may7be re-driven (a.k.a., relayed) by a series of buffers (e.g., data by bidirectional buffer circuitry 115aa 115ba-115bc and command / address information by buffer circuitry 116aa 116ba-l 16bc) while being propagated across base die 1 10 between processor 120 and respective ones of memory device stacks 130a-130b.

[0024] In an embodiment, CA interface 123 and CA interfaces 131 a-13 lb operate at a signaling rate that is compatible with, for example, HBM3. CA interface 123 may also, in some embodiments, comprise two separate HBM3 CA interfaces each dedicated to a respective one of memory device stack 130a-13 lb. Thus, it should be understood that in this embodiment, CA interface 123 may have, or substantially have, two times the number of command / address signals as each of CA interface 131a and CA interface 131b. Also in this embodiment, each of the CA interface that comprise CA interface 123, and the data interfaces 124a- 124b. may be operated independently of the other. In other words, in this embodiment, a first memory channel interface comprising CA interface 131a and data interface 132a may be operated by processor 120 (e.g., via CA interface 123 and data interface 124a) independently of a second memory channel interface comprising CA interface 131b and data interface 132b (e.g., via CA interface 123 and data interface 124b).

[0025] In an embodiment, data interfaces 124a- 124b and data interfaces 132a- 132b operate at a signaling rate that is compatible with, for example, HBM3. Thus, data interfaces 124a-124b may be viewed as two separate data interfaces each dedicated to a respective one of memory device stack 130a- 130b. Accordingly, data interfaces 124a- 124b, taken together, may have, or substantially have, two times the number of data signals as each of data interface 132a and data interface 132b. In this embodiment, SERDES 119 may not be present, may be bypassed, or may be configured not to serialize / deserialize (e.g., configured or put in a mode to operate at a 1: 1 serialization / deserialization factor).

[0026] In an embodiment, data interfaces 132a-132b operate at a signaling rate that is compatible with a vertical signaling rate of DRAM stacks. However, data interfaces 114a- 114b and data interfaces 124a-124b operate at a signaling rate that is N times (e.g., N=2, 4, 8, etc.) greater than the rate of data interfaces 132a-132b of memory device stacks 130a-130b. In this embodiment, SERDES 119 serializes and deserializes the data to and from data interfaces 114a-l 14b such that the data propagated across base die 110 operates at a signalingrate that is compatible with data interfaces 132a-132b of memory device stacks 130a-130b while data communicated between base die 110 and processor 120 operates at a signaling rate that is a positive integer multiple of the memory device stacks 130a-130b signaling rate.

[0027] Figure 2 is a diagram illustrating a second example stacked memory system. In Figure 2, memory system 200 comprises base (a.k.a., logic) die 210, processor 220, memorydevice stack 230a, memory- device stack 230b, and substrate 240. Base die 210 comprises stack “A” CA interface circuitry 211a. stack "B CA interface circuitry 211b, stack “A?’ data interface circuitry 212a, stack “B” data interface circuitry 212b, processor CA interface circuitry- 213, processor stack data interface circuitry- 214, stack “A” bidirectional buffer circuitry 215aa, stack “B” bidirectional buffer circuitry 215ba-215bc, stack “A” CA buffer circuitry 216aa, stack ”B ' CA buffer circuitry 216ba-216bc, control circuitry 217, multiplexer / demultiplex er (MUX / DEMUX) circuitry 218, and serializer / deserializer (SERDES) circuitry 219.

[0028] Processor 220 comprises command / address (CA) interface 223, data interface 224, and controller 225. Base die 210 is disposed on substrate / package 240. Memory device stack 230a and memory device stack 230b are disposed (e.g.. active circuitry down) on base die 210 (e g., active circuitry- up). Processor 220 is at least partially disposed (e g., active circuitry- down) on base die 210. In Figure 2, memory- device stack 230a is disposed closer to processor 220 than memory device stack 230b. Thus, signal lines coupling processor 220 with memory device stack 230b may- be routed underneath memory device stack 230a.

[0029] C A interface 223 of processor 220 is operatively coupled to CA interface 213 of base die 210. Data interface 224 of processor 220 is operatively- coupled to data interface 214 of base die 210. CA interface 213 and data interface 214 of base die 210 are operatively coupled to SERDES circuitry 219. SERDES circuitry 219 is operatively coupled to bidirectional buffer circuitry 215aa 215ba-215bc and buffer circuitry 216aa 216ba-216bc.

[0030] Data signals to and from SERDES circuitry 219 are operatively- coupled to data interface 232a of memory- device stack 230a via bidirectional buffer circuitry- 215aa, and data interface 212a. Data signals to and from SERDES circuitry 219 are operatively coupled to data interface 232b of memory device stack 230b via bidirectional buffer circuitry 215ba- 215bc, and data interface 212b. Command / address signals from SERDES circuitry- 219 are operatively coupled to CA interface 231a of memory- device stack 230a via buffer circuitry 216aa and CA interface 211a. Command / address signal from SERDES circuitry 219 are operatively coupled to CA interface 231b of memory device stack 230b via buffer circuitry 216ba-216bc, and CA interface 21 lb.

[0031] Processor 220 is at least partially disposed on base die 210 to allow command / address and data signals communicated via CA interface 223 and data interface 224, respectively, (a.k.a., memory channel signals) to be communicated via base die 210 with memory device stacks 230a-230b. Memory device stack 230a is disposed on base die 210 to allow command / address signals and data signals (a.k.a., memory' channel signals) communicated via CA interface 231a and data interface 232a to be communicated via base die 210 with processor 220 (and controller 225, in particular) via CA interface 223 and data interface 224, respectively. Memory' device stack 230b is disposed on base die 210 to allow command / address signals and data signals communicated via CA interface 231b and data interface 232b to be communicated via base die 210 with processor 220 (and controller 225, in particular) via CA interface 223 and data interface 224, respectively.

[0032] CA interface 223 and data interface 224 of processor 220 may be electrically and / or physically connected to base die 210 via conductive connections such as, for example, solder balls, bumps, copper fusion, etc. CA interfaces 23 la-23 lb and data interfaces 232a- 232b of memory device stacks 230a-230b, respectively, may be electrically and / or physically connected to base die 210 via conductive connections such as, for example, solder balls, bumps, copper fusion, etc. In an embodiment, CA interface 213 of base die 210 is disposed directly underneath CA interface 223 of processor 220. Likewise, data interface 214 of base die 21 Ois disposed directly underneath data interface 224 of processor 220. By positioning CA interface 213 and data interface 214 directly beneath their counterpart interfaces on processor 220, the signaling channel between processor 220 and base die 210 may be made as short as is practicably possible - thereby possibly decreasing power consumption and / or increasing signaling bandwidth.

[0033] Processor 220 and memory device stacks 230a-230b may comprise integrated circuit type devices, such as those commonly referred to as '‘chips”. In an embodiment, memory device stacks 230a-230b may be, or comprise a stack of dynamic random access memory (DRAM) integrated circuit die co-packaged together and coupled to each other via wired bonds and / or through-silicon vias (TSVs) and / or copper fusion. Examples of a stacked die component comprising DRAM integrated circuit dies include High Bandwidth Memory (HBM) ty pe components. However, rather than each memory device stack 230a- 230b having a dedicated, and separate, base die, memory' device stack 230a and memory' device stack 230b may be HBM compatible DRAM memory die stacks, without base logic dies, that “share” base die 210. Thus, memory device stacks 230a-230b may share some or all of the functions (e.g., memory built-in self-test - MBIST, and / or direct Access testcircuitry) performed by the circuitry (e.g., control circuitry 217. and / or interface circuitry 21 la-21 lb. 212a-212b) of base die 210.

[0034] A memory controller, such as controller 225 of processor 220, manages the flow of data going to and from memory devices. Functionality of a memory controller may be included on a single die with the processing circuitry of processor 220, or included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC) , or included as a chiplet separate from processor 220. Processor 220 may include, for example, northbridge functionality, an application specific functionality, a load-reduction memory buffer functionality, a graphics processor unit (GPU), a system-on-chip (SoC) or an integrated circuit device that includes many circuit blocks such as ones selected from graphics cores, processor cores, and MPEG encoder / decoders, etc.

[0035] It should be understood that disposing processor 220 and memory device stacks 230a-230b on base die 210 may result in the signal coupling between processor 220 and memory7device stacks 230a-230b being shorter, and therefore allowing for faster communication and lower power consumption than if those couplings were made via a separate interposer, and / or substrate 240 and / or system component (e.g., host PC board). In an embodiment, the distance between the base die 210 connections to processor 220 (e.g., CA interface 223 and data interface 224) and the base die connections to memory device stack 230a (e.g., CA interface 231a and data interface 232a) may be, for example, in the neighborhood of 2.5 mm. Similarly, the distance between the base die 210 connections to processor 220 (e.g., CA interface 223 and data interface 224) and the base die connections to memory device stack 230b (e.g., CA interface 231b and data interface 232b) may be, for example, in the neighborhood of 15mm.

[0036] It should also be understood that more than one (e.g., 4, 6. 8, etc.) base die with two or more memory- device stacks disposed on them may be disposed on substrate 240 and also partialty disposed under processor 220 and interconnected with processor 220 via their respective base die. Processor 220, base die 210, memory- device stacks 230a-230b may be viewed or referred to as, for example, part of an assembly and / or a component that includes substrate 240. The component comprising memory system 200 may be further disposed on, for example, a printed circuit (PC) board of a host system.

[0037] In an embodiment, base die 210 interconnects processor 220 and memory' device stacks 230a-230b. In particular, base die 210 functions to communicate signals (e.g., data - DQ, and command / address - CA, signals) transmitted or received via CA interface 223 and data interface 224 of processor 220. These signals may be re-driven (a.k.a., relayed) by aseries of buffers (e.g., data by bidirectional buffer circuitry 215aa 215ba-215bc and command / address information by buffer circuitry 216aa 216ba-216bc) while being propagated across base die 210 between processor 220 and respective ones of memory device stacks 230a-230b.

[0038] Base die 210 (and SERDES 219, in particular) converts high-speed signals communicated from data interface 224 (i.e., received from controller 225) into multiple lower-speed parallel signals. These lower-speed parallel signals may be further separated, by MUX / DEMUX 218, into data signals to be communicated with memory device stack 230a and data signal to be communicated with memory' device stack 230b. The separated signals may be re-driven by a series of buffers (e.g., bidirectional buffer circuitry 215aa 215ba- 215bc) while being propagated across base die 210 before being communicated with data interfaces 232a-232b.

[0039] Similarly, base die 210 (and MUX / DEMUX 218, in particular) combines signals received via data interfaces 232a-232b (i.e., received from memory device stacks 230a-230b, respectively) into a reduced number of parallel signals (e.g., via interleaving, multiplexing, etc.). These combined lower-speed signals received from MUX / DEMUX 218 are further converted by SERDES 219 into a even smaller number of higher-speed parallel signals (e.g., via interleaving, multiplexing, etc.). As they are propagated from memory' device stacks 230a-230b across base die 210, the lower-speed parallel signals from memory device stacks 230a-230b may be re-driven by a series of buffers (e.g.. bidirectional buffer circuitry 215aa 215ba-215bc) before being multiplexed and serialized and communicated with data interface 224.

[0040] In an embodiment, CA interface 223 and CA interfaces 23 la-23 lb operate at a signaling rate that is compatible with, for example, HBM3. CA interface 223 may also, in some embodiments, comprise two separate HBM3 CA interfaces each dedicated to a respective one of memory device stack 230a-23 lb. Thus, it should be understood that in this embodiment, CA interface 223 may have, or substantially have, two times the number of command / address signals as each of CA interface 231a and CA interface 231b. Also in this embodiment, each of the CA interface that comprise CA interface 223. and the respective interleaved signaling of data interface 224, may be operated independently of the other. In other words, in this embodiment, a first memory' channel interface comprising CA interface 231a and data interface 232a may be operated by processor 220 (e.g., via CA interface 223 and the interleaved data communication of data interface 224) independently of a secondmemory' channel interface comprising CA interface 231b and data interface 232b (e.g., via CA interface 223 and the interleaved data communication of data interface 224).

[0041] In an embodiment, data interfaces 232a-232b operate at a signaling rate that is compatible with, for example, HBM3. Thus, data interface 224 may be viewed as two separate, but interleaved, data interfaces each dedicated to a respective one of memory device stack 230a-230b. Accordingly, data interface 224 may have, or substantially have, the same number of data signals as each of data interface 132a and data interface 132b, but is operated at twice the signaling rate (due to MUX / DEMUX 1 18). In this embodiment, SERDES 219 may not be present, may be bypassed, or may be configured not to serialize / deserialize (e.g., configured or put in a mode to operate at a 1: 1 serialization / deserialization factor).

[0042] In an embodiment, data interfaces 232a-232b operate at a signaling rate that is compatible with a vertical signaling rate of DRAM stacks. However, data interface 214 and data interface 224 operate at a signaling rate that is N times (e.g., N=2, 4, 8, etc.) greater than the rate of data interfaces 232a-232b of memory device stacks 230a-230b. In this embodiment. SERDES 219 serializes and deserializes, and MUX / DEMUX 218 multiplexes and demultiplexes the data to and from data interface 214 such that the data propagated across base die 210 operates at a signaling rate that is compatible with data interfaces 232a- 232b of memory' device stacks 230a-230b while data communicated between base die 210 and processor 220 operates at a signaling rate that is a positive integer multiple of the memory device stacks 230a-230b signaling rate.

[0043] In Figure 1 and Figure 2, separate buffer circuitry 116aa-l 16ba 216aa-216ba chains are illustrated as providing CA signals to stack “A” 130a 230a and stack “B” 130b 230b, respectively. However, it should be understood that, in some embodiments, a single buffer chain may provide CA signals to both stack ‘"A” 130a 230a and stack “B” 130b 230b (e.g., by removing buffer circuitry 116ba 216ba and having the output of buffer circuitry 116aa and 216aa couple to both CA interface 11 la 21 la and the input to buffer circuitry 116bb 216bb.) Similarly, processor 120 is illustrated in Figure 1 and Figure 2 as having a single CA interface 123 coupled to a single CA interface 113 which is then split by SERDES 119 219 into two CA signals groups that are provided to two buffer circuitry 116aa-l 16ba 216aa-216ba chains. It should be understood that, in some embodiments, processor 120 may have a two CA interfaces (e.g., one CA interface from processor 120 for each stack 130a- 130b 230a-230b) respectively coupled to two CA interfaces of base die 110 whose signals are then respectively provided to two buffer circuitry 116aa-l 16ba 216aa-216ba chains (e.g., via SERDES 1 19 219 or directly).

[0044] Figures 3A-3B are diagrams illustrating overlapping communication for stacked memory accesses. The example communication timing illustrated in Figures 3A-3B may be used by, for example, memory system 100. In Figures 3A-3B, stack #1 may be memory device stack 130a and stack #2 may be memory device stack 130b.

[0045] Figure 3A illustrates example timing for a read operation. In Figure 3A, the row information communication lines (R-Com - e.g., of CA interface 123) transmit an “Activate” (ACT) command and a “Precharge” (PRE) command. These illustrated ACT and PRE commands are illustrated in Figure 3A to illustrate they do not occupy bandwidth on the column information communication lines and may or may not be related to the commands illustrated in Figure 3A that are communicated via the column information communications lines. Likewise, the timing of these illustrated ACT and PRE commands is only for illustration purposes and should not be taken to imply a timing relationship to the commands illustrated in Figure 3A that are communicated via the column information communications lines.

[0046] The column information communications lines (C-Com — e g., of CA interface 123) transmit the following commands / addresses, in order: “read bank group A of stack #1” (RD SI A), “read bank group A of stack #2” (RD S2A), “read bank group B of stack #1” (RD SIB), and “read bank group B of stack #2” (RD S2B). In response to the RD S1A command / address, the data interface of stack #1 outputs the requested / addressed data (shown as DQ @ stack #1) from its bank group A. Following the data from bank group A. stack #1 outputs the requested data from its bank group B in response to the RD S 1 B command. These bursts of data are received at the data interface dedicated to stack #1 on processor 120 (e.g., data interface 122a - shown as DQsi @ processor).

[0047] Similarly, and overlapping with the bursts of data from stack #1, stack #2, in response to the RD S2A command / address, the data interface of stack #2 outputs the requested / addressed data (shown as DQ @ stack #2) from its bank group A. Following the data from bank group A, stack #2 outputs the requested data from its bank group B in response to the RD S2B command. These bursts of data are received at the data interface dedicated to stack #2 on processor 120 (e.g., data interface 122b - shown as DQs2 @ processor) and also overlap with the bursts of data being received via the DQsi interface.

[0048] Figure 3B illustrates example timing for a write operation. In Figure 3B, the row information communication lines (R-Com - e.g., of CA interface 123) transmit an “Activate” (ACT) command and a “Precharge” (PRE) command. These illustrated ACT and PRE commands are illustrated in Figure 3B to illustrate they do not occupy bandwidth on thecolumn information communication lines and may or may not be related to the commands illustrated in Figure 3B that are communicated via the column information communications lines. Likewise, the timing of these illustrated ACT and PRE commands is only for illustration purposes and should not be taken to imply a timing relationship to the commands illustrated in Figure 3B that are communicated via the column information communications lines.

[0049] The column information communications lines transmit the following commands / addresses, in order: "write bank group A of stack #1” (WR SI A), “write bank group A of stack #2’’ (WR S2A), “write bank group B of stack #1” (WR SIB), and “write bank group B of stack #2” (WR S2B). Following the transmission of the WR S1A command / address. the stack #1 data interface of processor 120 outputs the data to be written to the specified address of stack # 1 ’s bank group A. Following the data to be written to bank group A, the stack #1 data interface of processor 120 outputs the data to be w ritten to the specified address of bank group B in response to the WR SIB command. These bursts of data are received at the data interface of stack #1.

[0050] Similarly, and overlapping with the bursts of data transmitted to stack #1. following the transmission of the WR S2A command / address, the stack #2 data interface of processor 120 outputs the data to be written to the specified address of stack #2’s bank group A. Following the data to be written to bank group A, the stack #2 data interface of processor 120 outputs the data to be written to the specified address of bank group B in response to the WR S2B command. These bursts of data are received at the data interface of stack #2 and overlap with the bursts of data being received by stack #1.

[0051] Figures 4A-4B are diagrams illustrating interleaved communication for stacked memory accesses. The example communication timing illustrated in Figures 4A-4B may be used by, for example, memory system 200. In Figures 4A-4B, stack #1 may be memory device stack 230a and stack #2 may be memory device stack 230b.

[0052] Figure 4A illustrates example timing for a read operation. In Figure 4A, the row information communication lines (R-Com - e g., of CA interface 123) transmit an “Activate” (ACT) command and a “Precharge” (PRE) command. These illustrated ACT and PRE commands are illustrated in Figure 4 A to illustrate they do not occupy bandw idth on the column information communication lines and may or may not be related to the commands illustrated in Figure 4A that are communicated via the column information communications lines. Likewise, the timing of these illustrated ACT and PRE commands is only for illustration purposes and should not be taken to imply a timing relationship to the commandsillustrated in Figure 4A that are communicated via the column information communications lines.

[0053] The column information communications lines (C-Com - e.g., of CA interface 223) transmit the following commands / addresses, in order: '‘read bank group A of stack #1” (RD SI A), “read bank group A of stack #2” (RD S2A), “read bank group B of stack #1” (RD SIB), and “read bank group B of stack #2” (RD S2B). In response to the RD SI A command / address. the data interface of stack #1 outputs the requested / addressed data (shown as DQ @ stack #1) from its bank group A. Following the data from bank group A, stack #1 outputs the requested data from its bank group B in response to the RD SIB command.

[0054] Similarly, and overlapping with the bursts of data from stack #1, stack #2, in response to the RD S2A command / address, the data interface of stack #2 outputs the requested / addressed data (shown as DQ @ stack #2) from its bank group A. Following the data from bank group A, stack #2 outputs the requested data from its bank group B in response to the RD S2B command. The bursts of data from stack #1 and the bursts of data from stack #2 are then doubled in data rate and then interleaved (e.g.. by SERDES 219) before being received at the data interface of processor 220 (e.g.. data interface 224 - shown as DQ @ processor).

[0055] Figure 4B illustrates example timing for a write operation. In Figure 4B, the row information communication lines (R-Com - e g., of CA interface 123) transmit an “Activate” (ACT) command and a “Precharge” (PRE) command. These illustrated ACT and PRE commands are illustrated in Figure 4B to illustrate they do not occupy bandwidth on the column information communication lines and may or may not be related to the commands illustrated in Figure 3A that are communicated via the column information communications lines. Likewise, the timing of these illustrated ACT and PRE commands is only for illustration purposes and should not be taken to imply a timing relationship to the commands illustrated in Figure 4B that are communicated via the column information communications lines.

[0056] The column information communications lines transmit the following commands / addresses, in order: “write bank group A of stack #1” (WR SI A), “write bank group A of stack #2” (WR S2A), “write bank group B of stack #1” (WR SIB), and “write bank group B of stack #2” (WR S2B). Following the transmission of the WR S1A command / address, the stack #1 data interface of processor 220 outputs the data to be written to the specified address of stack # 1 ’s bank group A at a rate that is double the rate stack # Es data interface operates. Following the data to be written to bank group A of stack #1, the datainterface of processor 220 outputs the data to be written to the specified address of bank group A of stack #2 at a rate that is double the rate stack #2’s data interface operates. Following the data to be written to bank group A of stack #2, the data interface of processor 220 outputs the data to be written to the specified address of bank group B of stack #1 at a rate (i.e., bandwidth which is signaling speed times number of parallel bits) that is double the rate stack #l’s data interface operates. Following the data to be written to bank group B of stack #1. the data interface of processor 220 outputs the data to be written to the specified address of bank group B of stack #2 at a rate that is double the rate stack #2’s data interface operates. The bursts of data for stack #1 and the bursts of data for stack #2 are then halved in data rate (e.g., by SERDES 219) and deinterleaved (demultiplexed — e.g.. by MUX / DEMUX 218) and before being received at the data interfaces of stack #1 and stack #2, respectively.

[0057] Figure 5 is a flowchart illustrating a method of accessing multiple memory stacks disposed on a base die. One or more steps illustrated in Figure 5 may be performed by, for example, system 100, system 200, and / or their components. By a processing device partially disposed on a base die. at least one of a first set of stacked memory device disposed on the base die is accessed via signals of a first external interface that couples the first set of stacked memory devices to the base die (502). For example, processor 120 may access one or more dies in memory device stack 130a via base die 110, CA interface 131a, and data interface 132a.

[0058] By the processing device, at least one of a second set of stacked memory device disposed on the base die is accessed via signals of a second external interface that couples the second set of stacked memory devices to the base die (504). For example, processor 120 may access one or more dies in memory device stack 130b via base die 110, CA interface 131b, and data interface 132b. By the based die, the signals of the first external interface and the second external interface are coupled with an external interface of the processing device (506). For example, based die 110 may respectively couple, via one or more of buffer circuitry 115aa 115ba-115bc and buffer circuitry 116aa 116ba-116bc the signals of CA interfaces 131 a-131 b and data interfaces 132a-132b with CA interface 223 and data interfaces 122a- 122b.

[0059] Figure 6 is a flowchart illustrating a method of communicating signals to multiple memory' stacks disposed on a base die. One or more steps illustrated in Figure 6 may be performed by, for example, system 100, system 200, and / or their components. By a base die and from an external interface of a processing device at least partially disposed on the basedie. command / address signals are received (602). For example, base die 110 may receive, from CA interface 121, command / address signals from processor 120.

[0060] By the base die, the command / address signals are relayed to a first external interface of a first set of stacked memory devices disposed on the base die (604). For example, buffers 116aa ofbase die 110 may relay the command / address signals received from processor 120 to CA interface 131a of memory’ device stack 130a. By the base die. the command / address signals are relay ed to a second external interface of a second set of stacked memory devices disposed on the base die (606). For example, buffer circuitry 116ba-l 16bc of base die 110 may relay the command / address signals received from processor 120 to CA interface 131b of memory device stack 130b.

[0061] Figure 7 is a flowchart illustrating a method of communicating data signals between a processor and multiple memory stacks disposed on a base die. One or more steps illustrated in Figure 7 may be performed by, for example, system 200, and / or their components. By a base die and from a first external interface of a first set of stacked memory devices disposed on the base die, first data signals are received (702). For example, base die 210 may receive, from memory device stack 230a, a first burst of data signals from data interface 232a.

[0062] By the base die and from a second external interface of a second set of stacked memory devices disposed on the base die, second data signals are received (704). For example, base die 210 may receive, from memory device stack 230b. a second burst of data signals from data interface 232b. By the base die, the first data signals and the second data signals are time multiplexed to generate time multiplexed data signals (706). For example, MUX / DEMUX 218 of based die 210 may receive and time multiplex the first burst of data signals and the second burst of data signals (see, e.g., “DQ @ processor” in Figure 4A).

[0063] By the base die, the time multiplexed data signals are transmitted to an external interface of a processing device that is at least partially disposed on the base die (708). For example, the time multiplexed data signals generated by MUX / DEMUX 218 of based die 210 may be transmitted to data interface 224.

[0064] Figure 8 is a flowchart illustrating a method of communicating data signals from a processor to multiple memory stacks disposed on a base die. One or more steps illustrated in Figure 8 may be performed by, for example, system 200, and / or their components. By a base die and from an external interface of a processing device at least partially disposed on the base die, time multiplexed data signals are received (802). For example, base die 210 mayreceive, from data interface 224 of processor 220, a first burst of data that is time multiplexed with a second burst of data (see, e.g., DQ @ processor” in Figure 4B).

[0065] The time multiplexed data signals are time demultiplexed by the base die to generate first data signals and second data signals (804). For example, MUX / DEMUX 218 of base die 210 may time demultiplex the time multiplexed first burst of data and second burst of data to generate a slower data rate first burst of data signals and a slower data rate second burst of data signals. By the base die and to a first external interface of a first set of stacked memory devices disposed on the base die, the first data signals are transmitted (806). For example, base die 210 may transmit the first burst of data signals to data interface 232a of memory device stack 230a.

[0066] By the base die and to a second external interface of a first set of stacked memory devices disposed on the base die, the second data signals are transmitted (808). For example, base die 210 may transmit the second burst of data signals to data interface 232b of memory device stack 230b.

[0067] Figure 9 is a flowchart illustrating a method of concurrently accessing multiple memory stacks disposed on a base die. One or more steps illustrated in Figure 9 may be performed by, for example, system 100, and / or their components. By a base die and from an external interface of a processing device at least partially disposed on the base die, a first command to access a first set of stacked memory device disposed on the base die is received (902). For example, base die 110 may receive, from CA interface 121 of processor 120, a first command that is to configured access at least one die in memory device stack 130a.

[0068] By the base die and from the external interface of a processing device, a second command to access a second set of stacked memory device disposed on the base die is received (904). For example, base die 110 may receive, from CA interface 121 of processor 120, a second command that is configured to access at least one die in memory device stack 130b.

[0069] By the base die and to a first command / address interface of the first set of stacked memory devices, the first command is transmitted (906). For example, base die 110 may transmit, via buffers 116a. the first command to CA interface 131a of memory device stack 130a. By the base die and to a second command / address interface of the second set of stacked memory devices, the second command is transmitted (908). For example, base die 110 may transmit, via buffer circuitry 116a- 116c, the second command to CA interface 131b of memory device stack 130b.

[0070] By the base die and from a first data interface of the first set of stacked memory' devices, first data accessed in response to the first command is received (910). For example, bidirectional buffers 115aa of base die 1 10 may receive a first burst of data, from data interface 132a of memory device stack 130a, that was accessed in response to the first command. By the base die and from a second data interface of the second set of stacked memory devices, second data accessed in response to the second command is received (912). For example, bidirectional buffers 115bc of base die 110 may receive a second burst of data, from data interface 132b of memory device stack 130b, that was accessed in response to the second command.

[0071] By the base die and to a first data interface of the processing device, the first data is transmitted (914). For example, base die 110 may transmit the first burst of data to data interface 122a of processor 120. By the base die and to a second data interface of the processing device, the second data is transmitted concurrently with the transmission of the first data (916). For example, base die 110 may transmit, concurrently with transmitting the first burst of data to data interface 122a, the second burst of data to data interface 122b of processor 120.

[0072] Figure 10 is a flowchart illustrating a method of interleaving data communication of concurrent accesses to multiple memory' stacks disposed on a base die. One or more steps illustrated in Figure 10 may be performed by, for example, system 200. and / or their components. By a base die and from an external interface of a processing device at least partially disposed on the base die, a first command to access a first set of stacked memory device disposed on the base die is received (1002). For example, base die 210 may receive, from CA interface 223 of processor 220, a first command that is configured to access at least one die in memory device stack 230a.

[0073] By the base die and from the external interface of a processing device, a second command to access a second set of stacked memory device disposed on the base die is received (1004). For example, base die 210 may receive, from CA interface 223 of processor 220, a second command that is configured to access at least one die in memory device stack 230b (1004).

[0074] By the base die and to a first command / address interface of the first set of stacked memory' devices, the first command is transmitted (1006). For example, base die 210 may transmit, via buffers 216a, the first command to CA interface 231a of memory device stack 230a. By the base die and to a second command / address interface of the second set of stacked memory devices, the second command is transmitted (1008). For example, base die210 may transmit, via buffers 216a- 116c, the second command to CA interface 231b of memory device stack 230b.

[0075] By the base die and from a first data interface of the first set of stacked memory devices, first data accessed in response to the first command is received (1010). For example, SERDES 219 of base die 210, via bidirectional buffers 215aa of base die 210, may receive a first burst of data, from data interface 232a of memory’ device stack 230a, that was accessed in response to the first command. By the base die and from a second data interface of the second set of stacked memory devices, second data accessed in response to the second command is received (1012). For example, MUX / DEMUX 218 of base die 210, via bidirectional buffers 215aa-215ac of base die 210, may receive a second burst of data, from data interface 232b of memory device stack 230b. that was accessed in response to the second command.

[0076] By the base die, the first data and the second data are time multiplexed to generate time multiplexed data (1014). For example, MUX / DEMUX 218 may increase the data rate (e.g., double) and time multiplex the first burst of data and the second burst of data to generate a time multiplexed data burst that includes the first burst of data and the second burst of data. By the base die and to a data interface of the processing device, the time multiplexed data is transmitted (1016). For example, base die 210 may transmit the time multiplexed data burst that includes the first burst of data and the second burst of data to data interface 224 of processor 220.

[0077] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of memory system 100, memory system 200, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by earner waves.

[0078] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL. formats supporting geometry' description languages (such as GDSII. GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readablemedia may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0079] Figure 11 is a block diagram illustrating one embodiment of a processing system 1100 for including, processing, or generating, a representation of a circuit component 1120. Processing system 1100 includes one or more processors 1102, a memory 1104, and one or more communications devices 1106. Processors 1 102, memory 1104. and communications devices 1106 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1108.

[0080] Processors 1102 execute instructions of one or more processes 1112 stored in a memory 1104 to process and / or generate circuit component 1120 responsive to user inputs 1114 and parameters 1 116. Processes 1112 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry7and / or generate photomasks for electronic circuitry'. Representation 1120 includes data that describes all or portions of memory’ system 100, memory system 200, and their components, as shown in the Figures.

[0081] Representation 1120 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 1120 may be stored on storage media or communicated by carrier waves.

[0082] Data formats in which representation 1120 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email

[0083] User inputs 1114 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1116 may include specifications and / or characteristics that are input to help define representation 1120. For example, parameters 1116 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0084] Memory' 1104 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1112, user inputs 1114. parameters 1116, and circuit component 1120.

[0085] Communications devices 1106 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1100 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1106 may transmit circuit component 1120 to another system. Communications devices 1106 may receive processes 1112, user inputs 1114, parameters 1116, and / or circuit component 1120 and cause processes 1112, user inputs 1114, parameters 1116, and / or circuit component 1120 to be stored in memory 1104.

[0086] Implementations discussed herein include, but are not limited to, the following examples:

[0087] Example 1: An assembly, comprising: a base die; a first set of stacked memory devices disposed on the base die, each of the first set of stacked memory devices comprising at least a first memory array, the first memory array to be accessed via signals of a first external interface that couples the first set of stacked memory' devices to the base die; a second set of stacked memory devices disposed on the base die, each of the second set of stacked memory devices comprising at least a second memory array, the second memory array to be accessed via signals of a second external interface that couples the second set of stacked memory devices to the base die; and a processing device at least partially disposed on the base die, the base die to couple the signals of the first external interface and the signals of the second external interface with an external interface of the processing device.

[0088] Example 2: The assembly of claim 1, wherein the base die further comprises: buffer circuitry' to relay the signals of the first external interface and the second external interface.

[0089] Example 3: The assembly of claim 1, wherein the base die further comprises: serializer / deserializer circuitry to time multiplex and time demultiplex at least a portion of the signals of the first external interface and the second external interface for communication with the external interface of the processing device.

[0090] Example 4: The assembly of claim 1, wherein the signals of the first external interface are time multiplexed with the signals of the second external interface.

[0091] Example 5: The assembly of claim 1, wherein the signals of the first external interface and the signals of the second external interface are carried by disjoint sets of conductors on the base die.

[0092] Example 6: The assembly of claim 1, wherein the signals of the first external interface comprises a first set of command / address signals and a first set of data signals and the signals of the second external interface comprises a second set of command / address signals and a second set of data signals.

[0093] Example 7: The assembly of claim 6, wherein the first set of command / address signals and the second set of command / address signals are both based on a same set of command / address signals transmitted by the processing device.

[0094] Example 8: A component, comprising: a first set of stacked memory integrated circuit die and a second set of stacked memory integrated circuit die each disposed on a base integrated circuit die; and a processing device die overlapping a portion of the base integrated circuit die and coupled via the portion of the base integrated circuit die to communicate, via the base integrated circuit die, memory’ channel signals with the first set of stacked memory integrated circuit die and the second set of stacked memory integrated circuit die.

[0095] Example 9: The component of claim 8, wherein the memory channel signals include command / address signals that are common to both the first set of stacked memory’ integrated circuit die and the second set of stacked memory integrated circuit die.

[0096] Example 10: The component of claim 9, wherein the memory channel signals include a first set of data signals that are communicated with the first set of stacked memory integrated circuit die and a second set of data signals that are communicated with the second set of stacked memory integrated circuit die where the first set of data signals and the second set of data signals are disjoint sets.

[0097] Example 11: The component of claim 10, wherein the base integrated circuit die comprises time multiplex / demultiplex circuitry to interleave the first set of data signals and the second set of data signals for communication with the processing device.

[0098] Example 12: The component of claim 8, wherein the base integrated circuit die comprises buffer circuitry to relay the memory channel signals.

[0099] Example 13: The component of claim 8, wherein the memory channel signals comprise first memory’ channel signals communicated with the first set of stacked memory’ integrated circuit die and second memory channel signals communicated with the second set of stacked memory integrated circuit die.

[0100] Example 14: The component of claim 13, wherein the first memory' channel signals and the second memory channel signals to operate independently of each other.

[0101] Example 15: A method, comprising: accessing, by a processing device partially disposed on a base die, at least one of a first set of stacked memory devices disposed on the base die via signals of a first external interface that couples the first set of stacked memory devices to the base die; accessing, by the processing device, at least one of a second set of stacked memory devices disposed on the base die via signals of a second external interface that couples the second set of stacked memory devices to the base die; and coupling, by the base die, the signals of the first external interface and the signals of the second external interface with an external interface of the processing device.

[0102] Example 16: The method of claim 15. further comprising: relaying, by the base die, the signals of the first external interface and the signals of the second external interface.

[0103] Example 17: The method of claim 15, further comprising: time multiplexing, by the base die, first data signals received from the first external interface and second data signals received from the second external interface to generate first time multiplexed data signals; and transmitting the first time multiplexed data signals to the external interface of the processing device.

[0104] Example 18: The method of claim 17, further comprising: time demultiplexing, by the base die, second time multiplexed data signals received from the external interface of the processing device to generate third data signals and fourth data signals; transmitting the third data signals to the first external interface; and transmitting the fourth data signals to the second external interface.

[0105] Example 19: The method of claim 15, further comprising: receiving, by the base die and from the external interface of the processing device, command / address signals: transmitting the command / address signals to the first external interface; and transmitting the command / address signals to the second external interface.

[0106] Example 20: The method of claim 15, further comprising: receiving, by the base die and from the external interface of the processing device, first command / address signals; transmitting the first command / address signals to the first external interface; receiving, by the base die and from the external interface of the processing device, second command / address signals; and transmitting the second command / address signals to the second external interface.

[0107] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to theprecise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

CLAIMSWhat is claimed is:

1. An assembly, comprising: a base die; a first set of stacked memory devices disposed on the base die, each of the first set of stacked memory devices comprising at least a first memory array, the first memory array to be accessed via signals of a first external interface that couples the first set of stacked memory’ devices to the base die; a second set of stacked memory devices disposed on the base die, each of the second set of stacked memory devices comprising at least a second memory array’, the second memory’ array to be accessed via signals of a second external interface that couples the second set of stacked memory’ devices to the base die; and a processing device at least partially disposed on the base die, the base die to couple the signals of the first external interface and the signals of the second external interface with an external interface of the processing device.

2. The assembly of claim 1, wherein the base die further comprises: buffer circuitry to relay the signals of the first external interface and the second external interface.

3. The assembly of claim 1, wherein the base die further comprises: serializer / deserializer circuitry to time multiplex and time demultiplex at least a portion of the signals of the first external interface and the second external interface for communication with the external interface of the processing device.

4. The assembly of claim 1, wherein the signals of the first external interface are time multiplexed with the signals of the second external interface.

5. The assembly of claim 1, wherein the signals of the first external interface and the signals of the second external interface are carried by disjoint sets of conductors on the base die.

6. The assembly of claim 1, wherein the signals of the first external interface comprises a first set of command / address signals and a first set of data signals and the signals of the second external interface comprises a second set of command / address signals and a second set of data signals.

7. The assembly of claim 6, wherein the first set of command / address signals and the second set of command / address signals are both based on a same set of command / address signals transmitted by the processing device.

8. A component, comprising: a first set of stacked memory integrated circuit die and a second set of stacked memory integrated circuit die each disposed on a base integrated circuit die; and a processing device die overlapping a portion of the base integrated circuit die and coupled via the portion of the base integrated circuit die to communicate, via the base integrated circuit die, memory channel signals with the first set of stacked memory integrated circuit die and the second set of stacked memory integrated circuit die.

9. The component of claim 8, wherein the memory channel signals include command / address signals that are common to both the first set of stacked memory integrated circuit die and the second set of stacked memory integrated circuit die.

10. The component of claim 9, wherein the memory channel signals include a first set of data signals that are communicated with the first set of stacked memory integrated circuit die and a second set of data signals that are communicated with the second set of stacked memory integrated circuit die where the first set of data signals and the second set of data signals are disjoint sets.

11. The component of claim 10, wherein the base integrated circuit die comprises time multiplex / demultiplex circuitry to interleave the first set of data signals and the second set of data signals for communication with the processing device.

12. The component of claim 8, wherein the base integrated circuit die comprises buffer circuitry to relay the memory channel signals.

13. The component of claim 8, wherein the memory channel signals comprise first memory channel signals communicated with the first set of stacked memory integrated circuit die and second memory channel signals communicated with the second set of stacked memory integrated circuit die.

14. The component of claim 13, wherein the first memory channel signals and the second memory channel signals to operate independently of each other.

15. A method, comprising: accessing, by a processing device partially disposed on a base die, at least one of a first set of stacked memory devices disposed on the base die via signals of a first external interface that couples the first set of stacked memory devices to the base die; accessing, by the processing device, at least one of a second set of stacked memory devices disposed on the base die via signals of a second external interface that couples the second set of stacked memory devices to the base die; and coupling, by the base die, the signals of the first external interface and the signals of the second external interface with an external interface of the processing device.

16. The method of claim 15, further comprising: relaying, by the base die, the signals of the first external interface and the signals of the second external interface.

17. The method of claim 15, further comprising: time multiplexing, by the base die. first data signals received from the first external interface and second data signals received from the second external interface to generate first time multiplexed data signals; and transmitting the first time multiplexed data signals to the external interface of the processing device.

18. The method of claim 17, further comprising: time demultiplexing, by the base die, second time multiplexed data signals received from the external interface of the processing device to generate third data signals and fourth data signals; transmitting the third data signals to the first external interface; and transmitting the fourth data signals to the second external interface.

19. The method of claim 15, further comprising: receiving, by the base die and from the external interface of the processing device, command / address signals; transmitting the command / address signals to the first external interface: and transmitting the command / address signals to the second external interface.

20. The method of claim 15, further comprising: receiving, by the base die and from the external interface of the processing device, first command / address signals; transmitting the first command / address signals to the first external interface; receiving, by the base die and from the external interface of the processing device, second command / address signals; and transmitting the second command / address signals to the second external interface.

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