Integrated circuit packages and packaging substrates and methods for manufacturing integrated circuit packages

Abstract

An embodiment integrated circuit package is provided. The integrated circuit package comprises a package component, a packaging substrate, conductive connectors, and an underfill material. The packaging substrate comprises a plurality of bond pads, an uppermost dielectric layer encircling each of the plurality of bond pads, and microstructures disposed on a top surface of the uppermost dielectric layer. A depth of the microstructures is in a range from about 0.1 μm to about 30 μm. The conductive connectors are between the package component and the packaging substrate. The conductive connectors electrically couple the package component to the plurality of bond pads of the packaging substrate. The underfill material surrounds the conductive connectors and in physical contact with the microstructures.

Description

INTEGRATED CIRCUIT PACKAGES AND PACKAGING SUBSTRATES AND METHODS FOR MANUFACTURING INTEGRATED CIRCUIT PACKAGESBACKGROUNDRelated Application

[0001] This application claims priority to U.S. Provisional Patent Application Ser. No. 63 / 584,912, filed on Sep. 25, 2023, entitled “Underfill Process and Semiconductor Structures,” which is incorporated herein by reference in its entirety.Field of the Invention

[0002] The present disclosure relates to integrated circuit packages, packaging substrates, and methods for manufacturing integrated circuit packages. In particular, some embodiments of the present disclosure relate to integrated circuit packages with an underfill, packaging substrates for mounting a package component, and methods for manufacturing integrated circuit packages including an underfill dispensing process.Description of Related Art

[0003] Underfill is normally an epoxy or polymer material that fills gaps between a chip and its carrier or a finished package and the PCB substrate. Underfill may protect electronic products from shock, drop, and vibration and reduces the strain on fragile solder connections caused by the difference in thermal expansion between the silicon chip and carrier.

[0004] In capillary underfill applications, a precise volume of underfill material is dispensed along the side of a chip or package to flow underneath through capillary action, filling air gaps around solder balls that connect chip packages to the PCB or stacked chips in multi-chip packages.

[0005] Capillary underfill may offer advantages over molded underfill for high-performance computing devices, including CPU, GPU, and Al processors in datacenter, autonomous driving, and mobile devices with Al capability. For example, it may be easier to manage and control the capillary underfill process to prevent potential reliability issues such as voids. Also, the capillary underfill may have better underfill penetration for larger chips with more complex and large bump layouts. However, the underfill dispensing process can still be challenging.SUMMARY

[0006] According to the present disclosure, an integrated circuit package is provided. The integrated circuit package comprises a package component, a packaging substrate, conductive connectors, and an underfill material. The packaging substrate comprises a plurality of bond pads, an uppermost dielectric layer encircling each of the plurality of bond pads, and microstructures disposed on a top surface of the uppermost dielectric layer. A depth of the microstructures is in a range from about 0.1 pm to about 30 pm. The conductive connectors are between the package component and the packaging substrate. The conductive connectors electrically couple the package component to the plurality of bond pads of the packaging substrate. The underfill material surrounds the conductive connectors and in physical contact with the micro structures.

[0007] In some embodiments, the package component comprises an integrated circuit device.

[0008] In some embodiments, the microstructures are formed by applying a laser surface treatment to the uppermost dielectric layer.

[0009] In some embodiments, the microstructures comprise a plurality of line-like microstructures.

[0010] In some embodiments, an aspect ratio of the micro structures is in a range from about 0.3 to about 30.

[0011] In some embodiments, the microstructures comprise periodic microstructures.

[0012] In some embodiments, a spacing period of the periodic microstructures is in a range from about 1 pm to about 50 pm.

[0013] In some embodiments, each of the conductive connectors extends through a respective opening of the uppermost dielectric layer and physically contact a respective bond pad of the plurality of bond pads.

[0014] In some embodiments, the underfill material further comprises a plurality of fillers, and a depth of the microstructures is smaller than an average size of the plurality of fillers.

[0015] In some embodiments, some of the microstructures are disposed between a bond pad and an adjacent bond pad of the plurality of bond pads.

[0016] According to the present disclosure, a method for manufacturing an integrated circuit package is provided. The method comprises providing a packaging substrate comprises a plurality of bond pads, an uppermost dielectric layer encircling each of the plurality of bond pads, and microstructures disposed on a top surface of the uppermost dielectric layer, wherein providing the packaging substrate comprises applying a laser surface treatment to the uppermost dielectric layer to form the microstructures. The method comprises attaching a package component to thepackaging substrate. The method comprises dispensing an underfill material between the package component and the top surface of the uppermost dielectric layer, wherein the underfill material flows through the microstructures.

[0017] In some embodiments, applying the laser surface treatment comprises exposing the uppermost dielectric layer to multiple-beam interference of laser or using a phase-masks or an intensity-mask.

[0018] In some embodiments, applying the laser surface treatment comprises using a laser with a wavelength in a range from about 190 nm to about 2000 nm.

[0019] In some embodiments, applying the laser surface treatment comprises using a laser with a pulse width in a range from about 0.1 ps to about 15 ps.

[0020] In some embodiments, attaching the package component to the packaging substrate comprises attaching the package component to the packaging substrate with conductive connectors.

[0021] In some embodiments, the microstructures comprise a plurality of line-like microstructures.

[0022] In some embodiments, the plurality of line-like microstructures extend in a first direction, and dispensing the underfill material comprises moving an underfill dispenser along a second direction substantially not parallel to the first direction.

[0023] In some embodiments, the second direction is substantially perpendicular to the first direction.

[0024] In some embodiments, the package component comprises an integrated circuit device.

[0025] In some embodiments, a depth of the microstructures is in a range from about 0.1 pm to about 30 pm.

[0026] In some embodiments, an aspect ratio of the micro structures is in a range from about 0.3 to about 30.

[0027] In some embodiments, the microstructures comprise periodic microstructures.

[0028] In some embodiments, a spacing period of the periodic microstructures is in a range from about 1 pm to about 50 pm.

[0029] According to the present disclosure, a packaging substrate for mounting a first package component in a first bonding region of the packaging substrate is provided. The packaging substrate comprises one or more metallization layers, a first plurality of bond pads, an uppermost dielectric layer, and first microstructures. The one or more metallization layers each comprises adielectric layer and a conductive layer. The first plurality of bond pads are disposed in the first bonding region. The first plurality of bond pads are disposed over and electrically connected to the one or more metallization layers. The uppermost dielectric layer is disposed over the one or more metallization layers and encircling each of the first plurality of bond pads. The uppermost dielectric layer has a bottom surface facing the one or more metallization layer and a top surface opposite to the bottom surface. The first microstructures are disposed in the first bonding region and on the top surface of the uppermost dielectric layer. A depth of the first microstructures is in a range from about 0.1 pm to about 30 pm.

[0030] In some embodiments, the first microstructures are formed by applying a laser surface treatment to the uppermost dielectric layer.

[0031] In some embodiments, the first microstructures comprise a plurality of line-like microstructures.

[0032] In some embodiments, an aspect ratio of the first microstructures is in a range from about 0.3 to about 30.

[0033] In some embodiments, the first microstructures comprise first periodic microstructures.

[0034] In some embodiments, a spacing period of the first periodic microstructures is in a range from about 1 pm to about 50 pm.

[0035] In some embodiments, the packaging substrate further comprises a second plurality of bond pads and second microstructures. The second plurality of bond pads are disposed in a second bonding region of the packaging substrate. The second plurality of bond pads are disposed over and electrically connected to the one or more metallization layers. The uppermost dielectric layer encircles each of the second plurality of bond pads. The second micro structures disposed are disposed in the second bonding region and on the top surface of the uppermost dielectric layer.

[0036] In some embodiments, a pitch of the second plurality of bond pads is different from a pitch of the first plurality of bond pads.

[0037] In some embodiments, the first microstructures and the second microstructures are different in at least one of depth, aspect ratio, spacing period, and shape.

[0038] In some embodiments, the first microstructures comprise first periodic microstructures, and the second microstructures comprise second periodic microstructures.

[0039] In some embodiments, a spacing period of the first periodic microstructures is substantially equal to a spacing period of the second periodic microstructures.BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG. 1A is a schematic diagram illustrating a packaging substrate according to one embodiment of the present disclosure.

[0041] FIG. IB is a schematic top view of the packaging substrate shown in FIG. 1A according to one embodiment of the present disclosure.

[0042] FIG. 1C is a picture of an exemplified microstructures according to one embodiment of the present disclosure.

[0043] FIG. ID is a schematic diagram illustrating the exemplified microstructures shown in FIG. 1C according to one embodiment of the present disclosure.

[0044] FIGS. 2 to 4B are schematic diagrams illustrating intermediate stages in the manufacture of an integrated circuit package according to one embodiment of the present disclosure.

[0045] FIG. 5 is a schematic top view of a packaging substrate according to another embodiment of the present disclosure.

[0046] FIG. 6 is a schematic top view of a packaging substrate according to another embodiment of the present disclosure.

[0047] FIG. 7 is a picture of an exemplified microstructures according to another embodiment of the present disclosure.DETAILED DESCRIPTION OF EMBODIMENTS

[0048] The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is used in conjunction with a detailed description of certain specific embodiments of the technology. Certain terms may even be emphasized below; however, any terminology intended to be interpreted in any restricted manner will be specifically defined as such in this Detailed Description section. Components and achievement of a semiconductor structure or a device, according to the present disclosure may be illustrated in the following drawings and embodiments. However, the size and shape shown on drawings for the semiconductor structure(s) or the device(s) do not limit the features of the present disclosure.

[0049] The phrase “on” used in this application can mean directly on or indirectly on with intervening elements or layers. The spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0050] FIG. 1A is a schematic diagram illustrating a packaging substrate according to one embodiment of the present disclosure. FIG. IB is a schematic top view of the packaging substrate shown in FIG. 1A.

[0051] Referring to FIGS. 1A to IB, a packaging substrate 200 is provided. The packaging substrate 200 comprises a plurality of first bond pads 210a, an uppermost dielectric layer 220, and first microstructures 230a. The packaging substrate 200 may be a PCB substrate, an ABF substrate, a BGA substrate, a semiconductor substrate, etc. In some embodiments, the packaging substrate 200 may be used for mounting a package component (e.g., the first package component 100 shown in FIG. 2) in a first bonding region BRI of the packaging substrate 200.

[0052] In the embodiment shown in FIG. 1A, the packaging substrate 200 includes a core substrate 250. The core substrate 250 may include a material such as Ajinomoto build-up film (ABF), a pre-impregnated composite fiber (prepreg) material, an epoxy, a molding compound, an epoxy molding compound, fiberglass -reinforced resin materials, printed circuit board (PCB) materials, silica filler, polymer materials, polyimide materials, paper, glass fiber, non-woven glass fabric, glass, ceramic, other laminates, the like, or combinations thereof. In some embodiments, the core substrate 250 may be a double-sided copper-clad laminate (CCE) substrate or the like. Insome other embodiments, the core substrate may be multilayered and may be formed by alternately laminating multiple dielectric layers and multiple conductive layers.

[0053] The packaging substrate 200 may further comprise one or more metallization layers 240. The one or more metallization layers 240 may be formed on each side of the core substrate 250. As shown in FIG. 1A, metallization layers 240a and 240b are formed on the front side of the core 250. The packaging substrate 200 may further comprise through vias 260 extending through the core substrate 250 and electrically connecting the front side to the backside of the core substrate 250. Each of the one or more metallization layers 240 comprises a dielectric layer and a patterned conductive layer. For example, the metallization layer 240a comprises a dielectric layer 242a and a patterned conductive layer 244a, and the metallization layer 240b comprises a dielectric layer 242b and a patterned conductive layer 244b. The patterned conductive layers may be electrically connected by conductive vias. The patterned conductive layers including the patterned conductive layers 244a and 244b, the conductive vias, and the through vias 260 may provide electrical routing and interconnection. In some embodiments, the patterned conductive layers, the conductive vias, and the through vias 260 may include dummy features for increasing thermal conductivity. In some embodiments, the dielectric layers 242a and 242b may be build-up layers. The patterned conductive layers 244a and 244b and / or the through vias 260 may comprise one or more layers of copper, nickel, aluminum, other conductive materials, the like, or a combination thereof. The dielectric layers 242a and 242b may include materials such as a build-up material, ABF, a prepreg material, a laminate material, another material similar to those described above for the core substrate 250, the like, or combinations thereof. In some other embodiments, a packaging substrate may comprise more or fewer metallization layers than the packaging substrate 200 shown in FIG. 1A. In some other embodiments, a core substrate may be omitted.

[0054] As shown in FIG. 1A, the first plurality of bond pads 210a are disposed over and electrically connected the one or more metallization layers 240, wherein at least one of the first plurality of bond pads 210a is electrically connected to at least one of the metallization layers 240. The first plurality of bond pads 210a may be disposed in the first bonding region BRI, such that a package component can be electrically connected to the metallization layers 240 through the first plurality of bond pads 210a when it is properly mounted on the packaging substrate 200 in the first bonding region BRI. The first plurality of bond pads 210a may comprise conductive material, e.g., nickel, gold, the like, or a combination thereof. In some embodiments, the first plurality of bond pads 210a may have a pitch Pl from about 100 pm or smaller to about 600 pm or larger than 600 pm.

[0055] The uppermost dielectric layer 220 is disposed over the one or more metallization layers 240. The uppermost dielectric layer 220 may comprise a solder resist material, a PBO material, a nitride, an oxide, a polyimide, a low-temp polyimide, combinations thereof, or the like. The uppermost dielectric layer 220 encircles each of the first plurality of bond pads 210a. For example, the uppermost dielectric layer 220 may be patterned using a suitable photolithographic and etching process to form openings 220o exposing portions of the first plurality of bond pads 210a. In some embodiments, portions of an uppermost metallization layer that are exposed from a respective opening may become the first plurality of bond pads.

[0056] As shown in FIG. 1A, in some embodiments, conductive connectors 300 may be formed on the first plurality of bond pads 210a. The conductive connectors 300 are electrically coupled to the one or more metallization layers 240 through the first plurality of bond pads 210a. The conductive connectors 300 may comprise ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel- electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors 300 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. For simplicity, FIG. IB only shows thirty-six bond pads 210a. However, the numbers of the first plurality of bond pads 210a and the conductive connectors 300 are not limited thereto. In some embodiments, about 40,000 to about 100,000, about 150,000, about 200,000 or more conductive connectors may be disposed on a packaging substrate.

[0057] As shown in FIG. 1 A and IB, the first microstructures 230a is disposed on the top surface 220t of the uppermost dielectric layer 220. Specifically, the uppermost dielectric layer 220 has a bottom surface 220b and a top surface 220t. The bottom surface 220b is facing the metallization layer 240, and the top surface 220t is opposite to the bottom surface 220b. In some embodiments, the first microstructures 230a is disposed in the first bonding region BRI of the packaging substrate 200. The first bonding region BRI may be a predetermined region in which a package component can be mounted on and in which an underfill material is to be dispensed. In some embodiments, the first microstructures 230a may be formed only in the first bonding region BRI. In some embodiments, the first microstructures 230a may be distributed substantially throughout the entire first bonding region BRI. As shown in FIG. 1A, at least some of the first microstructures 230a are disposed between a bond pad and an adjacent bond pad of the plurality of bond pads 210a. The first microstructures 230a may include microstructures of dot-shape, line-shape, grid-shape, crossshape, or irregular- shape.

[0058] In some embodiments, a laser surface treatment may be applied to the uppermost dielectric layer 220 to form the first microstructures 230a. For example, the laser surface treatment may include using modulated laser(s) LR to scan within a specific region (e.g., the first bonding region BRI) of the uppermost dielectric layer 220, such that the top surface 220t of the uppermost dielectric layer 220 can be reshaped, e.g., through ablation of the surface material, to form the first microstructures 230a. Continuous or pulse laser beam may be used. Usage of a short pulse laser (e.g., nanosecond, picosecond, or femtosecond pulse) may reduce the average power applied to the substrate. In some embodiments, a laser with a pulse width in a range from about 0.1 ps to about 15 ps may be used.

[0059] In some embodiments, a laser surface treatment may include exposing the uppermost dielectric layer 220 to multiple-beam interference of laser. For example, interference of 2 or 4 or more laser beams may be used. In some embodiments, a laser surface treatment may include exposing the uppermost dielectric layer 220 to a light source using phase-mask(s), such as diffractive optical element (DOE) or holographic mask, with a laser. In some embodiments, a laser surface treatment may include exposing the uppermost dielectric layer 220 to a light source using intensity-mask(s) (amplitude-mask(s)) with a laser. A spacing period of the microstructures may be controlled by adjusting the interference fringes. A laser with a wavelength in a range from about 190 nm to about 2000 nm may be used. In some embodiments, a laser with a wavelength in a range from about 240 nm to about 370 nm, from about 490 nm to about 550 nm, or from about 980 nm to about 1100 nm may be used. In some embodiments, by using laser with a wavelength from about 490 nm to about 550 nm, microstructures with desired quality may be formed, while defects and / or peeling of the uppermost dielectric layer 220 may be avoided. For example, laser(s) with a pulse width of about 15 ps or lower (e.g., about 2 ps or from about 0.1 ps to about 1 ps), a wavelength from about 490 nm to about 550 nm, a power from about lOOmW to about 2W, a repetition rate from about 50kHz to about 1MHz may be used. These values are merely examples and are not intended to be limiting. In some embodiments, Laser-Induced Periodic Surface Structures (LIPSS) may be formed using femtosecond lasers (e.g., laser with pulse widths less than 1 picosecond) with wavelengths, for example, from about 240 nm to about 280 nm. These values are merely examples and are not intended to be limiting. In some other embodiments, a laser surface treatment may include a point-to-point writing using a single beam laser.

[0060] As shown in FIG. 1A and IB, the microstructures are formed before one or more respective package component(s) are mounted onto the packaging substrate. The microstructures formed through the methods discussed herein may remain substantially unchanged during the subsequent processes. The distribution of the microstructures may be controlled, e.g., by scanningregion and / or power of the modulated Laser. Also, microstructures of desired shape and distribution can be formed through control of conditions and parameters of the modulated Laser (e.g., wavelength, fringe spacing, pulse width, power, angle, the like, or combinations thereof).

[0061] FIG. 1C is a picture of an exemplified first microstructures 230a according to one embodiment of the present disclosure, and FIG. ID is a schematic diagram illustrating the exemplified first microstructures 230a shown in FIG. 1C. In some embodiments, a depth D of the first microstructures 230a may be in a range from about 0.1 pm to about 30 pm, or from about 0.5 pm to about 10 pm. An aspect ratio of the first microstructures 230a, which is determined by ratio of a depth D to a width W of the first microstructures 230a, may be in a range from about 0.3 to about 30. In some embodiments, a width W of the first microstructures 230a may be in a range from about 1 pm to about 10 pm. As shown in FIGS. 1C and ID, the first microstructures 230a may comprise first periodic microstructures 230ap. Periodic microstructures are microstructures that include a unit structure which substantially repeats itself over an equal space interval. In some embodiments, the first periodic microstructures 230ap may include a unit structure of dot-shape, line-shape, grid-shape, cross-shape, or irregular shape. A spacing period SP of the first periodic microstructures 230ap may be in a range from about 1 pm to about 50 pm, or in some embodiments, in a range from about 2 pm to about 25 pm, or from about 5 pm to about 25 pm. As will be further described below with respect to FIG. 3, the disposition of the first microstructures 230a may result in a decrease in the time required to complete the subsequent underfill filling process. The disposition of the first microstructures 230a with one or more of the aforementioned characteristics may achieve a more desirable outcome.

[0062] In some embodiments, the first microstructures 230a may comprise a plurality of linelike microstructures ML For example, as shown in FIGS. 1C and ID, substantially straight trench structures and / or substantially straight ridge structures may be formed. The plurality of line-like microstructures Ml may extend in the same direction, for example, in a first direction DI. In some embodiments, the plurality of line-like microstructures Ml extend continuously over a considerable length in the first bonding region BRI. In some embodiments, each of the line-like microstructures Ml may have a length from about 2 pm or about 10 pm to about 100 mm. These values are merely examples and are not intended to be limiting. This configuration of the first microstructures 230a may result in a decrease in the time required for the subsequent underfill filling process and may further prevent formation of bubbles and / or voids. However, the present disclosure is not limited thereto. In some other embodiments, other types of structures, such as grid structures (e.g., the structures shown in FIG. 7), similar spaced structures, or irregular shaped structures having similar depth and / or similar spacing may be formed.

[0063] As shown in FIG. 2, a package component 100 is attached to the packaging substrate 200. The package component 100 may include one or more integrated circuit devices 102, which may include devices designed for an intended purpose such as a memory chip (e.g., a DRAM chip, a stacked memory chip, a high-bandwidth memory (HBM) chip, etc.), a logic chip, a central processing unit (CPU) chip, an VO chip, a system-on-a-chip (SoC), a chip on a wafer (CoW), an integrated fan-out structure (InFO), a package, the like, or a combination thereof. The package component 100 may include electrical circuit element(s), such as transistors, capacitors, inductors, resistors, metallization layers, conductive connectors, and the like, therein, as desired for a particular functionality. In some embodiments, the package component 100 may include more than one of the same type of device or may include different devices. In some embodiments, the package component may include a packaged device comprising a plurality of integrated circuit devices attached to an interposer. As shown in FIG. 2, the package component 100 may comprise conductive pads 110, e.g., under bump metallurgy (UBM), and a passivation layer 120 between adjacent conductive pads 110. In some embodiments, multiple package components with the same or different functions may be attached to the packaging substrate in a respective bonding region (e.g., the second bonding region BR2 or the third bonding region BR3 shown in FIGS. 5 and 6) of the packaging substrate.

[0064] The package component 100 may be attached to the packaging substrate 200 with conductive connectors 300. The package component 100 may be placed on the conductive connectors 300 on the packaging substrate 200. The conductive connectors 300 may provide electrical connection between the package component 100 and the one or more metallization layers 240 of the packaging substrate 200. The package component 100 may be placed on the conductive connectors 300 using a placement process such as a pick-and-place process, or the like. The package component 100 may be placed such that conductive pads 110 of the package component 100 are aligned with the conductive connectors 300, and the conductive connectors 300 bond the conductive pads 110 and the first bond pads 210a. In some other embodiments, the package component 100 may be attached to the packaging substrate 200 by face-to-face bonds. For example, direct bonding, metal bonding, or the like may be used to attach the package component 100 without the use of solder.

[0065] As shown in FIG. 3, an underfill material 400 is dispensed into the space (gaps) between the package component 100 and the top surface 220t of the uppermost dielectric layer 220. The underfill material 400 may be any acceptable material, such as a polymer, epoxy, molding underfill, or the like. The underfill material 400 may flow by capillary action. Specifically, the underfillmaterial 400 may flow through the microstructures 230a and fill the gap(s) between the package component 100 and the uppermost dielectric layer 220.

[0066] In an embodiment where the first microstructures comprise a plurality of line-like microstructures Ml extending in a first direction DI (e.g., the first microstructures 230a as shown in FIGS. 1C and ID), an underfill dispenser 50 may move along a second direction D2, wherein the second direction D2 is substantially not parallel to the first direction DI. This may result in a further reduction in the time required for underfill dispensing, since the underfill material 400 may flow faster in the first direction DI. In some embodiments, an underfill dispenser 50 may move along a second direction D2 substantially perpendicular to the first direction DI. The underfill material 400 may then be cured in a curing process. The underfill material 400 may be solidified after the curing process. In some embodiments, the curing process is performed using a thermal cure process. In some embodiments, Ultra-Violet (UV) curing may be used.

[0067] In some embodiments, the first bonding region BRI may have a size (e.g., a length or a width of the bonding region) from about 10 mm to larger than about 30 mm (e.g., about 50 mm or larger). In some embodiments, an overall underfill dispensing area including a plurality of adjacent bonding regions, each of which may be similar to the first bonding region, may have a size of about 50 mm or larger (for example, about 150 mm or more). In such circumstances, a considerable amount of time may be required to complete the dispensing process. In some instances, an underfill material may be heated before dispensing for better flowability. However, the heated underfill material may be partially cured and hardened during the process. Therefore, underfill dispensing process applied to a large area may be challenging. In the present disclosure, by forming the microstructures (e.g., the first microstructures) described above on the packaging substrate, the flowability of the underfill material in the bonding region may be increased. The processing time may be reduced, and / or usage of an underfill material with a lower temperature may be possible. As such, underfill material can be properly dispensed throughout a large overall underfill dispensing area. This may also decrease void formation in the underfill material. Furthermore, microstructures with specific configuration, e.g., line-shaped structures, may also facilitate control of flow direction of the underfill material.

[0068] As shown in FIG. 4A, an integrated circuit package 10 is formed. FIG. 4A is a schematic diagram illustrating an integrated circuit package according to one embodiment of the present disclosure, and FIG. 4B is a schematic partial enlarged view of the integrated circuit package shown in FIG. 4A. Referring to FIGS. 4A and 4B, the integrated circuit package 10 comprises a package component 100, a packaging substrate 200, conductive connectors 300, and an underfill material 400. The integrated circuit package 10 may be a FC BGA package, a 3D IC package, a2.5D IC package, a flip-chip chip-scale package (FCCSP), a flip-chip system in package (FCSiP), a fan-out wafer level package (FOWLP), a multi-chip IC package, a fan-out chip on substrate package (FOCoS), or the like.

[0069] The packaging substrate 200 may comprise a plurality of bond pads 210a, an uppermost dielectric layer 220, and first microstructures 230a. The uppermost dielectric layer 220 encircles each of the plurality of bond pads 210a. The first microstructures 230a are disposed on a top surface 220t of the uppermost dielectric layer 220. As shown in FIG. 4B, in some embodiments, the uppermost dielectric layer 220 may have a thickness T1 in a range from about from about 10 pm to about 50 pm, e.g., about 20 pm or under about 20 pm. Details of the plurality of bond pads 210a, the uppermost dielectric layer 220, the first microstructures 230a, and other details of the packaging substrate 200 may be substantially similar to that described above with respect to FIGS. 1A to ID, and related description is omitted for brevity.

[0070] The package component 100 may include one or more integrated circuit device 102. In some embodiments, the package component may include a packaged device comprising a plurality of integrated circuit devices attached to an interposer. Details of the package component 100 and the integrated circuit device 102 may be substantially similar to that described above with respect to FIG. 2, and related description is omitted for brevity.

[0071] The conductive connectors 300 is disposed between the package component 100 and the packaging substrate 200. The conductive connectors 300 are electrically coupling the package component 100 to the plurality of bond pads 210a of the packaging substrate 200. For example, the conductive connectors 300 may bond the conductive pads 110 of the package component 100 and the first bond pads 210a. As shown in FIGS. 4A and 4B, each of the conductive connectors 300 extends through a respective opening 220o of the uppermost dielectric layer 220 and physically contact a respective bond pad of the plurality of bond pads 210a. Other details of the conductive connectors 300 may be substantially similar to that described above with respect to FIG. 1A, and related description is omitted for brevity.

[0072] The underfill material 400 surrounds the conductive connectors 300. At least a portion of the underfill material 400 is disposed between the package component 100 and the packaging substrate 200. In some embodiments, a thickness T2 of the underfill material 400 may be from about 20 pm to about 150 pm. As described above with respect to FIG. 3, the underfill material 400 flows along the first microstructures 230a and fills the gap between the package component 100 and the uppermost dielectric layer 220. As a result, the underfill material 400 is in physical contact with the first microstructures 230a.

[0073] The underfill material 400 may further comprises a plurality of fillers 410. The fillers 410 may comprise silicon dioxide. The size of the fillers 410 may be, for example, from about 2 pm or smaller (e.g., about 1 pm) to about 3 pm or larger (e.g., about 5 pm). In some embodiments, a depth of the first microstructures 230a may be formed to be smaller than an average size (a D50 size) of the plurality of fillers 410. This may reduce the possibility of fillers 410 being trapped in the valleys of the microstructures 230a, which may result in formation of voids in the underfill. Other details and formation methods of the underfill material 400 may be substantially similar to that described above with respect to FIG. 3, and related description is omitted for brevity.

[0074] FIG. 5 is a schematic top view of a packaging substrate according to another embodiment of the present disclosure. The packaging substrate 200A shown in FIG. 5 may be substantially similar to the packaging substrate 200 described above with respect to FIGS. 1A to ID, where like reference numerals indicate like elements.

[0075] Referring to FIG. 5, the packaging substrate 200A further comprises a second plurality of bond pads 210b. The second plurality of bond pads 210b may be similar to the first plurality of bond pads 210a and may be disposed in the same metallization layer as the first plurality of bond pads 210a. The uppermost dielectric layer 220 encircles each of the second plurality of bond pads 210b. The second plurality of bond pads 210b may be disposed over and electrically connected the one or more metallization layers, wherein at least one of the second plurality of bond pads 210b is electrically connected to at least one of the metallization layers.

[0076] In the embodiment shown in FIG. 5, the packaging substrate 200A has more than one bonding region (e.g., a first bonding region BRI, a second bonding region BR2, and a third bonding region BR3). One or more package components may be mounted on the packaging substrate 200A in each one of the bonding regions. Details of the package components may be similar to that of the first package component 100 described above with respect to FIG. 2. The second plurality of bond pads 210b may be disposed in the second bonding region BR2 of the packaging substrate 200A, such that a package component can be electrically connected to the metallization layers through the second plurality of bond pads 210b when it is properly mounted on the packaging substrate 200A in the second bonding region BR2.

[0077] The second plurality of bond pads 210b may have a pitch P2 from about 100 pm or smaller to about 600 pm or larger than 600 pm. In the embodiment shown in FIG. 5, a pitch P2 of the second plurality of bond pads 210b is different from a pitch Pl of the first plurality of bond pads 210a. The pitch P2 of the second plurality of bond pads 210b may be larger than the pitch Pl of the first plurality of bond pads 210a. However, the present disclosure is not limited thereto. In some other embodiments, a pitch P2 of the second plurality of bond pads 210b may be substantiallyequal to or smaller than a pitch Pl of the first plurality of bond pads 210a. The material and formation method of the second plurality of bond pads 210b may be substantially similar to those of the first plurality of bond pads 210a.

[0078] Referring to FIG. 5, the packaging substrate 200A may further comprise second microstructures 230b. The second microstructures 230b may be disposed on the top surface 220t of the uppermost dielectric layer 220. As shown in FIG. 5, the second microstructures 230b may be disposed in the second bonding region BR2 of the packaging substrate 200A. The formation method(s) of the second microstructures 230b may be substantially similar to those of the first microstructures 230a. The second microstructures 230b may have a configuration similar to that described above with respect to FIGS. 1C and ID. Specifically, a depth of the second microstructures 230b may be in a range from 0.1 pm to about 30 pm, or from about 0.5 pm to about 10 pm. In some embodiments, the second microstructures 230b may comprise second periodic microstructures similar to the first periodic microstructures 230ap described above. In some embodiments, the second microstructures 230b may comprise a plurality of line-like microstructures. However, the present disclosure is not limited thereto. With the disposition of the second microstructures 230b, the flowability of the underfill material in the second bonding region BR2 may be increased, which renders the underfill dispensing process in a large overall underfill dispensing area possible and decreases void formation in the underfill material. The processing time may also be reduced.

[0079] As shown in FIG. 5, the packaging substrate 200A may further comprise a third plurality of bond pads 210c similar to the second plurality of bond pads 210b. The third plurality of bond pads 210c may be disposed in the third bonding region BR3 for electrical connection of the package component(s) mounted in the third bonding region BR3. The packaging substrate 200A may further comprise third microstructures 230c similar to the second microstructures 230b. The third microstructures 230c may be disposed in the third bonding region BR3 of the packaging substrate 200A for increasing flowability of the underfill material in the third bonding region BR3. For simplicity, FIG. 5 only shows thirty-six bond pads 210a, nine bond pads 210b, and nine bond pads 210c. However, the numbers of the first plurality of bond pads 210a, the second plurality of bond pads 210b, and the third plurality of bond pads 210c are not limited thereto.

[0080] In the embodiment shown in FIG. 5, the first microstructures 230a, the second microstructures 230b, and the third microstructures 230c may have substantially the same configurations. For example, the first microstructures 230a, the second microstructures 230b, and the third microstructures 230c may have substantially the same shape, substantially the same depth, aspect ratio, and spacing period. In some embodiments, the first microstructures 230a, the secondmicrostructures 230b, and the third microstructures 230c may each includes a plurality of line-like microstructures similar to that described above with respect to FIGS. 1C and ID. In some embodiments, at least some of the line-like microstructures extend continuously across the bonding region. In some other embodiments, more or less bonding regions substantially similar to the first bonding region BRI, the second bonding region BR2, and the third bonding region BR3 may be disposed on a packaging substrate.

[0081] FIG. 6 is a schematic top view of a packaging substrate according to another embodiment of the present disclosure. The packaging substrate 200B shown in FIG. 6 may be substantially similar to the packaging substrate 200A described above with respect to FIG. 5, where like reference numerals indicate like elements. In the embodiment shown in FIG. 6, the first microstructures 230a’ and the second microstructures 230b’ may be different in at least one of depth, aspect ratio, spacing period, and shape. For example, the second microstructures 230b’ may have a larger or smaller width and / or larger or smaller spacing period than the first microstructures 230a’. However, the present disclosure is not limited thereto. The difference in the configuration of the microstructures can be achieved by altering the conditions and parameters of the modulated Laser.

[0082] FIG. 7 is a picture of another exemplified microstructures according to one embodiment of the present disclosure. As shown in FIG. 7, the first microstructures 230a” may comprise a plurality of grid structures. The grid structures may be seen as a crossing pattern of two trench structures extend in different directions or a crossing pattern of two ridge structures extend in different directions. In the embodiment shown in FIG. 7, the first microstructures 230a” may comprise first periodic microstructures 230ap”. The first periodic microstructures 230ap” may include a unit structure of grid-shape. Details and formation methods of the first microstructures 230a” may be substantially similar to the first microstructures 230a described above with respect to FIGS. 1C to ID, and related description is omitted for brevity.

[0083] The foregoing description of embodiments is provided to enable any person skilled in the art to make and use the subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the novel principles and subject matter disclosed herein may be applied to other embodiments without the use of the innovative faculty. The claimed subject matter set forth in the claims is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. It is contemplated that additional embodiments are within the spirit and true scope of the disclosed subject matter. Thus, it is intended that the present invention covers modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. An integrated circuit package comprising: a package component; a packaging substrate comprising a plurality of bond pads, an uppermost dielectric layer encircling each of the plurality of bond pads, and microstructures disposed on a top surface of the uppermost dielectric layer, a depth of the microstructures being in a range from about 0.1 pm to about 30 pm; conductive connectors between the package component and the packaging substrate and electrically coupling the package component to the plurality of bond pads of the packaging substrate; and an underfill material surrounding the conductive connectors and in physical contact with the microstructures.

2. The integrated circuit package of claim 1, wherein the package component comprises an integrated circuit device.

3. The integrated circuit package of claim 1, wherein the microstructures are formed by applying a laser surface treatment to the uppermost dielectric layer.

4. The integrated circuit package of claim 1, wherein the microstructures comprise a plurality of line-like microstructures.

5. The integrated circuit package of claim 1, wherein an aspect ratio of the microstructures is in a range from about 0.3 to about 30.

6. The integrated circuit package of claim 1, wherein the microstructures comprise periodic microstructures.

7. The integrated circuit package of claim 6, wherein a spacing period of the periodic microstructures is in a range from about 1 pm to about 50 pm.

8. The integrated circuit package of claim 1, wherein each of the conductive connectors extends through a respective opening of the uppermost dielectric layer and physically contact a respective bond pad of the plurality of bond pads.

9. The integrated circuit package of claim 1, wherein the underfill material further comprises a plurality of fillers, and a depth of the microstructures is smaller than an average size of the plurality of fillers.

10. The integrated circuit package of claim 1, wherein some of the microstructures are disposed between a bond pad and an adjacent bond pad of the plurality of bond pads.

11. A method for manufacturing an integrated circuit package comprising: providing a packaging substrate comprising a plurality of bond pads, an uppermost dielectric layer encircling each of the plurality of bond pads, and microstructures disposed on a top surface of the uppermost dielectric layer, wherein providing the packaging substrate comprises applying a laser surface treatment to the uppermost dielectric layer to form the microstructures; attaching a package component to the packaging substrate; dispensing an underfill material between the package component and the top surface of the uppermost dielectric layer, wherein the underfill material flows through the microstructures.

12. The method of claim 11, wherein applying the laser surface treatment comprises exposing the uppermost dielectric layer to multiple-beam interference of laser or using a phase-masks or an intensity-mask.

13. The method of claim 11, wherein applying the laser surface treatment comprises using a laser with a wavelength in a range from about 190 nm to about 2000 nm.

14. The method of claim 11, wherein applying the laser surface treatment comprises using a laser with a pulse width in a range from about 0.1 ps to about 15 ps.

15. The method of claim 11, wherein attaching the package component to the packaging substrate comprises attaching the package component to the packaging substrate with conductive connectors.

16. The method of claim 11, wherein the microstructures comprise a plurality of line-like microstructures.

17. The method of claim 16, wherein the plurality of line-like microstructures extend in a first direction, and dispensing the underfill material comprises moving an underfill dispenser along a second direction substantially not parallel to the first direction.

18. The method of claim 17, wherein the second direction is substantially perpendicular to the first direction.

19. The method of claim 11, wherein the package component comprises an integrated circuit device.

20. The method of claim 11, wherein a depth of the microstructures is in a range from about 0.1 pm to about 30 pm.

21. The method of claim 11, wherein an aspect ratio of the microstructures is in a range from about 0.3 to about 30.

22. The method of claim 11, wherein the microstructures comprise periodic microstructures.

23. The method of claim 22, wherein a spacing period of the periodic microstructures is in a range from about 1 pm to about 50 pm.

24. A packaging substrate for mounting a first package component in a first bonding region of the packaging substrate, the packaging substrate comprising: one or more metallization layers each comprising a dielectric layer and a conductive layer; a first plurality of bond pads in the first bonding region, the first plurality of bond pads disposed over and electrically connected to the one or more metallization layers; an uppermost dielectric layer disposed over the one or more metallization layers and encircling each of the first plurality of bond pads, the uppermost dielectric layer having a bottom surface facing the one or more metallization layer and a top surface opposite to the bottom surface; andfirst microstructures disposed in the first bonding region and on the top surface of the uppermost dielectric layer, a depth of the first microstructures being in a range from about 0.1 pm to about 30 pm.

25. The packaging substrate of claim 24, wherein the first microstructures are formed by applying a laser surface treatment to the uppermost dielectric layer.

26. The packaging substrate of claim 24, wherein the first microstructures comprise a plurality of line-like microstructures.

27. The packaging substrate of claim 24, wherein an aspect ratio of the first microstructures is in a range from about 0.3 to about 30.

28. The packaging substrate of claim 24, wherein the first microstructures comprise first periodic microstructures.

29. The packaging substrate of claim 28, wherein a spacing period of the first periodic microstructures is in a range from about 1 pm to about 50 pm.

30. The packaging substrate of claim 24 further comprising: a second plurality of bond pads in a second bonding region of the packaging substrate, the second plurality of bond pads disposed over and electrically connected to the one or more metallization layers, the uppermost dielectric layer encircling each of the second plurality of bond pads; and second microstructures disposed in the second bonding region and on the top surface of the uppermost dielectric layer.

31. The packaging substrate of claim 30, wherein a pitch of the second plurality of bond pads is different from a pitch of the first plurality of bond pads.

32. The packaging substrate of claim 30, wherein the first microstructures and the second microstructures are different in at least one of depth, aspect ratio, spacing period, and shape.

33. The packaging substrate of claim 30, wherein the first microstructures comprise first periodic microstructures, and the second microstructures comprise second periodic microstructures.

34. The packaging substrate of claim 33, wherein a spacing period of the first periodic microstructures is substantially equal to a spacing period of the second periodic microstructures.

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