Level shifter circuit

Abstract

A level shifter circuit 1 comprises first to fourth P-type transistors, first and second N-type transistors, and a pull-up circuit 30. The first N-type transistor and the first P-type transistor are provided between an input node and an output node, and the second P-type transistor is provided between a first power supply and the output node. The second N-type transistor and the third P-type transistor are provided between an inverting input node and an inverting output node, and the fourth P-type transistor is provided between the first power supply and the inverting output node. The pull-up circuit 30 is configured to pull up the second node to a third power supply when the first node goes from high level to low level, and to pull up the first node to the third power supply when the second node goes from high level to low level.

Description

Level Shift Circuit

[0001] The present invention relates to a level shift circuit that converts the voltage of a signal to a required level when the signal is transmitted between circuits supplied with different power supply voltages.

[0002] A level shift circuit is used, for example, in an interface section that transmits a signal from a circuit that operates at a relatively low voltage inside an LSI to a circuit that operates at a relatively high voltage outside the LSI, and converts the voltage of the signal.

[0003] In recent years, as transistors have become smaller, the voltage stress (withstand voltage) that transistors can tolerate has been decreasing. Against this background, a level shift circuit that performs voltage conversion within a predetermined withstand voltage range has been disclosed in prior art documents.

[0004] The level shift circuit in Patent Document 1 is configured to boost the low-level voltage in addition to boosting the high-level voltage. By lowering the voltage between the low and high levels in this way, the voltage applied between the terminals of the transistor (for example, between the gate and source, or between the source and drain) is lowered, and voltage stress on the transistor is alleviated.

[0005] U.S. Patent No. 7,151,391

[0006] However, in the case of the configuration shown in FIG. 1 of Patent Document 1, there is a problem that the operation of the level shift circuit cannot keep up with the lower operating voltage required to meet the demand for lower power consumption and / or faster circuit operation to meet the demand for higher functionality.

[0007] The present disclosure aims to solve the above problems.

[0008] A level shift circuit according to one aspect of the present disclosure includes an input node receiving an input signal that transitions between a first power supply and a second power supply having a potential lower than that of the first power supply, a first N-type transistor provided between the input node and a first node and having a gate connected to the first power supply, a first P-type transistor provided between the first node and an output node and having a gate connected to the first power supply, a second P-type transistor provided between the output node and the first power supply and having a gate connected to the first node, an inverting input node receiving an inverted input signal obtained by inverting the input signal, and a second N-type transistor provided between the inverting input node and a second node and having a gate connected to the first power supply. a third P-type transistor provided between the second node and a third node, the gate of which is connected to the first power supply; a fourth P-type transistor provided between the third node and the first power supply, the gate of which is connected to the second node; and a pull-up circuit provided between the first node and the second node, the pull-up circuit comprising: a first pull-up circuit that pulls up the second node to a third power supply having a higher potential than the first power supply when the first node transitions from a high level to a low level; and a second pull-up circuit that pulls up the first node to the third power supply when the second node transitions from a high level to a low level.

[0009] In the level shift circuit of this aspect, the first pull-up circuit operates to pull up the second node to the third power supply when the first node transitions from high to low, thereby quickly decreasing the voltage at the output node. This prevents delays in the output signal output to the output node. Similarly, the second pull-up circuit operates to pull up the first node to the third power supply when the second node transitions from high to low, thereby quickly increasing the voltage at the output node. This prevents delays in the output signal output to the output node. This allows for faster circuit operation than when no pull-up circuit is provided.

[0010] Furthermore, the level shift circuit of this embodiment is configured with two power supplies, the first power supply and the third power supply, and does not use a bias voltage (corresponding to VBIAS in Patent Document 1), meaning that a circuit for generating a bias voltage is not required.

[0011] In the present disclosure, a level shift circuit can achieve a lower operating voltage and / or faster circuit operation.

[0012] 1. Circuit diagram showing an example of the configuration of a level shift circuit according to a first embodiment. 2. Circuit diagram showing an example of the configuration of a pull-up circuit. 3. Diagram showing an example of the voltage waveforms of each node of the level shift circuit. 4. Circuit diagram showing an example of the configuration of a level shift circuit according to a second embodiment. 5. Circuit diagram showing an example of the configuration of a level shift circuit according to a third embodiment. 6. Circuit diagram showing a modified version of the level shift circuit according to the first embodiment.

[0013] The following describes embodiments. Note that specific numerical values ​​and the like shown in the following embodiments are merely examples to facilitate understanding of the invention and are not intended to limit the scope of the invention. In addition, in the following description, common symbols and names may be used for nodes and terminals of a circuit and signals passing through those nodes and terminals, and common symbols may be used for the names of power supplies and the power supply voltages of those power supplies.

[0014] First Embodiment A level shift circuit 1 is configured with two power supplies, a first power supply VDD and a third power supply VDDIO, and is a circuit that boosts a high-level voltage from VDD to VDDIO and boosts a low-level voltage from VSS to VDD. The third power supply VDDIO is a power supply with a higher voltage than the first power supply VDD. In the following description, a low level may be simply referred to as 'L' and a high level may be simply referred to as 'H'.

[0015] The level shift circuit 1 receives an input signal IN that transitions between a first power supply VDD and a ground VSS (corresponding to a second power supply) from an input terminal IN (input node in), and outputs an output signal OUT that transitions between a third power supply VDDIO and the first power supply VDD from an output terminal OUT (output node out). In other words, the input signal IN is a signal with an amplitude of VDD, and the output signal OUT is a signal with an amplitude of (VDDIO-VDD).

[0016] FIG. 1 shows an example of a circuit diagram of a level shift circuit 1 according to the first embodiment.

[0017] The level shift circuit 1 includes a first circuit 10, a second circuit 20, a pull-up circuit 30, and an inverter 5 that inverts an input signal IN to generate an inverted input signal INB.

[0018] The inverter 5 receives the input signal IN as an input and outputs an inverted input signal INB to the inverted input node inb of the second circuit 20. The power supply terminal of the inverter 5 is connected to the first power supply VDD, and the ground terminal is connected to the ground VSS. Note that the inverter 5 may be omitted from FIG. 1. For example, a configuration may be adopted in which the input signal IN and the inverted input signal INB are generated in a circuit (not shown) preceding the level shift circuit 1 and input to the level shift circuit 1. This also applies to other drawings (other embodiments).

[0019] The first circuit 10 and the second circuit 20 are circuits that step up an input voltage input to an input terminal IN and output it from an output terminal OUT. The first circuit 10 and the second circuit 20 have a symmetrical configuration.

[0020] Each circuit will be described below with reference to the drawings.

[0021] -First Circuit- The first circuit 10 includes an N-type transistor N1 and P-type transistors P1, P2, and P9. Note that the N-type transistor and the P-type transistor in this disclosure are, for example, transistors with a MOS structure.

[0022] The input node in of the first circuit 10 is connected to the input terminal IN, and receives the input signal IN.

[0023] An N-type transistor N1 (corresponding to a first N-type transistor) is provided between an input node in and a node n11 (corresponding to a first node), with its gate connected to a first power supply VDD. A P-type transistor P9 (corresponding to a first P-type transistor) is provided between the node n11 and an output node out, with its gate connected to the first power supply VDD. In other words, the N-type transistor N1 and the P-type transistor P9 are connected in series between the input node in and the output node out.

[0024] In this disclosure, "connection" is a concept that broadly encompasses electrical connection, and includes not only direct connection but also indirect electrical connection via passive elements (not shown) or the like.

[0025] The P-type transistor P1 (corresponding to the thirteenth P-type transistor) is provided between the third power supply VDDIO and the output node out, and has a gate connected to the inverted output node outb (corresponding to the third node).

[0026] The P-type transistor P2 (corresponding to a second P-type transistor) is provided between the output node out and the first power supply VDD, and has its gate connected to the node n11.

[0027] The second circuit 20 includes an N-type transistor N2 and P-type transistors P3, P4, and P10. An inverting input node inb, which is an input node of the second circuit 20, is connected to the output of the inverter 5 and receives an inverting input signal INB.

[0028] An N-type transistor N2 (corresponding to a second N-type transistor) is provided between the inverting input node inb and a node n12 (corresponding to a second node), with its gate connected to the first power supply VDD. A P-type transistor P10 (corresponding to a third P-type transistor) is provided between the node n12 and the inverting output node outb, with its gate connected to the first power supply VDD. In other words, the N-type transistor N2 and the P-type transistor P10 are connected in series between the inverting input node inb and the inverting output node outb.

[0029] The P-type transistor P3 (corresponding to a fourteenth P-type transistor) is provided between the third power supply VDDIO and the inverting output node outb, and has its gate connected to the output node out.

[0030] The P-type transistor P4 (corresponding to a fourth P-type transistor) is provided between the inverting output node outb and the first power supply VDD, and has its gate connected to the node n12.

[0031] As described above, the P-type transistor P1 is connected between the third power supply VDDIO and the output node out, and the P-type transistor P3 is connected between the third power supply VDDIO and the inverted output node outb. Furthermore, the gate of the P-type transistor P1 is connected to the inverted output node outb, and the gate of the P-type transistor P3 is connected to the output node out, forming a so-called cross-coupled connection. In the following description, the above configuration may be referred to as a "cross-coupled connection" or a "cross-coupled structure."

[0032] -Pull-Up Circuit- The pull-up circuit 30 is a circuit provided between the node n11 and the node n12, and operates by receiving power from the first power supply VDD and the third power supply VDDIO.

[0033] The pull-up circuit 30 includes a circuit 40 and a circuit 50 that are symmetrical to each other.

[0034] The circuit 40 includes P-type transistors P6, P7, P11, and P14.

[0035] The P-type transistor P7 (corresponding to the eleventh P-type transistor) is provided between the third power supply VDDIO and node n16 (corresponding to the seventh node), with its gate connected to node n14 (corresponding to the sixth node). The P-type transistor P14 (corresponding to the twelfth P-type transistor) is provided between node n16 and node n11, with its gate connected to the first power supply VDD. In other words, the P-type transistor P7 and the P-type transistor P14 are connected in series between the third power supply VDDIO and node n11.

[0036] The P-type transistor P6 (corresponding to a sixth P-type transistor) is provided between the node n13 (corresponding to a fourth node) and the first power supply VDD, and has its gate connected to the node n11.

[0037] The P-type transistor P11 (corresponding to a fifth P-type transistor) is provided between the node n11 and the node n13, and has a gate connected to the first power supply VDD.

[0038] The circuit 50 includes P-type transistors P5, P8, P12, and P13.

[0039] The P-type transistor P5 (corresponding to the seventh P-type transistor) is provided between the third power supply VDDIO and a node n15 (corresponding to the fifth node), and has its gate connected to the node n13. The P-type transistor P12 (corresponding to the eighth P-type transistor) is provided between the node n15 and a node n12, and has its gate connected to the first power supply VDD. In other words, the P-type transistor P5 and the P-type transistor P12 are connected in series between the third power supply VDDIO and the node n12.

[0040] The P-type transistor P8 (corresponding to the tenth P-type transistor) is provided between the node n14 and the first power supply VDD, and has its gate connected to the node n12.

[0041] The P-type transistor P13 (corresponding to a ninth P-type transistor) is provided between the node n12 and the node n14, and has a gate connected to the first power supply VDD.

[0042] In terms of functionality, the pull-up circuit 30 has a function of assisting the boost conversion operations of the first circuit 10 and the second circuit 20. Specifically, the pull-up circuit 30 includes a first pull-up circuit 60 and a second pull-up circuit 70. The first pull-up circuit 60 is a circuit that pulls up the node n12 to the third power supply VDDIO when the node n11 transitions from high to low. The second pull-up circuit 70 is a circuit that pulls up the node n11 to the third power supply VDDIO when the node n12 transitions from high to low.

[0043] 2, the first pull-up circuit 60 includes the aforementioned P-type transistors P5, P6, P11, and P12, and the second pull-up circuit 70 includes the aforementioned P-type transistors P7, P8, P13, and P14.

[0044] [Operation of Level Shift Circuit] Next, the operation of the level shift circuit 1 according to this embodiment will be described.

[0045] --Operation example (1-1)--The operation when 'L' is input as the input signal IN and 'L' is output as the output signal OUT will be described below, that is, the operation when the voltage of the input signal is VSS and the voltage of the output signal is VDD. In the following explanation, the gate-source voltage Vgs of a transistor will be simply referred to as "Vgs".

[0046] In the first circuit 10, since the input signal IN is 'L', the N-type transistor N1 turns on, the node n11 becomes 'L' (voltage VSS), and the P-type transistor P2 turns on. As a result, the voltage of the output node out becomes VDD, and 'L' (voltage VDD) is output to the output terminal OUT. Furthermore, as the voltage of the output node out becomes VDD, the P-type transistor P9 turns off.

[0047] In the second circuit 20, the voltage of the output node out is VDD, so the P-type transistors P3 and P10 are turned on, causing the voltages of the node n12 and the inverted output node outb to become VDDIO, and the P-type transistors P1 and P4 and the N-type transistor N2 are turned off.

[0048] In the pull-up circuit 30, the P-type transistor P6 turns on, and the voltage of the node n13 becomes VDD. This turns off the P-type transistor P11, and turns on the P-type transistors P5 and P12. This causes the node n12 to be pulled up to the third power supply VDDIO.

[0049] On the other hand, since the P-type transistor P13 is turned on and the P-type transistor P8 is turned off, the voltage of the node n14 becomes VDDIO, and the P-type transistors P7 and P14 are turned off.

[0050] --Operation Example (1-2)-- The operation when 'H' is input as the input signal IN and 'H' is output as the output signal OUT, that is, the operation when the voltage of the input signal is VDD and the voltage of the output signal is VDDIO, will be described. Because the first circuit 10 and the second circuit 20 have a symmetrical configuration, and the circuit 40 and the circuit 50 have a symmetrical configuration, the operation is opposite to that of the above-mentioned "Operation Example (1-1)."

[0051] In the second circuit 20, since the inverting input signal INB is 'L', the N-type transistor N2 turns on, the node n12 becomes 'L' (voltage VSS), and the P-type transistor P4 turns on. As a result, the voltage of the inverting output node outb becomes VDD, and the P-type transistor P10 turns off.

[0052] In the first circuit 10, since the voltage of the inverting output node outb is VDD, the P-type transistors P1 and P9 are turned on. As a result, the voltages of the node n11 and the output node out become VDDIO, and 'H' (VDDIO) is output from the output terminal OUT. In addition, the P-type transistors P2, P3, and N-type transistor N1 are turned off.

[0053] In the pull-up circuit 30, the P-type transistor P8 turns on, and the voltage of the node n14 becomes VDD. This turns off the P-type transistor P13, and turns on the P-type transistors P7 and P14. This causes the node n11 to be pulled up to the third power supply VDDIO.

[0054] On the other hand, since the P-type transistor P11 is turned on and the P-type transistor P6 is turned off, the voltage of the node n13 becomes VDDIO, and the P-type transistors P5 and P12 are turned off.

[0055] --Operation Example (1-3)-- The operation when the input signal IN changes from 'L' to 'H' and the output signal OUT changes from 'L' to 'H' will be described.

[0056] The on / off state of each transistor and the voltage of each node transition from the above-mentioned "Operation Example (1-1)" to the "Operation Example (1-2)." Below, specific operations are explained for the "case where the pull-up circuit 30 is provided (Example)" and the "case where the pull-up circuit 30 is not provided (Comparative Example)."

[0057] (Example of Operation When a Pull-Up Circuit is Provided [Example]) When the input signal IN changes from 'L' to 'H', the inverted input signal INB changes from 'H' to 'L'. That is, the voltage of the inverted input signal INB drops from VDD. During this process, the Vgs of the N-type transistor N2 exceeds the threshold, turning on the N-type transistor N2, and the voltage of the node n12 drops from VDDIO. At this time, in the pull-up circuit 30, the Vgs of the P-type transistor P8 exceeds the threshold, turning on the P-type transistor P8. As a result, the voltage of the node n14 starts to drop from VDDIO.

[0058] In the pull-up circuit 30, node n14 is connected to the gate of P-type transistor P7 but not to node n15, and therefore does not have a cross-coupled structure. Therefore, even when P-type transistor P8 begins to turn on, "conduction between the third power supply VDDIO and the first power supply VDD" does not occur via P-type transistors P5 and P8. As a result, the voltage at node n14 drops before the voltage at inverted output node outb.

[0059] Therefore, the P-type transistor P7 turns on before the P-type transistor P1, and the voltage of the node n11 rises before the voltage of the output node out. In other words, the pull-up circuit 30 operates to pull up the node n11 to the third power supply VDDIO when the node n12 transitions from high to low.

[0060] Thereafter, when Vgs of P-type transistor P9 exceeds the threshold and P-type transistor P9 turns on, node n11 and output node out become conductive, and the voltage of output node out begins to rise. As a result, the voltage rise at output node out becomes faster and P-type transistor P3 turns off earlier than in the case where pull-up circuit 30, which will be described later, is not provided. Furthermore, due to the action of the cross-coupled structure, the voltage drop at inverted output node outb and the turn-on of P-type transistor P1 are accelerated, so there is no delay in the signal output to output terminal OUT (signal transition from 'L' to 'H').

[0061] (Example of Operation When a Pull-Up Circuit is Not Provided [Comparative Example]) When the input signal IN changes from 'L' to 'H', the inverted input signal INB changes from 'H' to 'L'. That is, the voltage of the inverted input signal INB drops from VDD. During this process, the Vgs of the N-type transistor N2 exceeds the threshold, turning on the N-type transistor N2, and the voltage of the node n12 drops from VDDIO. Then, the Vgs of the P-type transistor P4 exceeds the threshold, turning on the P-type transistor P4. As a result, the voltage of the inverted output node outb starts to drop from VDDIO. At this time, the P-type transistor P3 is still on, so there is a period of conduction between the third power supply VDDIO and the first power supply VDD via the P-type transistors P3 and P4. Therefore, the voltage drop at the inverted output node outb is gradual until the P-type transistor P3 begins to turn off, causing a delay in turning on the P-type transistor P1.

[0062] After that, when the P-type transistor P1 begins to turn on, the voltage at the output node out begins to rise from VDD. At this time, the P-type transistor P2 is still on, so there is a period of conduction between the third power supply VDDIO and the first power supply VDD via the P-type transistors P1 and P2. Therefore, the voltage rise at the output node out is gradual until the P-type transistor P2 begins to turn off, and the turn-off of the P-type transistor P3 is delayed. Furthermore, the turn-on of the P-type transistor P9 is delayed, so the voltage rise at the node n11 is gradual, and the turn-off of the P-type transistor P2 is delayed. Furthermore, due to the cross-coupled structure, if the turn-off of the P-type transistor P3 is delayed, the turn-on of the P-type transistor P1 is delayed, and if the turn-on of the P-type transistor P1 is delayed, the turn-off of the P-type transistor P3 is further delayed. As a result, the output signal OUT (transition from 'L' to 'H') output from the output terminal OUT is delayed.

[0063] --Operation Example (1-4)-- The operation when the input signal IN changes from 'H' to 'L' and the output signal OUT changes from 'H' to 'L' will be described.

[0064] The on / off state of each transistor and the voltage of each node transition from the above-mentioned "Operation Example (1-2)" to the "Operation Example (1-1)." Below, specific operations are explained for the cases "when pull-up circuit 30 is provided (Example)" and "when pull-up circuit 30 is not provided (Comparative Example)."

[0065] (Example of operation when a pull-up circuit is provided [embodiment]) When the input signal IN drops from 'H' to 'L', the Vgs of N-type transistor N1 exceeds the threshold, turning on N-type transistor N1, and the voltage at node n11 drops from VDDIO. At this time, in pull-up circuit 30, the Vgs of P-type transistor P6 exceeds the threshold, turning on P-type transistor P6. This causes the voltage at node n13 to start dropping from VDDIO.

[0066] In the pull-up circuit 30, node n13 is connected to the gate of P-type transistor P5 but not to node n16, so it is not a cross-coupled structure. Therefore, even if P-type transistor P6 begins to turn on, "conduction between the third power supply VDDIO and the first power supply VDD" does not occur via P-type transistors P7 and P6. As a result, the voltage at node n13 drops before the voltage at output node out.

[0067] Therefore, the P-type transistor P5 turns on before the P-type transistor P3, and the voltage of the node n12 rises before the voltage of the inverted output node outb. In other words, the pull-up circuit 30 operates to pull up the node n12 to the third power supply VDDIO when the node n11 transitions from high to low.

[0068] Thereafter, when Vgs of the P-type transistor P10 exceeds the threshold and the P-type transistor P10 turns on, the node n12 and the inverting output node outb become conductive, and the voltage of the inverting output node outb begins to rise. As a result, the voltage rise at the inverting output node outb becomes faster than in the case where the pull-up circuit 30 described below is not provided, and the P-type transistor P1 turns off earlier. Furthermore, due to the action of the cross-coupled structure, the voltage drop at the output node out and the turn-on of the P-type transistor P3 are accelerated, so there is no delay in the signal output to the output terminal OUT (signal transition from 'H' to 'L').

[0069] (Example of operation when no pull-up circuit is provided [Comparative example]) When the input signal IN drops from 'H' to 'L', the Vgs of the N-type transistor N1 exceeds the threshold, turning on the N-type transistor N1, and the voltage at the node n11 drops from VDDIO. Then, the Vgs of the P-type transistor P2 exceeds the threshold, and the P-type transistor P2 begins to turn on. This causes the voltage at the output node out to drop from VDDIO. At this time, the P-type transistor P1 is still on, so there is a period of conduction between the third power supply VDDIO and the first power supply VDD via the P-type transistors P1 and P2. Therefore, the voltage drop at the output node out is gradual until the P-type transistor P1 begins to turn off, causing a delay in turning on the P-type transistor P3.

[0070] After that, when the P-type transistor P3 begins to turn on, the voltage of the inverting output node outb begins to rise from VDD. At this time, the P-type transistor P4 is still on, so there is a period of conduction between the third power supply VDDIO and the first power supply VDD via the P-type transistors P3 and P4. Therefore, the voltage rise at the inverting output node outb is gradual until the P-type transistor P4 begins to turn off, and the turn-off of the P-type transistor P1 is delayed. Furthermore, the turn-on of the P-type transistor P10 is delayed, so the voltage rise at the node n12 is gradual, and the turn-off of the P-type transistor P4 is delayed. Furthermore, due to the cross-coupled structure, if the turn-off of the P-type transistor P1 is delayed, the turn-on of the P-type transistor P3 is delayed, and if the turn-on of the P-type transistor P3 is delayed, the turn-off of the P-type transistor P1 is further delayed. As a result, the output signal OUT (transition from 'H' to 'L') output from the output terminal OUT is delayed.

[0071] [Effects of the First Embodiment] As described above, by adopting the configuration of the present embodiment, the output of the signal to the output terminal OUT is not delayed compared to when the pull-up circuit 30 is not provided, and the circuit can be made faster.

[0072] Specifically, in the operation example (1-3), when the node n12 transitions from high to low, the pull-up circuit 30 operates to pull up the node n11 to the third power supply VDDIO, so that the voltage rise at the output node out is accelerated and the P-type transistor P3 is turned off early. Furthermore, the voltage drop at the inverted output node outb and the turn-on of the P-type transistor P1 are accelerated, so that the output signal OUT (transition from 'L' to 'H') output from the output terminal OUT is not delayed.

[0073] Similarly, in the operation example (1-4), when the node n11 transitions from high level to low level, the pull-up circuit 30 operates to pull up the node n12 to the third power supply VDDIO, so that the voltage rise at the inverted output node outb is accelerated and the P-type transistor P1 is turned off earlier. Furthermore, because the voltage drop at the output node out and the turn-on of the P-type transistor P3 are accelerated, there is no delay in the output signal OUT (transition from 'H' to 'L') output from the output terminal OUT.

[0074] In the level shift circuit 1 of this embodiment, since the inverter 5 is provided, the signal propagation time from the input terminal IN to the output terminal OUT is longer in the operation example (1-3) than in the operation example (1-4). Therefore, if the signal propagation time becomes longer as the operating voltage decreases, the difference will widen, but this can be suppressed in this embodiment.

[0075] Furthermore, the level shift circuit 1 of this embodiment is configured with two power supplies, a first power supply VDD and a third power supply VDDIO, and does not use a bias voltage (corresponding to VBIAS in Patent Document 1), meaning that a circuit for generating a bias voltage is not required.

[0076] Second Embodiment FIG. 4 shows an example of a circuit diagram of a level shift circuit 1 according to a second embodiment. In FIG. 4, components corresponding to those in FIG. 1 are assigned common reference numerals. The following description will focus on differences from the first embodiment. Note that elements (e.g., transistors and inverters) assigned the same reference numerals in FIGS. 1 and 4 are not intended to be limited to the same design parameters / process parameters, etc. In other words, the technical scope of the present disclosure includes configurations in which the various parameters of elements assigned the same reference numerals in FIGS. 1 and 4 differ from each other. The same applies to the relationships between the other drawings.

[0077] The level shift circuit 1 of this embodiment is configured to accelerate the rise of the voltages at the output node out and the inverted output node outb compared to the first embodiment.

[0078] In this embodiment, in the first circuit 10, the gate of the P-type transistor P1 is connected to a node n14 (see FIG. 2) of the pull-up circuit 30, instead of the inverting output node outb in the first embodiment. Also, in the second circuit 20, the gate of the P-type transistor P3 is connected to a node n13 (see FIG. 2) of the pull-up circuit 30, instead of the output node out in the first embodiment.

[0079] [Operation of Level Shift Circuit] Next, the operation of the level shift circuit 1 according to this embodiment will be described, focusing on differences from the operation of the level shift circuit 1 according to the first embodiment.

[0080] --Operation Example (2-1)-- The operation when the input signal IN changes from 'L' to 'H' will be described.

[0081] In the first embodiment, the P-type transistor P7 turns on before the P-type transistor P1, and the voltage at the node n11 rises before the voltage at the output node out. Then, the P-type transistor P9 turns on, causing the voltage at the output node out to rise.

[0082] In contrast, in this embodiment, the gates of P-type transistor P7 and P-type transistor P1 are connected to a common node n14, so they turn on at the same time. As a result, the voltage at node n11 and the voltage at output node out rise at the same time. Furthermore, since P-type transistor P1 and P-type transistor P3 are not cross-coupled, the voltage at output node out rises regardless of the operation of P-type transistor P3. As a result, the voltage at output node out can be raised more quickly than in the first embodiment.

[0083] --Operation Example (2-2)-- The operation when the input signal IN changes from 'H' to 'L' will be described.

[0084] As in the case of the above-described operation example (1-4), in this operation example, the first circuit 10 and the second circuit 20 perform operations opposite to each other compared to the operation example (2-1). As a result, the voltage of the inverting output node outb rises regardless of the operation of the P-type transistor P1. This allows the voltage of the inverting output node outb to rise more quickly compared to the first embodiment.

[0085] As described above, according to the second embodiment, the voltage at the output node out and the voltage at the inverted output node outb can be increased more quickly than in the first embodiment, thereby enabling a faster circuit operation than in the first embodiment.

[0086] <Third Embodiment> Fig. 5 shows an example of a circuit diagram of a level shift circuit 1 according to a third embodiment. In Fig. 5, components corresponding to those in Fig. 1 are assigned the same reference numerals as in Fig. 1. The following description will focus on differences from the other embodiments.

[0087] The level shift circuit 1 of this embodiment eliminates the P-type transistors P1 and P3 from the configurations of the first and second embodiments. For example, the drive capability, i.e., the transistor size, of P-type transistor P7 may be set so that the operation of P-type transistor P1 in the first and second embodiments is included in P-type transistor P7. Similarly, the drive capability, i.e., the transistor size, of P-type transistor P5 may be set so that the operation of P-type transistor P3 is included in P-type transistor P5.

[0088] [Operation of Level Shift Circuit] In this embodiment, the voltages of node n11, node n12, output node out, and inverted output node outb are increased by turning on P-type transistor P5 (see FIG. 2) and P-type transistor P7 (see FIG. 2) of pull-up circuit 30. As a result, the level shift circuit 1 according to this embodiment operates in the same manner as in the second embodiment, and the same effects can be obtained.

[0089] [Operation and Effects of Third Embodiment] As described above, according to this embodiment, the operation is similar to that of the second embodiment, and the same effects are obtained.

[0090] Furthermore, since the arrangement of P-type transistor P1 and P-type transistor P3 and their wiring (including the transistor arrangement area and wiring area) are not required, the circuit area can be reduced compared to the first and second embodiments. For example, when the drive capability of P-type transistor P5 and P-type transistor P7 does not need to be expanded, such as when used for control signals (enable / disable signals, etc.) that are slower than clock and data signals, the circuit area can be further reduced.

[0091] It should be noted that the technology disclosed herein is not limited to the configurations described in the above embodiments, and can be applied to embodiments in which appropriate modifications, substitutions, additions, omissions, etc. Furthermore, the components described in the above embodiments can be combined to create new embodiments.

[0092] <Modification> Fig. 6 shows a modification of the level shift circuit 1 according to the first embodiment. In Fig. 6, components corresponding to those in Fig. 1 are assigned the same reference numerals as in Fig. 1. The following description will focus on the differences from the first embodiment.

[0093] In addition to the configuration of the first embodiment, the level shift circuit 1 of this embodiment has a capacitance C1 between the output node out and the node n11, and a capacitance C2 between the inverted output node outb and the node n12.

[0094] The configurations of the capacitors C1 and C2 are not particularly limited. For example, a capacitive element may be used as the capacitors C1 and C2, or a transistor capacitance such as a gate capacitance or an S / D capacitance (source-drain capacitance) may be used. The same applies to the capacitors C3 and C4 described later.

[0095] The pull-up circuit 30 may have the same configuration as that of the first embodiment (see FIG. 2) or the configuration shown in FIG. 7. Specifically, the first circuit 10 and the second circuit 20 shown in FIG. 1 may be combined with the pull-up circuit 30 shown in FIG. 7, or the first circuit 10 and the second circuit 20 shown in FIG. 6 may be combined with the pull-up circuit 30 shown in FIG. 2 or the pull-up circuit 30 shown in FIG. 7.

[0096] -Pull-up Circuit- Fig. 7 shows another example of the configuration of the pull-up circuit 30. In Fig. 7, components corresponding to those in Fig. 2 are given the same reference numerals as in Fig. 2.

[0097] 2, the pull-up circuit 30 of Fig. 7 includes a capacitor C3 between the nodes n11 and n13, and a capacitor C4 between the nodes n12 and n14. In the example of Fig. 7, the first pull-up circuit 60 includes the capacitor C3 in addition to the P-type transistors P5, P6, P11, and P12 described above. The second pull-up circuit 70 includes the capacitor C4 in addition to the P-type transistors P7, P8, P13, and P14 described above.

[0098] [Operation of Level Shift Circuit] Next, the operation of the level shift circuit 1 according to this modification will be described. Here, the operations of the first circuit 10, the second circuit 20, and the pull-up circuit 30 will be described together.

[0099] --Operation when voltage rises at output node / inverted output node-- When the voltage at the output node out rises, the pull-up circuit 30 raises the voltage at node n11, and the P-type transistor P9 turns on, establishing electrical continuity between the output node out and node n11, thereby assisting the rise in voltage at the output node out. This makes it possible to hasten the rise in voltage at the output node out.

[0100] Similarly, when the voltage at the inverting output node outb rises, the pull-up circuit 30 raises the voltage at the node n12, and the P-type transistor P10 turns on, establishing electrical continuity between the inverting output node outb and the node n12, thereby assisting the rise in the voltage at the inverting output node outb. This makes it possible to hasten the rise in the voltage at the inverting output node outb.

[0101] Here, by adding the capacitor C1, the voltage at the output node out rises together with the voltage at the node n11 even before the P-type transistor P9 turns on. Similarly, by adding the capacitor C2, the voltage at the inverted output node outb rises together with the voltage at the node n12 even before the P-type transistor P10 turns on.

[0102] Furthermore, by adding the capacitor C3, the voltage at the node n13 also rises before the P-type transistor P11 turns on. Similarly, by adding the capacitor C4, the voltage at the node n14 also rises before the P-type transistor P13 turns on.

[0103] --Operation when voltage drops at output node / inverted output node-- When the voltage at the output node out drops, the N-type transistor N1 turns on, causing the voltage at node n11 to drop, the P-type transistor P9 turns off, and then the P-type transistor P2 turns on, causing the voltage at the output node out to drop to the voltage of the first power supply VDD. Similarly, when the voltage at the inverted output node outb drops, the N-type transistor N2 turns on, causing the voltage at node n12 to drop, the P-type transistor P10 turns off, and then the P-type transistor P4 turns on, causing the voltage at the inverted output node outb to drop to the voltage of the first power supply VDD.

[0104] Here, when the capacitor C1 is added, the voltage at the output node out drops along with the voltage drop at the node n11 even before the P-type transistor P2 turns on. Similarly, when the capacitor C2 is added, the voltage at the inverted output node outb drops along with the voltage drop at the node n12 even before the P-type transistor P4 turns on.

[0105] Furthermore, by adding the capacitor C3, the voltage at the node n13 also drops before the P-type transistor P6 turns on. Similarly, by adding the capacitor C4, the voltage at the node n14 also drops before the P-type transistor P8 turns on.

[0106] [Operation and Effect of Modification] As described above, according to this modification, the voltage rise and fall of the output node out and the inverted output node outb can be accelerated, thereby enabling a high-speed circuit.

[0107] In the above description of the "variations," modifications of the first embodiment have been described, but similar modifications can also be applied to the second or third embodiment, and equivalent effects can be obtained. Specifically, for example, in the above modifications, an example has been described in which capacitors C1 and C2 are provided in addition to the configuration of the first embodiment. However, in the second and third embodiments, capacitors C1 and C2 may be provided in the same positions as in the first embodiment, and equivalent effects can be obtained. Furthermore, in the second and third embodiments, the pull-up circuit 30 of FIG. 2 may be replaced by the pull-up circuit 30 of FIG. 7, and equivalent effects can be obtained.

[0108] The level shift circuit of the present disclosure is extremely useful because it is compatible with lower operating voltages and / or higher speed circuit operations.

[0109] 1 Level shift circuit 30 Pull-up circuit N1 N-type transistor (first N-type transistor) N2 N-type transistor (second N-type transistor) P1 P-type transistor (thirteenth P-type transistor) P2 P-type transistor (second P-type transistor) P3 P-type transistor (fourteenth P-type transistor) P4 P-type transistor (fourth P-type transistor) P5 P-type transistor (seventh P-type transistor) P6 P-type transistor (sixth P-type transistor) P7 P-type transistor (eleventh P-type transistor) P8 P-type transistor (tenth P-type transistor) P9 P-type transistor (first P-type transistor) P10 P-type transistor (third P-type transistor) P11 P-type transistor (fifth P-type transistor) P12 P-type transistor (eighth P-type transistor) P13 P-type transistor (ninth P-type transistor) P14 P-type transistor (twelfth P-type transistor) n11 Node (first node) n12 Node (second node) n13 Node (fourth node) n14 Node (sixth node) n15 Node (fifth node) n16 Node (seventh node) n17 Node (third node) in Input node inb Inverting input node out Output node outb Inverting output node (third node) VDD First power supply VDDIO Third power supply VSS Ground (second power supply) C1 Capacitor (first capacitor) C2 Capacitor (second capacitor) C3 Capacitor (first capacitor) C4 Capacitor (second capacitor)

Claims

1. A transistor comprising: an input node receiving an input signal which transitions between a first power supply and a second power supply having a potential lower than that of the first power supply; a first N-type transistor provided between the input node and the first node, the gate of which is connected to the first power supply; a first P-type transistor provided between the first node and an output node, the gate of which is connected to the first power supply; a second P-type transistor provided between the output node and the first power supply, the gate of which is connected to the first node; an inverting input node receiving an inverted input signal obtained by inverting the input signal; a second N-type transistor provided between the inverting input node and a second node, the gate of which is connected to the first power supply; a third P-type transistor provided between the second node and a third node, the gate of which is connected to the first power supply; a fourth P-type transistor provided between the third node and the first power supply, the gate of which is connected to the second node; and a pull-up circuit provided between the first node and the second node, a first pull-up circuit that pulls up the second node to a third power supply having a higher potential than the first power supply when the first node transitions from a high level to a low level; and a second pull-up circuit that pulls up the first node to the third power supply when the second node transitions from a high level to a low level.

2. In the level shift circuit according to claim 1, the first pull-up circuit comprises: a fifth P-type transistor provided between the first node and a fourth node, the gate of which is connected to the first power supply; a sixth P-type transistor provided between the fourth node and the first power supply, the gate of which is connected to the first node; a seventh P-type transistor provided between the third power supply and a fifth node, the gate of which is connected to the fourth node; and an eighth P-type transistor provided between the fifth node and the second node, the gate of which is connected to the first power supply; and the second pull-up circuit comprises: a ninth P-type transistor provided between the second node and a sixth node, the gate of which is connected to the first power supply; a tenth P-type transistor provided between the sixth node and the first power supply, the gate of which is connected to the second node; an eleventh P-type transistor provided between the third power supply and a seventh node, the gate of which is connected to the sixth node; a twelfth P-type transistor provided between the seventh node and the first node, the gate of the twelfth P-type transistor being connected to the first power supply; 3. A level shift circuit as claimed in claim 2, comprising: a thirteenth P-type transistor provided between said third power supply and said output node, the gate of which is connected to said sixth node; and a fourteenth P-type transistor provided between said third power supply and said third node, the gate of which is connected to said fourth node.

4. A level shift circuit as claimed in claim 2, wherein the first pull-up circuit comprises a first capacitance element provided between the first node and the fourth node, and the second pull-up circuit comprises a second capacitance element provided between the second node and the sixth node.

5. A level shift circuit as claimed in claim 1, comprising: a thirteenth P-type transistor provided between said third power supply and said output node, the gate of which is connected to said third node; and a fourteenth P-type transistor provided between said third power supply and said third node, the gate of which is connected to said output node.

6. A level shift circuit as claimed in claim 1, comprising: a first capacitance element provided between said first node and said output node; and a second capacitance element provided between said second node and said third node.

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