Pixel circuit, display device, and method for driving same

Abstract

The present application discloses a display device that is a current-driven display device in which pause driving is performed and can display a high-definition image. In a pixel circuit 15 of an organic EL display device, a drive transistor T2 has a gate terminal connected to a source terminal thereof via a holding capacitor Cst, and connected to a data signal line Dj via a pause control transistor T1b and a write control transistor T1a in order, and has a drain terminal connected to an anode electrode of an organic EL element OL via a light emission control transistor T3, and the anode electrode is connected to an initialization voltage line Vini via an initialization transistor T4. The write control transistor T1a and the initialization transistor T4 are controlled by a scanning signal SC(i), and the pause control transistor T1b is controlled by a light emission control signal EM(i). In a non-refresh frame period, writing of data voltage to the holding capacitor Cst is suppressed by the pause control transistor T1b in an off state.

Description

Pixel circuit, display device, and driving method thereof

[0001] The present disclosure relates to a current-driven display device that includes display elements that are driven by current, such as organic EL (Electro Luminescence) elements, and in particular to a pixel circuit used in the display device.

[0002] In recent years, organic EL display devices equipped with pixel circuits including organic EL elements (also called organic light-emitting diodes (OLEDs)) have been put to practical use. The pixel circuits of organic EL display devices include, in addition to the organic EL elements, drive transistors, write control transistors, and storage capacitors. Thin-film transistors are used for the drive transistors and write control transistors, and a storage capacitor is connected to a gate terminal serving as a control terminal of the drive transistor. A voltage corresponding to a video signal representing an image to be displayed (more specifically, a voltage indicating the gradation value of a pixel to be formed by the pixel circuit) is applied as a data voltage to the storage capacitor via a data signal line from the drive circuit. The organic EL elements are self-luminous display elements that emit light at a brightness corresponding to the current flowing through them. The drive transistor is connected in series with the organic EL element and controls the current flowing through the organic EL element according to the voltage stored in the storage capacitor.

[0003] On the other hand, display devices that perform pause driving are known as low-power display devices. Pause driving is a driving method in which, when continuously displaying the same image, a drive period (refresh period) and a pause period (non-refresh period) are set, and the drive circuit operates during the drive period and stops operating during the pause period. This type of pause driving is also called "low-frequency driving." This type of pause driving is suitable for displaying still images.

[0004] US Patent Application Publication No. 2020 / 0118487 US Patent Application Publication No. 2021 / 0020104 Japanese Patent Application Publication No. 2020-079942

[0005] A pixel circuit in an organic EL display device typically includes a light-emission control transistor for turning off an organic EL element during a period when a data voltage is written to the pixel circuit. In each pixel circuit, during a non-light-emission period when the organic EL element is turned off by the light-emission control transistor, in addition to writing a data voltage, the organic EL element is initialized by discharging the accumulated charge in the parasitic capacitance of the organic EL element (hereinafter, this initialization is referred to as "OLED initialization"). Note that OLED initialization is also called "anode initialization" or "anode reset" because it initializes the voltage of the anode electrode of the organic EL element (hereinafter, "anode voltage"). This anode initialization blocks the influence of past display history on the light-emitting behavior of the organic EL element OL.

[0006] However, in an organic EL display device that performs the aforementioned pause driving, anode initialization is performed during a non-refresh period while suppressing the writing of data voltages. Therefore, a transistor serving as a switching element for controlling the writing of data voltages and a transistor serving as a switching element for performing anode initialization must be controlled on / off by different control signals. As a result, in addition to a circuit that generates a first scanning signal used as a control signal for data writing in each pixel circuit, a circuit that generates a second scanning signal as a control signal for anode initialization in each pixel circuit is provided in the scanning-side driving circuit. Furthermore, each pixel circuit requires a control signal line for anode initialization in addition to a control signal line for data writing, which increases the layout area of ​​the pixel circuit and makes it difficult to achieve high-resolution display images.

[0007] Therefore, in a current-driven display device such as an organic EL display device that performs pause driving, it is desirable to achieve high-definition image display while suppressing an increase in the scanning side drive circuit and an increase in the layout area of ​​the pixel circuit.

[0008] a first power supply line connected to the first scanning signal line; a second power supply line connected to the second power supply line; and a control terminal connected to the first data signal line via the write control switching element. The pixel circuit according to some embodiments of the present invention is for a display device having a display unit including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of light emission control lines, a first power supply line, a second power supply line, and an initialization voltage line for supplying a predetermined fixed voltage as an initialization voltage, the pixel circuit comprising: a display element driven by a current; a holding capacitor; a drive transistor for controlling a current flowing to the display element in accordance with a voltage held in the holding capacitor; a write control switching element having a control terminal connected to one of the plurality of first scanning signal lines; a light emission control switching element provided in series with the display element and having a control terminal connected to one of the plurality of light emission control lines; and an initialization switching element. The drive transistor has a first conduction terminal connected to the first power supply line directly or indirectly via at least one element, a second conduction terminal connected to the second power supply line directly or indirectly via at least one element, and a control terminal connected to one of the plurality of data signal lines via at least the write control switching element. the display element has a first electrode connected to the initialization voltage line via the initialization switching element and a second electrode connected to the second power supply line, the initialization switching element having a control terminal connected to the one first scanning signal line, or another one of the plurality of first scanning signal lines adjacent to the one scanning signal line in scanning order, or a signal line connected to a control terminal of another switching element other than the write control switching element among switching elements included in the pixel circuit, a current path extending from the one data signal line via the write control switching element to a fixed voltage line is formed when a voltage of the one data signal line is to be written to the pixel circuit as a data voltage, the current path including: a write destination capacitive element provided in series with the write control switching element; and a pause control switching element provided in series with the write control switching element and the write destination capacitive element,The pause control switching element has a control terminal connected to a signal line connected to a control terminal of another switching element, which is neither the write control switching element nor the initialization switching element, among the switching elements included in the pixel circuit.

[0009] a display device according to some embodiments of the present invention, comprising: a display unit including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of light-emitting control lines, a first power supply line, a second power supply line, an initialization voltage line for supplying a predetermined fixed voltage as an initialization voltage, and a plurality of pixel circuits; a data-side driving circuit that generates a plurality of data signals and applies them to the plurality of data signal lines; a scanning-side driving circuit that selectively drives the plurality of first scanning signal lines and selectively drives the plurality of light-emitting control lines; and a display control circuit that controls the data-side driving circuit and the scanning-side driving circuit so that driving periods consisting of refresh frame periods during which voltages of the plurality of data signals are written to the plurality of pixel circuits as data voltages and idle periods consisting of non-refresh frame periods during which writing of data voltages to the plurality of pixel circuits is stopped alternately; the display element includes an emission control switching element provided in series with the display element and having a control terminal connected to one of the plurality of emission control lines; and an initialization switching element, wherein the drive transistor has a first conduction terminal connected to the first power supply line directly or indirectly via at least one element, a second conduction terminal connected to the second power supply line directly or indirectly via at least one element, and a control terminal connected to one of the plurality of data signal lines via at least the write control switching element, and the display element has a first electrode connected to the initialization voltage line via the initialization switching element and a second electrode connected to the second power supply line,the initialization switching element has a control terminal connected to the one first scanning signal line, or another first scanning signal line among the plurality of first scanning signal lines that is adjacent to the one scanning signal line in scanning order, or a signal line that is connected to a control terminal of a switching element other than the write control switching element among the switching elements included in the pixel circuit, a current path from the one data signal line via the write control switching element to a fixed voltage line is formed when a voltage of the one data signal line is to be written to the pixel circuit as a data voltage, the current path including: a write destination capacitive element provided in series with the write control switching element; and a pause control switching element provided in series with the write control switching element and the write destination capacitive element, the pause control switching element having a control terminal connected to a signal line that is connected to a control terminal of a switching element other than the write control switching element or the initialization switching element among the switching elements included in the pixel circuit, The scanning side drive circuit is controlled so that, during the refresh frame period, the pause control switching element is in an on state when the write control switching element is in an on state during a non-light-emitting period in which the display element is in an off state, and is in an off state during the non-refresh frame period while the write control switching element is in an on state during the non-light-emitting period; and the scanning side drive circuit is controlled so that, during the light-emitting period in which the display element is in a light-emitting state, the write control switching element and the initialization switching element are in an off state, and the light-emitting control switching element is in an on state, regardless of whether it is the refresh frame period or the non-refresh frame period.

[0010] a control terminal connected to the first power supply line directly or indirectly via at least one element, a second power supply line directly or indirectly via at least one element, and a control terminal connected to the second power supply line directly or indirectly via at least one element, and a control terminal connected to the first data signal line via at least the write control switching element; a drive transistor configured to control a current flowing through the display element in accordance with a voltage held in the hold capacitor; a write control switching element having a control terminal connected to one of the first scanning signal lines; a light-emitting control switching element provided in series with the display element and having a control terminal connected to the one of the light-emitting control lines; and an initialization switching element; the display element has a first electrode connected to the initialization voltage line via the initialization switching element and a second electrode connected to the second power supply line, the initialization switching element having a control terminal connected to the one first scanning signal line, or another one of the plurality of first scanning signal lines adjacent to the one scanning signal line in scanning order, or a signal line connected to a control terminal of another switching element other than the write control switching element among switching elements included in the pixel circuit, in each of the plurality of pixel circuits, a current path extending from the one data signal line via the write control switching element to a fixed voltage line is formed when a voltage of the one data signal line is to be written to the pixel circuit as a data voltage, the current path including: a write destination capacitive element provided in series with the write control switching element; and a pause control switching element provided in series with the write control switching element and the write destination capacitive element,the pause control switching element has a control terminal connected to a signal line connected to a control terminal of another switching element, other than the write control switching element or the initialization switching element, among the switching elements included in the pixel circuit, and the driving method comprises a pause driving step of generating a plurality of data signals and applying them to the plurality of data signal lines, and driving the plurality of first scanning signal lines and the plurality of light-emitting control lines, so that drive periods consisting of refresh frame periods in which voltages of the plurality of data signals are written to the plurality of pixel circuits as data voltages and pause periods consisting of non-refresh frame periods in which writing of data voltages to the plurality of pixel circuits is stopped appear alternately, the pause driving step comprising: a non-light-emitting period step of driving the plurality of first scanning signal lines and the plurality of light-emitting control lines so that, during the refresh frame periods, the pause control switching element is in an on state when the write control switching element is in an on state during a non-light-emitting period in which the display element is in an off state, and is in an off state during the non-refresh frame periods while the write control switching element is in an on state; Whether it is the refresh frame period or the non-refresh frame period, during the light emission period in which the display element is in an emitting state, the method includes an emission period step in which the plurality of first scanning signal lines and the plurality of light emission control lines are driven so that the write control switching element and the initialization switching element are in an off state and the light emission control switching element is in an on state.

[0011] According to some of the above embodiments of the present invention, a pixel circuit for a display device having a display unit including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of light-emission control lines, a first power supply line, a second power supply line, and an initialization voltage line for supplying a predetermined fixed voltage as an initialization voltage, is provided with a current-driven display element, a holding capacitor, a drive transistor, a write control switching element, a light-emission control switching element, and an initialization switching element, and a current path extending from one of the plurality of data signal lines via the write control switching element to the fixed voltage line is formed when the voltage of the one data signal line is to be written to the pixel circuit as a data voltage, and the current path further includes a pause control switching element provided in series with the write control switching element and the write-destination capacitive element. In such a display device, when pause drive is performed in which drive periods consisting of refresh frame periods and pause periods consisting of non-refresh frame periods alternate, the plurality of first scanning signal lines and the plurality of light-emitting control lines are driven so that, during the refresh frame periods, the pause control switching element is in an on state when the write control switching element is in an on state during the non-light-emitting period, and is in an off state during the non-refresh frame periods while the write control switching element is in an on state during the non-light-emitting period. Furthermore, in either the refresh frame period or the non-refresh frame period, the plurality of first scanning signal lines and the plurality of light-emitting control lines are driven so that, during the light-emitting period, the write control switching element and the initialization switching element are in an off state, and the light-emitting control switching element is in an on state. In driving the plurality of first scanning signal lines and the plurality of light-emitting control lines in this manner, the write control switching element is controlled by one of the plurality of first scanning signal lines, and the light-emitting control switching element is controlled by one of the plurality of light-emitting control lines.Furthermore, the initialization switching element is controlled by the one first scanning signal line, or another first scanning signal line among the plurality of first scanning signal lines that is adjacent to the one first scanning signal line in the scanning order, or a signal line connected to a control terminal of a switching element other than the write control switching element among the switching elements included in the pixel circuit, and the pause control switching element is controlled by a signal line connected to a control terminal of a switching element other than the write control switching element and the initialization switching element among the switching elements included in the pixel circuit. Therefore, even when pause driving is performed, it is possible to appropriately write the data voltage to the holding capacitor and initialize the organic EL element (anode initialization) without increasing the number of control signals (scanning signals, light-emission control signals, etc.) that control the switching elements in the pixel circuit, compared to normal driving in which only refresh frame periods are continuously repeated. This makes it possible to achieve high-resolution image display in a display device that performs pause driving without increasing the size of the scanning drive circuit or the layout area of ​​the pixel circuit.

[0012] FIG. 1 is a block diagram showing the overall configuration of a display device according to a first embodiment. FIG. 2 is a timing chart for explaining a schematic operation in a pause drive mode of the display device according to the first embodiment. FIG. 3 is a circuit diagram showing the configuration of a pixel circuit in a first comparative example. FIG. 4 is a timing chart for explaining the operation in a refresh frame period of the pixel circuit in the first comparative example. FIG. 5 is a timing chart for explaining the operation in a non-refresh frame period of the pixel circuit in the first comparative example. FIG. 6 is a circuit diagram showing the configuration of a pixel circuit in the first embodiment. FIG. 7 is a timing chart for explaining the operation in a refresh frame period of the pixel circuit in the first embodiment. FIG. 8 is a timing chart for explaining the operation in a non-refresh frame period of the pixel circuit in the first embodiment. FIG. 9 is a circuit diagram showing the configuration of a pixel circuit in a display device according to a second embodiment. FIG. 10 is a timing chart for explaining the operation in a refresh frame period of the pixel circuit in the second embodiment. FIG. 11 is a timing chart for explaining the operation in a non-refresh frame period of the pixel circuit in the second embodiment. FIG. 12 is a block diagram showing the overall configuration of a display device according to a third embodiment. FIG. 13 is a circuit diagram showing the configuration of a pixel circuit in the third embodiment. FIG. 14 is a timing chart for explaining the operation in a refresh frame period of the pixel circuit in the third embodiment. FIG. 15 is a timing chart for explaining the operation in a non-refresh frame period of the pixel circuit in the third embodiment. FIG. 10 is a circuit diagram for explaining an operation of the pixel circuit in the third embodiment during a write initialization period. FIG. 11 is a circuit diagram for explaining an operation of the pixel circuit in the third embodiment during a data write period. FIG. 12 is a circuit diagram for explaining an operation of the pixel circuit in the third embodiment during a threshold detection period. FIG. 13 is a circuit diagram for explaining an operation of the pixel circuit in the third embodiment during a threshold compensation period. FIG. 14 is a circuit diagram for explaining an operation of the pixel circuit in the third embodiment during a light emission period. FIG. 15 is a circuit diagram for explaining an operation of the pixel circuit in the third embodiment during an anode initialization period within a non-refresh frame period.FIG. 1 is a circuit diagram showing the configuration of a pixel circuit in a second comparative example. FIG. 2 is a timing chart illustrating the operation of the pixel circuit in the second comparative example during a refresh frame period. FIG. 3 is a timing chart illustrating the operation of the pixel circuit in the second comparative example during a refresh frame period. FIG. 4 is a circuit diagram showing the configuration of a pixel circuit in a third comparative example. FIG. 5 is a timing chart illustrating the operation of the pixel circuit in the third comparative example during a refresh frame period. FIG. 6 is a timing chart illustrating the operation of the pixel circuit in the third comparative example during a non-refresh frame period. FIG. 7 is a circuit diagram showing the configuration of a pixel circuit in a display device according to a fourth embodiment. FIG. 8 is a timing chart illustrating the operation of the pixel circuit in the fourth embodiment during a refresh frame period. FIG. 9 is a timing chart illustrating the operation of the pixel circuit in the fourth embodiment during a non-refresh frame period. FIG. 10 is a circuit diagram showing the configuration of a pixel circuit in a fourth comparative example. FIG. 11 is a timing chart illustrating the operation of the pixel circuit in the fourth comparative example during a refresh frame period. FIG. 12 is a timing chart illustrating the operation of the pixel circuit in the fourth comparative example during a non-refresh frame period. 13 is a timing chart for explaining an operation of the pixel circuit in the fifth embodiment in a non-refresh frame period.

[0013] Hereinafter, embodiments will be described with reference to the accompanying drawings. In each transistor described below, the gate terminal corresponds to the control terminal, one of the drain terminal and the source terminal corresponds to the first conduction terminal, and the other corresponds to the second conduction terminal. Furthermore, although the transistor in each of the following embodiments is, for example, a thin-film transistor, the present invention is not limited thereto. Furthermore, in this specification, "connection" means "electrical connection" unless otherwise specified, and includes not only direct connection but also indirect connection via another element, within the scope of the present invention.

[0014] 1 is a block diagram showing the overall configuration of a display device 10 according to a first embodiment. This display device 10 is an organic EL display device having two operating modes: a normal drive mode and a pause drive mode. That is, in the normal drive mode, the display device 10 operates such that refresh frame periods Trf, in which image data (data voltages in each pixel circuit) of the display unit are successively repeated. In the pause drive mode, the display device 10 operates such that drive periods TDp consisting only of refresh frame periods (hereinafter also referred to as "RF frame periods") Trf and pause periods TPp consisting of multiple non-refresh frame periods (hereinafter also referred to as "NRF frame periods") Tnrf, in which rewriting of image data of the display unit is stopped, alternate.

[0015] As shown in FIG. 1 , this display device 10 includes a display unit 11, a display control circuit 20, a data-side drive circuit 30, a scanning-side drive circuit 40, and a power supply circuit 50. The data-side drive circuit 30 functions as a data signal line drive circuit (also referred to as a “data driver”). The scanning-side drive circuit 40 functions as a scan signal line drive circuit (also referred to as a “gate driver”) and a light-emission control circuit (also referred to as an “emission driver”). In the configuration shown in FIG. 1 , these two scanning-side circuits are implemented as a single scanning-side drive circuit 40, but these two circuits may be appropriately separated, or may be arranged separately on one side and the other side of the display unit 11. Furthermore, at least a portion of the data-side drive circuit and the scanning-side drive circuit may be formed integrally with the display unit 11. These points also apply to other embodiments and modifications described below. The power supply circuit 50 generates a high-level power supply voltage ELVDD, a low-level power supply voltage ELVSS, and an initialization voltage Vini, which will be described later, to be supplied to the display unit 11, as well as power supply voltages (not shown) to be supplied to the display control circuit 20, the data side drive circuit 30, and the scanning side drive circuit 40.

[0016] The display unit 11 is provided with m (m is an integer of 2 or greater) data signal lines D1, D2, ..., Dm and n scanning signal lines SC1, SC2, ..., SCn that intersect with the data signal lines D1, D2, ..., Dm, and n light-emitting control lines (emission lines) EM1 to EMn that are arranged along the n scanning signal lines SC1 to SCn, respectively. The display unit 11 also has m x n pixel circuits 15 arranged in a matrix along the m data signal lines D1 to Dm and the n scanning signal lines SC1 to SCn. Each pixel circuit 15 corresponds to one of the m data signal lines D1 to Dm and one of the n scanning signal lines SC1 to SCn (hereinafter, when distinguishing between pixel circuits 15, the pixel circuit corresponding to the ith scanning signal line and the jth data signal line Dj is also referred to as the "pixel circuit in the ith row and jth column," and is denoted by the symbol "Pix(i, j)"). Each pixel circuit 15 corresponds to one of the n light emission control lines EM1 to EMn.

[0017] The display unit 11 is also provided with power supply lines (not shown) common to each pixel circuit 15. Specifically, a first power supply line (hereinafter referred to as the "high-level power supply line" and denoted by the symbol "ELVDD" like the high-level power supply voltage) is provided as a fixed voltage line for supplying a high-level power supply voltage ELVDD for driving the organic EL elements (described below), and a second power supply line (hereinafter referred to as the "low-level power supply line" and denoted by the symbol "ELVSS" like the low-level power supply voltage) is provided as a fixed voltage line for supplying a low-level power supply voltage ELVSS for driving the organic EL elements. The display unit 11 is also provided with an initialization voltage line (denoted by the symbol "Vini" like the initialization voltage) (not shown) as a fixed voltage line for supplying an initialization voltage Vini used in a reset operation (also referred to as an "initialization operation") for initializing each pixel circuit 15. The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are supplied from a power supply circuit 50.

[0018] The display control circuit 20 receives an input signal Sin from outside the display device 10, which includes image information representing the image to be displayed and timing control information for image display, generates a data-side control signal Scd and a scanning-side control signal Scs based on this input signal Sin, and outputs the data-side control signal Scd to the data-side driving circuit 30 and the scanning-side control signal Scs to the scanning-side driving circuit 40, respectively.

[0019] The data-side drive circuit 30 drives the data signal lines D1 to Dm based on a data-side control signal Scd from the display control circuit 20. That is, the data-side drive circuit 30 generates m data signals D(1) to D(m) representing the image to be displayed based on the data-side control signal Scd and applies them to the data signal lines D1 to Dm, respectively. However, when operating in the pause drive mode, a refresh operation, i.e., writing of data voltages to the pixel circuits Pix(1,1) to Pix(n,m), is not performed during the NRF frame period Tnrf, and therefore the data-side drive circuit 30 does not need to output the data signals D(1) to D(m). For this reason, in this embodiment, the output terminals of the data-side drive circuit 30 that should output the data signals D(1) to D(m) are in a high-impedance state (Hi-Z) (see FIG. 2, described below).

[0020] The scanning side drive circuit 40 functions as a scanning signal line drive circuit that drives the n scanning signal lines SC1 to SCn and as a light emission control circuit that drives the light emission control lines EM1 to EMn based on the scanning side control signal Scs from the display control circuit 20.

[0021] More specifically, during both the refresh frame period Trf and the non-refresh frame period Tnrf, the scanning-side drive circuit 40, as a scanning signal line drive circuit, sequentially selects n scanning signal lines SC1 to SCn for a predetermined period corresponding to one horizontal period based on the scanning-side control signal Scs, applies an active signal to the selected scanning signal line SCk (where k is an integer satisfying 1≦k≦n), and applies an inactive signal to the unselected scanning signal lines. This collectively selects m pixel circuits Pix(k,1) to Pix(k,m) corresponding to the selected scanning signal line SCk. As a result, during the selection period of the scanning signal line SCk (hereinafter referred to as the "kth scanning selection period"), the voltages of m data signals D(1) to D(m) (hereinafter, these voltages may be simply referred to as "data voltages" without distinction) applied from the data-side drive circuit 30 to the data signal lines D1 to Dm are written as pixel data to the pixel circuits Pix(k,1) to Pix(k,m), respectively. 5, in this embodiment, the scanning signal lines SCi are connected to the gate terminals of the N-channel transistors in the pixel circuits 15 (i1=1 to n), so that a high-level (H-level) voltage is applied as an active signal to the selected scanning signal lines SCi, and a low-level (L-level) voltage is applied as an inactive signal to the unselected scanning signal lines SCi. On the other hand, when the scanning signal lines are connected to the gate terminals of the P-channel transistors in the pixel circuits as in other embodiments, an L-level voltage is applied as an active signal to the selected scanning signal lines, and an H-level voltage is applied as an inactive signal to the unselected scanning signal lines.

[0022] Furthermore, during the refresh frame period Trf, the scanning-side drive circuit 40 drives the emission control lines EM1 to EMn so that they are selectively deactivated in conjunction with the driving of the scanning signal lines SC1 to SCn. That is, the scanning-side drive circuit 40, as an emission control circuit, applies an emission control signal indicating non-emission of light to the i-th emission control line EMi during a predetermined period including the i-th horizontal period, and applies an emission control signal indicating emission of light during other periods (i = 1 to n) based on the scanning-side control signal Scs. The organic EL elements in the pixel circuits Pix(i,1) to Pix(i,m) corresponding to the i-th scanning signal line SCi (hereinafter also referred to as "i-th row pixel circuits") emit light at a luminance corresponding to the data voltage written to each of the i-th row pixel circuits Pix(i,1) to Pix(i,m) while the emission control line EMi is in an activated state (in this embodiment, while the voltage of the emission control line EMi is at an H level). The scanning side drive circuit 40 also drives the light emission control lines EM1 to EMn so as to selectively deactivate them during the non-refresh frame period Tnrf (details will be described later).

[0023] <1.2 General Operation> As described above, the display device 10 according to this embodiment has two operation modes: a normal drive mode and a pause drive mode. This embodiment is characterized by the configuration of the pixel circuit for pause drive, so the following description of the operation of the display device and its pixel circuit according to this embodiment will focus on the operation in the pause drive mode (the same applies to other embodiments). First, with reference to FIG. 2, a general operation of the display device 10 in the pause drive mode will be described.

[0024] 2 is a timing chart for explaining an outline of the operation of the display device 10 in the pause drive mode. As shown in Fig. 2, a drive period TDp consisting of only an RF frame period (refresh frame period) Trf and a pause period TPp consisting of a plurality of NRF frame periods (non-refresh frame periods) Tnrf are alternately repeated.

[0025] During the RF frame period Trf constituting the drive period TDp, the scanning-side drive circuit 40 generates scan signals SC(1) to SC(n) that sequentially go high for a predetermined period as shown in FIG. 2 and applies them to the scan signal lines SC1 to SCn, respectively. The scanning-side drive circuit 40 also generates light-emission control signals EM(1) to EM(n) as shown in FIG. 2 that sequentially go inactive (low) in response to the driving of the scan signal lines SC1 to SCn, and applies them to the light-emission control lines EM1 to EMn, respectively. Meanwhile, the data-side drive circuit 30 generates data signals D(1) to D(m) that change in response to the scan signals SC(1) to SC(n), as shown in FIG. 2, based on the data-side control signal Scd from the display control circuit 20, and applies them to the data signal lines D1 to Dm, respectively. In this way, by driving the scanning signal lines SC1 to SCn, the light-emission control lines EM1 to EMn, and the data signal lines D1 to Dm in the display unit 11, initialization and writing of a data voltage to each pixel circuit Pix(i, j) are performed during the non-light-emission period, and each pixel circuit Pix(i, j) emits light at a luminance according to the written data voltage. Note that in the example shown in Figure 2, the drive period TDp is made up of only one RF frame period Trf, but it may be made up of two or more RF frame periods Trf.

[0026] During the NRF frame period Tnrf in the pause period TPp, the scanning side drive circuit 40 drives the scanning signal lines SC1 to SCn in the same manner as in the RF frame period Trf, and also drives the light-emission control lines EM1 to EMn in the same manner as in the RF frame period Trf. However, as shown in FIG. 2 , the drive waveforms of the light-emission control lines EM1 to EMn during the NRF frame period Tnrf, i.e., the waveforms of the light-emission control signals EM(1) to EM(n), are slightly different from the waveforms of the light-emission control signals EM(1) to EM(n) during the RF frame period Trf, and the light-emission control signals EM(1) to EM(n) are maintained at the L level during the non-light-emission period (details will be described later). During the NRF frame period Tnrf, anode initialization is performed during the non-light-emission period in the same way as during the RF frame period, but writing of the data voltage is suppressed (details will be described later).

[0027] In the normal drive mode, the scan-side drive circuit 40 drives the scan signal lines SC1 to SCn and the light-emission control lines EM1 to EMn so that the operation in the RF frame period Trf is continuously repeated. The drive in this RF frame period is the same as the drive in the RF frame period Trf that constitutes the drive period TDp in the pause drive mode.

[0028] The external input signal Sin includes an operation mode signal Sm that indicates whether the display unit 11 is to be driven in the normal drive mode or the pause drive mode described above. This operation mode signal Sm is provided to the scan-side drive circuit 40 as part of the scan-side control signal Scs, and to the data-side drive circuit 30 as part of the data-side control signal Scd. As described above, the scan signal lines SC1 to SCn are driven in the same manner (same cycle and same duty ratio) regardless of whether the drive mode is the normal drive mode or the pause drive mode, and regardless of whether the drive mode is the RF frame period Trf or the NRF frame period Tnrf. On the other hand, the emission control lines EM1 to EMn are driven in slightly different manners between the RF frame period Trf and the NRF frame period Tnrf, as described above, in the pause drive mode, based on the operation mode signal Sm, so that anode initialization is performed during the NRF frame period Tnrf while data writing is suppressed.

[0029] <1.3 Configuration and Operation of Pixel Circuit> Below, we will first explain the configuration and operation of a pixel circuit in a display device as a comparative example of this embodiment (hereinafter also referred to as the "pixel circuit in Comparative Example 1"), and then explain the configuration and operation of pixel circuit 15 in this embodiment while comparing it with the configuration and operation of the pixel circuit in Comparative Example 1. Note that in the display section of the display device as Comparative Example 1, n first scanning signal lines SC11 to SC1n and n second scanning signal lines SC21 to SC2n are arranged instead of the n scanning signal lines SC1 to SCn in the first embodiment. Furthermore, the scanning-side driving circuit in the first comparative example generates n first scanning signals SC1(1) to SC1(n) and n second scanning signals SC2(1) to SC2(n) instead of n scanning signals SC(1) to SC(n), applies the first scanning signals SC1(1) to SC1(n) to the first scanning signal lines SC11 to SC1n, respectively, and applies the second scanning signals SC2(1) to SC2(n) to the second scanning signal lines SC21 to SC2n, respectively. Note that the display device as the first comparative example is a display device that performs pause driving in the same manner as in this embodiment, and the other parts of the display device are the same as those of the display device according to this embodiment, so the same reference numerals are used to designate the same or corresponding parts, and descriptions thereof will be omitted.

[0030] 1.3.1 Configuration and Operation of Pixel Circuit in First Comparative Example FIG. 3 is a circuit diagram showing the configuration of a pixel circuit 15a in the first comparative example. More specifically, it is a circuit diagram showing the configuration of the pixel circuit 15a corresponding to the ith first scanning signal line SC1i and the jth data signal line Dj, i.e., the pixel circuit Pix(i, j) in the ith row and jth column (1≦i≦n, 1≦j≦m). This pixel circuit 15a is the basis of the pixel circuit 15 in this embodiment and includes one organic EL element OL as a display element, four transistors T1 to T4 (hereinafter referred to as the "write control transistor T1," the "drive transistor T2," the "emission control transistor T3," and the "initialization transistor T4"), and one storage capacitor Cst. The transistors T1 to T4 are N-channel transistors. The storage capacitor Cst is a capacitive element having two electrodes, a first electrode and a second electrode. In the pixel circuit 15, the transistors T1, T3, and T4, other than the drive transistor T2, function as switching elements.

[0031] To the pixel circuit Pix(i, j), there are connected a corresponding first scanning signal line SC1i (hereinafter, also referred to as a "corresponding first scanning signal line" in the description focusing on the pixel circuit), a corresponding second scanning signal line SC2i (hereinafter, also referred to as a "corresponding second scanning signal line" in the description focusing on the pixel circuit), a corresponding light emission control line EMi (hereinafter, also referred to as a "corresponding light emission control line" in the description focusing on the pixel circuit), a corresponding data signal line Dj (hereinafter, also referred to as a "corresponding data signal line" in the description focusing on the pixel circuit), an initialization voltage line Vini, a high-level power supply line ELVDD, and a low-level power supply line ELVSS.

[0032] 3 , in the pixel circuit Pix(i, j) of the first comparative example, the drive transistor T2 has a drain terminal connected to the high-level power line ELVDD, a source terminal connected to the anode electrode of the organic EL element OL via the emission control transistor T3, and a gate terminal connected to the corresponding data signal line Dj via the write control transistor T1 and to the source terminal of the drive transistor T2 via the storage capacitor Cst. The anode electrode of the organic EL element OL is also connected to the initialization voltage line Vini via the initialization transistor T4, and the cathode electrode of the organic EL element OL is connected to the low-level power line ELVSS. The gate terminal of the write control transistor T1 is connected to the corresponding first scanning signal line SC1i, the gate terminal of the emission control transistor T3 is connected to the corresponding emission control line EMi, and the gate terminal of the initialization transistor T4 is connected to the corresponding second scanning signal line SC2i. Therefore, the first scanning signal SC1(i), the light-emission control signal EM(i), and the second scanning signal SC2(i) are respectively applied to the gate terminals of the write control transistor T1, the light-emission control transistor T3, and the initialization transistor T4.

[0033] Next, the operation of pixel circuit 15a shown in Fig. 3, i.e., pixel circuit Pix(i,j) in row i and column j in the first comparative example, will be described with reference to Fig. 4A and Fig. 4B in addition to Fig. 3. In this description, it is assumed that the display device of the first comparative example is operating in pause drive mode. Fig. 4A is a timing chart for describing the operation of pixel circuit 15a in the first comparative example during an RF frame period Trf, and Fig. 4B is a timing chart for describing the operation of pixel circuit 15a in the first comparative example during an NRF frame period Tnrf. During the RF frame period Trf, in the pixel circuit Pix(i, j), the period during which the first scanning signal SC1(i) ​​and the second scanning signal SC2(i) are both at L level and the light-emission control signal EM(i) is at H level is the light-emission period during which the organic EL element is in a light-emitting state, and the other periods are non-light-emitting periods during which the organic EL element is in an extinguished state, and the light-emission control signal EM(i) is generally at L level, except for a predetermined period within the non-light-emitting period that is set as the data write period Tw, during which it is at H level. During the NRF frame period Tnrf, as shown in FIG. 4B, the period during which the light-emission control signal EM(i) is at H level is the light-emission period during which the organic EL element is in a light-emitting state, and the period during which the light-emission control signal EM(i) is at L level is the non-light-emitting period during which the organic EL element is in an extinguished state.

[0034] During the RF frame period Trf, the corresponding first scanning signal line SC1i, corresponding second scanning signal line SC2i, and corresponding light-emission control signal line EMi connected to the pixel circuit Pix(i,j) are driven by signals SC1(i), SC2(i), and EM(i), respectively, as shown in FIG. 4A. That is, the first scanning signal SC1(i), which is the signal of the corresponding first scanning signal line SC1i, is at an H level only for a predetermined period provided as a data write period Tw within the non-light-emission period in which the light-emission control signal EM(i) is at an L level, and is at an L level for the rest of the period. The second scanning signal SC2(i), which is the signal of the corresponding second scanning signal line SC2i, is also at an H level only for a predetermined period Tai (hereinafter referred to as the "anode initialization period") provided within the non-light-emission period, and is at an L level for the rest of the period. The pixel circuit Pix(i,j) operates as follows based on these signals SC1(i), SC2(i), and EM(i).

[0035] That is, in the non-light-emitting period, during the data write period Tw, the write control transistor T1, the light-emitting control transistor T3, and the initialization transistor T4 are in the ON state, and the voltage of the corresponding data signal line Dj (the voltage of the data signal D(j)) is written to the holding capacitor Cst as the data voltage Vdata (a voltage of Vdata-Vini is held in the holding capacitor Cst). Also, during the anode initialization period Tai (the same period as the data write period Tw in the example shown in FIG. 4A ), the initialization transistor T4 is in the ON state, so that the anode electrode of the organic EL element OL is initialized with the initialization voltage Vini (the charge accumulated in the organic EL element OL is discharged).

[0036] During the subsequent light emission period, since the write control transistor T1 and the initialization transistor T4 are both in the off state and the light emission control transistor T3 is in the on state, a current I1 corresponding to the data voltage Vdata written to the storage capacitor Cst (the voltage Vdata-Vini stored in the storage capacitor Cst) is supplied from the drive transistor T2 to the organic EL element OL, and the organic EL element OL emits light at a brightness corresponding to this current I1.

[0037] During the NRF frame period Tnrf, the corresponding first scanning signal line SC1i, corresponding second scanning signal line SC2i, and corresponding emission control signal line EMi connected to the pixel circuit Pix(i, j) are driven as shown in FIG. 4B . That is, like the RF frame period Trf, the second scanning signal SC2(i) is at the H level only during the anode initialization period Tai provided within the non-emission period and is at the L level during other periods, whereas the first scanning signal SC1(i) ​​is maintained at the L level, unlike the RF frame period Trf. Therefore, the write control transistor T1 is maintained in the OFF state during the NRF frame period Tnrf, and the initialization transistor T4 is maintained in the ON state only during the anode initialization period Tai. This prevents the data voltage Vdata from being written to the storage capacitor Cst, and initializes the anode during the non-emission period.

[0038] As can be seen from FIG. 4A , when pause driving is not performed (in normal drive mode), the display device is driven so that only RF frame periods are continuous, and therefore, in the pixel circuit 15a, the write control transistor T1 for writing the data voltage Vdata and the initialization transistor T4 for anode initialization can be controlled by the same scan signal. However, as can be seen by comparing FIG. 4A with FIG. 4B , when pause driving is performed, a control signal (SC2) for the initialization transistor T4 is required in addition to the control signal (SC1) for the write control transistor T1 in order to perform anode initialization while suppressing the writing of the data voltage Vdata to the storage capacitor Cst during the NRF frame period. This results in an increase in the scan-side drive circuit and the layout area of ​​the pixel circuit compared to when pause driving is not performed, making it difficult to achieve high-resolution display images. Therefore, the pixel circuit 15 in this embodiment is configured to appropriately write the data voltage Vdata to the storage capacitor Cst and initialize the organic EL element OL (anode initialization) without increasing the control signal, even when pause driving is performed. The pixel circuit 15 according to this embodiment will be described below. Note that the configuration and operation of the pixel circuit 15 according to this embodiment that are not specifically described below are assumed to be the same as those of the pixel circuit according to the first comparative example.

[0039] 5 is a circuit diagram showing the configuration of a pixel circuit 15 according to the present embodiment. More specifically, it is a circuit diagram showing the configuration of the pixel circuit 15 corresponding to the ith scan signal line SCi and the jth data signal line Dj, i.e., the pixel circuit Pix(i, j) in the ith row and jth column (1≦i≦n, 1≦j≦m). Like the pixel circuit 15a in the first comparative example shown in FIG. 3 , this pixel circuit 15 includes an organic EL element OL as a display element, a drive transistor T2, an emission control transistor T3, an initialization transistor T4, and a storage capacitor Cst. However, instead of the write control transistor T1, this pixel circuit 15 includes an N-channel write control transistor T1a as a switching element and an N-channel pause control transistor T1b as a switching element connected in series with the write control transistor T1a, which is different from the pixel circuit 15a in the first comparative example. The gate terminal of the drive transistor T2 is connected to the corresponding data signal line Dj via the pause control transistor T1b and the write control transistor T1a, the gate terminals of the write control transistor T1a and the initialization transistor T4 are connected to the corresponding scan signal line SCi, and the gate terminal of the pause control transistor T1b is connected to the corresponding emission control line EMi. The other configuration of this pixel circuit 15 is the same as that of the pixel circuit 15a in the first comparative example shown in FIG. 3, so description thereof will be omitted.

[0040] Next, the operation of the pixel circuit 15 shown in Fig. 5, i.e., the pixel circuit Pix(i, j) in the ith row and jth column in this embodiment, will be described with reference to Fig. 6A and Fig. 6B in addition to Fig. 5. Fig. 6A is a timing chart for explaining the operation of the pixel circuit 15 in this embodiment during an RF frame period Trf, and Fig. 6B is a timing chart for explaining the operation of the pixel circuit 15 in this embodiment during an NRF frame period Tnrf.

[0041] During the RF frame period Trf, the corresponding scanning signal line SCi and corresponding light-emission control signal line EMi connected to the pixel circuit Pix(i,j) are driven by the scanning signal SC(i) and light-emission control signal EM(i), respectively, as shown in FIG. 6A. In this embodiment, the period from time t1 to t4 shown in FIG. 6A is a non-light-emission period, and during this period t1 to t4, the light-emission control signal EM(i) is not maintained at L level but is instead at H level for a predetermined period from t2 to t3. The scanning signal SC(i) is at H level during this predetermined period from t2 to t4 and at L level during other periods, and this predetermined period from t2 to t4 is the data write period Tw and also the anode initialization period Tai in this embodiment. The pixel circuit Pix(i,j) in this embodiment operates as follows based on the scanning signal SC(i) and light-emission control signal EM(i).

[0042] That is, during the period t2-t3, which is the data write period Tw and the anode initialization period Tai among the periods t1-t4 corresponding to the non-light-emitting period in the first comparative example, the write control transistor T1a, the pause control transistor T1b, the light-emission control transistor T3, and the initialization transistor T4 are turned on, and the voltage of the corresponding data signal line Dj is written to the storage capacitor Cst as the data voltage Vdata (the voltage Vdata-Vini is stored in the storage capacitor Cst). During this period t2-t3, the initialization transistor T4 is turned on, so that the anode electrode of the organic EL element OL is initialized to the initialization voltage Vini. Note that during this period t2-t3, the light-emission control transistor T3 is on, but the initialization transistor T4 is also on. Therefore, the current I1 from the drive transistor TD flows to the initialization voltage line Vini via the light-emission control transistor T3 and the initialization transistor T4, and the organic EL element OL remains in an unlit state. Therefore, the period t1-t4 is also a non-light-emitting period in this embodiment. Thereafter, during the light emission period when the light emission control signal EM(i) is at H level, the write control transistor T1a and the initialization transistor T4 are both in the off state and the light emission control transistor T3 is in the on state, so that a current I1 corresponding to the data voltage Vdata written to the storage capacitor Cst is supplied from the drive transistor T2 to the organic EL element OL, and the organic EL element OL emits light at a luminance corresponding to this current I1. Note that although the pause control transistor T1b is in the on state during the light emission period, the write control transistor T1a connected in series thereto is in the off state, so the operation of the pixel circuit 15 during this light emission period is substantially the same as the operation of the pixel circuit 15a in the first comparative example.

[0043] During the NRF frame period Tnrf, the corresponding scan signal line SCi and corresponding emission control signal line EMi connected to the pixel circuit Pix(i,j) are driven by the scan signal SC(i) and emission control signal EM(i), respectively, as shown in FIG. 6B . That is, during the NRF frame period Tnrf, the emission control signal EM(i) maintains an L level during the non-emission period (periods t1 to t4), unlike during the RF frame period Trf. Meanwhile, during the NRF frame period Tnrf, the scan signal SC(i) is at an H level only during the anode initialization period (periods t2 to t3) Tai provided within the display periods t1 to t4, as in the RF frame period Trf, and is at an L level during the other periods. As a result, during the anode initialization period Tai, the initialization transistor T4 is in an on state, and the anode electrode of the organic EL element OL is initialized to the initialization voltage Vini. During this anode initialization period Tai, the write control transistor T1a is also turned on by the scanning signal SC(i), but the pause control transistor T1b connected in series to this write control transistor T1a is turned off, so the voltage of the corresponding data signal line Dj is not written to the holding capacitor Cst. Therefore, the holding capacitor Cst holds a voltage (Vdata-Vref) equivalent to the data voltage Vdata written in the immediately preceding RF frame period Trf. Thereafter, during the light emission period from time t4 onwards, the light emission control transistor T3 and the pause control transistor T1b are turned on, but the write control transistor T1a and the initialization transistor T4 are turned off. Therefore, a current I1 corresponding to the data voltage Vdata written to the holding capacitor Cst in the immediately preceding RF frame period Trf is supplied from the drive transistor T2 to the organic EL element OL, and the organic EL element OL emits light at a brightness corresponding to this current I1.

[0044] 5, in the pixel circuit Pix(i, j), the gate terminal of the drive transistor T2 is connected to the corresponding data signal line Dj via the pause control transistor T1b and the write control transistor T1a, which are connected in series. The gate terminal of the write control transistor T1a is connected to the corresponding scan signal line SCi, which is connected to the gate terminal of the initialization transistor T4, and the gate terminal of the pause control transistor T1b is connected to the corresponding emission control line EMi, which is connected to the gate terminal of the emission control transistor T3. With this configuration, when the voltage of the corresponding data signal line Dj (the voltage of the data signal D(j)) is to be written as the data voltage Vdata to the pixel circuit Pix(i,j) during the non-emission period in the RF frame period Trf, a current path is formed in the pixel circuit Pix(i,j) from the corresponding data signal line Dj via the write control transistor T1a, the pause control transistor T1b, the holding capacitor Cst, the emission control transistor T3, and the initialization transistor T4 to the initialization voltage line Vini, and the data voltage Vdata is written to the holding capacitor Cst via this current path (see FIG. 6A ). On the other hand, during the non-emission period in the NRF frame period Tnrf, the pause control transistor T1b is controlled to an off state by the emission control signal EM(i), thereby suppressing the writing of the voltage of the corresponding data signal line Dj to the holding capacitor Cst (see FIG. 6B ). In this way, during the NRF frame period Tnrf, the pause control transistor T1b, which is controlled by the light emission control signal EM(i), suppresses writing of the voltage of the corresponding data signal line to the holding capacitor Cst, so even when pause driving is performed, it is possible to appropriately write the data voltage Vdata to the holding capacitor Cst and initialize (anode initialize) the organic EL element OL without increasing the control signal that controls the transistor in the pixel circuit Pix(i, j).As a result, in a display device that performs pause driving, it is possible to achieve high-definition image display while suppressing increases in the scanning side drive circuit and the layout area of ​​the pixel circuit.

[0045] 2. Second Embodiment Next, an organic EL display device according to a second embodiment will be described. This organic EL display device has the same configuration as the display device according to the first embodiment, except for the configuration of the pixel circuit. Therefore, the following description of the display device according to this embodiment will focus on the configuration and operation of the pixel circuit in this embodiment, and for the configuration of the display device according to this embodiment other than the pixel circuit, the same or corresponding parts will be assigned the same reference numerals, and detailed description will be omitted (see FIGS. 1 and 2).

[0046] 7 is a circuit diagram showing the configuration of a pixel circuit 16 in this embodiment, and more specifically, the configuration of a pixel circuit Pix(i,j) in the ith row and jth column (1≦i≦n, 1≦j≦m). As shown in FIG. 7, this pixel circuit 16 differs from the pixel circuit 15 in the first embodiment (FIG. 5) in which the organic EL element OL is connected to the source side of the drive transistor T2 in that the organic EL element OL is connected to the drain side of the drive transistor T2. The other configuration of this pixel circuit 16 is similar to that of the pixel circuit 15 in the first embodiment, and therefore the same or corresponding parts are designated by the same reference numerals and their description will be omitted.

[0047] FIG. 8A is a timing chart for explaining the operation of the pixel circuit 16 in this embodiment during an RF frame period Trf, and FIG. 8B is a timing chart for explaining the operation of the pixel circuit 15a in this embodiment during an NRF frame period Tnrf.

[0048] 8A and 8B with FIG. 6A and 6B, the scanning signal SC(i) and light-emission control signal EM(i) that respectively drive the corresponding scanning signal line SCi and corresponding light-emission control line EMi connected to pixel circuit 16 in this embodiment, i.e., the signals SC(i) and EM(i) that control the transistors T1a, T1b, T3, and T4 as switching elements included in pixel circuit 16, have the same waveforms as the signals SC(i) and EM(i) that control the transistors T1a, T1b, T3, and T4 as switching elements included in pixel circuit 15 in the first embodiment, and change at the same timing. Therefore, pixel circuit 16 in this embodiment operates in the same way as pixel circuit 15 in the first embodiment.

[0049] 7, 8A, and 8B, when the voltage of the corresponding data signal line Dj is to be written as the data voltage Vdata to the pixel circuit Pix(i,j) during the non-emission period in the RF frame period Trf, a current path is formed in the pixel circuit Pix(i,j) from the corresponding data signal line Dj via the write control transistor T1a, the pause control transistor T1b, and the holding capacitor Cst to the low-level power supply line ELVSS, and the data voltage Vdata is written to the holding capacitor Cst via this current path (see FIG. 8A). On the other hand, during the non-emission period in the NRF frame period Tnrf, the pause control transistor T1b is controlled to an off state by the emission control signal EM(i), thereby suppressing the writing of the voltage of the corresponding data signal line Dj to the holding capacitor Cst (see FIG. 8B). Therefore, in this embodiment as well, when pause driving is performed, the data voltage Vdata can be written to the holding capacitor Cst and the organic EL element OL can be initialized (anode initialized) appropriately without increasing the control signal that controls the transistor in the pixel circuit 16, thereby achieving the same effect as in the first embodiment.

[0050] 3. Third Embodiment 3.1 Overall Configuration and General Operation Next, an organic EL display device 10b according to a third embodiment will be described. Like the first embodiment, the organic EL display device 10b according to this embodiment has two operating modes: a normal drive mode and a pause drive mode. In the pause drive mode, the display device operates such that a drive period TDp consisting of one or more RF frame periods Trf and a pause period TPp consisting of multiple NRF frame periods Tnrf alternate (see FIG. 2 ). Note that the configuration and operation of the display device 10b according to this embodiment that are not newly described below are assumed to be the same as those of the display device 10 according to the first embodiment.

[0051] 9 is a block diagram showing the overall configuration of a display device 10b according to this embodiment. Similar to the first embodiment, this display device 10b also includes a display unit 11, a display control circuit 20, a data drive circuit 30, a scan drive circuit 40, and a power supply circuit 50. However, in this display device 10b, instead of the n scanning signal lines SC1 to SCn in the first embodiment, n first scanning signal lines SC11 to SC1n, n second scanning signal lines SC21 to SC2n, and n third scanning signal lines SC31 to SC3n are arranged in the display unit 11, and a scanning-side drive circuit 40 generates first scanning signals SC1(1) to SC1(n) and applies them to the first scanning signal lines SC11 to SC1n, respectively, generates second scanning signals SC2(1) to SC2(n) and applies them to the second scanning signal lines SC21 to SC2n, respectively, and generates third scanning signals SC3(1) to SC3(n) and applies them to the third scanning signal lines SC31 to SC3n, respectively. The display unit 11 is provided with m×n pixel circuits 17 arranged in a matrix along the m data signal lines D1 to Dm and the n first scanning signal lines SC11 to SC1n. Furthermore, n+1 light emission control lines EM1, EM2, ..., EMn, EM1n+1 are arranged in the display unit 11. Each pixel circuit 17 corresponds to one of the n first scanning signal lines SC11 to SC1n, one of the n second scanning signal lines SC21 to SC2n, one of the n third scanning signal lines SC31 to SC3n, and one of the n light emission control lines EM1 to EMn.

[0052] As in the first embodiment, the display unit 11 is provided with a high-level power supply line ELVDD, a low-level power supply line ELVSS, and an initialization voltage line Vini as fixed voltage lines common to each pixel circuit 17. In addition, in this embodiment, a reference voltage line (denoted by the symbol "Vref" like the reference voltage) is provided as a fixed voltage line (not shown) for supplying a reference voltage Vref in an initialization operation and a data write operation (to be described later) in each pixel circuit 17. The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, the initialization voltage Vini, and the reference voltage Vref are supplied from a power supply circuit 50.

[0053] As in the first embodiment described above (see FIG. 1), the display control circuit 20 receives an input signal Sin from outside the display device 10, which includes image information representing the image to be displayed and timing control information for image display, generates a data-side control signal Scd and a scanning-side control signal Scs based on this input signal Sin, and outputs the data-side control signal Scd to the data-side drive circuit 30 and the scanning-side control signal Scs to the scanning-side drive circuit 40, respectively.

[0054] The data-side drive circuit 30 is substantially the same as that in the first embodiment, and therefore its description will be omitted. Unlike the first embodiment, the scan-side drive circuit 40 functions as a scan signal line drive circuit that drives n first scan signal lines SC11 to SC1n, n second scan signal lines SC21 to SC2n, and n third scan signal lines SC31 to SC3n, and as a light-emission control circuit that drives n+1 light-emission control lines EM1 to EMn+1.

[0055] In the pause drive mode, the data-side drive circuit 30 and the scanning-side drive circuit 40 generate data signals, scan signals, and the like as drive signals for operating the pixel circuits Pix(1,1) to Pix(n,m) so that drive periods TDp consisting of one or more RF frame periods Trf and pause periods TPp consisting of multiple NRF frame periods Tnrf alternate (see FIG. 2 ). In this embodiment, the scanning-side drive circuit 40 generates, as the drive signals, second scan signals SC2(1) to SC2(n) and third scan signals SC3(1) to SC3(n) in addition to first scan signals SC1(1) to SC1(n), which correspond to the scan signals SC(1) to SC(n) in the first embodiment. The second scanning signals SC2(1) to SC2(n) and the third scanning signals SC3(1) to SC3(n) have different forms (signal change timing) in the RF frame period Trf and the NRF frame period Tnrf in the pause drive mode, and these will be described in detail later (see FIGS. 11A and 11B, which will be described later). In addition, in this embodiment, the scan-side drive circuit 40 generates n+1 light-emission control signals EM(1) to EM(n+1) instead of the n light-emission control signals EM(1) to EM(n) in the first embodiment (details will be described later with reference to FIGS. 11A and 11B).

[0056] 3.2 Pixel Circuit Configuration FIG. 10 is a circuit diagram showing the configuration of a pixel circuit 17 according to this embodiment, more specifically, the configuration of a pixel circuit Pix(i,j) in the ith row and jth column (1≦i≦n, 1≦j≦m). Unlike the pixel circuit 15 according to the first embodiment, this pixel circuit 17 has a function to compensate for variations and fluctuations in the threshold voltage of its internal drive transistor (hereinafter referred to as an “internal compensation function”). As shown in FIG. 10 , like the pixel circuit 15 according to the first embodiment, this pixel circuit 17 includes a write control transistor T1a, a pause control transistor T1b, a drive transistor T2, an emission control transistor T3, an initialization transistor T4, and a storage capacitor Cst. In addition, the pixel circuit 17 includes a write capacitor short-circuiting transistor T5, a reference voltage supply transistor T6, and a power supply transistor T7 as switching elements, as well as a write capacitor Cw. In the pixel circuit 15 of the first embodiment, the capacitive element to which the voltage of the corresponding data signal line Dj is to be written as the data voltage Vdata, i.e., the capacitive element to which it is to be written, is the holding capacitor Cst, but in the pixel circuit 17 of this embodiment, it is the writing capacitor Cw.

[0057] 9 and 10 , the pixel circuit Pix(i, j) in the i-th row and j-th column in this embodiment is connected to a corresponding first scanning signal line (corresponding first scanning signal line) SC1i, a corresponding second scanning signal line (corresponding second scanning signal line) SC2i, a corresponding third scanning signal line (corresponding third scanning signal line) SC3i, a corresponding light emission control line (corresponding light emission control line) EMi, an light emission control line immediately after the corresponding light emission control line EMi (hereinafter, in the description focusing on the pixel circuit, this will be referred to as the “subsequent light emission control line”) EMi+1, a corresponding data signal line (corresponding data signal line) Dj, an initialization voltage line Vini, a reference voltage line Vref, a high-level power supply line ELVDD, and a low-level power supply line ELVSS.

[0058] 10 , in this pixel circuit Pix(i,j), a write capacitor Cw is connected in series to a storage capacitor Cst, one end of the write capacitor Cw is connected to the gate terminal of a drive transistor T2, and the gate terminal of the drive transistor T2 is connected to the source terminal of the drive transistor T2 via the write capacitor Cw and the storage capacitor Cst. A write capacitor short-circuiting transistor T5 is connected in parallel to the write capacitor Cw, and when the write capacitor short-circuiting transistor T5 is turned on, both ends of the write capacitor Cw are short-circuited. A node Na corresponding to the connection point between the write capacitor Cw and the storage capacitor Cst is connected to a reference voltage line Vref via a reference voltage supply transistor T6. The drain terminal of the drive transistor T2 is connected to a high-level power supply line ELVDD via a power supply transistor T7. Furthermore, a corresponding first scanning signal line SC1i is connected to the gate terminals of the write control transistor T1a and the initialization transistor T4, a corresponding second scanning signal line SC2i is connected to the gate terminals of the reference voltage supply transistor T6 and the pause control transistor T1b, a corresponding third scanning signal line SC3i is connected to the gate terminal of the write capacitor short-circuit transistor T5, and a subsequent light-emission control line EMi+1 is connected to the gate terminal of the power supply transistor T7. Other configurations of this pixel circuit 17 (Pix(i,j)) are the same as those of the pixel circuit 15 in the first embodiment shown in FIG. 5, and therefore description thereof will be omitted.

[0059] 10, that is, the operation of the pixel circuit Pix(i,j) in the ith row and jth column in this embodiment will be described with reference to Fig. 11A, Fig. 11B, and Fig. 12A to Fig. 12F in addition to Fig. 10. In this description, it is assumed that the display device 10b according to this embodiment is operating in the pause drive mode.

[0060] FIG. 11A is a timing chart for explaining the operation of the pixel circuit 17 in this embodiment during an RF frame period Trf, and FIG. 11B is a timing chart for explaining the operation of the pixel circuit 17 in this embodiment during an NRF frame period Tnrf.

[0061] 11A , the operation of the pixel circuit 17 in this embodiment during an RF frame period (refresh frame period) Trf will be described. During the RF frame period Trf, the corresponding first scanning signal line SC1i, the corresponding second scanning signal line SC2i, the corresponding third scanning signal line SC3i, the corresponding light-emission control signal line EMi, and the subsequent light-emission control line EMi+1, which are connected to the pixel circuit Pix(i, j), are driven by the first scanning signal SC1(i), the second scanning signal SC2(i), the third scanning signal SC3(i), the light-emission control signal EM(i), and the light-emission control signal EM(i+1), respectively, as shown in FIG. 11A, the period from time t1 to t8 is a non-light-emitting period in which the organic EL element OL is in an off state in this embodiment, and the light-emitting control signal (hereinafter also referred to as the "corresponding light-emitting control signal") EM(i) applied to the corresponding light-emitting control line EMi is at an H level except for periods t1 to t7 within the non-light-emitting period, and within the period t1 to t7, it is at an H level only for periods t4 to t5 and is at an L level for the rest of the period. During period t4 to t5 when the corresponding light-emitting control signal EM(i) is at an H level, the first scanning signal SC1(i) ​​is also at an H level, and this first scanning signal SC1(i) ​​is maintained at an L level except for periods t4 to t5. As shown in FIG. 11A, the light-emitting control signal (hereinafter also referred to as the "subsequent light-emitting control signal") EM(i+1) applied to the subsequent light-emitting control line EMi+1 is at an H level except for periods t2 to t8, and within the period t2 to t8, it is at an H level only for periods t5 to t6 and is at an L level for the rest of the period. Since the corresponding light-emission control signal EM(i) is applied to the gate terminal of the light-emission control transistor T3 and the subsequent light-emission control signal EM(i+1) is applied to the gate terminal of the power supply transistor T7, the organic EL element OL is in an extinguished state during a period in which at least one of the corresponding light-emission control signal EM(i) and the subsequent light-emission control signal EM(i+1) is at the L level (see FIG. 10). Therefore, in the example shown in FIG. 11A, as described above, the period t1 to t8 is a non-light-emission period, and periods other than the periods t1 to t8 are light-emission periods in which the organic EL element OL is in an emitting state.

[0062] In this embodiment, the non-emission period in the RF frame period Trf is provided in the following order: a write initialization period Twi, a data write period Tw, a threshold detection period Tth, and a threshold compensation period Tcm. In the example shown in FIG. 11A , the period t3 to t4 is the write initialization period Twi, the period t4 to t5 is the data write period Tw, the period t5 to t6 is the threshold detection period Tth, and the period t6 to t7 is the threshold compensation period Tcm.

[0063] 11A, the first scanning signal SC1(i) ​​is at H level only during period t4 to t5 and at L level the rest of the time, the second scanning signal SC2(i) is at L level only during period t3 to t7 and at H level the rest of the time, and the third scanning signal SC3(i) is at L level only during period t4 to t6 and at H level the rest of the time. The signals SC1(i) ​​to SC3(i), EM(i), and EM(i+1) shown in FIG. 11A cause the pixel circuit Pix(i,j) to operate as follows:

[0064] During the write initialization period Twi (period t3 to t4), the first scanning signal SC1(i) ​​is at an L level, the second scanning signal SC2(i) and the third scanning signal SC3(i) are at an H level, and the corresponding light-emission control signal EM(i) and the subsequent light-emission control signal EM(i+1) are at an L level. FIG. 12A shows the state of the pixel circuit Pix(i,j) during this write initialization period Twi. In FIG. 12A, dotted circles and dotted x marks are used to indicate the on / off state of each transistor functioning as a switching element. A dotted circle indicates that the transistor within it is in an on state, and a dotted x mark indicates that the transistor with the dotted circle is in an off state. This representation method is also used in FIGS. 12B to 12F. 12A, the write capacitor Cw is initialized with both ends shorted and given the reference voltage Vref, and the voltage of the node Na (the connection point between the write capacitor Cw and the hold capacitor Cst) becomes Vref. Hereinafter, this operation of the pixel circuit Pix(i,j) during the write initialization period Twi is referred to as "write initialization."

[0065] During the next period from t4 to t5, i.e., the data write period Tw, the first scanning signal SC1(i) ​​and the second scanning signal SC2(i) are at the H level, the third scanning signal SC3(i) is at the L level, the corresponding light-emission control signal EM(i) is at the H level, and the subsequent light-emission control signal EM(i+1) is at the L level. Figure 12B shows the state of the pixel circuit Pix(i,j) during this data write period Tw. During the data write period Tw, the pixel circuit Pix(i,j) is in the state shown in Figure 12B, so that the voltage of the corresponding data signal line is applied as the data voltage Vdata to the gate terminal of the drive transistor T2 (hereinafter, a node including this gate terminal will be referred to as "node Ng"), the reference voltage Vref is applied to the node Na, and the initialization voltage Vini is applied to the source terminal of the drive transistor T2. As a result, the data voltage Vdata is written to the write capacitor Cw via the current path indicated by the thick dotted line in FIG. 12B, causing the write capacitor Cw to hold a voltage Vdata-Vref, and the hold capacitor Cst to hold a voltage Vref-Vini. Furthermore, because the initialization transistor T4 is in the on state, the initialization voltage Vini is applied to the anode electrode of the organic EL element OL, thereby performing anode initialization. In this manner, during the data write period Tw, a data write operation is performed in which the voltage of the corresponding data signal line Dj is written to the write capacitor Cw as the data voltage Vdata, and anode initialization is also performed. Therefore, the data write period Tw in the RF frame period trf also serves as the anode initialization period Tai.

[0066] During the next period t5 to t6, i.e., the threshold detection period Tth, the first scanning signal SC1(i) ​​and the third scanning signal SC3(i) are at the L level, the second scanning signal SC2(i) is at the H level, the corresponding light-emission control signal EM(i) is at the L level, and the subsequent light-emission control signal EM(i+1) is at the H level. Figure 12C shows the state of the pixel circuit Pix(i,j) during this threshold detection period Tth. During the threshold detection period Tth, the pixel circuit Pix(i,j) is in the state shown in Figure 12C, so that the node Ng is in a floating state, the reference voltage Vref is applied to the node Na, the drain terminal of the drive transistor T2 is electrically connected to the high-level power supply line ELVDD, and the source terminal of the drive transistor T2 is electrically disconnected from the organic EL element OL and the initialization transistor T4. Immediately before this threshold detection period Tth, the drive transistor T2 is in an on state because its gate-source voltage Vgs is Vdata-Vini (see FIG. 12B), which is sufficiently greater than its threshold voltage Vth. Therefore, during the threshold detection period Tth, current flows from the high-level power supply line ELVDD to the holding capacitor Cst via the power supply transistor T7 and the drive transistor T2, causing the holding voltage of the holding capacitor Cst to drop from Vref-Vini, and accordingly, the gate-source voltage Vgs of the drive transistor T2 also drops. The flow of current into the holding capacitor Cst stops when this gate-source voltage Vgs drops to the threshold voltage Vth of the drive transistor T2. Therefore, at the end time t6 of the threshold detection period Tth, the gate-source voltage Vgs of the drive transistor T2 is equal to its threshold voltage Vth. This operation of the pixel circuit Pix(i, j) during the threshold detection period Tth is called "threshold detection" or "threshold sampling."

[0067] During the next period t6 to t7, i.e., the threshold compensation period Tcm, the first scanning signal SC1(i) ​​is at the L level, the second scanning signal SC2(i) and the third scanning signal SC3(i) are at the H level, and the corresponding light-emission control signal EM(i) and the subsequent light-emission control signal EM(i+1) are at the L level. FIG. 12D shows the state of the pixel circuit Pix(i,j) during this threshold compensation period Tcm. When the pixel circuit Pix(i,j) reaches the state shown in FIG. 12D, both ends of the writing capacitor Cw are shorted. Note that during the threshold compensation period Tcm, as during the threshold detection period Tth, the node Na is still supplied with the reference voltage Vref. As can be seen from the threshold detection operation described above, immediately before this threshold compensation period Tcm, the writing capacitor Cw holds a voltage Vdata-Vref, and the gate-source voltage Vgs of the drive transistor T2 is equal to the threshold voltage Vth. Therefore, the following voltage is held in the holding capacitor Cst: Vth - (Vdata - Vref) = Vref - (Vdata - Vth) ... (1) During the threshold compensation period Tcm, the ends of the write capacitor Cw are short-circuited, so that the gate-source voltage Vgs of the drive transistor T2 becomes equal to the holding voltage of the holding capacitor Cst, and Vgs = Vref - (Vdata - Vth) ... (2).

[0068] At time t7, when the threshold detection period Tth ends, the corresponding light-emission control signal EM(i) transitions to an H level. At a subsequent time t8, the subsequent light-emission control signal EM(i+1) also transitions to an H level, ending the non-light-emission period and starting the light-emission period. During this light-emission period, the first scanning signal SC1(i) ​​and the second scanning signal SC2(i) are at an L level, the third scanning signal SC3(i) is at an H level, and the corresponding light-emission control signal EM(i) and the subsequent light-emission control signal EM(i+1) are at an H level. Figure 12E shows the state of the pixel circuit Pix(i,j) during this light-emission period. When the pixel circuit Pix(i,j) transitions to the state shown in Figure 12E, both the light-emission control transistor T3 and the power supply transistor T7 are turned on, causing a current I1 to flow from the high-level power supply line ELVDD to the low-level power supply line ELVSS via the power supply transistor T7, the drive transistor T2, the light-emission control transistor T3, and the organic EL element OL. This current I1 is the drive current for the organic EL element OL, and the organic EL element OL emits light at a luminance corresponding to this drive current I1. Since the drive transistor T2 operates in the saturation region, this drive current I1 is given by the following formula: I1=(β / 2)(Vgs-Vth) 2 ...(3) β=μ×(W / L)×Cox ...(4) In the above formulas (3) and (4), Vth, μ, W, L, and Cox represent the threshold voltage, mobility, gate width, gate length, and gate insulating film capacitance per unit area of ​​the driving transistor T2, respectively. Substituting the above formula (2) into the above formula (3), the following formula is obtained: I1=(β / 2)(Vref-Vdata) 2 …(5)

[0069] According to the above formula (5), the drive current I1 does not depend on the threshold voltage Vth. Therefore, during the light-emitting period, the organic EL element OL emits light with a luminance corresponding to the data voltage Vdata applied from the corresponding data signal line Dj, regardless of the threshold voltage Vth of the drive transistor T2.

[0070] 11B , the operation of the pixel circuit 17 in the NRF frame period (non-refresh frame period) Tnrf in this embodiment will be described. During the NRF frame period Tnrf, the corresponding first scanning signal line SC1i, the corresponding second scanning signal line SC2i, the corresponding third scanning signal line SC3i, the corresponding light-emission control signal line EMi, and the subsequent light-emission control line EMi+1 connected to the pixel circuit Pix(i, j) are driven by the first scanning signal SC1(i), the second scanning signal SC2(i), the third scanning signal SC3(i), the corresponding light-emission control signal EM(i), and the subsequent light-emission control signal EM(i+1), respectively, as shown in FIG. 11B . As shown in FIG. 11B , during the NRF frame period Tnrf, the corresponding light-emission control signal EM(i) and the subsequent light-emission control signal EM(i+1) change at the same timing as during the RF frame period Trf. Therefore, even in the NRF frame period Tnrf, the periods t1 to t8 shown in FIG. 11B are non-light emitting periods, and periods other than the periods t1 to t8 are light emitting periods in which the organic EL element OL is in a light emitting state.

[0071] As shown in FIG. 11B , the first scanning signal SC1(i) ​​is at an H level only during the period t4 to t5 and at an L level during the other periods. The second scanning signal SC2(i) is maintained at an L level regardless of whether it is an emission period or a non-emission period, and the third scanning signal SC3(i) is maintained at an H level regardless of whether it is an emission period or a non-emission period. The period t4 to t5 corresponds to the anode initialization period Tai, as with the RF frame period Trf. During the NRF frame period Tnrf, the off-state pause control transistor T1b suppresses writing of the data voltage Vdata to the pixel circuit Pix(i,j), and the NRF frame period Tnrf does not include any of the write initialization period Twi, data writing period Tw, threshold detection period Tth, and threshold compensation period Tcm.

[0072] 11B, regardless of whether it is a light-emitting period or a non-light-emitting period, the pause control transistor T1b and the reference voltage supply transistor T6 are in the off state, and the write capacitor short-circuit transistor T5 is in the on state. Therefore, the voltage Vref-(Vdata-Vth) held in the holding capacitor Cst during the immediately preceding RF frame period Trf is held as is and continues to be applied between the gate and source of the drive transistor T2.

[0073] During the non-light-emitting period, at least one of the light-emitting control transistor T3 and the power supply transistor T7 is in an off state, so the organic EL element does not emit light. During the non-light-emitting period, the first scanning signal SC1(i) ​​is at an H level only during the anode initialization period Tai. Figure 12F shows the state of the pixel circuit Pix(i,j) during this anode initialization period Tai. When the pixel circuit Pix(i,j) reaches the state shown in Figure 12F, the voltage Vref-(Vdata-Vth) held in the holding capacitor Cst during the immediately preceding RF frame period Trf is maintained and continues to be applied between the gate and source of the drive transistor T2, and the initialization voltage Vini is applied to the anode electrode of the organic EL element OL, performing anode initialization.

[0074] Then, at time t8, the non-light-emitting period ends and the light-emitting period begins. During this light-emitting period, the voltage Vref-(Vdata-Vth) held in the holding capacitor Cst during the immediately preceding RF frame period Trf remains applied between the gate and source of the drive transistor T2 (see equation (2) above), and, as in the light-emitting period during the immediately preceding RF frame period Trf, a drive current I1 based on this voltage Vref-(Vdata-Vth) flows to the organic EL element OL (see equations (2) and (5) above), causing the organic EL element OL to emit light at a luminance corresponding to this drive current I1.

[0075] 3.4 Comparative Example The pixel circuit 17 in this embodiment has a configuration in which a pause control transistor T1b is provided which is connected in series to the write control transistor T1a, and the gate terminal of the drive transistor T2 is connected to the corresponding data signal line via the pause control transistor T1b and the write control transistor T1a. Below, a display device that does not have such a configuration but has a pixel circuit having the same function as this embodiment and performs pause driving will be described as a second comparative example.

[0076] Fig. 13 is a circuit diagram showing the configuration of a pixel circuit 17a in the second comparative example. In this pixel circuit 17a, the write control transistor T1a and the pause control transistor T1b in the pixel circuit 17 of the present embodiment shown in Fig. 10 are replaced with a single transistor T1a, and a fourth scanning signal line SC4i, one of fourth scanning signal lines SC41 to SC4n newly provided in the second comparative example, is connected to the gate terminal of the initialization transistor T4 instead of the third scanning signal line S3i.

[0077] FIG. 14A is a timing chart for explaining the operation of the pixel circuit 17a in the second comparative example during an RF frame period Trf, and FIG. 14B is a timing chart for explaining the operation of the pixel circuit 17a in the second comparative example during an NRF frame period Tnrf.

[0078] 14A and 14B with 11A and 11B, the first scanning signal SC1(i) ​​in the second comparative example is at the H level only for a predetermined period t4 to t5 within the non-light-emitting period during the RF frame period Trf and is at the L level for the other periods, but unlike the present embodiment, is maintained at the L level for the entire NRF frame period Tnrf. Also, the fourth scanning signal SC4(i) applied to the fourth scanning signal line SC4i connected to the gate terminal of the initialization transistor T4 is at the H level only for the period t4 to t5 included in the non-light-emitting period during both the RF frame period Trf and the NRF frame period Tnrf and is at the L level for the other periods.

[0079] The first scanning signal line SC1i, the second scanning signal line SC2i, the third scanning signal line SC3i, the fourth scanning signal line SC4i, the corresponding light-emission control line EMi, and the subsequent light-emission control line EMi+1 connected to the pixel circuit 17a in the second comparative example are driven as shown in Figures 14A and 14B. This causes the pixel circuit 17a to function in the same way as the pixel circuit 17 in this embodiment. However, in the second comparative example, in addition to the first to third scanning signal lines SC11 to SC1n, SC21 to SC2n, and SC31 to SC3n in this embodiment, a fourth scanning signal line SC41 to SC4n is newly required, which results in an increase in the scanning-side drive circuit and an increase in the layout area of ​​the pixel circuit.

[0080] <3.5 Effects> According to the present embodiment as described above, as shown in FIG. 10 , in the pixel circuit Pix(i, j), the gate terminal of the drive transistor T2 is connected to the corresponding data signal line Dj via the pause control transistor T1b and the write control transistor T1a which are connected to each other in series, the gate terminal of the write control transistor T1a is connected to the corresponding first scanning signal line SC1i which is connected to the gate terminal of the initialization transistor T4, and the gate terminal of the pause control transistor T1b is connected to the corresponding second scanning signal line SC2i.

[0081] In addition, in this embodiment, as shown in FIG. 10, a write capacitor Cw, a write capacitance short-circuiting transistor T5, a reference voltage supply transistor T6, and a power supply transistor T7 are provided, and the gate terminal of the reference voltage supply transistor T6 is connected to the second scanning signal line SC2i which is connected to the gate terminal of the pause control transistor T1b, the gate terminal of the write capacitance short-circuiting transistor T5 is connected to the third scanning signal line SC3i, and the gate terminal of the power supply transistor T7 is connected to the subsequent light emission control signal EM(i+1), thereby performing the above-mentioned threshold detection and threshold compensation (see FIGS. 12C and 12D). Furthermore, when the voltage of the corresponding data signal line Dj is to be written as the data voltage Vdata to the pixel circuit Pix(i,j) during the non-light-emitting period in the RF frame period Trf, a current path is formed in the pixel circuit Pix(i,j) from the corresponding data signal line Dj through the write control transistor T1a, the pause control transistor T1b, the write capacitor Cw, and the reference voltage supply transistor T6 to the reference voltage line Vref, and the data voltage Vdata is written to the write capacitor Cw via this current path (see FIGS. 11A and 12B). Meanwhile, during the non-light-emitting period in the NRF frame period Tnrf, the pause control transistor T1b is controlled to an off state by the second scan signal SC2(i), thereby suppressing the writing of the voltage of the corresponding data signal line Dj to the write capacitor Cw (see FIGS. 11B and 12F). Therefore, according to this embodiment, threshold compensation is performed within the pixel circuit 17, while achieving the same effects as those of the first embodiment.

[0082] 15 to 18B, an organic EL display device according to a fourth embodiment will be described. The display device according to this embodiment is based on a display device using pixel circuit 18a shown in Fig. 15, which is described in Patent Document 3 (JP 2020-079942 A), and is configured to enable pause driving while suppressing an increase in the scanning side drive circuit and an increase in the layout area of ​​the pixel circuit, thereby realizing high-definition image display.

[0083] <4.1 Third Comparative Example> Before describing this embodiment, a display device using the pixel circuit 18a shown in FIG. 15 will be described as a third comparative example.

[0084] As shown in FIG. 15, the pixel circuit 18a in the third comparative example includes an organic EL element OL as a display element, five P-channel transistors TD, TE1, TE2, TS2, and TS3 (hereinafter referred to as the "drive transistor TD," the "first light-emission control transistor TE1," the "second light-emission control transistor TE2," the "write control transistor TS2," and the "initialization transistor TS3"), one N-channel transistor (hereinafter referred to as the "reference voltage supply transistor") TS1, and a holding capacitor Cst. Also connected to this pixel circuit 18a are a power supply line for a positive power supply VDDEL (hereinafter referred to as the "positive power supply line" and also denoted by the symbol "VDDEL"), a power supply line for a ground power supply VSSEL (hereinafter referred to as the "ground power supply line" and also denoted by the symbol "VSSEL"), a voltage line for supplying a reference voltage Vref (hereinafter referred to as the "reference voltage line" and also denoted by the symbol "Vref"), one data signal line Data of a plurality of data signal lines formed on a predetermined substrate in the display device, one first scanning signal line Scan1 of a plurality of first scanning signal lines formed on the substrate, one second scanning signal line Scan2 of a plurality of second scanning signal lines formed on the substrate, one first light-emitting control line EM1 of a plurality of first light-emitting control lines formed on the substrate, and one second light-emitting control line EM2 of a plurality of second light-emitting control lines formed on the substrate. Of these, the reference voltage line Vref also functions as the initialization voltage line Vini in the first embodiment. In the following, the data signal transmitted by the data signal line Data, the first scanning signal transmitted by the first scanning signal line Scan1, the second scanning signal transmitted by the second scanning signal line Scan2, the first light-emitting control signal transmitted by the first light-emitting control line EM1, and the second light-emitting control signal transmitted by the second light-emitting control line EM2 will also be indicated by the symbols "Data", "Scan1", "Scan2", "EM1", and "EM2", respectively. In this pixel circuit 18a, the transistors TS1 to TS3, TE1, and TE2 other than the drive transistor TD all function as switching elements.

[0085] 15, in this pixel circuit 18a, the drive transistor TD has a source terminal connected to a positive power supply line VDDEL via a first light-emission control transistor and to a data signal line Data via a write control transistor TS2, a drain terminal connected to an anode electrode of the organic EL element OL via a second light-emission control transistor TE2, and a gate terminal connected to a reference voltage line Vref via a reference voltage supply transistor TS1 and to the source terminal of the drive transistor TD via a storage capacitor Cst. The anode electrode of the organic EL element OL is also connected to an initialization voltage line Vini via an initialization transistor T4, and the cathode electrode of the organic EL element OL is connected to a ground power supply line VSSEL. The gate terminal of the reference voltage supply transistor TS1 is connected to a first scanning signal line Scan1, the gate terminals of the write control transistor TS2 and the initialization transistor TS3 are connected to a second scanning signal line Scan2, the gate terminal of the first light-emitting control transistor TE1 is connected to a first light-emitting control line EM1, and the gate terminal of the second light-emitting control transistor TE2 is connected to a second light-emitting control line EM2.

[0086] Next, the operation of the pixel circuit 18a in the third comparative example will be described. In this description, it is assumed that the display device in the third comparative example operates in the pause drive mode.

[0087] FIG. 16A is a timing chart for explaining the operation of the pixel circuit 18a in the third comparative example during an RF frame period Trf, and FIG. 16B is a timing chart for explaining the operation of the pixel circuit 18a in the third comparative example during an NRF frame period Tnrf.

[0088] During the RF frame period Trf, the second light-emission control line EM2, the first light-emission control line EM1, the first scanning signal line Scan1, and the second scanning signal line Scan2 connected to the pixel circuit 18a are driven as shown in FIG. 16A. As a result, during the data write period Tw, which is provided within the non-light-emission period in which the organic EL element OL is in an off state, the write control transistor TS2 and the reference voltage supply transistor TS1 are in an on state, so that the voltage of the data signal line Data is written to the storage capacitor Cst as the data voltage Vdata, and the voltage Vdata-Vref is stored in the storage capacitor Cst. Furthermore, during this data write period Tw, the second light-emission control transistor TE2 is in an off state and the initialization transistor TS3 is in an on state, so that the reference voltage Vref is applied to the anode electrode of the organic EL element OL, thereby performing anode initialization. Therefore, the data write period Tw also serves as the anode initialization period Tai. During the subsequent light-emitting period, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are on, and the write control transistor TS2, the reference voltage supply transistor TS1, and the initialization transistor TS3 are off, causing a current corresponding to the data voltage Vdata written to the holding capacitor Cst during the data write period Tw in the immediately preceding non-light-emitting period to flow through the organic EL element OL, causing the organic EL element OL to emit light at a brightness corresponding to that current.

[0089] During the NRF frame period Tnrf, the second light-emission control line EM2, the first light-emission control line EM1, the first scanning signal line Scan1, and the second scanning signal line Scan2 connected to the pixel circuit 18a are driven as shown in FIG. 16B . As a result, during the anode initialization period Tai provided within the non-light-emission period in which the organic EL element OL is extinguished, the second light-emission control transistor TE2 is in the off state and the initialization transistor TS3 is in the on state, thereby performing anode initialization for the organic EL element OL, as in the RF frame period Trf. However, unlike the RF frame period Trf, the first scanning signal Scan1 is maintained at the L level regardless of whether it is the non-light-emission period or the light-emission period, thereby maintaining the reference voltage supply transistor TS1 in the off state, and therefore the data voltage Vdata is not written to the storage capacitor Cst.

[0090] As can be seen from the above, when performing pause driving in the third comparative example, it is necessary to change the second scanning signal Scan2 that controls the initialization transistor TS3 at the same timing regardless of whether it is the RF frame period Trf or the NRF frame period Tnrf, while changing the first scanning signal Scan1 that controls the reference voltage supply transistor TS1 at different timing depending on whether it is the RF frame period Trf or the NRF frame period Tnrf (changing it during the RF frame period and not during the NRF frame period). Therefore, when performing pause driving in the third comparative example, two types of scanning signals, a first scanning signal and a second scanning signal, are required.

[0091] As can be seen from the above operation of the pixel circuit 18a in the third comparative example (see FIGS. 15, 16A, and 16B), the light-emitting period or the non-light-emitting period is determined by the second light-emitting control signal EM2, and the first light-emitting control signal EM1 can be considered to be a signal that controls the first light-emitting control transistor TE1 so that the supply of the positive power supply VDDEL to the source terminal of the drive transistor TD is stopped for a predetermined period for writing the data voltage and initializing the anode, and the positive power supply VDDEL is supplied to the source terminal of the drive transistor TD during other periods. For this reason, the first light-emitting control transistor TE1 can be called the "power supply transistor TE1," and the first light-emitting control signal EM1 can be called the "power supply control signal EM1," and it can be considered that "plurality of power supply control lines" are formed on the substrate in the display device instead of the plurality of first light-emitting control lines.

[0092] <4.2 Pixel Circuit in Fourth Embodiment> Next, a pixel circuit in a display device according to a fourth embodiment will be described. The display device according to this embodiment differs from the third comparative example in that it does not include the first scanning signal line Scan1 and a circuit for driving it. However, the configuration and operation of the display device according to this embodiment that are not newly described below are assumed to be the same as those of the display device of the third comparative example.

[0093] 17 is a circuit diagram showing the configuration of a pixel circuit 18 according to the present embodiment. Similar to the pixel circuit 18a in the third comparative example shown in FIG. 15 , this pixel circuit 18 includes one organic EL element OL as a display element, a drive transistor TD, first and second light-emission control transistors TE1 and TE2 as power supply transistors, a write control transistor TS2, an initialization transistor TS3, and a storage capacitor Cst. However, this pixel circuit 18 differs from the pixel circuit 18a in the third comparative example in that, instead of the N-channel reference voltage supply transistor TS1, the pixel circuit 18 includes an N-channel reference voltage supply transistor T1c as a switching element and a P-channel pause control transistor T1b as a switching element connected in series with the reference voltage supply transistor T1c, and the gate terminal of the drive transistor T2 is connected to the reference voltage line Vref via the pause control transistor T1b and the reference voltage supply transistor T1c. In the pixel circuit 18, a first light emission control line EM1 is connected to the gate terminal of the reference voltage supply transistor T1c, and a second light emission control line EM2 is connected to the gate terminal of the pause control transistor T1b.

[0094] Next, the operation of the pixel circuit 18 in this embodiment will be described. In this description, it is assumed that the display device according to this embodiment is operating in the pause drive mode.

[0095] FIG. 18A is a timing chart for explaining the operation of the pixel circuit 18 in this embodiment during an RF frame period Trf, and FIG. 18B is a timing chart for explaining the operation of the pixel circuit 18a in this embodiment during an NRF frame period Tnrf.

[0096] 18A , during the RF frame period Trf, the second light-emitting control line EM2 connected to the pixel circuit 18, the first light-emitting control line EM1 serving as a power supply control line, and the second scanning signal line Scan2 are driven. As a result, during the data write period Tw provided within the non-light-emitting period in which the organic EL element OL is in an off state, the write control transistor TS2, the reference voltage supply transistor T1c, and the pause control transistor T1b are in an on state based on the second scanning signal Scan2, the first light-emitting control signal EM1 serving as a power supply control signal, and the second light-emitting control signal EM2. As a result, similar to the third comparative example, the voltage of the data signal line Data is written to the holding capacitor Cst as the data voltage Vdata, and the voltage Vdata-Vref is held in the holding capacitor Cst. During this data write period Tw, the second light-emission control transistor TE2 is in an off state and the initialization transistor TS3 is in an on state based on the second light-emission control signal EM2 and the second scan signal Scan2, so that the reference voltage Vref is applied to the anode electrode of the organic EL element OL, thereby performing anode initialization. Therefore, the data write period Tw also serves as the anode initialization period Tai. During the subsequent light-emission period, the first light-emission control transistor (power supply transistor) TE1 and the second light-emission control transistor TE2 are in an on state, while the initialization transistor TS3, the write control transistor TS2, and the reference voltage supply transistor TS1 are in an off state. As a result, a current corresponding to the data voltage Vdata written to the storage capacitor Cst during the data write period Tw in the immediately preceding non-light-emission period flows through the organic EL element OL, causing the organic EL element OL to emit light at a brightness corresponding to that current.

[0097] During the NRF frame period Tnrf, the second emission control line EM2, the first emission control line (power supply control line) EM1, and the second scanning signal line Scan2 connected to the pixel circuit 18 are driven as shown in FIG. 18B . As a result, during the anode initialization period Tai, which is provided within the non-emission period in which the organic EL element OL is turned off, the second emission control transistor TE2 is turned off and the initialization transistor TS3 is turned on based on the second emission control signal EM2 and the second scanning signal Scan2, thereby performing anode initialization for the organic EL element OL, similar to the RF frame period Trf. However, unlike the RF frame period Trf, during the non-emission period, the second emission control signal EM2 is maintained at an H level, so the pause control transistor T1b is maintained off and the gate terminal of the drive transistor TD is in a floating state. Therefore, during the non-emission period of the NRF frame period Tnrf, the data voltage Vdata is not written to the storage capacitor Cst. During the subsequent light-emitting period, the first light-emitting control transistor (power supply transistor) TE1 and the second light-emitting control transistor TE2 are in the on state and the initialization transistor TS3, the write control transistor TS2, and the reference voltage supply transistor TS1 are in the off state based on the first light-emitting control signal (power supply control signal) EM1, the second light-emitting control signal EM2, and the second scanning signal Scan2. As a result, a current corresponding to the data voltage Vdata written to the holding capacitor Cst during the data write period Tw in the non-light-emitting period of the immediately preceding RF frame period Trf flows to the organic EL element OL, and the organic EL element OL emits light at a brightness corresponding to that current.

[0098] 4.3 Effects According to the present embodiment as described above, when the voltage of the corresponding data signal line Data is to be written as the data voltage Vdata to the pixel circuit 18 during the non-light-emitting period in the RF frame period Trf, a current path is formed in the pixel circuit 18 from the corresponding data signal line Data via the write control transistor TS2, the holding capacitor Cst, the pause control transistor T1b, and the reference voltage supply transistor T1c to the reference voltage line Vref, and the data voltage Vdata is written to the holding capacitor Cst via this current path (see FIG. 18A ). On the other hand, during the non-light-emitting period in the NRF frame period Tnrf, the pause control transistor T1b is controlled to an off state by the second light-emission control signal EM2, thereby suppressing the writing of the voltage of the corresponding data signal line Data to the holding capacitor Cst (see FIG. 18B ). 17 using a P-channel type drive transistor TD, unlike a display device using a conventional pixel circuit 18a (FIG. 15) such as the pixel circuit 18a in the third comparative example, even when pause driving is performed, the data voltage Vdata can be written to the holding capacitor Cst and the organic EL element OL can be initialized (anode initialized) appropriately without increasing the control signal that controls the transistor in the pixel circuit 18. As a result, similar to the first embodiment, even in a display device that performs pause driving and that has a pixel circuit using a P-channel type drive transistor, it is possible to achieve high-definition image display while suppressing an increase in the size of the scanning side drive circuit and an increase in the layout area of ​​the pixel circuit.

[0099] 5. Fifth Embodiment Next, an organic EL display device according to a fifth embodiment will be described with reference to FIGS. 19 to 22B. The display device according to this embodiment is based on a display device using pixel circuit 19a shown in FIG. 19 described in Patent Document 3 (JP 2020-079942 A), and is configured to enable pause driving while suppressing an increase in the scanning-side drive circuit and an increase in the layout area of ​​the pixel circuit, thereby realizing high-resolution image display. However, while transistor TS3 in pixel circuit 19a shown in FIG. 19 is a P-channel type, in a pixel circuit equivalent to pixel circuit 19a described in Patent Document 3, transistor TS3 is an N-channel type. Also, for convenience of explanation, in FIG. 19, the reference symbols of some transistors in pixel circuit 19a have been changed from those in the pixel circuit described in Patent Document 3.

[0100] 5.1 Fourth Comparative Example Before describing this embodiment, a display device using the pixel circuit 19 a shown in Fig. 19 will be described as a fourth comparative example. Note that the configuration and operation of the display device as the fourth comparative example that are not newly described below are assumed to be the same as those of the display device as the third comparative example.

[0101] 19, the pixel circuit 19a in the fourth comparative example includes an organic EL element OL as a display element, four P-channel transistors TD, TE, TS2, and TS3 (hereinafter referred to as the "drive transistor TD," the "emission control transistor TE," the "write control transistor TS2," and the "initialization transistor TS3"), and a storage capacitor Cst. In this pixel circuit 19a, the write control transistor TS2 is an N-channel transistor, but the other transistors TD, TE, and TS3 are all P-channel transistors. Furthermore, the transistors TS2, TS3, and TE other than the drive transistor TD all function as switching elements.

[0102] 19, in this pixel circuit 19a, the drive transistor TD has a source terminal connected to the positive power supply line VDDEL, a drain terminal connected to the anode electrode of the organic EL element OL via the emission control transistor TE, and a gate terminal connected to the data signal line Data via the write control transistor TS2 and to the source terminal of the drive transistor TD via the storage capacitor Cst. The anode electrode of the organic EL element OL is also connected to the initialization voltage line Vini via the initialization transistor T4, and the cathode electrode of the organic EL element OL is connected to the ground power supply line VSSEL. The gate terminal of the write control transistor TS2 is connected to the first scanning signal line Scan1, the gate terminal of the initialization transistor TS3 is connected to the second scanning signal line Scan2, and the gate terminal of the emission control transistor TE is connected to the emission control line EM.

[0103] FIG. 20A is a timing chart for explaining the operation of the pixel circuit 19a in the fourth comparative example during an RF frame period Trf, and FIG. 20B is a timing chart for explaining the operation of the pixel circuit 19a in the fourth comparative example during an NRF frame period Tnrf.

[0104] During the RF frame period Trf, the emission control line EM, the first scanning signal line Scan1, and the second scanning signal line Scan2 connected to the pixel circuit 19a are driven as shown in FIG. 20A . As a result, during the data write period Tw, which is provided within the non-emission period in which the organic EL element OL is turned off, the write control transistor TS2 is in an ON state, so that the voltage of the data signal line Data is written to the storage capacitor Cst as the data voltage Vdata, and the voltage Vdata-VDDEL is stored in the storage capacitor Cst. Furthermore, during this data write period Tw, the emission control transistor TE is in an OFF state and the initialization transistor TS3 is in an ON state, so that the reference voltage Vref is applied to the anode electrode of the organic EL element OL, thereby performing anode initialization. Therefore, the data write period Tw also serves as the anode initialization period Tai. During the subsequent emission period, the emission control signal EM is in an ON state, and the write control transistor TS2 and the initialization transistor TS3 are in an OFF state. As a result, a current corresponding to the data voltage Vdata written to the storage capacitor Cst during the data write period Tw in the immediately preceding non-light emitting period flows to the organic EL element OL, and the organic EL element OL emits light at a luminance corresponding to that current.

[0105] During the NRF frame period Tnrf, the emission control line EM, the first scanning signal line Scan1, and the second scanning signal line Scan2 connected to the pixel circuit 19a are driven as shown in FIG. 22B . As a result, during the anode initialization period Tai, which is provided within the non-emission period in which the organic EL element OL is turned off, the emission control transistor TE is in the off state and the initialization transistor TS3 is in the on state, thereby performing anode initialization for the organic EL element OL, similar to the RF frame period Trf. However, unlike the RF frame period Trf, the first scanning signal Scan1 is maintained at the L level, so the write control transistor TS2 is maintained in the off state. Therefore, during the NRF frame period Tnrf, the data voltage Vdata is not written to the storage capacitor Cst. During the subsequent emission period, the emission control transistor TE is in the on state, and the write control transistor TS2 and the initialization transistor TS3 are in the off state. As a result, a current corresponding to the data voltage Vdata written to the storage capacitor Cst during the data write period Tw in the non-light emitting period of the immediately preceding RF frame period Trf flows to the organic EL element OL, and the organic EL element OL emits light at a brightness corresponding to that current.

[0106] As can be seen from the above, when pause driving is performed in the fourth comparative example, it is necessary to change the second scanning signal Scan2 that controls the initialization transistor TS3 at the same timing regardless of whether it is the RF frame period Trf or the NRF frame period Tnrf, while changing the first scanning signal Scan1 that controls the write control transistor TS2 at different timing depending on whether it is the RF frame period Trf or the NRF frame period Tnrf (changing it during the RF frame period and not during the NRF frame period). Therefore, when pause driving is performed in the fourth comparative example, two types of scanning signals, a first scanning signal and a second scanning signal, are required.

[0107] <5.2 Pixel Circuit in Fifth Embodiment> Next, a pixel circuit in a display device according to a fifth embodiment will be described. The display device according to this embodiment differs from the fourth comparative example in that it does not include the first scanning signal line Scan1 and a circuit for driving it. However, the configuration and operation of the display device according to this embodiment that are not newly described below are assumed to be the same as those of the display device of the fourth comparative example.

[0108] 21 is a circuit diagram showing the configuration of a pixel circuit 19 according to the present embodiment. Similar to the pixel circuit 19a of the fourth comparative example shown in FIG. 19 , this pixel circuit 19 includes one organic EL element OL as a display element, a drive transistor TD, an emission control transistor TE, an initialization transistor TS3, and a storage capacitor Cst. However, this pixel circuit 19 differs from the pixel circuit 19a of the fourth comparative example in that, instead of the N-channel write control transistor TS2, this pixel circuit 19 includes a P-channel write control transistor T1a as a switching element and an N-channel pause control transistor T1b as a switching element connected in series with the write control transistor T1a. The gate terminal of the drive transistor TD is connected to the data signal line Data via the write control transistor T1a and the pause control transistor T1b. The gate terminal of the write control transistor T1a is connected to the second scanning signal line Scan2, and the gate terminal of the pause control transistor T1b is connected to the emission control line EM.

[0109] Next, the operation of the pixel circuit 19 in this embodiment will be described. In this description, it is assumed that the display device according to this embodiment is operating in the pause drive mode.

[0110] FIG. 22A is a timing chart for explaining the operation of the pixel circuit 19 in this embodiment during an RF frame period Trf, and FIG. 22B is a timing chart for explaining the operation of the pixel circuit 19 in this embodiment during an NRF frame period Tnrf.

[0111] During the RF frame period Trf, the emission control line EM and the second scanning signal line Scan2 connected to the pixel circuit 19 are driven as shown in FIG. 22A . As a result, during a data write period Tw (here, the period during which the second scanning signal Scan2 is at an L level) provided within a non-emission period in which the organic EL element OL is in an off state, the write control transistor T1a and the pause control transistor T1b are in an on state. Therefore, similar to the fourth comparative example, the voltage of the data signal line Data is written to the storage capacitor Cst as the data voltage Vdata, and the voltage Vdata-VDDEL is stored in the storage capacitor Cst. Furthermore, during this data write period Tw, based on the emission control signal EM and the second scanning signal Scan2, the emission control transistor TE is in an off state and the initialization transistor TS3 is in an on state. Therefore, the reference voltage Vref is applied to the anode electrode of the organic EL element OL, thereby performing anode initialization. Therefore, the data write period Tw also serves as the anode initialization period Tai. In the subsequent light-emitting period, the light-emitting control transistor TE is in an on state, and the initialization transistor TS3, the write control transistor T1a, and the pause control transistor T1b are in an off state, so that a current corresponding to the data voltage Vdata written to the storage capacitor Cst during the data write period Tw in the immediately preceding non-light-emitting period flows to the organic EL element OL, and the organic EL element OL emits light at a luminance corresponding to that current.

[0112] During the NRF frame period Tnrf, the emission control line EM and the second scanning signal line Scan2 connected to the pixel circuit 19 are driven as shown in FIG. 22B . As a result, during the anode initialization period Tai, which is provided within the non-emission period in which the organic EL element OL is turned off, the emission control transistor TE is turned off and the initialization transistor TS3 is turned on based on the emission control signal EM and the second scanning signal Scan2, thereby performing anode initialization for the organic EL element OL, similar to the RF frame period Trf. However, unlike the RF frame period Trf, at least one of the write control transistor T1a and the pause control transistor T1b is turned off during the non-emission period. Therefore, during the non-emission period of the NRF frame period Tnrf, the data voltage Vdata is not written to the storage capacitor Cst. During the subsequent emission period, the emission control transistor TE is turned on and the initialization transistor TS3, the write control transistor T1a, and the pause control transistor T1b are turned off based on the emission control signal EM and the second scanning signal Scan2. As a result, a current corresponding to the data voltage Vdata written to the storage capacitor Cst during the data write period Tw in the non-light emitting period of the immediately preceding RF frame period Trf flows to the organic EL element OL, and the organic EL element OL emits light at a brightness corresponding to that current.

[0113] 5.3 Effects According to the present embodiment as described above, when the voltage of the corresponding data signal line Data is to be written as the data voltage Vdata to the pixel circuit 19 during the non-emission period in the RF frame period Trf, a current path is formed in the pixel circuit 19 from the corresponding data signal line Data via the write control transistor T1a, the pause control transistor T1b, and the holding capacitor Cst to the positive power supply line VDDEL, and the data voltage Vdata is written to the holding capacitor Cst via this current path (see FIG. 22A ). On the other hand, during the non-emission period in the NRF frame period Tnrf, the pause control transistor T1b is controlled to an off state by the light emission control signal EM, thereby suppressing the writing of the voltage of the corresponding data signal line Data to the holding capacitor Cst (see FIG. 22B ). 21 using a P-channel drive transistor TD, unlike a display device using pixel circuit 19a (FIG. 19) in the fourth comparative example, even when pause driving is performed, the data voltage Vdata can be written to the holding capacitor Cst and the organic EL element OL can be initialized (anode initialized) appropriately without increasing the control signal that controls the transistor in pixel circuit 19. As a result, similar to the first embodiment, a display device that performs pause driving and that has a pixel circuit using a P-channel drive transistor can also achieve high-definition image display while suppressing an increase in the scanning-side drive circuit and an increase in the layout area of ​​the pixel circuit.

[0114] 6. Modifications The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, the following modifications are possible.

[0115] In each of the above embodiments, pixel circuits 15 to 19 include one or both of an N-channel transistor and a P-channel transistor. The P-channel transistors are thin-film transistors (hereinafter referred to as "LTPS-TFTs") having a channel layer formed from, for example, high-mobility low-temperature polysilicon. The N-channel transistors are thin-film transistors (hereinafter referred to as "oxide TFTs") having a channel layer formed from, for example, an oxide semiconductor (typically indium gallium zinc oxide (InGaZnO)) having good off-leakage characteristics. In pixel circuits 15 to 19 in the above embodiments, it is preferable to use an oxide TFT for at least one of the transistors serving as switching elements connected to the drive transistors T2 and TD. For example, it is particularly preferable to use an oxide TFT for at least one of the transistors serving as switching elements connected to the gate terminals of the drive transistors, such as the write control transistor T1a and pause control transistor T1b (see FIG. 5) included in pixel circuit 15 in the first embodiment. This is because oxide TFTs have low leakage current, enabling more stable low-frequency driving. However, the transistors that can be used in the pixel circuit are not limited to LTPS-TFTs and oxide TFTs.

[0116] Furthermore, the channel types of the transistors included in the pixel circuits of the above embodiments may be appropriately changed between P-channel and N-channel types to operate in the same manner. For example, in pixel circuit 17 of the third embodiment shown in Figure 10, transistors T1a, T1b, and T3 to T7 serving as switching elements are all N-channel, but some or all of them may be P-channel transistors. However, it is necessary to match the conductivity types of the write control transistor T1a and the initialization transistor T4, the conductivity types of the pause control transistor T1b and the reference voltage supply transistor T6, and the conductivity types of the light-emission control transistor T3 and the power supply transistor T7.

[0117] Furthermore, the control signals to be supplied to the gate terminals of the transistors serving as switching elements included in pixel circuits 15 to 19 in the above embodiments are not limited to the control signals used in the above embodiments, and other signals having substantially the same functions may be used. For example, in pixel circuit 17 (Pix(i,j)) in the above third embodiment, a first scanning signal SC1(i) ​​is supplied to the gate terminal of initialization transistor T4, and therefore the period during which first scanning signal SC1(i) ​​is at an H level is the anode initialization period Tai. However, instead, a subsequent first scanning signal SC1(i+1) may be supplied to the gate terminal of initialization transistor T4, and the period during which this signal is at an H level may be the anode initialization period Tai.

[0118] In pixel circuits 15 to 19 in each of the above embodiments, when the voltage of a corresponding data signal line, which is a data signal line connected to the pixel circuit, is to be written to the pixel circuit as a data voltage Vdata, a current path from the data signal line via a write control transistor and a holding capacitor Cst or a write capacitor Cw provided in series therewith to a fixed voltage line such as a power supply line or a reference voltage line is formed in the pixel circuit as a current path for charging and discharging the holding capacitor Cst or the write capacitor Cw when writing the data voltage Vdata. However, the present invention is not limited to the configuration of pixel circuits 15 to 19 in each of the above embodiments, and any configuration may be used as long as a pause control transistor T1b is provided as a new switching element in series with other switching elements and the holding capacitor Cst provided in the current path for charging and discharging the holding capacitor Cst or the write capacitor Cw formed in the pixel circuit when writing the data voltage Vdata. With this configuration, even when pause driving is performed, it is possible to properly write the data voltage to the holding capacitor Cst and initialize (anode initialize) the organic EL element OL without increasing the control signals (scanning signals, light-emitting control signals, etc.) for controlling the transistors serving as switching elements included in the pixel circuit. Note that the order (routing order) of elements along such a current path from the corresponding data signal line to the fixed voltage line is not limited to the routing order along the current path in each embodiment, and can be changed as appropriate depending on the configuration of the pixel circuit without departing from the spirit of the invention.

[0119] Although the embodiments have been described above using an organic EL display device as an example, the present invention is not limited to organic EL display devices and can be applied to any display device that uses a current-driven display element and performs pause driving. Display elements that can be used here include, for example, organic EL elements, i.e., organic light-emitting diodes (OLEDs), inorganic light-emitting diodes, quantum dot light-emitting diodes (QLEDs), and the like.

[0120] 10, 10b... Display device 11... Display unit 15-19... Pixel circuit 20... Display control circuit 30... Data side drive circuit (data signal line drive circuit) 40... Scanning side drive circuit (scanning signal line drive circuit / light-emission control circuit) Pix(j, i)... Pixel circuit (i = 1 to n, j = 1 to m) SCi... Scanning signal line (i = 1, 2, ..., n) SC1i... First scan signal line (i = 1, 2, ..., n) SC2i... Second scan signal line (i = 1, 2, ..., n) SC3i... Third scan signal line (i = 1, 2, ..., n) EMi... Light-emission control line (i = 1 to n) EM1i... First light-emission control line (power supply control line) (i = 1 to n) EM2i... Second light-emission control line (i = 1 to n) Dj... Data signal line (j = 1 to m) ELVDD...High-level power supply line, high-level power supply voltage ELVSS...Low-level power supply line, low-level power supply voltage OL...Organic EL element (display element) Cst...Retention capacitor Cw...Write capacitor T1...Write control transistor (write control switching element) T2...Drive transistor T3...Emission control transistor (emission control switching element) T4...Initialization transistor (initialization switching element) T1a...Write control transistor (write control switching element) T1b...Pause control transistor (pause control switching element) TS1...Reference voltage supply transistor (reference voltage supply switching element) TS2...Write control transistor (write control switching element) TS3...Initialization transistor (initialization switching element) T1c...Reference voltage supply transistor (reference voltage supply switching element) TD...Drive period TP...Pause period Trf...Refresh frame period (RF frame period) Tnrf...Non-refresh frame period (NRF frame period)

Claims

1. A pixel circuit for a display device having a display unit including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of light emission control lines, a first power supply line, a second power supply line, and an initialization voltage line for supplying a predetermined fixed voltage as an initialization voltage, comprising: a display element driven by a current; a holding capacitor; a drive transistor for controlling a current flowing to the display element in accordance with a voltage held in the holding capacitor; a write control switching element having a control terminal connected to one of the plurality of first scanning signal lines; a light emission control switching element provided in series with the display element and having a control terminal connected to one of the plurality of light emission control lines; and an initialization switching element; wherein the drive transistor has a first conduction terminal connected directly or indirectly via at least one element to the first power supply line, a second conduction terminal connected directly or indirectly via at least one element to the second power supply line, and a control terminal connected to at least one of the plurality of data signal lines via the write control switching element; the display element has a first electrode connected to the initialization voltage line via the initialization switching element and a second electrode connected to the second power supply line, the initialization switching element has a control terminal connected to the one first scanning signal line, or another one of the plurality of first scanning signal lines adjacent to the one scanning signal line in scanning order, or a signal line connected to a control terminal of another switching element other than the write control switching element among the switching elements included in the pixel circuit, a current path extending from the one data signal line via the write control switching element to a fixed voltage line is formed when a voltage of the one data signal line is to be written to the pixel circuit as a data voltage, the current path including: a write destination capacitive element provided in series with the write control switching element; and a pause control switching element provided in series with the write control switching element and the write destination capacitive element,A pixel circuit, wherein the pause control switching element has a control terminal connected to a signal line connected to a control terminal of another switching element among switching elements included in the pixel circuit, the other switching element being neither the write control switching element nor the initialization switching element.

2. The pixel circuit of claim 1, wherein the write control switching element and the initialization switching element are transistors of the same conductivity type, a control terminal of the initialization switching element is connected to the one first scanning signal line, and the control terminal of the pause control switching element is connected to the one light emission control line.

3. The pixel circuit of claim 2, wherein the first power supply line is a high-voltage power supply line, the second power supply line is a low-voltage power supply line, the write-in capacitive element is the holding capacitor, the drive transistor is an N-channel transistor, the pause control switching element and the emission control switching element are transistors of the same conductivity type, the first electrode of the display element is connected to the second conduction terminal of the drive transistor via the emission control switching element, and the control terminal of the drive transistor is connected to the second conduction terminal of the drive transistor via the holding capacitor and is connected to the one data signal line via the pause control switching element and the write control switching element.

4. The pixel circuit of claim 2, wherein the first power supply line is a low-voltage power supply line, the second power supply line is a high-voltage power supply line, the write-in capacitive element is the holding capacitor, the drive transistor is an N-channel transistor, the pause control switching element and the emission control switching element are transistors of the same conductivity type, the first electrode of the display element is connected to the second conduction terminal of the drive transistor via the emission control switching element, and the control terminal of the drive transistor is connected to the first conduction terminal of the drive transistor via the holding capacitor and is connected to the one data signal line via the pause control switching element and the write control switching element.

5. The pixel circuit of claim 2, wherein the first power supply line is a high-voltage side power supply line, the second power supply line is a low-voltage side power supply line, the write-in capacitive element is the holding capacitor, the drive transistor is a P-channel transistor, the pause control switching element and the emission control switching element are transistors of different conductivity types, the first electrode of the display element is connected to the second conduction terminal of the drive transistor via the emission control switching element, and the control terminal of the drive transistor is connected to the first conduction terminal of the drive transistor via the holding capacitor and is connected to the one data signal line via the write control switching element and the pause control switching element.

6. The display device further comprises a power supply switching element and a reference voltage supply switching element connected in series with the pause control switching element, wherein the display unit further includes a plurality of power supply control lines and a reference voltage line for supplying a predetermined fixed voltage, the reference voltage line is a fixed voltage line also serving as the initialization voltage line, the first power supply line is a high-voltage side power supply line, the second power supply line is a low-voltage side power supply line, the destination capacitive element is the holding capacitor, the drive transistor is a P-channel type transistor, the pause control switching element and the emission control switching element are transistors of the same conductivity type, the first electrode of the display element is connected to the second conduction terminal of the drive transistor via the emission control switching element, and the control terminal of the drive transistor is connected to the first conduction terminal of the drive transistor via the holding capacitor and is connected to the reference voltage line via the pause control switching element and the reference voltage supply switching element, 3. The pixel circuit according to claim 2, wherein the first conduction terminal of the drive transistor is connected to the first power supply line via the power supply switching element and is connected to the one data signal line via the write control switching element, and the power supply switching element has a control terminal connected to one power supply control line of the plurality of power supply control lines.

7. The display device further comprises a write capacitor as the write destination capacitive element, a reference voltage supply switching element, and a write capacitance short-circuit switching element, wherein the display unit further includes a reference voltage line for supplying a predetermined fixed voltage, a plurality of second scanning signal lines, and a plurality of third scanning signal lines, the first power supply line is a high-voltage side power supply line, the second power supply line is a low-voltage side power supply line, the drive transistor is an N-channel type transistor, the write control switching element and the initialization switching element are transistors of the same conductivity type, and the pause control switching element and the reference voltage supply switching element are transistors of the same conductivity type, the first electrode of the display element is connected to the second conduction terminal of the drive transistor via the emission control switching element, the control terminal of the pause control switching element is connected to one second scanning signal line of the plurality of second scanning signal lines, and the reference voltage supply switching element has a control terminal connected to the one second scanning signal line, 2. The pixel circuit of claim 1, wherein the write capacitor short-circuit switching element has a control terminal connected to one of the plurality of third scanning signal lines, the control terminal of the drive transistor is connected to a connection point between the write capacitor and the storage capacitor via the write capacitor, is connected to the connection point via the write capacitor short-circuit switching element, and is connected to the one data signal line via the pause control switching element and the write control switching element, the second conduction terminal of the drive transistor is connected to the connection point via the storage capacitor, and the connection point is connected to the reference voltage line via the reference voltage supply switching element.

8. The pixel circuit according to claim 1, wherein at least one of the switching elements connected to the drive transistor is a thin-film transistor having a channel layer formed of an oxide semiconductor.

9. The pixel circuit according to claim 8, wherein at least one of the write control switching element and the pause control switching element is a thin film transistor having a channel layer formed of an oxide semiconductor.

10. A display unit including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of light emission control lines, a first power line, a second power line, an initialization voltage line for supplying a predetermined fixed voltage as an initialization voltage, and a plurality of pixel circuits; a data side driving circuit that generates a plurality of data signals and applies them to the plurality of data signal lines; a scanning side driving circuit that selectively drives the plurality of first scanning signal lines and selectively drives the plurality of light emission control lines; and a display control circuit that controls the data side driving circuit and the scanning side driving circuit so that a driving period consisting of a refresh frame period during which the voltages of the plurality of data signals are written to the plurality of pixel circuits as data voltages and a pause period consisting of a non-refresh frame period during which writing of data voltages to the plurality of pixel circuits is stopped appear alternately, wherein each of the plurality of pixel circuits comprises: a display element driven by a current, a holding capacitor, a driving transistor that controls the current flowing to the display element in accordance with the voltage held in the holding capacitor, and a write control switching element having a control terminal connected to one of the plurality of first scanning signal lines, the pixel circuit includes an emission control switching element provided in series with the display element and having a control terminal connected to one of the plurality of emission control lines; and an initialization switching element, wherein the drive transistor has a first conduction terminal connected directly or indirectly via at least one element to the first power supply line, a second conduction terminal connected directly or indirectly via at least one element to the second power supply line, and a control terminal connected to at least one data signal line of the plurality of data signal lines via the write control switching element, the display element has a first electrode connected to the initialization voltage line via the initialization switching element and a second electrode connected to the second power supply line, and the initialization switching element has a control terminal connected to the one first scanning signal line, or another one of the plurality of first scanning signal lines adjacent to the one scanning signal line in the scanning order, or a signal line connected to a control terminal of a switching element other than the write control switching element among switching elements included in the pixel circuit,the display control circuit controls the scanning side drive circuit so that, in each of the plurality of pixel circuits, a current path from the one data signal line via the write control switching element to a fixed voltage line is formed when a voltage of a data signal applied to the one data signal line is to be written to the pixel circuit as a data voltage, the current path includes: a write destination capacitive element provided in series with the write control switching element; and a pause control switching element provided in series with the write control switching element and the write destination capacitive element, the pause control switching element having a control terminal connected to a signal line connected to a control terminal of another switching element among the switching elements included in the pixel circuit, the other switching element being neither the write control switching element nor the initialization switching element, the display control circuit controls the scanning side drive circuit so that, during the refresh frame period, the pause control switching element is in an on state when the write control switching element is in an on state in a non-light-emitting period in which the display element is in an off state, and, during the non-refresh frame period, the pause control switching element is in an off state while the write control switching element is in an on state in the non-light-emitting period, A display device that controls the scanning side drive circuit so that the write control switching element and the initialization switching element are in the off state and the emission control switching element is in the on state during an emission period in which the display element is in an emission state, regardless of whether it is the refresh frame period or the non-refresh frame period.

11. The display device according to claim 10, wherein the write control switching element and the initialization switching element are transistors of the same conductivity type, a control terminal of the initialization switching element is connected to the one first scanning signal line, and the control terminal of the pause control switching element is connected to the one light-emitting control line, and the display control circuit controls the scanning side drive circuit to generate a signal to be applied to the one first scanning signal line as a signal having the same waveform in both the refresh frame period and the non-refresh frame period, and generate a signal to be applied to the one light-emitting control signal line as a signal having a different waveform in the refresh frame period and the non-refresh frame period, thereby causing the pause control switching element to be in an on state during the refresh frame period when the write control switching element is in an on state during the non-light-emitting period, and to be in an off state during the non-refresh frame period while the write control switching element is in an on state.

12. The display device of claim 11, wherein the first power supply line is a high-voltage side power supply line, the second power supply line is a low-voltage side power supply line, the write-in capacitive element is the holding capacitor, the drive transistor is an N-channel type transistor, the pause control switching element and the emission control switching element are switching elements of the same conductivity type, the first electrode of the display element is connected to the second conduction terminal of the drive transistor via the emission control switching element, and the control terminal of the drive transistor is connected to the second conduction terminal of the drive transistor via the holding capacitor and is connected to the one data signal line via the pause control switching element and the write control switching element.

13. The display device of claim 11, wherein the first power supply line is a low-voltage power supply line, the second power supply line is a high-voltage power supply line, the write-in capacitance element is the holding capacitor, the drive transistor is an N-channel transistor, the pause control switching element and the emission control switching element are transistors of the same conductivity type, the first electrode of the display element is connected to the second conduction terminal of the drive transistor via the emission control switching element, and the control terminal of the drive transistor is connected to the first conduction terminal of the drive transistor via the holding capacitor and is connected to the one data signal line via the pause control switching element and the write control switching element.

14. The display device of claim 11, wherein the first power supply line is a high-voltage side power supply line, the second power supply line is a low-voltage side power supply line, the write-in capacitive element is the holding capacitor, the drive transistor is a P-channel transistor, the pause control switching element and the emission control switching element are transistors of different conductivity types, the first electrode of the display element is connected to the second conduction terminal of the drive transistor via the emission control switching element, and the control terminal of the drive transistor is connected to the first conduction terminal of the drive transistor via the holding capacitor and is connected to the one data signal line via the write control switching element and the pause control switching element.

15. The display unit further includes a plurality of power supply control lines and a reference voltage line for supplying a predetermined fixed voltage, the first power supply line being a high-voltage side power supply line and the second power supply line being a low-voltage side power supply line, the scanning side drive circuit further selectively drives the plurality of power supply control lines, each of the plurality of pixel circuits further includes a power supply switching element and a reference voltage supply switching element connected in series with the pause control switching element, the destination capacitance element being the holding capacitor, the drive transistor being a P-channel type transistor, the pause control switching element and the emission control switching element being switching elements of the same conductivity type, the first electrode of the display element being connected to the second conduction terminal of the drive transistor via the emission control switching element, and the control terminal of the drive transistor being connected to the first conduction terminal of the drive transistor via the holding capacitor and connected to the reference voltage line via the pause control switching element and the reference voltage supply switching element, 12. The display device according to claim 11, wherein the first conduction terminal of the drive transistor is connected to the first power supply line via the power supply switching element and is connected to the one data signal line via the write control switching element, the power supply switching element having a control terminal connected to one power supply control line of the plurality of power supply control lines, and the display control circuit controls the scanning side drive circuit so that the power supply switching element is in an off state when the write control switching element or the pause control switching element is in an on state and is in an on state during the light emission period.

16. The display device further comprises a write capacitor as the write destination capacitive element, a reference voltage supply switching element, and a write capacitance short-circuit switching element, wherein the display unit further includes a reference voltage line for supplying a predetermined fixed voltage, a plurality of second scanning signal lines, and a plurality of third scanning signal lines, the scanning side driving circuit further selectively drives the plurality of second scanning signal lines and selectively drives the plurality of third scanning signal lines, the first power supply line is a high-voltage side power supply line, the second power supply line is a low-voltage side power supply line, the driving transistor is an N-channel type transistor, the write control switching element and the initialization switching element are transistors of the same conductivity type, and the pause control switching element and the reference voltage supply switching element are transistors of the same conductivity type, the first electrode of the display element is connected to the second conductive terminal of the driving transistor via the light emission control switching element, and the control terminal of the pause control switching element is connected to one second scanning signal line of the plurality of second scanning signal lines, the reference voltage supply switching element has a control terminal connected to the one second scanning signal line, the write capacitor short-circuit switching element has a control terminal connected to one third scanning signal line of the plurality of third scanning signal lines, the control terminal of the drive transistor is connected to a connection point between the write capacitor and the hold capacitor via the write capacitor, is connected to the connection point via the write capacitor short-circuit switching element, and is connected to the one data signal line via the pause control switching element and the write control switching element, the second conduction terminal of the drive transistor is connected to the connection point via the hold capacitor, and the connection point is connected to the reference voltage line via the reference voltage supply switching element, and the display control circuit isduring a write period provided within the non-light-emitting period in the refresh frame period, the write control switching element, the pause control switching element, the reference voltage supply switching element, the light-emitting control switching element and the initialization switching element are in an on state and the write capacitor short-circuit switching element is in an off state, and during a write initialization period provided before the write period in the non-light-emitting period, the write control switching element is in an off state and the write capacitor short-circuit switching element is in an on state, and during a threshold detection period provided after the write period in the non-light-emitting period in the refresh frame period, the write control switching element and the write capacitor short-circuit switching element are in an off state and the reference voltage supply switching element is in an on state, and during a threshold compensation period provided after the threshold detection period in the non-light-emitting period in the refresh frame period, the write capacitor short-circuit switching element and the reference voltage supply switching element are in an on state and the write control switching element is in an off state, 11. The display device according to claim 10, wherein the scanning side drive circuit is controlled so that, during the non-light-emitting period in the non-refresh frame period, the write control switching element and the initialization switching element are in an on state and the pause control switching element and the reference voltage supply switching element are maintained in an off state, and, during the light-emitting period, whether in the refresh frame period or the non-refresh frame period, the write control switching element, the pause control switching element, and the reference voltage supply switching element are maintained in an off state and the write capacitor short-circuit switching element and the light-emitting control are maintained in an on state.

17. A method for driving a display device having a display unit including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of light-emitting control lines, a first power supply line, a second power supply line, an initialization voltage line for supplying a predetermined fixed voltage as an initialization voltage, and a plurality of pixel circuits, each of the plurality of pixel circuits including: a display element driven by a current, a holding capacitor, a drive transistor for controlling a current flowing to the display element in accordance with a voltage held in the holding capacitor, a write control switching element having a control terminal connected to one of the plurality of first scanning signal lines, a light-emitting control switching element provided in series with the display element and having a control terminal connected to one of the plurality of light-emitting control lines, and an initialization switching element, the drive transistor having a first conduction terminal connected directly or indirectly via at least one element to the first power supply line, a second conduction terminal connected directly or indirectly via at least one element to the second power supply line, and a control terminal connected to one of the plurality of data signal lines via at least the write control switching element, the display element has a first electrode connected to the initialization voltage line via the initialization switching element and a second electrode connected to the second power supply line, the initialization switching element having a control terminal connected to the one first scanning signal line, or another one of the plurality of first scanning signal lines adjacent to the one scanning signal line in scanning order, or a signal line connected to a control terminal of another switching element other than the write control switching element among the switching elements included in the pixel circuit, in each of the plurality of pixel circuits, a current path from the one data signal line via the write control switching element to a fixed voltage line is formed when a voltage of the one data signal line is to be written to the pixel circuit as a data voltage, the current path including: a write destination capacitive element provided in series with the write control switching element; and a pause control switching element provided in series with the write control switching element and the write destination capacitive element,the pause control switching element has a control terminal connected to a signal line connected to a control terminal of another switching element, other than the write control switching element or the initialization switching element, among the switching elements included in the pixel circuit, and the driving method includes a pause driving step of generating a plurality of data signals and applying them to the plurality of data signal lines and driving the plurality of first scanning signal lines and the plurality of light-emitting control lines so that a drive period consisting of a refresh frame period in which voltages of the plurality of data signals are written to the plurality of pixel circuits as data voltages and a pause period consisting of a non-refresh frame period in which writing of data voltages to the plurality of pixel circuits is stopped appear alternately, the pause driving step including: a non-light-emitting period step of driving the plurality of first scanning signal lines and the plurality of light-emitting control lines so that, during the refresh frame period, the pause control switching element is in an on state when the write control switching element is in an on state in a non-light-emitting period in which the display element is in an off state, and, during the non-refresh frame period, the pause control switching element is in an off state while the write control switching element is in an on state in the non-light-emitting period; and an emission period step of driving the plurality of first scanning signal lines and the plurality of emission control lines so that the write control switching element and the initialization switching element are in an off state and the emission control switching element is in an on state during an emission period in which the display element is in an emission state, whether the period is the refresh frame period or the non-refresh frame period.

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